Objective:

To design Altera Nios 2 processor Instruction Subset Architecture.

Nios 2 is Altera's RISC processor. It is a soft processor. The instruction sub set for
this design is in such a way that it should be able to compute the dot product of two
input vectors. The instruction memory and data memory are separate, and it follows
the five stage pipelined architecture. The main five stages are Fetch, Decode,
Execute, Memory and Write Back. These modules are to be designed for the Nios 2
processor according to the architecture flow.
Work progress till now:
Fetch, Decode, and currently working on Execute stage, testbench is complete.
The initial background work for the processor is complete. I have understood the
architecture of Nios 2 processor and the data flow from the first stage in the pipeline
to the final stage of the pipeline. The various control signals involved were also
analysed. After the ground work was completed, the test bench was prepared, and
currently the test bench is ready for the computation of dot product according to
the material provided. In the main processor module, the fetch and the decode
stages have been completed. Currently I am working on the execute stage of the
architecture. The fetch stage will get the instruction from the memory and the
decode stage will decode the instruction to identify whether it is an I type, R type or
J type instruction. These two blocks have been completed.
Pending:
Write back and memory stage and Simulation (debugging).
The pending work is the next two stages namely, memory and write back. The
signals to be used for these stages have been identified and the coding for these
two blocks are yet to be completed. With these two stages the whole processor
module will be complete and then I can run it with the test bench that is already
completed.
Challenges faced:
Understanding the flow of signals from one stage to another.
Initially, it took me sometime to understand the architecture of Nios 2 processor.
Though the MIPS and Nios 2 almost have the same architectures, there are a few
instructions that are not present in MIPS that are required in Nios 2, like orhi, ori,
etc. The understanding of how each of these instruction works and how these
instructions are processed in the processor took me some time. But once that was
done, the modelling of the processor was more meaningful. Another challenge that I
faced was taking note of signals, that are flopped from each stage of the pipeline to
the next stage.