BG Thiet Ke Logic So Chuong 4 Phuongphapthietkeso

HC VIN CNG NGH BU CHNH VIN THNG
BI GING MN
THIT K LOGIC S
Ging vin:
TS. Nguyn Ngc Minh
in thoi/E-mail:
84-4- 3351 9391
B mn:
KTT-Khoa KTT
Hc k/Nm bin son: K 1/2012

1
CHNG 4- PHNG PHP

THIT K S
TS. Nguyn Ngc Minh
Khoa KTT1
BI GING: THIT K LOGIC S

CHNG 4- PHNG PHP THIT K S
NI DUNG CHNH CA CHNG

4.1 CC PHNG PHP M T MCH S
4.2 M HNH RTL
4.3 THIT K MCH T HP DNG VHDL
4.4 THIT K MCH TUN T C BN DNG VHDL
4.5 MY TRNG THI Hu HN FSM
4.6 MY TRNG THI ASM
4.7 PHNG PHP THIT K TOP-DOWM
4.8 PHNG PHP THIT K NG B
4.9 PHNG PHP THIT K KHNG NG B
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4.1 M HNH BIU DIN H THNG S
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M hnh hot ng (Behavioral views): l m hnh m t hot
ng, chc nng ca h thng di dng mi quan h gia u
vo, u ra, v nh thi m khng quan tm n cu trc bn
trong ca h thng.
+ Hnh thc biu din: c biu din bi m t chc nng, hot ng ca h
thng bng ngn ng t nhin, gin thi gian (s nh thi), phng trnh
logic, bng trng thi, lu gii thut, hnh trng thi.
+ y l m hnh c mc tru tng cao nht, v thng rt thch hp cho
cc mc ch m phng, g ri nhanh cho h thng.
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M hnh cu trc (Structural views) : l m hnh m t cu trc
bn trong ca h thng gm cc thnh phn con v cc kt ni
gia chng. M hnh ny ging nh s khi hay mch nguyn
l ca h thng.
+ Hnh thc biu din: c m t theo m hnh cu trc c th gm cc cu
trc cng logic c bn, cc Flip-Flop
+ Kiu m t ny cng c lp vi cng ngh thc hin mch, tuy nhin tng
tnh ti u cho mch, m hnh cu trc logic thng ny thng s dng cc cu
trc logic c xy dng sn, hoc chn trong th vin ca nh cung cp ph
hp vi loi cng ngh s dng.
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M hnh vt l (Physical views): l m hnh m t c tnh vt l
ca h thng v thm vo cc thng tin chi tit cho m hnh cu
trc nh xc nh kch thc hay v tr vt l ca cc linh kin trn
bo mch hay trn phin bn dn, cng nh cc ng dn vt l
ca mi ng kt ni.
+ Hnh thc biu din: biu din mch in PCB ca bo mch h thng, layout
ca ca IC
+ H thng s c m t mc chi tit nht, ti cu trc vt l bn dn,

cng nh cu trc bn trong nhng ti nguyn sn c trong cu kin, cch ny
ti u cho vic tng hp trn loi cu kin, cng ngh s dng.
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4.2 CC MC TRU TNG TRONG M T H

THNG S
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4.2 CC MC TRU TNG TRONG M T H THNG S
M t mc mch in (Circuit Level or Transistor Level): y l mc m t
c mc tru tng thp nht. H thng c m t theo m hnh cu trc s
dng cc cu trc c bn nh Transistor, in tr, T in, hay theo m hnh
hot ng s dng h phng trnh vi phn.
+ mc m t ny h thng s c tnh ton nh mt h thng tng t, m
trong tn hiu tn ton theo mc in p bin i theo gian v c gi tr trong
khong lin lc. H thng cng c th c m t theo m hnh vt l s dng
cu trc bn dn ca cc cu kin v kt ni gia chng.
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M t mc logic (Logic Lever or Gate Level): H thng c m t s dng
cc cu trc cng logic s bn nh AND, OR, XOR, MUX, phn t nh c bn
nh Flip-Flops Tn hiu c biu din theo cc mc logic 0, 1 v hot ng
vo- ra c tnh ton theo hm boolean.
+ mc m t ny s lng cng NAND 2 u tng ng trong mch c
s dng nh gi mc phc tp ca h thng.
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M t mc RTL (Register Transfer Level Mc truyn t thanh ghi): H
thng c m t s dng cc m-un chc c bn nh: cc b cng, b so
snh, khi nh, thanh ghi, Mux, Demux , hot ng ca h thng s c xc
nh bi cch d liu x l v chuyn i gia cc thanh ghi lu tr.
+ M t theo m hnh hot ng mc ny s dng nhng m t chung xc
nh cc php ton chc nng v nh tuyn d liu, v s dng my trng thi
FSM m t hot ng ca h thng. c im quan trng ca m t mc RTL
l s dng tn hiu clock chung cho cc cu trc nh. M hnh vt l cho mc m
t RTL c gi chung l floorplan. N rt hu ch cho chung ta tm ra nhng
ng thp nht gia cc phn t nh v xc nh chu k clock.
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M t mc h thng (System Level or Processor Level): l m t c mc
tru tng cao nht. Cc khi c bn c s dng xy dng h thng l cc
khi IP (Intellectual Properties) nh cc b x l, b nh, giao tip bus, M t
theo m hnh hot ng mc ny ging nh chng trnh lp trnh theo gii
thut nh cc ngn ng lp trnh bao bm cc bc tnh ton v truyn thng.
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V d: M t theo m hnh cu
trc
M hnh cu trc mc h thng in hnh ca h thng

s. Trong h thng s c xy dng t cc khi chnh
nh Vi x l, B nh, giao tip b nh,
15
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V d: M t theo m hnh hot

ng mc RTL
+ Khi x l trung tm (CPU) :
Khi ny gm 2 thnh phn:
- Khi ng d liu (Datapath):
Thc hin cc php x l s liu
ca h thng s, chng thng
gm cc khi thanh ghi, b m,
ghp knh, ALU khi tnh ton s
hc v logic....
- Khi iu khin (Control Unit):
Chc nng iu khin chnh cho
khi Datapath thc hin cc
bc x l s liu nh mong mun.
ISA (Instruction set

Architecture Kin trc
tp lnh): Tp lnh lp
trnh hot ng cho CPU.
Thng ch c trong cc
h thng phc tp, a
dng nh cc b vi x l
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V d: M t theo m hnh cu trc mc RTL
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M t theo m hnh cu trc (tt)

M t theo m hnh cu trc l m t cc phn
t con bn trong h thng v s kt ni ca
cc phn t con
V d: Vit VHDL m t theo m hnh cu trc mt

thanh ghi 4 bit c xy dng t 4 triger D
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4.1.2 Phng php m t theo m hnh hot ng

(Behavioral)
M hnh hot ng l mc m t tru tng nht, c
th l m t theo chc nng ca h thng
c im ca phng php ny l nhp thit k nhanh,
nhng cu trc ca phn cng thng khng r
V d: m t chc nng h
thng l: Nu mi khi c mt
sensor no c kch hot,
th h thng kim tra m bn
phm. Nu sau 20 giy m
khng c m bn phm nhp
ng nhp vo th ci bo ng
s c bt ln.
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4.1.2 Phng php m t theo m hnh hot ng

(Behavioral)
V d: m t chc nng h thng l: Nu mi khi c
mt sensor no c kch hot, th h thng kim
tra m bn phm. Nu sau 20 giy m khng c m
bn phm nhp ng nhp vo th ci bo ng s
c bt ln.
entity Security_1 is
port (Clk, Reset : in std_logic ;
Keypad : in std_logic_vector (3
downto 0) ;
Front_Door, Rear_Door, Window:
in boolean ;
Alarm_Siren : out boolean ) ;
end Security_1 ;
architecture Behavioral of Security_1 is

constant Delay_Period : time := 20 s;
begin
process (Keypad,Front_Door,Rear_Door,Window)
begin
if (Front_Door or Rear_Door or Window ) then
if (Keypad = 0011) then
Alarm_siren <= false ;
else
Alarm_Siren <= True after Delay_Period ;
end if ;
end if ;
end process ;
end Behavioral;
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4.1.3 Phng php m t theo m

hnh lung d liu RTL
a. M t mch logic t hp
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b. M t mch tun t
Tin trnh hot ng theo clock c th c m t
thnh tin trnh ng b hoc tin trnh khng ng
b
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4.2 M HNH RTL

RTL-Register Tranfer
Level l H thng s
c m t theo m hnh
hot ng mc truyn
t thanh ghi.
M hnh RTL c xy
dng t cc cu trc:
b nh, khi iu khin,
ng d liu, iu
khin vo/ra
Kiu m t ny thng c dng trong vic kim tra, m
phng h thng, cng nh cho vic tng hp vi mc c
lp vi cng ngh cao.
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+ Khi x l trung tm (CPU) :

Khi ny gm 2 thnh phn:
- Khi ng d liu
(Datapath): Thc hin cc php
x l s liu ca h thng s,
chng thng gm cc khi
thanh ghi, b m, ghp knh,
ALU khi tnh ton s hc v
logic....
- Khi iu khin (Control
Unit): Chc nng iu khin
chnh cho khi Datapath thc
hin cc bc x l s liu nh
mong mun.
ISA (Instruction set

Architecture Kin trc
tp lnh): Tp lnh lp
trnh hot ng cho CPU.
Thng ch c trong cc
h thng phc tp, a
dng nh cc b vi x l
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V d - M hnh cu trc mc RTL

25
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4.2 M HNH RTL (tt)

4.2.1 Khi Datapath
Datapath RTL gm cc khi thanh ghi v cc khi mch logic t

hp, c m t bng cc tin trnh t hp (combinatorial
process) v cc tin hot ng theo clock (clocked process).
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M t thnh 2 process c lp cho
mch tun t v mch t hp c lp
Kt hp mch t hp v tun t
trong mt process
27
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M u
Cc m hnh cu trc lnh to mch t hp :
-Cc cu trc tp lnh
-Testbench cho mch
-M t mch logic c bn
-B m
- Mch m ha, gii m

- Mch ghp knh
- Mch m ha u tin
- B cng
- Mch kim tra chn l
- ALU
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4.3.1 Cu trc tp lnh dng cho m t mch t hp

Mch logic t hp c th m t bng cc cu trc lnh
song song, tuy nhin thng dng cc process t
hp. Khi s dng process t hp tt c cc tn hiu
vo ca mch t hp phi c a vo danh sch tn
hiu kch thch
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M hnh kt ni ca cc Process
Process 1
A
B
G1
C<=A and B
...
G2
Process 2
If C = 1
then
...
C
C
Process 3
G3
process (C,..)
begin
Process n
C<=A and B
...
Process n4
process n
Process n1
C
C
If C = 1
then
...
Sig1
Sig2
process (...
Process n2
process (C,..)
begin
Process n3
Rst
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4.3.2 Testbech cho mch t hp
S tng qut chng trnh th Testbench n gin

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S tng chng trnh th Testbench y

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Trng hp 1: Vit m t to ra dng tn hiu n a nh
hnh v di y
33
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Trng hp 2: Vit m t
xung clock 1, clock2 c chu
k 100 ns
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V d to dng sng
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4.3.3 M t mch logic c bn

V d m t mch Mux 2 sang
1 c s mch nh sau:
nots
architecture mux21 of mux21

is
signal aout : STD_LOGIC;
signal bout : STD_LOGIC;
signal nots : STD_LOGIC;
begin
aout <= nots and a;
bout <= s and b;
nots <= not(s);
y <= bout or aout;
end mux21;
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4.3.4 Mch 3 trng thi
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4.3.5 Mch gii m 2:4

S dng cu trc lnh song song
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4.3.5 Mch gii m 3:8
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Mch gii m 3:8 (tt)
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Mch gii m LED 7 on dng WHEN
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Mch gii m LED 7 on dng Whit/Select/When
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Mch m ha 8 sang 3 dng

WHEN/ELSE
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Mch m ha 8 sang 3 dng WITH/SELECT/WHEN
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4.3.6 Mch Mux 4 sang 1
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Trng hp 1: Mch Mux 4 sang 1 dng WHEN/ELSE
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Trng hp 2: Mch Mux 4 sang 1 dng

WITH/SELECT/WHEN
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Trng hp 3: Mch Mux 4 sang 1 dng IF
48
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Trng hp 4: Mch Mux 4 sang 1 dng CASE
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4.3.7 MCH CNG BN PHN
end halfadd;
architecture halfadd of halfadd is
begin
s <= a xor b;
c <= a and b;
end halfadd;
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4.3.7 Mch cng ton phn 2 s NP 1 bit
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Mch cng 2 s NP 4 bit
52
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Mch cng ton phn 2 s NP 8 bit
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Mch cng ton phn 2 s NP

8 bit (tt)
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4.3.8 Mch so snh 2 s NP

8 bit
55
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4.3.9 Mch to bit parity chn t d liu 8 bit
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4.3.9 Mch to bit parity tng qut
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4.3.10 ALU
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4.3.10 ALU (tt)
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3.4.11 Mch min/max :
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4.3.12 Mch chuyn i m NP 4 bit sang Gray 4 bit
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4.4 THIT K MCH TUN T DNG VHDL

Tin trnh
ng b
Tin
trnh
khng
ng b
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Xung CLK cnh ln
Xung CLK cnh xung
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Trng hp 1: M t DFF s dng PROCESS (clk,rst)
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Trng hp 2: M t DFF s dng PROCESS (clk)
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Trng hp 3: M t DFF s dng PROCESS (clk,rst,d)
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4.4.4 Flip-Flop T
---- Flip-Flop T n gin
process (<clock>)
begin
if <clock>'event and <clock>=0' then
<output> <= not(<output>);
----Flip-Flop T c ng reset
end if;
process (<clock>, <reset>)
end process;
begin
if <reset>='1' then
<output> <= '0';
elsif (<clock>'event and <clock>='1') then
<output> <= not(<output>);
end if;
end process;
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4.4.5 THANH GHI n BIT
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Thit k thanh ghi dng lnh gn chn
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Thit k b m ln thp phn
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Thit k b m ln/xung thp phn (tt)
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B m nh phn li 4 bit u ra Q [3:0] hot ng vi sn

m clock, c np khng ng b gi tr c nh 1111 mc
tch cc thp:
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4.4.7 B NH R0M
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4.4.7 B NH RAM
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4.4.7 B NH RAM (tt)
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4.5 My trng thi hu hn FSM

4.5.1M
hnh my
trng thi
Mealy
76
Bi ging in T S
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4.5.2 M hnh
my trng thi
Moore
4.5.3 M
hnh my
trng thi
hn hp
Moore v
Mealy
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Mch m theo hnh trng thi
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V d: Lp hnh trng thi v vit chng trnh

VHDL m t b m ln/xung 4 bit
Bm vo y xem on chng trnh

VHDL
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THIT K MCH M
UP/DOWM CO IU
KHIN
process (<clock>, <reset>)

begin
if <reset>='1' then
<count> <= (others => '0');
elsif <clock>='1' and <clock>'event then
if <clock_enable>='1' then
if <load_enable>='1' then
<count> <= <input>;
else
if <count_direction>='1' then
<count> <= <count> + 1;
else
<count> <= <count> - 1;
end if;
end if;
end if;
end if;
end process;
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BI TP
Thit k b m Timer nh sau:
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4.6 MY TRNG THI ASM (Algorithmic State Machine)

Lu gii thut my
trng thi (Algorithmic
state machine: ASM
charts) l s tru tng
ha hnh vi ca my tun
t
Cc thnh phn ca mt
ASM nh sau:
***
Tn trng
thi
M trng thi
Hp trng thi
Danh
sch
xut
iu kin
Hp xut
theo iu
kin
Danh sch xut

theo iu kin
ng ra n khi
ASM khc
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4.6 MY TRNG THI ASM (Algorithmic State Machine) (tt)
V d: kt hp lu
ASM vi ng d liu
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86

4.6 MY TRNG THI ASM (Algorithmic State Machine)
Lu trng thi ASM h Moore cho mch m

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4.6 MY TRNG THI ASM (Algorithmic State Machine)(tt)
Lu trng thi ASM h Mealy cho mch m

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4.7 PHNG PHP THIT K TOP- DOWN
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4.7 PHNG PHP

THIT K TOPDOWN
* Mch ln c
phn chia thnh cc
mch nh hn
Mi mch nh ny
c c t bng
HDL
Mi mch nh c
th
c tng hp trong
thi gian chp nhn
c
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M hnh thit k top_down c bn

ca mch cng 4 bit
90
Cu hi
1. Trnh by nguyn l bt phm, thit k mch bt phm v
vit m t bng VHDL?
2. Thit k mch qut v nhn dng cho ma trn phm bm
(Keypad) 4x4?
3. Thit k m hnh n giao thng ti mt ng t v vit
m t bng VHDL?
4. Thit k mch iu khin ma trn LED 8x8, v vit m t
bng VHDL?
5. Thit k b iu khin truyn thng ni tip UART?
6. Thit k b lc FIR
7. Thit k mch iu khin ng c bc
91
NI DUNG CHNH CA CHNG

4.2 M HNH RTL
4.4 THIT K MCH TUN T C BN DNG VHDL
4.5 MY TRNG THI H HN FSM
4.6 MY TRNG THI ASM
4.7 PHNG PHP THIT K TOP-DOWM
4.8 PHNG PHP THIT K NG B
4.9 PHNG PHP THIT K KHNG NG B
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HC VIN CNG NGH BU CHNH VIN THNG

TS. Nguyn Ngc Minh

84-4- 3351 9391

Hc k/Nm bin son: K 1/2012

CHNG 4- PHNG PHP

BI GING: THIT K LOGIC S

NI DUNG CHNH CA CHNG

BI GING: THIT K LOGIC S

4.1 CC PHNG PHP M T MCH S

BI GING: THIT K LOGIC S

4.1 M HNH BIU DIN H THNG S

BI GING: THIT K LOGIC S

4.1 M HNH BIU DIN H THNG S

BI GING: THIT K LOGIC S

4.1 M HNH BIU DIN H THNG S

BI GING: THIT K LOGIC S

4.1 M HNH BIU DIN H THNG S

+ H thng s c m t mc chi tit nht, ti cu trc vt l bn dn,

BI GING: THIT K LOGIC S

4.2 CC MC TRU TNG TRONG M T H

BI GING: THIT K LOGIC S

BI GING: THIT K LOGIC S

BI GING: THIT K LOGIC S

BI GING: THIT K LOGIC S

BI GING: THIT K LOGIC S

BI GING: THIT K LOGIC S

M hnh cu trc mc h thng in hnh ca h thng

BI GING: THIT K LOGIC S

V d: M t theo m hnh hot

ISA (Instruction set

BI GING: THIT K LOGIC S

V d: M t theo m hnh cu trc mc RTL

BI GING: THIT K LOGIC S

M t theo m hnh cu trc (tt)

V d: Vit VHDL m t theo m hnh cu trc mt

BI GING: THIT K LOGIC S

4.1.2 Phng php m t theo m hnh hot ng

BI GING: THIT K LOGIC S

4.1.2 Phng php m t theo m hnh hot ng

architecture Behavioral of Security_1 is

BI GING: THIT K LOGIC S

4.1.3 Phng php m t theo m

BI GING: THIT K LOGIC S

BI GING: THIT K LOGIC S

4.2 M HNH RTL

BI GING: THIT K LOGIC S

+ Khi x l trung tm (CPU) :

ISA (Instruction set

BI GING: THIT K LOGIC S

V d - M hnh cu trc mc RTL

BI GING: THIT K LOGIC S

4.2 M HNH RTL (tt)

Datapath RTL gm cc khi thanh ghi v cc khi mch logic t

BI GING: THIT K LOGIC S

BI GING: THIT K LOGIC S

4.3 THIT K MCH T HP DNG VHDL

- Mch m ha, gii m

BI GING: THIT K LOGIC S

4.3.1 Cu trc tp lnh dng cho m t mch t hp

BI GING: THIT K LOGIC S

BI GING: THIT K LOGIC S

4.3.2 Testbech cho mch t hp

S tng qut chng trnh th Testbench n gin

BI GING: THIT K LOGIC S