HC VIN CNG NGH BU CHNH VIN THNG

BI GING MN

THIT K LOGIC S

Ging vin:

TS. Nguyn Ngc Minh

in thoi/E-mail:

84-4- 3351 9391

B mn:

KTT-Khoa KTT

Hc k/Nm bin son: K 1/2012

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CHNG 5
THIT K CC H THNG S
NG DNG VHDL
TS. Nguyn Ngc Minh
Khoa KTT1

BI GING: THIT K LOGIC S

CHNG 5- THIT K CC H THNG S NG DNG VHDL

NI DUNG CHNH CA CHNG

5.1 THIT K IU KHIN HIN TH LED, MA
TRN LED, LED 7 ON, VGA, LCD.
5.2 THIT K MCH IU KHIN MA TRN BN
PHM.
5.3. THIT K GIAO TIP PS2 VI BN PHM
5.4 THIT K GIAO TIP TRUYN THNG UART
5.5 THIT K B TRUY NHP VI SDRAM NGOI

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CHNG 5- THIT K CC H THNG S NG DNG VHDL

5.1. THIT K MCH IU KHIN HIN TH LED

5.1.1 Thit k mch
iu khin mn ch
th s LED

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CHNG 5- THIT K CC H THNG S NG DNG VHDL

Nguyn l qut :
+ Ban u LED 1 s c hin th bng cch cp
ngun cho LED1, v d liu s c a vo cc
chn iu khin ca LED1.
+ Sau ln lt cc LED2, LED3,LED4 c hin
th vi d liu tng ng ca tng con LED 7
thanh trong rt nhiu chu k.
+ V c tip tc nh vy cc LED c qut theo
th t.
+ Do s lu nh trn vng mc nn khi ta quan st
gn nh sng lin tc.

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CHNG 5- THIT K CC H THNG S NG DNG VHDL

S trin khai ng dng

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CHNG 5- THIT K CC H THNG S NG DNG VHDL

Yu cu vit VHDL gm c cc modul sau:

1. Khai bo cc tn hiu
2. Xy dng b chia tn (tn s xung clk
chun la 50M)
3. Xy dng b iu khin, thc t chnh l
b m mc 4
4. Xy dng khi iu khin qut LED v
chn knh
5.Xy dng khi lu cc m
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CHNG 5- THIT K CC H THNG S NG DNG VHDL
process(count_chiatan)
begin
if(count_chiatan="110010") then
CLK_1M<= not CLK_1M;
end if;
process(CLK_1M,countmode4)
end process;
begin
if(CLK_1M'event and
CLK_1M='1') then
countmode4<=countmode4+1;
end if;
process(countmode4)
end process;
begin
case countmode4 is
when "00" => temp<=HN;AN<="1000";
when "01" => temp<=HT;AN<="0100";
when "10" => temp<=HC;AN<="0010";
when others => temp<=HDV;AN<="0001";
end case;
end process;

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CHNG 5- THIT K CC H THNG S NG DNG VHDL

5.1.2 Thit k mch iu khin ma trn LED (8x8)

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CHNG 5- THIT K CC H THNG S NG DNG VHDL

Nguyn l qut
10

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CHNG 5- THIT K CC H THNG S NG DNG VHDL

5.1.2 (tt)

Xy dng
m hnh
Mch iu
khin hin
th ma trn
LED

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CHNG 5- THIT K CC H THNG S NG DNG VHDL

5.1.2 (tt)
process(count_mode8)
begin
case count_mode8 is
when "000" => colum<= "10000000";
when "001" => colum<= "01000000";
when "010" =>
when "011" =>
when "100" =>
when "101" =>

colum<= "00100000";
colum<= "00010000";
colum<= "00001000";
colum<= "00000100";

when "110" => colum<= "00000010";

when others => colum<= "00000001";
end case;

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CHNG 5- THIT K CC H THNG S NG DNG VHDL

5.1.2 (tt)
row <= a(63 downto 56) when count_mode8 =x"0" else
a(55 downto 48) when count_mode8 =x"1" else
a(47 downto 40) when count_mode8 =x"2"
else
a(39 downto 32) when count_mode8 =x"3"
else
a(31 downto 24) when count_mode8 =x"4"
else
a(23 downto 16) when count_mode8 =x"5"
else
a(15 downto 8) when count_mode8 =x"6"
else
a(7downto 0);
end Behavioral;

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CHNG 5- THIT K CC H THNG S NG DNG VHDL

5.1.2 (tt)
process(clk) --xung 2Kz
begin
if clk='1' and clk'event then
if dem = 12500 then
dem <= 0;
clk2khz <= not clk2khz;
else
dem <= dem +1;
end if;
end if;
end process;
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CHNG 5- THIT K CC H THNG S NG DNG VHDL
5.1.3 THIT K B M TN S T NG THAY I THANG O

Yu cu:Mch vo s c nhim v bin i tn hiu vo thnh

dng xung c mc logic CMOS v c cng chu k vi tn hiu
vo. Dng xung ny c a vo b m tn thc hin
o tn s, kt qu s c ch th trn c cu ch th s LED
7 on
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CHNG 5- THIT K CC H THNG S NG DNG VHDL
5.1.3 THIT K B M TN S T NG THAY I THANG O (tt)

Xy dng s trin khai cho yu cu 3.1.3

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CHNG 5- THIT K CC H THNG S NG DNG VHDL

5.1.3 (tt)

Lu thut ton
iu khin trong
b m tn

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CHNG 5- THIT K CC H THNG S NG DNG VHDL

5.1.3 (tt)

entity auto_freq_counter is
port( fx : in std_logic;
clk: in std_logic;
Seg : out std_logic_vector(6 downto 0);
dot: out std_logic;
AN : out std_logic_vector(2 downto 0);
Unit : out std_logic_vector(2 downto
0));
end auto_freq_counter;

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CHNG 5- THIT K CC H THNG S NG DNG VHDL

5.1.3 (tt)

else

process (clk)
begin
if clk='1' and clk'event then
if(over1='0') then
case scale is
when "00" =>
if chiatan=x"F423F" then
--clk=10MHz, T=0,1s.
chiatan<=x"00000";
Tch<='1';
else
chiatan<=chiatan+1;
Tch<='0';
end if;
when "01" =>
if chiatan=x"1869F" then
--T=0,1ms;
chiatan<=x"00000";
Tch<='1';
else

chiatan<=chiatan+1;
Tch<='0';
end if;
when "10" =>
if chiatan=x"0270F" then
chiatan<=x"00000";
Tch<='1';
else
chiatan<=chiatan+1;
Tch<='0';
end if;
when others =>
if chiatan=x"F423F" then
chiatan<=x"00000";
Tch<='1';
else
chiatan<=chiatan+1;
Tch<='0';
end if;

--1us

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CHNG 5- THIT K CC H THNG S NG DNG VHDL

5.1.3 (tt)
end case;
else
chiatan<=x"00000";
Tch<='1';
-- Tao xung vao
end if;
process(clk)
end if;
end process;
begin

if clk='1' and clk'event then

fx1<=fx;
fx2<=fx1;
end if;
end process;
fx3<= fx1 and (not fx2); -- dong bo xung dem fx va clk

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CHNG 5- THIT K CC H THNG S NG DNG VHDL

5.1.4. THIT K MCH GIAO TIP IU KHIN VGA

a. Gii thiu chun VGA

S khi mn hnh VGA

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CHNG 5- THIT K CC H THNG S NG DNG VHDL

5.1.4. THIT K MCH GIAO TIP IU KHIN VGA (tt)

Kt qu kt hp mu t 3
mu c bn nh bng
sau

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CHNG 5- THIT K CC H THNG S NG DNG VHDL

5.1.4. THIT K MCH GIAO TIP IU KHIN VGA (tt)

th thi gian xung qut mnh

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CHNG 5- THIT K CC H THNG S NG DNG VHDL

5.1.4. THIT K MCH GIAO TIP IU KHIN VGA (tt)

th thi gian iu khin VGA

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CHNG 5- THIT K CC H THNG S NG DNG VHDL

5.1.4. THIT K MCH GIAO TIP IU KHIN VGA (tt)

S
khi b
iu
khin
VGA

Cc tn hiu Hsync, Vsync kt ni vi cng VGA iu

khin qut ngang,dc mn hnh .
Thit k da trn 1 VGA 640x480 pixel ,tc qut
mi pixel l 25MH .
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CHNG 5- THIT K CC H THNG S NG DNG VHDL

5.1.4. THIT K MCH GIAO TIP IU KHIN VGA (tt)

pixel_x, pixel_y: Hai tn hiu
ny cho bit v tr tng i
ca im nh .

Mch to pixel to
ra cc tn hiu
tung ng vi cc
mu c bn .

tn hiu
video_on
dng kch
hot hay v
hiu ho mn
hnh hin th.
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CHNG 5- THIT K CC H THNG S NG DNG VHDL

5.1.4. THIT K MCH GIAO TIP IU KHIN VGA (tt)

Xy dng thut ton, code
Nu tn s ca thit b thc thi l 25MH, mch ng
b c th xy dng bng 2 b m . Mt b m mod 800
ng b qut ngang. Mt b m mod 525 cho vic
ng b qut dc.
Thit k trn c thc hin trn kit spartan 3AN
vi clock h thng l 50MHz, do cn phi to mt b
chia tn xung 25MHz. B chia tn ny c th ch n gin
l mt b m mod2. Chng ta to ra mt tn hiu Tick
25MHz cho php hoc dng b m, tn hiu ny cng
c kt ni vi p_tick, a ra ngoi b VGA_sync kt
hp vi b to pixel.
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CHNG 5- THIT K CC H THNG S NG DNG VHDL

5.1.5. THIT K MCH IU KHIN HIN TH LCD

S khi mch
iu khin LCD
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CHNG 5- THIT K CC H THNG S NG DNG VHDL

5.1.5. THIT K MCH IU KHIN HIN TH LCD (tt)

hnh trng thi iu khin LCD

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CHNG 5- THIT K CC H THNG S NG DNG VHDL

5.1.5. THIT K MCH IU KHIN HIN TH LCD (tt)

K t
LCD

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CHNG 5- THIT K CC H THNG S NG DNG VHDL

5.1.5. THIT K MCH IU KHIN HIN TH LCD (tt)

K t
LCD

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CHNG 5- THIT K CC H THNG S NG DNG VHDL

5.1.5. THIT K MCH IU KHIN HIN TH LCD (tt)

M hnh tng qut ca

khi iu khin

architecture Behavioral of LCD_Controller is

-- 16 state FSM.
type StateType is (Pwr_Up, Pwr_Up_Delay,
Off_Pwr_Up_Delay, Write_Data,Data_Setup_Delay,
E_Pulse_Hi, E_Hi_Time, E_Pulse_Lo,Proc_Comp_Delay,
Load_Next_Data, End_State, End_Pad_12,End_Pad_13,
End_Pad_14, End_Pad_15, End_Pad_16
);
signal State, Next_State: statetype := Pwr_Up;
-- Instruction Counter.
signal Inst_Cnt: STD_LOGIC_VECTOR (3 downto 0) :=
"0000";
signal Inst_Cnt_E: STD_LOGIC;
signal Data_RS_Bus: STD_LOGIC_VECTOR(8 downto 0);

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CHNG 5- THIT K CC H THNG S NG DNG VHDL

5.2 THIT K MCH IU KHIN MA TRN BN PHM

Ma trn bn phm
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CHNG 5- THIT K CC H THNG S NG DNG VHDL

5.2 (tt)
Lu thut ton
qut bn phm

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CHNG 5- THIT K CC H THNG S NG DNG VHDL

5.2 (tt)

-- khoi chia tan:

-- bo dem mode 4
-- quet hang thu nhat:
-- quet hang thu hai:
-- quet hang thu ba:
-- quet hang thu tu:
entity banphim4x4_vhdl is
Port ( clk : in STD_LOGIC;
colum : out STD_LOGIC_VECTOR (3 downto 0);
row : inout STD_LOGIC_VECTOR (3 downto 0):="0000";
button : out std_logic_vector (3 downto 0));
end banphim4x4_vhdl;
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CHNG 5- THIT K CC H THNG S NG DNG VHDL
process(CLK) -- quet hang thu nhat:
begin
if clk'event and clk='1' and row(0)='0' then
if (colum="1110") then button0<= x"0";
elsif (colum="1101") then button0<= x"1";
elsif (colum="1011") then button0<= x"2";
elsif (colum="0111") then button0<= x"3";
else button0<= X"0";
end if;
process(CLK) -- quet hang thu hai:
end if;
begin
end process;
if clk'event and clk='1' and row(1)='0' then
if (colum="1110") then button1<= x"4";
elsif (colum="1101") then button1<= x"5";
elsif (colum="1011") then button1<= x"6";
elsif (colum="0111") then button1<= x"7";
Bm vo y
else button1<= X"0";
xem ton
end if;
b chng
end if;
trnh VHDL
end process;
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CHNG 5- THIT K CC H THNG S NG DNG VHDL

5.3. THIT K GIAO TIP PS2 VI BN PHM

S khi mch giao tip ps2

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CHNG 5- THIT K CC H THNG S NG DNG VHDL

5.3. THIT K GIAO TIP PS2 VI BN PHM (tt)

M bn phm

Cu trc d liu truyn qua PS2

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CHNG 5- THIT K CC H THNG S NG DNG VHDL

5.3. THIT K GIAO TIP PS2 VI BN PHM (tt)

Entity PS2Rx is
Port (
clk,reset:in std_logic;
ps2d,ps2c:in std_logic;--keydata,keyclock
rx_en:in std_logic;
rx_done_tick : out std_logic;
dout: out std_logic_vector(7 downto 0)
);
End PS2Rx;
Architecture arch of PS2Rx is
Constant BRK: std_logic_vector(7 downto 0):=x"F0";
Type statetype is(idle,dps,load);
signal state_reg,state_next: statetype;
signal filter_reg,filter_next:std_logic_vector(7 downto 0);
signal f_ps2c_reg,f_ps2c_next:std_logic;
signal n_reg,n_next:unsigned(3 downto 0);
Bm vo y
signal fall_edge:std_logic;
xem ton
signal b_reg,b_next:std_logic_vector(10 downto 0);
b chng
trnh VHDL
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CHNG 5- THIT K CC H THNG S NG DNG VHDL

5.4. THIT K B IU KIN TRUYN THNG NI TIP UART

UART (universal asynchronous receiver and transmitter) l

mt giao thc truyn thng ni tip bt ng b

S khi b nhn d liu UART

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CHNG 5- THIT K CC H THNG S NG DNG VHDL

5.4. THIT K B IU KIN TRUYN THNG NI TIP UART (tt)

- Khi baud rate generator: To im nh du ly

mu ( sample ticks).
- Khi receiver : Nhn d liu , chuyn thnh cc bt
song song
- Interface circuit : cung cp b m FIFO, giao tip
vi h thng.
Trong thit k ny tc truyn ni tip baud rate = 19200 do tc
ly mu = 19200x16=307200 ticks/ second . Thit k thc hin trn kit
Spartan 3AN ca xilinx, c clock system = 50Mhz ,do cn c b m
mod (50.000.000/ 307200) = 163.

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CHNG 5- THIT K CC H THNG S NG DNG VHDL

Lu thut ton mch

receiver
Bm vo y
xem ton
b chng
trnh VHDL
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CHNG 5- THIT K CC H THNG S NG DNG VHDL

5.5. THIT K B TRUY NHP VI SDRAM NGOI

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