`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
//
// Company:
// Engineer:
//
// Create Date:
20:42:19 09/11/2009
// Design Name:
// Module Name:
real_time_clk_verilog
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
//
module real_time_clk_verilog(clk,clear,hour1,hour2,minute1,minute2,second1,secon
d2,hour_A2,min_A1,sec_A0,load,data_in);
input clk,clear;
output reg [6:0]hour1,hour2,minute1,minute2,second1,second2;
input load;
input hour_A2,min_A1,sec_A0;
input [7:0]data_in;
reg clk_sec,clk_msec;
reg [7:0]sec,min,hr;
integer timer_count1=0,timer_count2=0;
always@(posedge clk)
begin
if(timer_count1==3999)
begin
timer_count1=0;
clk_msec=1'b1;
end
else
begin
timer_count1=timer_count1+1;
clk_msec=1'b0;
end
end
always@(posedge clk_msec)
begin
if(timer_count2==999)
begin
timer_count2=0;
clk_sec=1'b1;
end
else
begin
timer_count2=timer_count2+1;
clk_sec=1'b0;
end
end

always@(negedge clk_sec)
begin
if(~clear)
begin
sec=0;
min=0;
hr=0;
end
else
if(~load)
begin
if(hour_A2)
begin
if(hr[7:4]==4'b0010)
begin
if(hr[3:0]<4'b0100)
hr=data_in;
end
else if(hr[7:4]<4'b0010)
hr=data_in;
else
hr=8'b0;
end
if(min_A1)
begin
if(min[7:4]<4'b0110)
min=data_in;
else
min=8'b0;
end
if(sec_A0)
begin
if(sec[7:4]<4'b0110)
sec=data_in;
else
sec=8'b0;
end
end
else
begin
if(sec[3:0]==4'b1001)
begin
sec[3:0]=4'b0;
if(sec[7:4]==4'b0101)
begin
sec[7:4]=4'b0;
if(min[3:0]==4'b1001)
begin
min[3:0]=4'b0;
if(min[7:4]==4'b0101)
begin
min[7:4]=4'b0;
if(hr==8'b00100011)
hr=0;
else if(hr[3:0]==4'b1001)
begin
hr[3:0]=4'b0;
hr[7:4]=hr[7:4]+1;
end

else
hr[3:0]=hr[3:0]+1; //hours count completed
end
else
min[7:4]=min[7:4]+1;
end
else
min[3:0]=min[3:0]+1;//minutes count completed
end
else
sec[7:4]=sec[7:4]+1;
end
else
sec[3:0]=sec[3:0]+1;//seconds count completed
end
end
always@(sec)
begin
case(sec[3:0])
4'b0000:second1=7'b1111110;
4'b0001:second1=7'b0110000;
4'b0010:second1=7'b1101101;
4'b0011:second1=7'b1111001;
4'b0100:second1=7'b0110011;
4'b0101:second1=7'b1011011;
4'b0110:second1=7'b1011111;
4'b0111:second1=7'b1110000;
4'b1000:second1=7'b1111111;
4'b1001:second1=7'b1111011;
default:second1=7'b1001111;
endcase
end
always@(sec)
begin
case(sec[7:4])
4'b0000:second2=7'b1111110;
4'b0001:second2=7'b0110000;
4'b0010:second2=7'b1101101;
4'b0011:second2=7'b1111001;
4'b0100:second2=7'b0110011;
4'b0101:second2=7'b1011011;
default:second2=7'b1001111;
endcase
end
always@(min)
begin
case(min[3:0])
4'b0000:minute1=7'b1111110;
4'b0001:minute1=7'b0110000;
4'b0010:minute1=7'b1101101;
4'b0011:minute1=7'b1111001;
4'b0100:minute1=7'b0110011;
4'b0101:minute1=7'b1011011;
4'b0110:minute1=7'b1011111;
4'b0111:minute1=7'b1110000;
4'b1000:minute1=7'b1111111;
4'b1001:minute1=7'b1111011;
default:minute1=7'b1001111;
endcase
end

always@(min)
begin
case(min[7:4])
4'b0000:minute2=7'b1111110;
4'b0001:minute2=7'b0110000;
4'b0010:minute2=7'b1101101;
4'b0011:minute2=7'b1111001;
4'b0100:minute2=7'b0110011;
4'b0101:minute2=7'b1011011;
default:minute2=7'b1001111;
endcase
end
always@(hr)
begin
case(hr[3:0])
4'b0000:hour1=7'b1111110;
4'b0001:hour1=7'b0110000;
4'b0010:hour1=7'b1101101;
4'b0011:hour1=7'b1111001;
4'b0100:hour1=7'b0110011;
4'b0101:hour1=7'b1011011;
4'b0110:hour1=7'b1011111;
4'b0111:hour1=7'b1110000;
4'b1000:hour1=7'b1111111;
4'b1001:hour1=7'b1111011;
default:hour1=7'b1001111;
endcase
end
always@(hr)
begin
case(hr[7:4])
4'b0000:hour2=7'b1111110;
4'b0001:hour2=7'b0110000;
4'b0010:hour2=7'b1101101;
default:hour2=7'b1001111;
endcase
end
endmodule