ADVANCED VLSI DESIGN I SEM 2014

ASSIGNMENT
5/9/15

Problem statement------Assignment 1--Design and simulate a jitter bounded ADPLL. Architecture given as
attachment
Assignment 2--Design a pipelined programmable 16 point FFT unit using assigned
asynchronous/ Synchronous methodology. You need to design your own registers/ flip
flops/ latchs and delay elements wherever required
Groups may choose their own asynchronous methodology.
No two groups should choose sam design methodology
Every design should be unique. No copying permitted.

Group -----2 Phase Bundled Data (Micropipeline)

Group ------4 Phase Dual Rail Data
Group ------2 Phase Dual Rail Data
Group ------4 Phase Bundled Data
Group ------2 Phase Bundled Data (Mousetrap Pipeline)
Group -----clocked (dual edge synchronous) pipeline . Use ADPLL of assignment 1 for
clock

Make groups on your own ( preferably 2 students per group)