UNIVERSITI TEKNIKAL MALAYSIA MELAKA

FAKULTI KEJURUTERAAN ELEKTRONIK & KEJURUTERAAN

KOMPUTER
BENM 1143: LOGIC CIRCUIT
TUTORIAL 5 (SOLUTION)
1. The invalid state of an S-R latch occurs when the input of S and R is S =1 and R=1.
2. A J-K flip-flop is in the toggle condition when the input of J and K is J =1 and K=1.
3. Write the truth table of negative edge triggered S-R flip-flop and J-K flip-flop.

S-R Flip-flop Truth Table

R
C
S
Q

0
0
Q
1

0
0
0

1
1
1

1
X
J-K Flip-flop Truth Table
C

J
0
0
1
1

Q
Q
1
0
X

0
1
0
1

Q
0
1
1

Q
1
0
1

Comments
Hold
Reset
Set
Invalid
Commen
ts
Hold
Reset
Set
Toggle

4. If the waveforms in figure 4 are applied to an active-LOW input S-R latch, draw the resulting
Q output waveforms in relation to the inputs. Assume that Q starts LOW.

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5. For a gated S-R latch, determine the Q and Q outputs for the inputs in figure 5. Assume Q
starts LOW.

6. For a gated D latch, the waveforms shown in figure 6 are observed on its inputs. Draw
timing diagram showing the output waveform you would expect to see at Q if the latch is
initial RESET.

7. For a positive edge-triggered J-K flip-flop with inputs as shown in figure 7 determine the Q
output relative to the clock. Assume that Q starts LOW.

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8. Two edge triggered S-R flip-flop are shown in figure 7. If the inputs are as shown, draw the
Q outputs of each flip-flop relative to the clock, and explain the difference between the two.
The flip-flops are initially RESET.

9. The circuit of Figure 9 (a) contains a D latch and two T flip-flop. Complete the timing
diagram at Figure 9 (b) by drawing the waveform of signals Q 0, Q1 and Q2. Assume that Q0,
Q1, and Q2 are initially RESET.

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10. The circuit of Figure 10 contains a D latch, a positive-edge-triggered and a negative edgetriggered D flip-flop. Sketch the waveform of signals y1, y2 and y3.

y1
x

y2
D

C
Q

y3

clock

Clock

y1

y2

y3

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