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BSIM464 Manual PDF
BSIM464 Manual PDF
4 MOSFET Model
-Users Manual
Developers:
BSIM4.6.4 Developers:
Professor Chenming Hu (project director), UC Berkeley
Professor Ali M. Niknejad(project director), UC Berkeley
Wenwei Yang, UC Berkeley
Darsen Lu, UC Berkeley
Technical Support:
Tanvir Hasan Morshed: morshedt@eecs.berkeley.edu
BSIM4.6.4 Manual Copyright 2009 UC Berkeley
Acknowledgement:
The development of BSIM4.6.4 benefited from the input of many BSIM
users, especially the Compact Model Council (CMC) member companies.
The developers would like to thank Xingming Liu and Jushan Xie at
Cadence, Joddy Wang, Robin Tan, Jane Xi and Weidong Liu at Synopsys,
Ben Gu at Freescale, James Ma at ProPlus Design, Joe Watts at IBM,
Geoffrey Coram at Analog Device, Wei-hung Chen at UC Berkeley, for
their valuable assistance in identifying the desirable modifications and
testing of the new model.
The BSIM project is partially supported by SRC and CMC.
Contents
Chapter 1: Effective Oxide Thickness, Channel Length and Channel Width .................... 1
1.1 Gate Dielectric Model ............................................................................................... 3
1.2 Poly-Silicon Gate Depletion...................................................................................... 4
1.3 Effective Channel Length and Width........................................................................ 7
Chapter 2: Threshold Voltage Model ............................................................................... 10
2.1 Long-Channel Model With Uniform Doping.......................................................... 10
2.2 Non-Uniform Vertical Doping ................................................................................ 11
2.3 Non-Uniform Lateral Doping: Pocket (Halo) Implant............................................ 13
2.4 Short-Channel and DIBL Effects ............................................................................ 14
2.5 Narrow-Width Effect............................................................................................... 16
Chapter 3: Channel Charge and Subthreshold Swing Models.......................................... 19
3.1 Channel Charge Model............................................................................................ 19
3.2 Subthreshold Swing n.............................................................................................. 22
Chapter 4: Gate Direct Tunneling Current Model ............................................................ 24
4.1 Model Selectors....................................................................................................... 25
4.2 Voltage Across Oxide Vox ....................................................................................... 25
4.3 Equations for Tunneling Currents ........................................................................... 26
4.3.1 Gate-to-Substrate Current (Igb = Igbacc + Igbinv)................................................. 26
4.3.2 Gate-to-Channel Current (Igc0) and Gate-to-S/D (Igs and Igd) ........................... 27
4.3.3. Partition of Igc .................................................................................................. 28
Chapter 5: Drain Current Model ....................................................................................... 30
5.1 Bulk Charge Effect.................................................................................................. 30
5.2 Unified Mobility Model .......................................................................................... 30
5.3 Asymmetric and Bias-Dependent Source/ Drain Resistance Model....................... 33
5.4 Drain Current for Triode Region............................................................................. 35
5.5 Velocity Saturation.................................................................................................. 36
5.6 Saturation Voltage Vdsat ........................................................................................... 37
5.6.1 Intrinsic case ..................................................................................................... 37
5.6.2 Extrinsic Case ................................................................................................... 37
BSIM4.6.4 Manual Copyright 2009 UC Berkeley
5.6.3Vdseff Formulation............................................................................................... 38
5.7 Saturation-Region Output Conductance Model ...................................................... 38
5.7.1 Channel Length Modulation (CLM)................................................................. 40
5.7.2 Drain-Induced Barrier Lowering (DIBL) ......................................................... 40
5.7.3 Substrate Current Induced Body Effect (SCBE) .............................................. 41
5.7.4 Drain-Induced Threshold Shift (DITS) by Pocket Implant ............................. 43
5.8 Single-Equation Channel Current Model................................................................ 43
5.9 New Current Saturation Mechanisms: Velocity Overshoot and Source End Velocity
Limit Model................................................................................................................... 44
A.4 Parameters for Asymmetric and Bias-Dependent Rds Model ............................... 142
A.5 Impact Ionization Current Model Parameters ...................................................... 143
A.6 Gate-Induced Drain Leakage Model Parameters ................................................. 144
A.7 Gate Dielectric Tunneling Current Model Parameters......................................... 145
A.8 Charge and Capacitance Model Parameters......................................................... 148
A.9 High-Speed/RF Model Parameters....................................................................... 150
A.10 Flicker and Thermal Noise Model Parameters................................................... 153
A.11 Layout-Dependent Parasitic Model Parameters ................................................. 154
A.12 Asymmetric Source/Drain Junction Diode Model Parameters .......................... 155
A.13 Temperature Dependence Parameters ................................................................ 159
A.14 Stress Effect Model Parameters ......................................................................... 161
A.15 Well-Proximity Effect Model Parameters.......................................................... 163
A.16 dW and dL Parameters........................................................................................ 164
A.17 Range Parameters for Model Application .......................................................... 166
A.18 Notes 1-8 ............................................................................................................ 167
Appendix B: Core Parameters ........................................................................................ 169
Appendix C: References ................................................................................................. 170
3.9
X DC V =VDDEOT ,V =V =0
gs
ds
bs
EPSRSUB
(1.1)
Figure 1.2. Charge distribution in a MOSFET with the poly gate depletion effect. The
device is in the strong inversion region.
qNGATE X
=
2 si
poly
(1.2)
(1.3)
where Eox is the electric field in the gate oxide. The gate voltage satisfies
Vgs VFB s = V poly + Vox
(1.4)
where Vox is the voltage drop across the gate oxide and satisfies Vox =
EoxTOXE.
From (1.2) and (1.3), we can obtain
a (Vgs VFB s V poly ) V poly = 0
2
(1.5)
where
a=
EPSROX 2
2q si NGATE TOXE 2
(1.6)
By solving (1.5), we get the effective gate voltage Vgse which is equal to
Vgse
EPSROX 2
q si NGATE TOXE 2
(1.7)
coxe 2
q gate NGATE
(1.8)
(1.9)
Weff =
Wdrawn
+ XW 2dW
NF
(1.10)
Weff ' =
Wdrawn
+ XW 2dW '
NF
(1.11)
The difference between (1.10) and (1.11) is that the former includes bias
dependencies. NF is the number of device fingers. dW and dL are modeled
by
dW = dW '+ DWG Vgsteff + DWB
dW ' = WINT +
s Vbseff s
(1.12)
WL
WW
WWL
+ WWN + WLN WWN
WLN
L
W
L W
dL = LINT +
LL
LW
LWL
+ LWN + LLN LWN
LLN
L
W
L W
WINT represents the traditional manner from which "delta W" is extracted
(from the intercept of straight lines on a 1/Rds~Wdrawn plot). The parameters
DWG and DWB are used to account for the contribution of both gate and
substrate bias effects. For dL, LINT represents the traditional manner from
which "delta L" is extracted from the intercept of lines on a Rds~Ldrawn plot).
The remaining terms in dW and dL are provided for the convenience of the
user. They are meant to allow the user to model each parameter as a function
of Wdrawn, Ldrawn and their product term. By default, the above geometrical
dependencies for dW and dL are turned off.
BSIM4.6.4 Manual Copyright 2009 UC Berkeley
Wdrawn
+ XW 2dW
NF
(1.14)
LLC LWC
LWLC
+ LWN + LLN LWN
LLN
L
W
L W
(1.15)
WLC WWC
WWLC
+ WWN + WLN WWN
WLN
L
W
L W
(1.16)
Wactive =
dL = DLC +
dW = DWC +
(1.13)
The meanings of DWC and DLC are different from those of WINT and LINT
in the I-V model. Unlike the case of I-V, we assume that these dimensions
are bias- dependent. The parameter Leff is equal to the source/drain to gate
overlap length plus the difference between drawn and actual POLY CD due
to processing (gate patterning, etching and oxidation) on one side.
The effective channel length Leff for the I-V model does not necessarily carry
a physical meaning. It is just a parameter used in the I-V formulation. This
Leff is therefore very sensitive to the I-V equations and also to the conduction
characteristics of the LDD region relative to the channel region. A device
with a large Leff and a small parasitic resistance can have a similar current
drive as another with a smaller Leff but larger Rds.
The Lactive parameter extracted from capacitance is a closer representation of
the metallurgical junction length (physical length). Due to the graded
source/drain junction profile, the source to drain length can have a very
BSIM4.6.4 Manual Copyright 2009 UC Berkeley
(1.17)
Wdrawn
WLC WWC
WWLC
Note: Any compact model has its validation limitation, so does BSIM4.
BSIM4 is its own valid designation limit which is larger than the warning
limit, shown in following table. For users reference, the fatal limitation in
BSIM4 is also shown.
Parameter name
Designed
Limitation(m)
Warning
Limitation(m)
Fatal
Limitation(m)
Leff
LeffCV
Weff
WeffCV
Toxe
Toxp
Toxm
1e-8
1e-8
1e-7
1e-7
5e-10
5e-10
5e-10
1e-9
1e-9
1e-9
1e-9
1e-10
1e-10
1e-10
0
0
0
0
0
0
0
s Vbs s
(2.1)
where VFB is the flat band voltage, VTH0 is the threshold voltage of the
long channel device at zero substrate bias, and is the body bias coefficient
given by
=
2q si N substrate
Coxe
(2.2)
(2.3)
10
(2.4)
VTH 0 = VFB + s + s
qD0
qD
+ K1NDEP s Vbs 1 s Vbs
si
Coxe
(2.5)
s Vbs s
(2.6)
with a definition of
s = 0.4 +
k BT NDEP
ln
q
ni
(2.7)
D1 = D10 + D11 =
X dep 0
( N ( x ) NDEP ) dx + ( N ( x ) NDEP ) dx
(2.8)
(2.9)
X dep 0
X dep
X dep 0
X dep
X dep 0
11
(2.10)
s Vbs s K 2 Vbs
(2.11)
k BT NDEP
ln
+ PHIN
q
ni
where
PHIN = qD10 si
(2.12)
VTH0, K1, K2, and PHIN are implemented as model parameters for model
flexibility. Appendix A lists the model selectors and parameters. Detail
information on the doping profile is often available for predictive modeling.
Like BSIM3v3, BSIM4 allows K1 and K2 to be calculated based on such
details as NSUB, XT, VBX, VBM, etc. (with the same meanings as in
BSIM3v3):
(2.13)
K1 = 2 2K 2 s VBM
K2 =
( 1 2 ) (
2 s
s VBX s
(2.14)
s VBM s + VBM
where 1 and 2 are the body bias coefficients when the substrate doping
concentration
are
equal
to
NDEP
and
NSUB,
respectively:
1 =
2q si NDEP
Coxe
(2.15)
2 =
2q si NSUB
Coxe
(2.16)
12
qNDEP XT 2
= s VBX
2 si
s Vbs s 1 +
LPEB
K 2 Vbs
Leff
(2.18)
LPE 0
+ K 1 1 +
1 s
L
eff
1 e Vds / vt Leff
Vth ( DITS ) = nvt ln
Leff + DVTP0 1 + e DVTP1Vds
(2.19)
For Vds of interest, the above equation is simplified and implemented as for
tempMod = 1:
Leff
Vth ( DITS ) = nvt ln
Leff + DVTP 0 1 + e DVTP1Vds
(2.20)
for tempMod = 2:
13
Leff
Vth ( DITS ) = nvt ln
Leff + DVTP 0 1 + e DVTP1Vds
(2.21)
Note: when tempMod =2, drain-induced threshold voltage shift (DITS) due
to pocket implant has no temperature dependence, so nominal temperature
(TNOM) is used as Eq.(3.22). when tempMod=0 or 1, Eq.(3.21) is used.
Leff
Vth ( DITS ) = nvtnom ln
Leff + DVTP 0 1 + e DVTP1Vds
(2.22)
(2.23)
k BT NDEP NSD
ln
q
ni 2
(2.24)
where NSD is the doping concentration of source/drain diffusions. The shortchannel effect coefficient th(Leff) in (2.23) has a strong dependence on the
channel length given by
14
(2.25)
0.5
cosh
( ) 1
Leff
lt
(2.26)
si TOXE X dep
EPSROX
(2.27)
2 si ( s Vbs )
qNDEP
Xdep is larger near the drain due to the drain voltage. Xdep /represents
the
average depletion width along the channel.
Note that in BSIM3v3 and [4], th(Leff) is approximated with the form of
Leff
2lt
th ( Leff ) = exp
Leff
+ 2 exp
lt
(2.28)
which results in a phantom second Vth roll-up when Leff becomes very small
(e.g. Leff < LMIN). In BSIM4, the function form of (2.25) is implemented
with no approximation.
To increase the model flexibility for different technologies, several
parameters such as DVT0, DVT1, DVT2, DSUB, ETA0, and ETAB are
introduced, and SCE and DIBL are modeled separately.
To model SCE, we use
th ( SCE ) =
0.5 DVT 0
cosh DVT1
Leff
lt
) 1
(2.29)
(2.30)
with lt changed to
BSIM4.6.4 Manual Copyright 2009 UC Berkeley
15
si TOXE X dep
(1 + DVT 2 Vbs )
EPSROX
(2.31)
0.5
cosh DSUB
Leff
lt 0
) 1
(2.32)
(2.33)
si TOXE X dep 0
(2.34)
EPSROX
with
X dep 0 =
2 si s
qNDEP
(2.35)
DVT1 is basically equal to 1/. DVT2 and ETAB account for substrate bias
effects on SCE and DIBL, respectively.
= 3
TOXE
s
Weff
(2.36)
16
(2.37)
TOXE
s
Weff '+ W 0
In addition, we must consider the narrow width effect for small channel
lengths. To do this we introduce the following
Vth ( Narrow- width2 ) =
0.5 DVT 0W
cosh DVT 1W
) 1
(2.38)
(Vbi s )
ltw =
EPSROX
(2.39)
(1 + DVT 2W Vbs )
1+
LPEB
K 2 oxVbseff
Leff
LPE 0
TOXE
+ K1ox 1 +
1 s + ( K 3 + K 3B Vbseff )
s
Leff
Weff '+ W 0
DVT 0W
DVT 0
(V )
0.5
+
s
cosh DVT 1W Leff Weff ' 1 cosh DVT 1 Leff 1 bi
ltw
lt
Leff
0.5
.ln
ETA
+
E
0
TAB
V
V
nv
(
)
bseff
ds
t
Leff
Leff + DVTP 0. 1 + e DVTP1VDS
cosh DSUB lt 0 1
17
TOXE
TOXM
(2.41)
TOXE
TOXM
(2.42)
and
K 2 ox = K 2
Note that all Vbs terms are substituted with a Vbseff expression as shown in
(2.43). This is needed in order to set a low bound for the body bias during
simulations since unreasonable values can occur during SPICE iterations if
this expression is not introduced.
Vbseff = Vbc + 0.5 (Vbs Vbc 1 ) +
(Vbs Vbc 1 )
41 Vbc
(2.43)
where 1 = 0.001V, and Vbc is the maximum allowable Vbs and found from
dVth/dVbs= 0 to be
(2.44)
K12
Vbc = 0.9 s
4 K 22
For positive Vbs, there is need to set an upper bound for the body bias as:
(2.45)
'
1 +
Vbseff = 0.95 s 0.5 0.95 s Vbseff
( 0.95
'
Vbseff
1 ) + 41.0.95 s
18
VOFFL
Leff
(3.1)
VOFFL
Leff
(3.2)
where
(3.3)
A unified charge density model considering the charge layer thickness effect
is derived for both subthreshold and inversion regions as
Qch 0 = Coxeff Vgsteff
(3.4)
Coxe Ccen
Coxe + Ccen
with Ccen =
si
(3.5)
X DC
19
(3.6)
2TOXP
0.7 BDOS
Here, ADOS and BDOS are the parameters to describe the density of states
in new materials and used to control the charge centroid. In the above
equations, Vgsteff the effective (Vgse-Vth) used to describe the channel charge
densities from subthreshold to strong inversion, is modeled by
Vgsteff
m (Vgse Vth )
nvt ln 1 + exp
nvt
=
(1 m ) (Vgse Vth ) Voff
2 s
exp
m + nCoxe
qNDEP si
nvt
(3.7)
'
where
m = 0.5 +
arctan ( MINV )
(3.8)
MINV is introduced to improve the accuracy of Gm, Gm/Id and Gm2/Id in the
moderate inversion region. To account for the drain bias effect, The y
dependence has to be included in (3.4). Consider first the case of strong
inversion
Qchs ( y ) = Coxeff (Vgse Vth AbulkVF ( y ) )
(3.9)
VF(y) stands for the quasi-Fermi potential at any given point y along the
channel with respect to the source. (3.9) can also be written as
Qchs ( y ) = Qchs 0 + Qchs ( y )
(3.10)
20
nvt
(3.11)
Taylor expansion of (3.11) yields the following (keeping the first two terms)
A V ( y)
Qchsubs ( y ) = Qchsubs 0 1 bulk F
nvt
(3.12)
(3.13)
AbulkVF ( y )
nvt
(3.14)
Qchs ( y ) Qchsubs ( y )
Qchs ( y ) + Qchsubs ( y )
(3.15)
VF ( y )
Qch 0
Vb
(3.16)
21
Vgsteff + 2vt
(3.17)
Abulk
Vb
(3.18)
V
Vgs Vth Voff '
I ds = I 0 1 exp ds exp
nvt
vt
where
I0 =
W
L
(3.20)
q si NDEP 2
vt
2 s
vt is the thermal voltage and equal to kBT/q. Voff = VOFF + VOFFL / Leff is
the offset voltage, which determines the channel current at Vgs = 0. In (3.19),
n is the subthreshold swing parameter. Experimental data shows that the
subthreshold swing is a function of channel length and the interface state
density. These two mechanisms are modeled by the following
n = 1 + NFACTOR
Cdep
Coxe
(3.21)
CdscTerm + CIT
Coxe
0.5
cosh DVT1
Leff
lt
) 1
(3.22)
22
23
As the gate oxide thickness is scaled down to 3nm and below, gate leakage
current due to carrier direct tunneling becomes important. This tunneling
happens between the gate and silicon beneath the gate oxide. To reduce the
tunneling current, high-k dielectrics are being studied to replace gate oxide.
In order to maintain a good interface with substrate, multi-layer dielectric
stacks are being proposed. The BSIM4 gate tunneling model has been shown
to work for multi-layer gate stacks as well. The tunneling carriers can be
either electrons or holes, or both, either from the conduction band or valence
band, depending on (the type of the gate and) the bias regime.
In BSIM4, the gate tunneling current components include the tunneling
current between gate and substrate (Igb), and the current between gate and
channel (Igc), which is partitioned between the source and drain terminals by
Igc = Igcs + Igcd. The third component happens between gate and source/drain
diffusion regions (Igs and Igd). Figure 4.1 shows the schematic gate tunneling
current flows.
24
(4.1)
(4.2)
(4.1) and (4.2) are valid and continuous from accumulation through
depletion to inversion. Vfbzb is the flat-band voltage calculated from zero-bias
Vth by
V fbzb = Vth
s K1 s
(4.3)
and
(V
fbzb
(4.4)
25
(4.5)
TOXE
NTOX
(4.6)
1
TOXE 2
Vgb V fbzb
(4.7)
(4.8)
26
EIGBINV
V
Vaux = NIGBINV vt log 1 + exp oxdepinv
NIGBINV vt
(4.9)
(4.10)
where A = 4.97232 A/V2 for NMOS and 3.42537 A/V2 for PMOS, B =
7.45669e11 (g/F-s2)0.5 for NMOS and 1.16645e12 (g/F-s2)0.5 for PMOS, and
for igcMod = 1:
Vgse VTH 0
Vaux = NIGC vt log 1 + exp
NIGC vt
(4.11)
for igcMod = 2:
Vgse VTH
Vaux = NIGC vt log 1 + exp
NIGC vt
(4.12)
Igs and Igd -- Igs represents the gate tunneling current between the gate and
the source diffusion region, while Igd represents the gate tunneling current
between the gate and the drain diffusion region. Igs and Igd are determined by
ECB for NMOS and HVB for PMOS, respectively.
I gs = Weff DLCIG A ToxRatioEdge Vgs Vgs '
(4.13)
exp B TOXE POXEDGE ( AIGS BIGS Vgs ' ) (1 + CIGS Vgs ' )
and
27
where A = 4.97232 A/V2 for NMOS and 3.42537 A/V2 for PMOS, B =
7.45669e11 (g/F-s2)0.5 for NMOS and 1.16645e12 (g/F-s2)0.5 for PMOS, and
ToxRatioEdge
TOXREF
TOXE POXEDGE
Vgs ' =
(V
Vgd ' =
(V
NTOX
(4.15)
(TOXE POXEDGE )
V fbsd ) + 1.0e 4
(4.16)
V fbsd ) + 1.0e 4
(4.17)
gs
gd
Vfbsd is the flat-band voltage between gate and S/D diffusions calculated as
If NGATE > 0.0
V fbsd =
k BT
NGATE
log
+ VFBSDOFF
q
NSD
(4.18)
(4.19)
and
28
(4.20)
Vdseff
B TOXE
1
2
Vgsteff 2 Vgsteff
(4.21)
29
Abulk
A0 Leff
L
2
XJ
X
dep
eff
= 1 + F doping
Leff
1 AGS V
gsteff
Leff + 2 XJ X dep
1
2
B0 1 + KETA Vbseff
+
Weff '+ B1
where the second term on the RHS is used to model the effect of nonuniform doping profiles
F doping =
+ K 2 ox K 3B
TOXE
s
Weff '+ W 0
(5.2)
Note that Abulk is close to unity if the channel length is small and increases as
the channel length increases.
30
QB + Qn / 2
(5.3)
si
The physical meaning of Eeff can be interpreted as the average electric field
experienced by the carriers in the inversion layer. The unified formulation of
mobility is then given by
eff =
0
1 + ( Eeff / E0 )
(5.4)
v
For an NMOS transistor with n-type poly-silicon gate, (6.3) can be rewritten
in a more useful form that explicitly relates Eeff to the device parameters
Eeff
Vgs + Vth
(5.5)
6TOXE
31
U0 f (Leff )
2
Vgsteff + 2Vth
Vgsteff + 2Vth
Vth TOXE
1+ (UA +UCVbseff )
+UB
+UD
2
TOXE
TOXE
Vgsteff + 2 Vth + 0.0001
mobMod = 1
(5.7)
eff =
U0 f (Leff )
2
Vgsteff + 2Vth
Vgsteff + 2Vth
Vth TOXE
1+ UA
+UB
(1+UC Vbseff ) +UD
2
TOXE
TOXE
Vgsteff + 2 Vth + 0.0001
mobMod = 2
(5.8)
eff =
U0 f ( Leff )
EU
1+ (UA+UC Vbseff )
+UD
2
TOXE
V
V
+
2
+
0.0001
th
gsteff
LP
(5.9)
mrtlMod=1
A new expression of the vertical field in channel is adopted:
(5.10)
BSIM4.6.4 Manual Copyright 2009 UC Berkeley
32
Eeff =
3.9
EPSRSUB
U 0 f ( Leff )
(5.11)
Vth EOT
V
2
0.00001
+
+
th
gsteff
mobMod=1
eff =
U 0 f ( Leff )
(5.12)
Vth EOT
V
+
+
2
0.00001
th
gsteff
U 0. f (Leff
V gsteff + C 0 .(VTH 0 V fb S )
1 + (UA + UC.Vbseff )
6.TOXE
(5.13)
EU
UD
UCS
Here, Vgsteff,Vth=Vgsteff(Vgse=Vth,Vds=Vbs=0).
33
Rds (V ) =
1
PRWB s Vbseff s + 1 + PRWG V
gsteff
(1e6 W )
(5.14)
WR
effcj
Rd (V ) =
1
Rs (V ) =
1
(5.15)
(1e6 W )
effcj
WR
NF
(5.16)
(1e6 W )WR NF
effcj
34
The diffusion source/drain resistance Rsdiff and Rddiff models are given in the
chapter of layout-dependence models.
dVF ( y )
dy
(5.17)
eff
1+
(5.18)
Ey
Esat
E
Vb
dy
1+ y
Esat
(5.19)
35
I ds 0
V
W eff Qch 0Vds 1 ds
2Vb
=
V
L 1 + ds
Esat L
(5.20)
I ds 0
R I
1 + ds ds 0
Vds
(5.21)
eff E
1 + E Esat
= VSAT
E < Esat
(5.22)
E Esat
where Esat corresponds to the critical electrical field at which the carrier
velocity becomes saturated. In order to have a continuous velocity model at
E = Esat, Esat must satisfy
Esat =
2VSAT
eff
(5.23)
36
(5.24)
(5.25)
b b 2 4ac
2a
where
1
a = Abulk 2Weff VSATCoxe Rds + Abulk 1
(5.26)
2
(Vgsteff + 2vt ) 1 + Abulk Esat Leff
b =
(5.27)
(5.28)
= A1Vgsteff + A2
(5.29)
37
(Vdsat Vds )
+ 4 Vdsat
(5.30)
38
The channel current is a function of the gate and drain voltage. But the
current depends on the drain voltage weakly in the saturation region. In the
following, the Early voltage is introduced for the analysis of the output
resistance in the saturation region:
I ds (Vgs , Vds ) = I dsat (Vgs , Vdsat ) +
Vds
I ds (Vgs ,Vds )
Vdsat
Vd
dVd
(5.31)
Vds 1
VA = I dsat
Vd
(5.32)
39
I ds (Vgs , Vds ) L
= I dsat
L
Vd
(5.33)
(5.34)
where
Cclm =
Vgsteff
1
F 1 + PVAG
PCLM
Esat Leff
Rds I dso
V
1+
Leff + dsat
Vdseff
Esat
litl
(5.35)
and the F factor to account for the impact of pocket implant technology is
(5.36)
F=
1 + FPROUT
Leff
Vgsteff + 2vt
siTOXE XJ
(5.37)
EPSROX
40
VADIBL
I ds (Vgs , Vds ) V
= I dsat
th
Vth
Vd
(5.38)
Vgsteff + 2vt
AbulkVdsat
1
) AbulkVdsat + Vgsteff + 2vt
Vgsteff
1 + PVAG
Esat Leff
where rout has a similar dependence on the channel length as the DIBL
effect in Vth, but a separate set of parameters are used:
rout =
PDIBLC1
2 cosh
DROUT Leff
lt 0
)2
+ PDIBLC 2
(5.40)
41
(5.41)
B litl
Ai
I ds (Vds Vdsat ) exp i
Bi
Vds Vdsat
Parameters Ai and Bi are determined from measurement. Isub affects the drain
current in two ways. The total drain current will change because it is the sum
of the channel current as well as the substrate current. The total drain current
can now be expressed as follows
Vds Vdsat
Bi
Ai
exp
Bi litl
Vds Vdsat
(5.42)
The Early voltage due to the substrate current VASCBE can therefore be
calculated by
VASCBE =
B litl
Bi
exp i
Ai
Vds Vdsat
(5.43)
PSCBE1 litl
PSCBE 2
exp
Leff
Vds Vdsat
(5.44)
42
1
F 1 + (1 + PDITSL Leff ) exp ( PDITSD Vds )
PDITS
(5.45)
I ds 0 NF
I ds 0
1 + RVdsdseff
V
1
ln A
1 +
Cclm VAsat
Vds V dseff
1 +
VADIBL
(5.46)
Vds V dseff
1 +
VADITS
Vds V dseff
1 +
VASCBE
(5.47)
where VAsat is
VAsat
gsteff
t
=
2
Rds vsatCoxeWeff Abulk 1 +
(5.48)
VAsat is the Early voltage at Vds = Vdsat. VAsat is needed to have continuous
drain current and output resistance expressions at the transition point
between linear and saturation regions.
BSIM4.6.4 Manual Copyright 2009 UC Berkeley
43
E
E x
)=
E
1 + E / Ec
(1 +
E
E x
(5.49)
This relationship is then substituted into (6.45) and the new current
expression including the velocity overshoot effect is obtained:
I DS , HD
V
I DS 1 + dseff
L E
eff sat
=
V
1 + dseffOV
Leff Esat
(5.50)
where
E satOV
Vds Vdseff
1 +
Esat litl
LAMBDA
= Esat 1 +
1 +
Esat litl
+
1
(5.51)
44
I DS , HD
(5.52)
Wqs
where qs is the source end inversion charge density. Source end velocity
limit gives the highest possible velocity which can be given through ballistic
transport as:
vsBT =
1 r
VTL
1+ r
(5.53)
Leff
XN Leff + LC
XN 3.0
(5.54)
The real source end velocity should be the lower of the two, so a final
Unified current expression with velocity saturation, velocity overshoot and
source velocity limit can be expressed as :
I DS =
(5.55)
I DS , HD
1 + ( vsHD / vsBT )2 MM
1/ 2 MM
where MM=2.0.
45
BETA0
ds Vdseff ) exp
V V
ds dseff
(V
I dsNoSCBE
(6.1)
V Vds V dseff
I ds 0 NF
1
1+
ln A 1 +
Rds I ds 0
VADIBL
1 + Vdseff Cclm VAsat
Vds V dseff
1 +
VADITS
(6.2)
(6.3)
3 Toxe
Vdb3
3 Toxe BGIDL
exp
46
(6.4)
3 Toxe
Vsb3
3 Toxe BGISL
exp
where AGIDL, BGIDL, CGIDL and EGIDL are model parameters for the
drain side and AGISL, BGISL, CGISL and EGISL are the model parameters
for the source side. They are explained in Appendix A. CGIDL and CGISL
account for the body-bias dependence of IGIDL and IGISL respectively. WeffCJ
and Nf are the effective width of the source/drain diffusions and the number
of fingers. Further explanation of WeffCJ and Nf can be found in the chapter of
the layout-dependence model.
mtrlMod=1
In this case, the work function difference (Vfbsd) between source/drain and
channel could be modeled as follows:
V fbsd = PHIG ( EASUB +
Eg 0
NSD
Eg 0
BSIM 4typy MIN
, vt ln
2
ni
2
(6.5)
BGIDL
EOT
Vdb3
3.9
exp
3
Vds Vgse EGIDL + V fbsd CGIDL + Vdb
(6.6)
47
BGISL
EOT
Vdb3
3.9
exp
3
Vds Vgse EGISL + V fbsd CGISL + Vdb
(6.7)
48
Capacitance Model
49
Capacitance Model
50
Capacitance Model
The accumulation charge and the substrate charge are associated with the
substrate while the channel charge comes from the source and drain
terminals
Qg = (Qsub + Qinv + Qacc )
Qb = Qacc + Qsub
Q = Q + Q
s
d
inv
(7.1)
The substrate charge can be divided into two components: the substrate
charge at zero source-drain bias (Qsub0), which is a function of gate to
substrate bias, and the additional non-uniform substrate charge in the
presence of a drain bias (Qsub). Qg now becomes
Qg = (Qinv + Qacc + Qsub 0 + Qsub )
(7.2)
The total charge is computed by integrating the charge along the channel.
The threshold voltage along the channel is modified due to the non-uniform
substrate charge by
Vth ( y ) = Vth (0) + ( Abulk 1)Vy
(7.3)
Lactive
Lactive
Lactive
Lactive
Lactive
Lactive
Qb = Wactive
0 qb dy = WactiveCoxe 0 Vth VFB s + ( Abulk 1)Vy dy
(7.4)
dVy
(7.5)
Ey
where Ey is expressed in
51
Capacitance Model
I ds =
(7.6)
All capacitances are derived from the charges to ensure charge conservation.
Since there are four terminals, there are altogether 16 components. For each
component
Cij =
Qi
V j
(7.7)
C = C
ij
ij
(7.8)
=0
Lactive
Vgsteff ,CV
(7.9)
Abulk
52
Capacitance Model
Vdsat ,CV =
(7.10)
Vgsteff ,CV
CLC
Abulk 1 +
Lactive
CLE
NOFF nvt
(7.11)
Model parameters CLC and CLE are introduced to consider the effect of
channel-length modulation. Abulk for the capacitance model is modeled by
A0 Leff
B 0
1
Abulk = 1 + F doping
+
Leff + 2 XJ X dep Weff '+ B1 1 + KETA Vbseff
(7.12)
where
F doping =
+ K 2 ox K 3B
TOXE
s
Weff '+ W 0
(7.13)
cvchargeMod=1
In order to improve the predictive modeling in the subthreshold region, a
new threshold voltage for C-V is introduced as following:
VgsteffCV =
m* + nCoxe
m* (Vgse Vth )
nvt ln 1 + exp
nvt
exp
qNDEP Si
nvt
m* = 0.5 +
arctan ( MINVCV )
(7.14)
(7.15)
VOFFCVL
Leff
(7.16)
53
Capacitance Model
Note: The default value of cvchargeMod is zero to keep the backward
compatibility.
7.2.3 Single Equation Formulation
Traditional MOSFET SPICE capacitance models use piece-wise equations.
This can result in discontinuities and non-smoothness at transition regions.
The following describes single-equation formulation for charge, capacitance
and voltage modeling in capMod = 1 and 2.
(a) Transition from depletion to inversion region
The biggest discontinuity is at threshold voltage where the inversion
capacitance changes abruptly from zero to Coxe. Concurrently, since the
substrate charge is a constant, the substrate capacitance drops abruptly to
zero at threshold voltage. The BSIM4 charge and capacitance models are
formulated by substituting Vgst with Vgsteff,CV as
Q (Vgst ) = Q (Vgsteff ,CV )
(7.17)
Vgsteff ,CV
(7.18)
Vg ,d , s ,b
(V
fbzb
(7.19)
where
54
Capacitance Model
V fbzb = Vth
(7.20)
s K1 s
(7.21)
7.2.4.Charge partitioning
The inversion charges are partitioned into Qinv = Qs + Qd. The ratio of Qd to
Qs is the charge partitioning ratio. Existing charge partitioning schemes are
0/100, 50/50 and 40/60 (XPART = 1, 0.5 and 0).
50/50 charge partition
This is the simplest of all partitioning schemes in which the inversion
charges are assumed to be contributed equally from the source and drain
terminals.
40/60 charge partition
This is the most physical model of the three partitioning schemes in which
the channel charges are allocated to the source and drain terminals by
assuming a linear dependence on channel position y.
55
Capacitance Model
Lactive
y
Qs = Wactive qc 1
Lactive
0
Lactive
y
Q
W
dy
=
active qc
d
Lactive
0
(7.22)
dy
56
Capacitance Model
Coxp Ccen
(7.23)
Coxp + Ccen
where
Ccen = si / X DC
(7.24)
57
Capacitance Model
Figure 7.2 Charge-thickness capacitance concept in CTM. Vgse accounts for the poly
depletion effect.
0.25
16
3
TOXP
2 10
(7.25)
where Ldebye is Debye length, and XDC is in the unit of cm and (Vgse - Vbseff VFBeff) / TOXP is in units of MV/cm. For numerical stability, (8.25) is
replaced by (8.26)
X DC = X max
1
X 0 + X 02 + 4 x X max
2
(7.26)
where
X 0 = X max X DC x
(7.27)
58
Capacitance Model
X DC =
(7.28)
2TOXP
0.7 BDOS
Here, the density of states parameters ADOS and BDOS are introduced to
control the charge centroid. Their default values are one.
Through the VFB term, equation (7.28) is found to be applicable to N+ or P+
poly-Si gates and even other future gate materials.
(iii) Body charge thickness in inversion
In inversion region, the body charge thickness effect is modeled by
including the deviation of the surface potential S (bias-dependence) from 2
B [2]
= s 2 B = t ln 1 +
MOIN K1ox 2 t
(7.29)
eff
(7.30)
where
(7.31)
mtrlMod=1
First, TOXP should be iteratively calculated by EOT as follows:
TOXP = EOT
3.9
X DC V =VDDEOT ,V =V =0
gs
ds
bs
EPSRSUB
(7.32)
59
Capacitance Model
X DC =
(7.33)
2TOXP
0.7 BDOS
With the calculated TOXP, XDC could be obtained at different gate voltage.
Now Ccen is equal to EPSRSUB/XDC. The other calculations are as same as
mtrlMod=0.
(7.34)
Qsub = Qg
(7.35)
Qinv = 0
(7.36)
Subthreshold region
Qsub 0
= Wactive LactiveCoxe
1 + 1 +
2
K1ox 2
(7.37)
Qg = Qsub 0
(7.38)
Qinv = 0
(7.39)
Vgs Vth
(7.40)
Abulk '
CLC CLE
Abulk ' = Abulk 1 +
Leff
(7.41)
(7.42)
60
Capacitance Model
Linear region
V
Abulk 'Vds 2
Qg = CoxeWactive Lactive Vgs VFBCV s ds +
A 'V
2
(7.43)
(7.44)
50/50 partitioning:
A 'V
Abulk '2 Vds 2
Qinv = CoxeWactive Lactive Vgs Vth s bulk ds +
A 'V
2
Qs = Qd = 0.5Qinv
(7.45)
(7.46)
40/60 partitioning:
(7.47)
+ 40
A
'
V
bulk
ds
6
8
V V
Abulk 'Vds
gs
th
Qd = CoxeWactive Lactive
+
Abulk 'Vds 2
2
2
12 Vgs Vth 2
Qs = ( Qg + Qb + Qd )
(7.48)
61
Capacitance Model
0/100 partitioning:
2
Vgs Vth A 'V
Abulk 'Vds )
(
bulk
ds
+
Qd = CoxeWactive Lactive
2
4
24
Qs = ( Qg + Qb + Qd )
(7.49)
(7.50)
Saturation region:
V
(7.51)
(1 Abulk ')Vdsat
Qb = CoxeWactive Lactive VFBCV + s Vth +
(7.52)
50/50 partitioning:
1
Qs = Qd = CoxeWactive Lactive (Vgs Vth )
3
(7.53)
40/60 partitioning:
4
CoxeWactive Lactive (Vgs Vth )
15
(7.54)
Qs = ( Qg + Qb + Qd )
(7.55)
Qd =
0/100 partitioning:
Qd = 0
(7.56)
Qs = ( Qg + Qb )
(7.57)
7.4.2 capMod = 1
Qg = ( Qinv + Qacc + Qsub 0 + Qsub )
(7.58)
62
Capacitance Model
Qsub 0
Qs = ( Qg + Qb + Qd )
(7.59)
Qinv = Qs + Qd
(7.60)
(7.61)
Vdsat ,cv =
(7.62)
(7.63)
Vgsteffcv
Abulk '
2
2
A
'
V
1
bulk
cveff
12 Vgsteff ,cv
Qsub
2
1 A '
(1 Abulk ') Abulk 'Vcveff
bulk
= Wactive LactiveCoxe
Vcveff
Abulk 'Vcveff
12
V
,
gsteff
cv
(7.64)
(7.65)
QS = QD =
Wactive LactiveCoxe
2
2
2
Abulk 'Vcveff
2
12 Vgsteff ,cv
(7.66)
Wactive LactiveCoxe
A 'V
3
2
Vgsteff ,cv 3 Vgsteff ,cv Abulk 'Vcveff
2
2
2
+ 2 V
'
( Abulk 'Vcveff
A
V
(
)
gsteff
cv
bulk
cveff
,
2 3
15
3
)
(7.67)
63
Capacitance Model
QD =
Wactive LactiveCoxe
A 'V
3
2
Vgsteff ,cv 3 Vgsteff ,cv Abulk 'Vcveff
2
2
1
+ V
( Abulk 'Vcveff
gsteff , cv ( Abulk 'Vcveff )
2
5
3
)
(7.68)
2
2
12 Vgsteff ,cv
(7.69)
2
2
A
'
V
Wactive LactiveCoxe
3
bulk
cveff
4 Vgsteff ,cv
(7.70)
QS =
Wactive LactiveCoxe
2
7.4.3 capMod = 2
Qacc = Wactive LactiveCoxeff Vgbacc
(7.71)
1
Vgbacc = V0 + V02 + 0.08V fbzb
(7.72)
(7.73)
1
Vcveff = Vdsat V1 + V12 + 0.08Vdsat
2
(7.74)
(V
gsteff ,CV
eff
Vgsteff ,cv
(7.76)
Abulk '
(7.75)
(V
gsteff ,CV
0.001) + Vg
2
(7.77)
(7.78)
64
Capacitance Model
2
1 A '
Vcveff
A 'V
2
12 Vgsteff ,cv bulk cveff
(7.79)
(7.80)
50/50 partitioning:
(7.81)
Wactive LactiveCoxeff
Abulk '2 Vcveff
1
Vgsteff ,cv Abulk 'Vcveff +
QS = QD =
Abulk 'Vcveff
2
2
12 (Vgsteff ,cv )
eff
2
40/60 partitioning:
(7.82)
QS =
Wactive LactiveCoxeff
A 'V
3
2
( Abulk 'Vcveff
'
(
)(
)
,
gsteff
cv
bulk
cveff
2 3
15
3
)
65
Capacitance Model
(7.83)
QD =
Wactive LactiveCoxeff
A 'V
3
2
5
2
5
3
)
0/100 partitioning:
(7.84)
QS =
Wactive LactiveCoxeff
2
2
2
12 Vgsteff ,cv
(7.85)
2
2
Wactive LactiveCoxeff
A
'
V
3
bulk
cveff
4 (Vgsteff ,cv )
eff
2
66
Capacitance Model
CF =
2 EPSROX 0
4.0e 7
log 1 +
TOXE
(7.86)
67
Capacitance Model
Qoverlap , s
Wactive
(7.87)
4Vgs ,overlap
CKAPPAS
CGSO Vgs + CGSL Vgs Vgs ,overlap
1 + 1
2
CKAPPAS
Vgs ,overlap =
1
Vgs + 1 (Vgs + 1 )2 + 41
2
1 = 0.02V
(7.88)
(7.89)
= CGDO Vgd
4Vgd ,overlap
CKAPPAD
+ CGDL Vgd Vgd ,overlap
1 + 1
2
CKAPPAD
Vgd ,overlap =
1
Vgd + 1 (Vgd + 1 )2 + 41
2
1 = 0.02V
(7.90)
(7.91)
68
Capacitance Model
Qoverlap , s = Wactive CGSO Vgs
(7.92)
(7.93)
(7.94)
69
TBGASUB Tnom 2
Tnom + TBGBSUB
(8.1)
70
Tnom
ni = NI 0SUB
300.15
3/ 2
Eg = BG 0SUB
TBGASUB 300.152
300.15 + TBGBSUB
Eg (300.15) Eg 0
exp
2vt
TBGASUB Temp 2
Temp + TBGBSUB
(8.2)
(8.3)
(8.4)
(8.5)
2TOXP
0.7 BDOS
Here, the density of states parameters ADOS and BDOS are introduced to
control the charge centroid.
3.9
X DC V =VDDEOT ,V =V =0
gs
ds
bs
EPSRSUB
(8.6)
71
Eg 0
NSD
Eg 0
BSIM 4typy MIN
, vt ln
2
ni
2
(8.7)
This new flat band equation improves the GIDL/GISL models as following:
Vds Vgse EGIDL + V fbsd
EPSRSUB
EOT
3.9
EPSRSUB
BGIDL
EOT
Vdb3
3.9
exp
3
Vds Vgse EGIDL + V fbsd CGIDL + Vdb
(8.8)
BGISL
EOT
Vdb3
3.9
exp
3
Vds Vgse EGISL + V fbsd CGISL + Vdb
(8.9)
72
3.9
EPSRSUB
U 0 f ( Leff )
Vth EOT
2
V
0.00001
+
+
th
gsteff
(8.11)
2
mobMod=1
eff =
U 0 f ( Leff )
Vth EOT
2
V
0.00001
+
+
th
gsteff
(8.12)
2
73
High-Speed/RF Models
These
two
models
both
work
with
multi-finger
configuration. The substrate resistance model does not include any geometry
dependence.
74
High-Speed/RF Models
MOSFET channel region is analogous to a bias-dependent RC distributed
transmission line (Figure 10. 1a). In the Quasi-Static (QS) approach, the gate
capacitor node is lumped with the external source and drain nodes (Figure
10. 1b). This ignores the finite time for the channel charge to build-up. One
way to capture the NQS effect is to represent the channel with n transistors
in series (Figure 10.1c), but it comes at the expense of simulation time. The
BSIM4 charge-deficit NQS model uses Elmore equivalent circuit to model
channel charge build-up, as illustrated in Figure 9.1d.
75
High-Speed/RF Models
source icheq(t) represents the equilibrium channel charging effect. The
capacitor C is to be the value of Cfact (with a typical value of Farad [11]) to
improve simulation accuracy. Qdef now becomes
Qdef ( t ) = Vdef C fact
(9.1)
Considering both the transport and charging component, the total current
related to the terminals D, G and S can be written as
iD,G , S (t ) = I D,G , S ( DC ) +
Qd , g , s (t )
(9.2)
(9.3)
and
Qd , g , s (t )
t
Qcheq (t ) Qdef (t )
t
(9.4)
76
High-Speed/RF Models
Qd , g , s (t )
t
= D, G, S xpart
(9.5)
Qdef (t )
where D,G,Sxpart are charge deficit NQS channel charge partitioning number
for terminals D, G and S, respectively; Dxpart + Sxpart = 1 and Gxpart = -1.
The transit time is equal to the product of Rii and WeffLeffCoxe, where Rii is
the intrinsic-input resistance [12] given by
I
W C kT
1
= XRCRG1 ds + XRCRG 2 eff eff oxeff B
Rii
qLeff
Vdseff
(9.6)
where Coxeff is the effective gate dielectric capacitance calculated from the
DC model. Note that Rii in (9.6) considers both the drift and diffusion
componets of the channel conduction, each of which dominates in inversion
and subthreshold regions, respectively.
9.1.2 AC Model
Similarly, the small-signal AC charge-deficit NQS model can be turned on
by setting acnqsMod = 1 and off by setting acnqsMod = 0.
For small signals, by substituting (9.3) into (9.5), it is easy to show that in
the frequency domain, Qch(t) can be transformed into
Qch ( t ) =
Qcheq ( t )
(9.7)
1 + j
where is the angular frequency. Based on (9.7), it can be shown that the
transcapacitances Cgi, Csi, and Cdi (i stands for any of the G, D, S and B
terminals of the device) and the channel transconductances Gm, Gds, and Gmbs
all become complex quantities. For example, now Gm have the form of
77
High-Speed/RF Models
Gm =
Gm 0
G
+ j m0 2 2
2 2
1+
1+
Cdg =
Cdg 0
+ j
2 2
1+
1+
(9.8)
and
Cdg 0
(9.9)
2 2
Those quantities with sub 0 in the above two equations are known from
OP (operating point) analysis.
78
High-Speed/RF Models
rgateMod = 1 (constant-resistance):
effcj
RSHG XGW + 3 NGCON
(9.10)
In this case, the gate resistance is the sum of the electrode gate resistance
(9.10) and the intrinsic-input resistance Rii as given by (9.6). An internal gate
node will be generated. trnqsMod = 0 (default) and acnqsMod = 0 (default)
should be selected for this case.
79
High-Speed/RF Models
rgateMod = 3 (IIR model with two nodes):
In this case, the gate electrode resistance given by (9.10) is in series with the
intrinsic-input resistance Rii as given by (9.6) through two internal gate
nodes, so that the overlap capacitance current will not pass through the
intrinsic-input resistance. trnqsMod = 0 (default) and acnqsMod = 0 (default)
should be selected for this case.
80
High-Speed/RF Models
No substrate resistance network is generated at all.
rbodyMod = 1 (On):
All five resistances in the substrate network as shown schematically below
are present simultaneously.
The resistors of the substrate network are scalable with respect to channel
length (L), channel width (W) and number of fingers (NF). The scalable
model allows to account for both horizontal and vertical contacts.
The scalable resistors RBPS and RBPD are evaluated through
81
High-Speed/RF Models
L
RBPS = RBPS 0 6
10
RBPSL
L
RBPD = RBPD 0 6
10
RBPDL
W
6
10
RBPSW
W
6
10
NF RBPSNF
RBPDW
NF RBPDNF
(9.11)
(9.12)
The resistor RBPB consists of two parallel resistor paths, one to the
horizontal contacts and other to the vertical contacts. These two resistances
are scalable and RBPB is given by a parallel combination of these two
resistances.
L
RBPBX = RBPBX 0 6
10
L
RBPBY = RBPBY 0 6
10
RBPB =
RBPBXL
RBPBYL
W
6
10
W
6
10
RBPBXW
NF RBPBNF
RBPBYW
NF RBPBYNF
RBPBX RBPBY
RBPBX + RBPBY
(9.13)
(9.14)
(9.15)
The resistors RBSB and RBDB share the same scaling parameters but have
different scaling prefactors. These resistors are modeled in the same way as
RBPB. The equations for RBSB are shown below. The calculation for RBDB
follows RBSB.
L
RBSBX = RBSBX 0 6
10
RBSDBXL
L
RBSBY = RBSBY 0 6
10
RBSDBYL
RBSB =
W
6
10
W
6
10
RBSDBXW
NF RBSDBXNF
RBSDBYW
NF RBSDBYNF
RBSBX RBSBY
RBSBX + RBSBY
(9.16)
(9.17)
(9.18)
82
High-Speed/RF Models
The implementation of rbodyMod = 2 allows the user to chose between the
5-R network (with all five resistors), 3-R network (with RBPS, RBPD and
RBPB) and 1-R network (with only RBPB).
If the user doesnt provide both the scaling parameters RBSBX0 and RBSBY0
for RBSB OR both the scaling parameters RBDBX0 and RBDBY0 for RBDB,
then the conductances for both RBSB and RBDB are set to GBMIN. This
converts the 5-R schematic to 3-R schematic where the substrate network
consists of the resistors RBPS, RBPD and RBPB. RBPS, RBPD and RBPB
are then calculated using (9.10), (9.11) and (9.12).
If the user chooses not to provide either of RBPS0 or RBPD0, then the 5-R
schematic is converted to 1-R network with only one resistor RBPB. The
conductances for RBSB and RBDB are set to GBMIN. The resistances RBPS
and RBPD are set to 1e-3 Ohm. The resistor RBPB is then calculated using
(9.12).
In all other situations, 5-R network is used with the resistor values calculated
from the equations aforementioned.
83
Noise Modeling
KF I ds AF
Coxe Leff 2 f EF
(10.1)
84
Noise Modeling
where f is device operating frequency.
k B Tq 2 eff I ds
C oxe ( Leff 2 LINTNOI ) Abulk f
2
ef
NOIA log N 0 + N
*
10
Nl + N
10
k B TI ds Lclm
NOIA + NOIB N l + NOIC N l
2
W eff ( Leff 2 LINTNOI ) 2 f ef 1010
Nl + N*
NOIC
2
2
+ NOIB ( N 0 N l ) +
N0 Nl
where eff is the effective mobility at the given bias condition, and Leff and
Weff are the effective channel length and width, respectively. The parameter
N0 is the charge density at the source side given by
N 0 = Coxe Vgsteff q
(10.3)
A V
Nl = Coxe Vgsteff 1 bulk dseff
V
gsteff + 2 t
(10.4)
N* is given by
N* =
k BT ( Coxe + Cd + CIT )
(10.5)
q2
85
Noise Modeling
where CIT is a model parameter from DC IV and Cd is the depletion
capacitance.
Lclm is the channel length reduction due to channel length modulation and
given by
Lclm
Esat =
Vds Vdseff
+ EM
Litl
= Litl log
Esat
2VSAT
(10.6)
eff
(10.7)
(10.8)
4k BT f
NTNOI
(10.9)
86
Noise Modeling
where Rds(V) is the bias-dependent LDD source/drain resistance, and the
parameter NTNOI is introduced for more accurate fitting of short-channel
devices. Qinv is modeled by
Qinv = Wactive LactiveCoxeff
AbulkVdseff
Abulk 2Vdseff 2
NF Vgsteff
+
A V
2
12 Vgsteff bulk2 dseff
(10.10)
tnoiMod = 1 (holistic)
In this thermal noise model, all the short-channel effects and velocity
saturation effect incorporated in the IV model are automatically included,
hency the name holistic thermal noise model. In addition, the
amplification of the channel thermal noise through Gm and Gmbs as well as
the induced-gate noise with partial correlation to the channel thermal noise
are all captured in the new noise partition model. Figure 10.1b shows
schematically that part of the channel thermal noise source is partitioned to
the source side.
The noise voltage source partitioned to the source side is given by
87
Noise Modeling
vd 2 = 4k BT tnoi 2
Vdseff f
(10.11)
I ds
and the noise current source put in the channel region with gate and body
amplication is given by
id 2 = 4k BT
Vdseff f
I ds
vd 2 ( Gm + Gds + Gmbs )
(10.12)
where
2
(10.13)
(10.14)
tnoi
Vgsteff
E L
sat eff
tnoi
Vgsteff
E L
sat eff
and
where RNOIB and RNOIA are model parameters with default values 0.37
and 0.577 respectively.
88
qVbs
I bs = I sbs exp
1 fbreakdown + Vbs Gmin
NJS kBTNOM
(11.1)
89
(11.2)
NJS k BTNOM
(11.3)
qVbs
I bs = I sbs exp
NJS k BTNOM
1 + Vbs Gmin
(11.4)
dioMod = 2 (resistance-and-breakdown):
Diode breakdown is always modeled. The exponential term (11.5) is
linearized at both the limiting current IJTHSFWD in the forward-bias mode
and the limiting current IJTHSREV in the reverse-bias mode.
qVbs
I bs = I sbs exp
NJS kBTNOM
1 fbreakdown + Vbs Gmin
(11.5)
90
qVbd
I bd = I sbd exp
1 f breakdown + Vbd Gmin
NJD k BTNOM
(11.6)
(11.7)
NJD k BTNOM
(11.8)
qVbd
I bd = I sbd exp
NJD k BTNOM
1 + Vbd Gmin
(11.9)
dioMod = 2 (resistance-and-breakdown):
BSIM4.6.4 Manual Copyright 2009 UC Berkeley
91
qVbd
I bd = I sbd exp
1 f breakdown + Vbd Gmin
NJD k BTNOM
(11.11)
I bs _ total = I bs
Vbs
VTSSWGS
Weffcj NF J tsswgs (T ) exp
Vbs
VTSSWS
Ps , deff J tssws (T ) exp
1
NJTSSW (T ) Vtm0 VTSSWS Vbs
Vbs
VTSS
1 + g `min Vbs
(11.12)
I bd _ total = I bd
Vbd
VTSSWGD
Weffcj NF J tsswgd (T ) exp
Vbd
VTSSWD
Pd , deff J tsswd (T ) exp
1
(
)
0
NJTSSWD
T
Vtm
VTSSWD
V
bd
Vbd
VTSD
1 + g`min Vbd
92
(11.13)
where Cjbs is the unit-area bottom S/B junciton capacitance, Cjbssw is the
unit-length S/B junction sidewall capacitance along the isolation edge, and
Cjbsswg is the unit-length S/B junction sidewall capacitance along the gate
edge. The effective area and perimeters in (11.13) are given in Chapter 11.
Cjbs is calculated by
if Vbs < 0
C jbs
Vbs
= CJS (T ) 1
PBS (T )
MJS
(11.14)
otherwise
Vbs
C jbs = CJS (T ) 1 + MJS
PBS (T )
(11.15)
Cjbssw is calculated by
if Vbs < 0
93
Vbs
= CJSWS (T ) 1
PBSWS (T )
MJSWS
(11.16)
otherwise
Vbs
C jbssw = CJSWS (T ) 1 + MJSWS
PBSWS (T )
(11.17)
Cjbsswg is calculated by
if Vbs < 0
MJSWGS
C jbsswg
Vbs
= CJSWGS (T ) 1
PBSWGS (T )
(11.18)
MJSWGS
C jbsswg
Vbs
= CJSWGS (T ) 1
PBSWGS (T )
(11.19)
otherwise
(11.20)
where Cjbd is the unit-area bottom D/B junciton capacitance, Cjbdsw is the
unit-length D/B junction sidewall capacitance along the isolation edge, and
Cjbdswg is the unit-length D/B junction sidewall capacitance along the gate
edge. The effective area and perimeters in (11.20) are given in Chapter 12.
Cjbd is calculated by
if Vbd < 0
C jbd
Vbd
= CJD (T ) 1
PBD (T )
MJD
(11.21)
otherwise
BSIM4.6.4 Manual Copyright 2009 UC Berkeley
94
Vbd
C jbd = CJD (T ) 1 + MJD
PBD (T )
(11.22)
Cjbdsw is calculated by
if Vbd < 0
C jbdsw
Vbd
= CJSWD (T ) 1
PBSWD (T )
MJSWD
(11.23)
otherwise
Vbd
C jbdsw = CJSWD (T ) 1 + MJSWD
PBSWD (T )
(11.24)
Cjbdswg is calculated by
if Vbd < 0
C jbdswg
Vbd
= CJSWGD (T ) 1
PBSWGD (T )
MJSWGD
(11.25)
otherwise
Vbd
C jbdswg = CJSWGD (T ) 1 + MJSWGD
PBSWGD (T )
(11.26)
95
96
97
If (PS is given)
if (perMod == 0)
Pseff = PS
else
Pseff = PS Weffcj NF
Else
Pseff computed from NF, DWJ, geoMod, DMCG, DMCI, DMDG,
DMCGT, and MIN.
If (AS is given)
Aseff = AS
Else
Aseff computed from NF, DWJ, geoMod, DMCG, DMCI, DMDG,
DMCGT, and MIN.
In the above, Pseff and Aseff will be used to calculate junction diode IV and
CV. Pseff does not include the gate-edge perimeter.
12.2.2 Source/Drain Diffusion Resistance
The source diffusion resistance is calculated by
If (number of source squares NRS is given)
Rsdiff = NRS RSH
Else if (rgeoMod == 0)
Source diffusion resistance Rsdiff is not generated.
Else
Rsdiff computed from NF, DWJ, geoMod, DMCG, DMCI, DMDG,
DMCGT, RSH, and MIN.
98
Else if (rgeoMod == 0)
Drain diffusion resistance Rddiff is not generated.
Else
Rddiff computed from NF, DWJ, geoMod, DMCG, DMCI, DMDG,
DMCGT, RSH, and MIN.
effcj
RSHG XGW + 3 NGCON
(12.1)
End source
End drain
Note
0
1
2
3
4
5
6
7
8
9
10
isolated
isolated
shared
shared
isolated
shared
merged
merged
merged
sha/iso
shared
isolated
shared
isolated
shared
merged
merged
isolated
shared
merged
shared
sha/iso
NF=Odd
NF=Odd, Even
NF=Odd, Even
NF=Odd, Even
NF=Odd
NF=Odd, Even
NF=Odd
NF=Odd, Even
NF=Odd
NF=Even
NF=Even
99
End-source contact
End-drain contact
0
1
2
3
4
5
6
7
8
No Rsdiff
wide
wide
point
point
wide
point
merged
merged
No Rddiff
wide
point
wide
point
merged
merged
wide
point
100
KT1L
Vth (T ) = Vth (TNOM ) + KT1 +
+ KT 2 Vbseff
Leff
1
TNOM
(13.1)
V fb (T ) = V fb (TNOM ) KT 1
1
TNOM
(13.2)
(13.3)
(13.4)
[1 + TVFBSDOFF (T TNOM )]
101
UTE
(13.5)
(13.6)
(13.7)
(13.8)
(13.9)
and
If TEMPMOD = 1 or 2,
U 0 (T ) = U 0 (TNOM ) (T TNOM )
UTE
(13.10)
(13.11)
(13.12)
(13.13)
(13.14)
and
If TEMPMOD = 3,
U 0 (T ) = U 0 (TNOM ) (T TNOM )
UTE
(13.15)
UCSTE
(13.16)
UA (T ) = UA (TNOM ) (T / TNOM )
UA1
(13.17)
UB (T ) = UB (TNOM ) (T / TNOM )
(13.18)
UB1
UC (T ) = UC (TNOM ) (T / TNOM )
UC1
(13.19)
and
102
UD1
(13.20)
It is worth pointing out that tempMod=3 only affects the mobility. Other
parameters such as Rs and Rd are same as those in tempMod=2.
(13.21)
(13.22)
(13.23)
(13.24)
(13.25)
(13.26)
(13.27)
and
103
(13.28)
If TEMPMOD = 1,
rdsMod = 0 (internal source/drain LDD resistance)
(13.29)
(13.30)
(13.31)
(13.32)
(13.33)
(13.34)
Source-side diode
The source-side saturation current is given by
I sbs = Aseff J ss (T ) + Pseff J ssws (T ) + Weffcj NF J sswgs (T )
(13.35)
where
(13.36)
Eg (TNOM ) Eg (T )
T
+ XTIS ln
v (TNOM ) vt (T )
TNOM
J ss (T ) = JSS (TNOM ) exp t
NJS
(13.37)
104
+ XTIS ln
v (TNOM ) vt (T )
TNOM
J ssws (T ) = JSSWS (TNOM ) exp t
NJS
and
Eg (TNOM ) Eg (T )
T
+ XTIS ln
k TNOM
kb T
TNOM
J sswgs (T ) = JSSWGS (TNOM ) exp b
NJS
(13.38)
Drain-side diode
(13.39)
where
(13.40)
Eg (TNOM ) Eg (T )
T
+ XTID ln
k TNOM
kb T
TNOM
J sd (T ) = JSD (TNOM ) exp b
NJD
(13.41)
Eg (TNOM ) Eg (T )
T
+ XTID ln
k TNOM
kb T
TNOM
J sswd (T ) = JSSWD (TNOM ) exp b
NJD
and
Eg (TNOM ) Eg (T )
T
+ XTID ln
k TNOM
kb T
TNOM
J sswgd (T ) = JSSWGD (TNOM ) exp b
NJD
(13.42)
105
JTWEFF
Weffcj
Eg (TNOM )
T
.exp
X tsswgs 1
k BT
TNOM
Eg (TNOM )
T
Eg (TNOM )
T
(13.44)
(13.45)
JTWEFF
Weffcj
Eg (TNOM )
T
.exp
X tsswgd 1
k BT
TNOM
(13.46)
Eg (TNOM )
T
k BT
TNOM
(13.47)
1
NJTSSWG (T ) = NJTSSWG (TNOM ) 1 + TNJTSSWG
TNOM
(13.48)
1
NJTSSW (T ) = NJTSSW (TNOM ) 1 + TNJTSSW
TNOM
(13.49)
1
NJTS (T ) = NJTS (TNOM ) 1 + TNTJS
TNOM
(13.50)
1
NJTSSWGD (T ) = NJTSSWGD(TNOM ) 1 + TNJTSSWGD
TNOM
(13.51)
(13.52)
1
NJTSSWD (T ) = NJTSSWD(TNOM ) 1 + TNJTSSWD
TNOM
(13.53)
106
(13.54)
The original TAT current densities Jtsswgs and Jtsswgd (i.e., Equ. 13.43 and 13.46) are width
independent, while in experiments narrower device shows higher TAT current per width.
Here, BSIM 4.6.2 introduced a new parameter JTWEFF to describe this phenomenon.
The backward compatibility is kept when JTWEFF is zero.
Source-side diode
(13.55)
(13.56)
and
CJSWGS (T ) = CJSWGS (TNOM ) 1 + TCJSWG (T TNOM )
(13.57)
The temperature dependences of the built-in potentials on the source side are
modeled by
PBS (T ) = PBS (TNOM ) TPB (T TNOM )
PBSWS (T ) = PBSWS (TNOM ) TPBSW (T TNOM )
(13.58)
(13.59)
and
PBSWGS (T ) = PBSWGS (TNOM ) TPBSWG (T TNOM )
(13.60)
Drain-side diode
The temperature dependences of zero-bias unit-length/area junction
capacitances on the drain side are modeled by
CJD (T ) = CJD (TNOM ) 1 + TCJ (T TNOM )
(13.61)
107
(13.62)
and
CJSWGD (T ) = CJSWGD (TNOM ) 1 + TCJSWG (T TNOM )
(13.63)
The temperature dependences of the built-in potentials on the drain side are
modeled by
PBD (T ) = PBD (TNOM ) TPB (T TNOM )
PBSWD (T ) = PBSWD (TNOM ) TPBSW (T TNOM )
(13.64)
(13.65)
and
PBSWGD (T ) = PBSWGD (TNOM ) TPBSWG (T TNOM )
(13.66)
(13.67)
and
Eg (T ) = 1.16
7.02 104 T 2
T + 1108
(13.68)
qE (TNOM )
TNOM TNOM
exp 21.5565981 g
300.15 300.15
2 k BT
(13.69)
mrtlMod=1
BSIM4.6.4 Manual Copyright 2009 UC Berkeley
108
TBGASUB Tnom 2
Tnom + TBGBSUB
Eg (300.15) = BG 0 SUB
Eg = BG 0SUB
TBGASUB 300.152
300.15 + TBGBSUB
TBGASUB Temp 2
Temp + TBGBSUB
(13.70)
(13.71)
(13.72)
300.15
3/ 2
Eg (300.15) Eg 0
exp
2vt
(13.73)
109
The
stress
influence
on
saturation
velocity
is
also
110
eff
1
effo
(14.1)
So,
eff
= 1 +
effo
(14.2)
eff
111
KU0
( Inv _ sa + Inv _ sb )
Kstress _ u 0
(14.3)
where:
BSIM4.6.4 Manual Copyright 2009 UC Berkeley
112
1
SA + 0.5 Ldrawn
Inv _ sb =
1
SB + 0.5 Ldrawn
LKU 0
WKU 0
+
Kstress _ u 0 = 1 +
LLODKU 0
(Wdrawn + XW + WLOD)WLODKU 0
( Ldrawn + XL)
+
PKU 0
Tempera
1 + TKU 0
LLODKU 0
WLODKU 0
(Wdrawn + XW + WLOD)
( Ldrawn + XL)
TNOM
So that:
eff =
sattemp =
(14.5)
effo
sattempo
(14.6)
and SAref , SBref are reference distances between OD edge to poly from one
and the other side.
14.1.2 Vth-related Equations
Vth0, K2 and ETA0 are modified to cover the doping profile change in the
devices with different LOD. They use the same 1/LOD formulas as shown in
section(14.1), but different equations for W and L scaling:
KVTH0
( Inv _ sa + Inv _ sb Inv _ saref Inv _ sbref )
Kstress_vth0
STK2
K 2 = K 2original +
( Inv _ sa + Inv _ sb Inv _ saref Inv _ sbref )
Kstress_vth0LODK2
STETA0
ETA0 = ETA0original +
( Inv _ sa + Inv _ sb Inv _ saref Inv _ sbref )
Kstress_vth0LODETA0
(14.7)
Where:
BSIM4.6.4 Manual Copyright 2009 UC Berkeley
113
LKVTH0
WKVTH0
+
LLODKVTH
( Ldrawn + XL)
(Wdrawn + XW + WLOD ) WLODKVTH
( Ldrawn + XL)
LLODKVTH
(14.9)
PKVTH0
(Wdrawn + XW + WLOD ) WLODKVTH
1
NF
NF 1
1
NF
NF 1
1
drawn + i ( SD + Ldrawn )
SA + 0.5 L
i =0
1
drawn + i ( SD + Ldrawn )
SB + 0.5 L
i =0
114
(14.10)
n
sw i
1
1
=
115
116
(15.1)
where SCA, SCB, SCC are instance parameters that represent the integral of
the first/second/third distribution function for scattered well dopant.
The guidelines for calculating the instance parameters SCA, SCB, SCC have
been developed by the Compact Model Council which can be found at the
CMC website [19].
117
118
119
120
f sim
f
f
P1m + sim P2m + sim P3m
P1
P2
P3
(16.1)
The variable fsim() is the objective function to be optimized. The variable fexp()
stands for the experimental data. P10, P20, and P30 represent the desired
extracted parameter values. P1(m), P2(m) and P3(m) represent parameter values
after the mth iteration.
121
(16.2)
where i=1, 2, 3 for this example. The (m+1) parameter values for P2 and P3
are obtained in an identical fashion. This process is repeated until the
incremental parameter change in parameter values Pi(m) are smaller than a
pre-determined value. At this point, the parameters P1, P2, and P3 have been
extracted.
BSIM4.6.4 Manual Copyright 2009 UC Berkeley
122
Physical Meaning
TNOM
Ldrawn
Wdrawn
XJ
Junction depth
Step 2
Extracted Parameters & Fitting Target Data
123
Step 3
Extracted Parameters & Fitting Target Data
Step 4
Extracted Parameters & Fitting Target Data
Step 5
Extracted Parameters & Fitting Target Data
Step 6
Extracted Parameters & Fitting Target Data
124
Vth(Vbs, L, W)
Step 7
Extracted Parameters & Fitting Target Data
DVT0W, DVT1W, DVT2W
Fitting Target Exp. Data: Vth(Vbs, L, W)
Step 8
Extracted Parameters & Fitting Target Data
K3, K3B, W0
Step 9
Extracted Parameters & Fitting Target Data
Step 10
Extracted Parameters & Fitting Target Data
CDSCD
Fitting Target Exp. Data: Subthreshold
region Ids(Vgs, Vbs)
125
Step 11
Extracted Parameters & Fitting Target Data
DWB
Fitting Target Exp. Data: Strong Inversion
region Ids(Vgs, Vbs)
Step 12
Extracted Parameters & Fitting Target Data
Step 13
Extracted Parameters & Fitting Target Data
B0, B1
Fitting Target Exp. Data: Isat(Vgs, Vbs)/W
126
DWG
Fitting Target Exp. Data: Isat(Vgs, Vbs)/W
Step 15
Extracted Parameters & Fitting Target Data
PSCBE1, PSCBE2
Step 16
Extracted Parameters & Fitting Target Data
Step 17
BSIM4.6.4 Manual Copyright 2009 UC Berkeley
127
Step 18
Extracted Parameters & Fitting Target Data
PDIBLCB
Step 19
Extracted Parameters & Fitting Target Data
Step 20
Extracted Parameters & Fitting Target Data
128
Step 21
Extracted Parameters & Fitting Target Data
KETA
Step 22
Extracted Parameters & Fitting Target Data
Step 23
Extracted Parameters & Fitting Target Data
129
Step 24
Extracted Parameters & Fitting Target Data
kvth0, lkvth0, wkvth0, pvth0, llodvth,
wlodvth
Vth(SA, SB, L, W)
Step 25
Extracted Parameters & Fitting Target Data
stk2, lodk2, steta0, lodeta0
Fitting Target Exp. Data: k2(SA, SB, L, W),
eta0(SA, SB, L, W)
130
Default
value
14
Binnable?
NA
VERSION
4.6.4
NA
BINUNIT
PARAMCHK
1
1
NA
NA
NA
Parameter name
LEVEL (SPICE3
parameter)
MOBMOD
MTRLMOD
RDSMOD
IGCMOD
IGBMOD
CVCHARGEMOD
CAPMOD
Mobility model
selector
New material model
selector
Bias-dependent
source/drain resistance
model selector
Gate-to-channel
tunneling current
model selector
Gate-to-substrate
tunneling current
model selector
Threshold voltage for
C-Vmodel selector
Capacitance model
selector
Note
BSIM4 also
set as the
default
model in
SPICE3
Berkeley
Latest
official
release
Parameters
checked
If 0,original
model is
used If 1,
new format
used
Rds(V)
modeled
internally
through IV
equation
NA
NA
NA
OFF
NA
OFF
NA
NA
131
0 (no gate
resistance)
Substrate resistance
network model selector
0 ( network
off)
NA
TRNQSMOD
(Also an instance
parameter)
NA
OFF
ACNQSMOD
(Also an instance
parameter)
AC small-signal NQS
model selector
NA
OFF
NA
NA
NA
No
If 0,original
model is
used If 1,
new format
used
1 (including
the gateedge
perimeter)
0 (isolated)
NA
NA
0 (no S/D
diffusion
resistance)
NA
FNOIMOD
TNOIMOD
DIOMOD
TEMPMOD
PERMOD
GEOMOD (Also
an instance
parameter)
Geometry-dependent
parasitics model
selector - specifying
how the end S/D
diffusions are
connected
Source/drain diffusion
resistance and contact
model selector specifying the end S/D
contact type: point,
wide or merged, and
how S/D parasitics
resistance is computed
RGEOMOD
(Instance
parameter only)
132
NA
133
Process Parameters
Parameter
name
EPSROX
Description
Gate dielectric constant
relative to vacuum
Default
value
3.9 (SiO2)
Binnable?
No
Note
Typically
greater than
or equal to
3.9
TOXE
3.0e-9m
No
EOT
1.5e-9m
No
TOXP
TOXE
No
TOXM
TOXE
No
DTOX
Defined as (TOXE-TOXP)
0.0m
No
XJ
GAMMA1
(1 in
equation)
GAMMA2
(2 in
equation)
NDEP
1.5e-7m
calculated
Yes
Note-1
NSUB
NGATE
NSD
V1/2
Fatal error if
not positive
Fatal error if
not positive
Fatal error if
not positive
Fatal error if
not positive
Note-1
Body-effect coefficient in
the bulk
calculated
Channel doping
concentration at depletion
edge for zero body bias
Substrate doping
concentration
Poly Si gate doping
concentration
Source/drain doping
concentration Fatal error if
not positive
1.7e17cm-3
Yes
Note-2
6.0e16cm-3
Yes
0.0cm-3
Yes
1.0e20cm-3
Yes
1/2
134
Process Parameters
VBX
XT
RSH
Doping depth
Source/drain sheet
resistance
Gate electrode sheet
resistance
RSHG
calculated
(V)
No
1.55e-7m
0.0ohm/
square
0.1ohm/
square
Yes
No
No
Note-3
Should not
be negative
Should not
be negative
135
Parameter
name
VTH0 or
VTHO
DELVTO
(Instance
parameter
only)
VFB
VDDEOT
LEFFEOT
WEFFEOT
TEMPEOT
PHIN
EASUB
EPSRSUB
EPSRSUB
NI0SUB
BG0SUB
TBGASUB
TBGBSUB
ADOS
Description
Long-channel threshold
voltage at Vbs=0
Default value
0.7V (NMOS)
-0.7V(PMOS)
Binnable?
Yes
Note
Note-4
0.0V
No
Flat-band voltage
Gate voltage at which EOT
is measured
Effective gate length at
which EOT is measured
Effective width at which
EOT is measured
Temperature at which EOT
is measured
Non-uniform vertical
doping effect on surface
potential
Electron affinity of
substrate
Dielectric constant of
substrate relative to vacuum
Dielectric constant of gate
relative to vacuum
Intrinsic carrier
concentration at
T=300.15K
Band-gap of substrate at
T=0K
First parameter of band-gap
change due to temperature
Second parameter of bandgap change due to
temperature
Density of states parameter
to control charge centroid
-1.0V
1.5V (NMOS)
-1.5V(PMOS)
Yes
Note-4
No
1u
No
10u
No
27oC
No
0.0V
Yes
4.05eV
No
11.7
No
11.7
No
1.45e16m3
No
1.16eV
No
7.02e-4eV/K
No
1108.0K
No
No
136
No
Yes
Note-5
0.0
Yes
Note-5
80.0
0.0 V-1
Yes
Yes
2.5e-6m
1.74e-7m
Yes
Yes
0.0m
Yes
-3.0V
Yes
2.2
Yes
0.5V1/2
DVT1
0.53
Yes
DVT2
Body-bias coefficient of
short-channel effect on Vth
First coefficient of draininduced Vth shift due to for
long-channel pocket
devices
-0.032V-1
Yes
0.0m
Yes
DVTP1
0.0V-1
Yes
Not
modeled if
binned
DVTP0
<=0.0
-
DVT0W
0.0
Yes
5.3e6m-1
Yes
-0.032V-1
Yes
0.067 m2/(Vs)
(NMOS);
0.025 m2/(Vs)
PMOS
Yes
DVTP0
DVT1W
DVT2W
U0
137
Coefficient of first-order
mobility degradation due to
vertical field
UB
Coefficient of secon-order
mobility degradation due to
vertical field
Coefficient of mobility
degradation due to bodybias effect
UC
UD
UCS
UP
LP
EU
VSAT
A0
AGS
B0
B1
KETA
A1
A2
Mobility Coulumb
scattering coefficient
Coulombic scattering
exponent
Mobility channel length
coefficient
Mobility channel length
exponential coefficient
Exponent for mobility
degradation of
MOBMOD=2
Saturation velocity
Coefficient of channellength dependence of bulk
charge effect
Coefficient of Vgs
dependence of bulk charge
effect
Bulk charge effect
coefficient for channel
width
Bulk charge effect width
offset
Body-bias coefficient of
bulk charge effect
First non-saturation effect
parameter
Second non-saturation
factor
1.0e-9m/V for
MOBMOD =0
and 1; 1.0e15m/V for
MOBMOD =2
Yes
Yes
Yes
Yes
Yes
0(1/m2)
Yes
1e-8(m)
Yes
1.0e-19m2/ V2
-0.0465V-1 for
MOBMOD=1;
-0.0465e-9
m/V2 for
MOBMOD =0
and 2
0.0m-2
1.67 (NMOS)
1.0 (PMOS)
1.67 NMOS);
1.0 (PMOS)
8.0e4m/s
1.0
Yes
Yes
0.0V-1
Yes
0.0m
Yes
0.0m
Yes
-0.047V-1
Yes
Yes
Yes
0.0V-1
1.0
138
WINT
LINT
DWG
DWB
VOFF
VOFFL
MINV
NFACTOR
ETA0
ETAB
DSUB
CIT
CDSC
CDSCB
CDSCD
PCLM
PDIBLC1
PDIBLC2
PDIBLCB
Channel-width offset
parameter
Channel-length offset
parameter
Coefficient of gate bias
dependence of Weff
Coefficient of body bias
dependence of Weff bias
dependence
Offset voltage in
subthreshold region for
large W and L
Channel-length dependence
of VOFF
Vgsteff fitting parameter for
moderate inversion
condition
Subthreshold swing factor
DIBL coefficient in
subthreshold region
Body-bias coefficient for
the subthreshold DIBL
effect
DIBL coefficient exponent
in subthreshold region
Interface trap capacitance
coupling capacitance
between source/ drain and
channel
Body-bias sensitivity of
Cdsc
Drain-bias sensitivity of
CDSC
Channel length modulation
parameter
Parameter for DIBL effect
on Rout
Parameter for DIBL effect
on Rout
Body bias coefficient of
DIBL effect on Rout
0.0m
No
0.0m
No
0.0m/V
Yes
0.0m/V1/2
Yes
-0.08V
Yes
-
0.0mV
No
0.0
Yes
1.0
0.08
Yes
Yes
-0.07V-1
Yes
DROUT
Yes
2.4e-4F/m
Yes
Yes
0.0F/(Vm2)
Yes
0.0(F/Vm2)
Yes
1.3
Yes
0.39
Yes
0.0086
Yes
-1
Yes
0.0F/m2
2
0.0V
139
Yes
4.24e8V/m
Yes
1.0e-5m/V
Yes
0.0
Yes
0.01V
Yes
0.0V/m0.5
Yes
PDITS
0.0V-1
Yes
PDITSL
Channel-length dependence
of drain-induced Vth shift for
Rout
0.0m-1
No
PDITSD
0.0V-1
Yes
Not
modeled if
binned
FPROUT
not
positive
Not
modeled if
binned
PDITS=0;
Fatal error
if binned
PDITS
negative
Fatal error
if PDITSL
negative
-
0.0
Yes
DROUT
PSCBE1
PSCBE2
PVAG
DELTA ( in
equation)
FPROUT
LAMBDA
Channel-length dependence
of DIBL effect on Rout
First substrate current
induced body-effect
parameter
Second substrate current
induced body-effect
parameter
Gate-bias dependence of
Early voltage
Parameter for DC Vdseff
If not
given or
(<=0.0),
velocity
overshoot
will be
turned off
140
Thermal velocity
LC
XN
2.05e5[m/s]
Yes
If not
given or
(<=0.0),
source end
thermal
velocity
will be
turned off
0.0[m]
No
5e9[m] at
room
temperatur
e
3.0
Yes
141
RDWMIN
RSW
RSWMIN
PRWG
PRWB
WR
NRS
(instance
parameter
only)
NRD
(instance
parameter
only)
Description
Zero bias LDD resistance
per unit width for
RDSMOD=0
LDD resistance per unit
width at high Vgs and
zero Vbs for RDSMOD=0
Zero bias lightly-doped
drain resistance Rd(V)
per unit width for
RDSMOD=1
Lightly-doped drain
resistance per unit width
at high Vgs and zero Vbs
for RDSMOD=1
Zero bias lightly-doped
source resistance Rs(V)
per unit width for
RDSMOD=1
Lightly-doped source
resistance per unit width
at high Vgs and zero Vbs
for RDSMOD=1
Gate-bias dependence of
LDD resistance
Body-bias dependence of
LDD resistance
Channel-width
dependence parameter of
LDD resistance
Number of source
diffusion squares
Number of drain
diffusion squares
Default value
Binnable?
Yes
Note
If negative,
reset to 0.0
No
100.0
ohm(m)WR
Yes
0.0
ohm(m)WR
No
100.0
ohm(m)WR
Yes
0.0
ohm(m)WR
No
1.0V-1
Yes
0.0V-0.5
Yes
1.0
Yes
1.0
No
1.0
No
200.0
ohm(m)WR
0.0
ohm(m)WR
142
Description
First parameter of impact
ionization current
Channel length scaling
parameter of impact ionization
current
First Vds dependent parameter
of impact ionization current
Default
value
0.0m/V
Binnable?
Yes
Note
-
0.0/V
Yes
0.0/V
Yes
143
Default
value
0.0mho
Binnable?
Yes
2.3e9V/m
Yes
BGIDL
CGIDL
0.5V3
Yes
Note
Igidl=0.0 if
binned
AGIDL
=0.0
Igidl=0.0 if
binned
BGIDL
=0.0
-
EGIDL
0.8V
Yes
AGIDL
Yes
BGIDL
Yes
Igisl=0.0 if
binned
AGISL
=0.0
Igisl=0.0 if
binned
BGISL
=0.0
AGISL
BGISL
CGISL
EGISL
Description
Pre-exponential coefficient
for GIDL
CGIDL
EGIDL
Yes
Yes
144
Tunneling
Description
Parameter for Igb in
accumulation
Parameter for Igb in
accumulation
Current
Default value
2
0.5
Model
Binnable?
Yes
Note
-
Yes
0.075V-1
Yes
1.0
Yes
AIGBINV
Yes
BIGBINV
1.11e-2 (Fs2/g)0.5
m-1
9.49e-4 (Fs2/g)0.5
m-1V-1
Fatal error
if binned
value not
positive
-
Yes
0.006V-1
Yes
1.1V
Yes
3.0
Yes
1.36e-2 (NMOS)
and 9.8e-3
(PMOS)
(Fs2/g)0.5m-1
Yes
Fatal error
if binned
value not
positive
-
Yes
CIGBACC
NIGBACC
CIGBINV
EIGBINV
NIGBINV
AIGC
BIGC
145
Yes
1.36e-2 (NMOS)
and 9.8e-3
(PMOS)
(Fs2/g)0.5m-1
Yes
BIGS
Yes
CIGS
1.71e-3 (NMOS)
and 7.59e-4
(PMOS)
(Fs2/g)0.5
m-1V-1
0.075 (NMOS)
and 0.03
(PMOS) V-1
Yes
LINT
Yes
1.36e-2 (NMOS)
and 9.8e-3
(PMOS)
(Fs2/g)0.5m-1
Yes
1.71e-3 (NMOS)
and 7.59e-4
(PMOS)
(Fs2/g)0.5 m-1V-1
0.075 (NMOS)
and 0.03
(PMOS) V-1
Yes
Yes
LINT
Yes
1.0
Yes
1.0
Yes
Fatal error
if binned
value not
positive
Fatal error
if binned
value not
positive
CIGC
AIGS
AIGD
Source/drain overlap
length for Igs
Parameter for Igd
BIGD
CIGD
DLCIG
DLCIGD
NIGC
POXEDGE
Source/drain overlap
length for Igd
Parameter for Igcs, Igcd ,Igs
and Igd
Factor for the gate oxide
thickness in source/drain
overlap regions
146
NTOX
TOXREF
VFBSDOFF
1.0
Yes
Fatal error
if binned
value not
positive
1.0
Yes
3.0e-9m
No
0.0V
Yes
Fatal error
if not
positive
-
147
Description
Charge partition parameter
Non LDD region source-gate
overlap capacitance per unit
channel width
Non LDD region drain-gate
overlap capacitance per unit
channel width
Gate-bulk overlap capacitance
per unit channel length
Overlap capacitance between
gate and lightly-doped source
region
Overlap capacitance between
gate and lightly-doped source
region
Coefficient of bias-dependent
overlap capacitance for the
source side
Coefficient of bias-dependent
overlap capacitance for the
drain side
Fringing field capacitance
Constant term for the short
channel model
Exponential term for the short
channel model
Channel-length offset
parameter for CV model
Channel-width offset parameter
for CV model
Flat-band voltage parameter
(for CAPMOD=0 only)
CV parameter in Vgsteff,CV for
weak to strong inversion
CV parameter in Vgsteff,CV for
week to strong inversion
Default
value
0.0
Binnable?
No
No
Note
Note-6
No
Note-6
0.0
F/m
Note-6
0.0F/m
Yes
0.0F/m
Yes
0.6V
Yes
CKAPPAS
Yes
calculated
(F/m)
1.0e-7m
Yes
Note-7
Yes
0.6
Yes
LINT (m)
No
WINT (m)
No
-1.0V
Yes
1.0
Yes
0.0V
Yes
calculated
(F/m)
calculated
(F/m)
148
MOIN
Channel-length dependence of
VOFFCVL
Vgsteff,CV fitting parameter for
moderate inversion condition
Exponential coefficient for
charge thickness in
CAPMOD=2 for accumulation
and depletion regions
Coefficient for the gate-bias
dependent surface potential
0.0
Yes
0.0
Yes
1.0m/V
Yes
15.0
Yes
149
XRCRG2
RBPB (Also
an instance
parameter)
Description
Parameter for distributed
channel-resistance effect for
both intrinsic-input resistance
and charge-deficit NQS models
Parameter to account for the
excess channel diffusion
resistance for both intrinsic
input resistance and chargedeficit NQS models
Resistance connected between
bNodePrime and bNode
Default
value
12.0
Binnable?
1.0
Yes
50.0ohm
No
Yes
RBPD (Also
an instance
parameter)
50.0ohm
No
RBPS (Also
an instance
parameter)
50.0ohm
No
RBDB (Also
an instance
parameter)
50.0ohm
No
Note
Warning
message
issued if
binned
XRCRG1
<=0.0
-
If less
than
1.0e3ohm,
reset to
1.0e3ohm
If less
than
1.0e3ohm,
reset to
1.0e3ohm
If less
than
1.0e3ohm,
reset to
1.0e3ohm
If less
than
1.0e3ohm,
reset to
1.0e3ohm
150
50.0ohm
No
GBMIN
1.0e12mho
No
50 Ohms
0.0
No
No
0.0
No
0.0
No
50 Ohms
No
0.0
No
0.0
No
0.0
No
100 Ohms
0.0
No
No
0.0
No
0.0
No
100 Ohms
No
0.0
No
0.0
No
0.0
No
100 Ohms
100 Ohms
100 Ohms
No
No
No
RBPS0
RBPSL
RBPSW
RBPSNF
RBPD0
RBPDL
RBPDW
RBPDNF
RBPBX0
RBPBXL
RBPBXW
RBPBXNF
RBPBY0
RBPBYL
RBPBYW
RBPBYNF
RBSBX0
RBSBY0
RBDBX0
If less
than
1.0e3ohm,
reset to
1.0e3ohm
Warning
message
issued if
less than
1.0e-20
mho
151
100 Ohms
0.0
No
No
0.0
No
0.0
No
0.0
No
0.0
No
0.0
No
152
Default
value
Binnable?
Note
6.25e41
(eV)-1s1EF -3
m for
NMOS;
6.188e40
(eV)-1s1EF -3
m for
PMOS
3.125e26
(eV)-1s1EF -1
m for
NMOS;
1.5e25
(eV)-1s1EF -1
m for
PMOS
No
No
No
EM
Saturation field
4.1e7V/m
No
AF
1.0
No
1.0
No
0.0 A2-EFs1-
No
No
1.0
No
1.5
No
Parameter
name
NOIA
NOIB
NOIC
EF
KF
EFF
LINTNOI
NTNOI
3.5
No
RNOIA
0.577
No
RNOIB
0.5164
No
TNOIA
TNOIB
0.0 m
153
Description
Distance from S/D contact
center to the gate edge
Distance from S/D contact
center to the isolation edge in
the channel-length direction
Same as DMCG but for merged
device only
DMCG of test structures
Number of device fingers
Default
value
0.0m
Binnable?
No
Note
-
DMCG
No
0.0m
No
0.0m
1
No
No
DWC (in
CVmodel)
0
(minimize
the drain
diffusion
number)
0.0m
No
Fatal
error if
less than
one
-
No
No
0.0m
No
0.0m
No
0.0m
No
No
Fatal
error if
less than
one; if
not equal
to 1 or 2,
warning
message
issued
and reset
to 1
154
Description
Limiting current in reverse
bias region
IJTHSFWD
IJTHDFWD
XJBVS
XJBVD
Default
value
IJTHSREV
=0.1A
IJTHDREV
=IJTHSREV
Binnable?
No
Note
If not
positive,
reset to
0.1A
IJTHSFWD
=0.1A
IJTHDFWD
=IJTHSFWD
No
If not
positive,
reset to
0.1A
XJBVS=1.0
XJBVD
=XJBVS
No
Note-8
BVS BVD
Breakdown voltage
BVS=10.0V
BVD=BVS
No
JSS JSD
JSS= 1.0e4A/m2
JSD=JSS
No
If not
positive,
reset to
10.0V
-
JSWS JSWD
Isolation-edge sidewall
reverse saturation current
density
JSWS
=0.0A/m
JSWD
=JSWS
No
155
JSWGS
=0.0A/m
JSWGD
=JSWGS
No
JTSS JTSD
Bottom trap-assisted
saturation current density
JTSS
=0.0A/m
JTSD=JTSS
No
JTSSWS
JTSSWD
JTSSWS
=0.0A/m2
JTSSWD
=JTSSWS
No
JTSSWGS
JTSSWGD
JTSSWGS
=0.0A/m
JTSSWGD
=JTSSWGS
No
JTWEFF
Trap-assistant tunneling
current density width
dependence
0.0
No
NJTS NJTSD
NJTS=20.0
NJTSD
=NJTS
No
NJTSSW
NJTSSWD
NJTSSW
=20.0
NJTSSWD
=NJTSSW
No
NJTSSWG
NJTSSWGD
Non-ideality factor
forJTSSWGS and JTSSWGD
NJTSSWG
=20.0
NJTSSWGD
=NJTSSWG
No
156
XTSS=0.02
XTSD=0.02
No
XTSSWS,
XTSSWD
Power dependence of
JTSSWS, JTSSWD on
temperature
XTSSWS
=0.02
XTSSWD
=0.02
No
XTSSWGS,
XTSSWGD
Power dependence of
JTSSWGS, JTSSWGD on
temperature
XTSSWGS
=0.02
XTSSWGD
=0.02
No
VTSS VTSD
VTSS=10V
VTSD
=VTSS
No
VTSSWS
VTSSWD
VTSSWS
=10V
VTSSWD
=VTSSWS
No
VTSSWGS
VTSSWGD
VTSSWGS
=10V
VTSSWGD
=VTSSWGS
No
TNJTS
TNJTSD
TNJTS=0.0
TNJTSD
=TNJTS
No
TNJTSSW
TNJTSSWD
TNJTSSW=
0.0
TNJTSSWD
=TNJTSSW
No
TNJTSSWG
=0.0
TNJTSSWGD
= TNJTSSWG
No
TNJTSSWG
Temperature coefficient for
TNJTSSWGD NJTSSWG and NJTSSWG
157
MJS MJD
MJSWS
MJSWD
CJSWS
CJSWD
CJS=5.0e-4
F/m2
CJD=CJS
No
MJS=0.5
MJD=MJS
MJSWS =0.33
MJSWD
=MJSWS
No
No
No
No
Isolation-edge sidewall
junction capacitance per unit
area
CJSWS=
5.0e-10 F/m
CJSWD
=CJSWS
CJSWGS
=CJSWS
CJSWGD
=CJSWS
CJSWGS
CJSWGD
MJSWGS
MJSWGD
MJSWGS
=MJSWS
MJSWGD
=MJSWS
No
PB
PBS=1.0V
PBD=PBS
No
PBSWS
PBSWD
Isolation-edge sidewall
junction built-in potential
PBSWS
=1.0V
PBSWD
=PBSWS
No
PBSWGS
PBSWGD
PBSWGS
=PBSWS
PBSWGD
=PBSWS
No
158
Parameter
name
TNOM
UTE
UCSTE
Description
Temperature at which
parameters are extracted
Mobility temperature
exponent
Temperature coefficient of
coulombic mobility
Default value
Binnable?
Note
27oC
No
-1.5
Yes
-4.775e-3
Yes
KT1
-0.11V
Yes
KT1L
0.0Vm
Yes
KT2
0.022
Yes
1.0e-9m/V
Yes
Yes
UA1
UB1
UC1
UD1
AT
PRT
NJS, NJD
-1.0e-18
(m/V)2
0.056V-1 for
MOBMOD=1;
0.056e-9m/ V2
for
MOBMOD=0
and 2
Yes
0.0(1/m)2
3.3e4m/s
Yes
0.0ohm-m
Yes
NJS=1.0;
NJD=NJS
No
Yes
159
TPB
XTIS=3.0;
Junction current temperature
exponents for source and drain XTID=XTIS
junctions, respectively
Temperature coefficient of PB
Temperature coefficient of
TPBSW
PBSW
Temperature coefficient of
TPBSWG
PBSWG
TCJ
Temperature coefficient of CJ
Temperature coefficient of
TCJSW
CJSW
Temperature coefficient of
TCJSWG
CJSWG
Temperature coefficient of
TVOFF
VOFF
TVFBSDOFF Temperature coefficient of
VFBSDOFF
No
0.0V/K
No
0.0V/K
No
0.0V/K
No
0.0K-1
No
0.0K-1
No
0.0K-1
No
0.0K-1
No
0.0K-1
No
160
Description
Default
value
Binnable?
Parameter
name
SA (Instance
Parameter)
0.0
SB (Instance
Parameter)
0.0
SD (Instance
Parameter)
0.0
SAref
1E-06[m]
No
1E-06[m]
No
0.0[m]
No
0.0[m]
No
SBref
WLOD
KU0
Note
If not
given
or(<=0),
stress
effect
will be
turned
off
If not
given
or(<=0),
stress
effect
will be
turned
off
For
NF>1 :If
not given
or(<=0),
stress
effect
will be
turned
off
>0.0
>0.0
161
TKU0
0.0[m]
No
1<=kvsat
<=1
0.0
No
LKU0
0.0
No
WKU0
0.0
No
PKU0
0.0
No
0.0
No
>0
0.0
No
>0
0.0[Vm]
No
LLODKU0
WLODKU0
KVTH0
LKVTH0
0.0
No
WKVTH0
0.0
No
0.0
No
0.0
No
>0
0.0
No
>0
0.0[m]
No
1.0
No
0.0[m]
No
1.0
No
PKVTH0
LLODVTH
WLODVTH
STK2
LODK2
STETA0
LODETA0
>0
>0
162
Default
value
Binnable?
Note
0.0
no
0.0
no
0.0
no
0.0[m]
no
If not
given ,
calculated
If not
given ,
calculated
If not
given ,
calculated
If not
given or
<=0.0,
turn off
WPE
0.0
No
Parameter
name
SCA
(Instance
Parameter)
SCB
(Instance
Parameter)
SCC
(Instance
Parameter)
SC (Instance
Parameter)
Description
WEB
WEC
KVTH0WE
0.0
Yes
K2WE
0.0
Yes
0.0
Yes
1e-6[m]
No
KU0WE
SCREF
0.0
No
>0.0
>0.0
-
>0
163
dW and dL Parameters
Parameter
name
WL
Description
Coefficient of length
dependence for width offset
Default name
0.0mWLN
Binnable?
No
WLN
1.0
No
WW
Coefficient of width
dependence for width offset
0.0mWWN
No
WWN
WWL
LL
No
No
No
LLN
1.0
No
LW
Coefficient of width
dependence for length offset
0.0mLWN
No
LWN
1.0
No
LWL
LLC
LWC
LWLC
WLC
No
Note
-
0.0
mLWN+LLN
LL
No
-
LW
No
LWL
No
WL
No
164
dW and dL Parameters
WWC
WWLC
Coefficient of width
dependence for CV channel
width offset
Coefficient of length and width
cross-term dependence for CV
channel width offset
WW
No
WWL
No
165
Parameter
name
LMIN
Description
Minimum channel length
Default
value
0.0m
Binnable?
No
Note
-
LMAX
1.0m
No
WMIN
0.0m
No
WMAX
1.0m
No
166
Notes 1-8
1 =
2q si NDEP
Coxe
2 =
2q si NSUB
Coxe
12Coxe 2
2q si
If both 1 and NDEP are not given, NDEP defaults to 1.7e17cm-3 and 1 is calculated
from NDEP.
( 1 2 ) (
2 s
s VBX s
s VBM s + VBM
167
Notes 1-8
Note-6: If CGSO is not given, it is calculated by
If (DLC is given and > 0.0)
CGSO = DLC Coxe CGSL
if (CGSO < 0.0), CGSO = 0.0
Else
CGSO = 0.6 XJ Coxe
If CGBO is not given, it is calculated by
CGBO = 2 DWC Coxe
Note-8:
For dioMod = 0, if XJBVS < 0.0, it is reset to 1.0.
For dioMod = 2, if XJBVS <=0.0, it is reset to 1.0.
For dioMod = 0, if XJBVD < 0.0, it is reset to 1.0.
For dioMod = 2, if XJBVD <=0.0, it is reset to 1.0.
168
Core Parameters
Binnable?
No
TOXP
TOXE
No
DTOX
XJ
NDEP
Defined as (TOXE-TOXP)
S/D junction depth
Channel doping concentration
at depletion edge for zero body
bias
Long-channel threshold voltage
at Vbs=0
0.0m
1.5e-7m
1.7e17cm-3
No
Yes
Yes
Note
Fatal
error if
not
positive
Fatal
error if
not
positive
Note-2
0.7V
(NMOS)
-0.7V
(PMOS)
0.5V1/2
Yes
Note-4
Yes
Note-5
0.0
Yes
Note-5
1.74e-7m
Yes
2.2
Yes
0.53
Yes
0.067
m2/(Vs)
(NMOS);
0.025
m2/(Vs)
PMOS
8.0e4m/s
Yes
Yes
VTH0 or
VTHO
Description
Electrical gate equivalent oxide
thickness
Default
value
3.0e-9m
U0
VSAT
Saturation velocity
K1
K2
LPE0
DVT0
DVT1
169
References
Appendix C: References
[1] Y. C. King, H. Fujioka, S. Kamohara, K. Chen, and Chenming Hu, DC electrical
oxide thickness model for quantization of the inversion layer in MOSFETs, Semicond.
Sci. Technol., vol. 13, pp. 963-966, 1998.
[2] Weidong Liu, Xiaodong Jin, Yachin King, and Chenming Hu, An efficient and
accurate compact model for thin-oxide-MOSFET intrinsic capacitance considering the
finite charge layer thickness, IEEE Trans. Electron Devices, vol. ED-46, May, 1999.
[3] Kanyu M. Cao, Weidong Liu, Xiaodong Jin, Karthik Vasanth, Keith Green, John
Krick, Tom Vrotsos, and Chenming Hu, Modeling of pocket implanted MOSFETs for
anomalous analog behavior, Tech. Dig. of IEDM, pp. 171-174, 1999.
[4] Z.H. Liu, C. Hu, J.H. Huang, T.Y. Chan, M.C. Jeng, P.K. Ko, and Y.C.
Cheng,Threshold Voltage Model For Deep-Submicrometer MOSFETs, IEEE Tran.
Electron Devices, vol. 40, pp. 86-95, 1993.
[5] J.A. Greenfield and R.W. Dutton, Nonplanar VLSI Device Analysis Using the
Solution of Poisson's Equation, IEEE Trans. Electron Devices, vol. ED-27, p.1520,
1980.
[6] H. S. Lee, An Analysis of the Threshold Voltage for Short-Channel IGFET's, SolidState Electronics, vol.16, p.1407, 1973.
[7] Yuhua Cheng and Chenming Hu, MOSFET Modeling & BSIM3 Users Guide,
Kluwer Academic Publishers, 1999.
[8] C. Hu, S. Tam, F.C. Hsu, P.K. Ko, T.Y. Chan and K.W. Kyle, "Hot-Electron Induced
MOSFET Degradation - Model, Monitor, Improvement," IEEE Trans. Electron Devices,
vol. 32, pp. 375-385, 1985.
[9] T. Y. Chen, J. Chen, P. K. Ko, C. Hu, The impact of gate-induced drain leakage
current on MOSFET scaling, Tech. Digest of IEDM, pp. 718-721, 1987.
[10] S. A. Parke, E. Moon, H-J. Wenn, P. K. Ko, and C. Hu, Design for suppression of
gate-induced drain leakage in LDD MOSFETs using a quasi 2D analytical model,
IEEE Trans. Electron Devices, vol. 39, no. 7, pp 1694-1703, 1992.
[11] Weidong Liu, Xiaodong Jin, J. Chen, M. Jeng, Z. Liu, Y. Cheng, K. Chen, M. Chan,
K. Hui, J. Huang, R. Tu, P. Ko, and Chenming Hu, BSIM3v3.2 MOSFET Model and
Users Manual, http://www-device.eecs.berkeley.edu/~bsim3.
[12] Xiaodong Jin, J-J Ou, C-H Chen, Weidong Liu, Paul Gray, and Chenming Hu, An
effective gate resistance model for CMOS RF and noise modeling, Tech. Dig. of
IEDM, pp. 961-964, 1998.
[13] Mansun Chan, K. Hui, R. Neff, C. Hu, P. Ko, A Relaxation time Approach to
Model the Non-Quasi-Static Transient Effects in MOSFETs, Tech. Dig. of IEDM, pp.
169-172, 1994.
170
References
[14] K.K. Hung, P. Ko, C. Hu, and Y. C. Cheng, A Physics-Based MOSFET Noise
Model for Circuit Simulators, IEEE Trans. Electron Devices, vol. 37, no. 5, pp. 13231333, 1990.
[15] Weidong Liu, Kanyu M. Cao, Xiaodong Jin, and Chenming Hu, BSIM4.0.0
Technical Notes, http:// www-device.eecs.berkeley.edu/~bsim3/bsim4.html.
[16] R.A.Bianchi, G.Bouche and O.Roux-dit-Buisson, "Accurate Modeling of Trench
Isolation Induced Mechanical Stress Effect on MOSFET Electrical Performance,"
IEDM 2002, pp. 117-120.
[17] Hook, T.B.; Brown, J.; Cottrell, P.; Adler, E.; Hoyniak, D.; Johnson, J.; Mann, R.,
Lateral ion implant straggle and mask proximity effect, IEEE Trans. Electron
Devices, Volume 50, no 9, pp 1946- 1951, Sept. 2003
[18] Yi-Ming Sheu, Ke-Wei Su, Sheng-Jier Yang, Hsien-Te Chen, Chih-Chiang Wang,
Ming-Jer Chen, and Sally Liu, Modeling Well Edge Proximity Effect on HighlyScaled MOSFETs, CICC 2005
[19] CMC Website : http://www.eigroup.org/cmc
171