Thit k h thng kha ca s

Thit k h thng n gin s dng ngn ng Verilog

Mc lc
I.

Gii thiu ti.....................................................................................................3

1.1

Mc ch........................................................................................................... 3

1.2

M t ti.......................................................................................................3

1.3

Yu cu............................................................................................................3

II.

1.3.1

Phn cng..................................................................................................3

1.3.2

Cc yu cu v thng s............................................................................3

M t h thng.......................................................................................................4
2.1

Tin trnh..........................................................................................................4

2.2

ha..............................................................................................................5

III.

Tng qut h thng..............................................................................................8

3.1

Mn hnh VGA.................................................................................................8

3.1.1

Gii thiu...................................................................................................8

3.1.2

C ch hot ng c bn ca mt CRT......................................................8

3.1.3

Cch qut VGA..........................................................................................9

3.1.4

Cch truyn nhn d liu.........................................................................10

3.1.5

Khi iu khin VGA..............................................................................10

3.2

Bn phm PS2.................................................................................................11

3.2.1

S chn PS2........................................................................................11

3.2.2

Scan code.................................................................................................11

3.3
IV.

B nh ROM..................................................................................................13
Thit k chi tit..................................................................................................15

4.1

Khi VGA Controller.....................................................................................15

4.1.1

Gii thiu v mn hnh CRT 648 480................................................15

4.1.2

Trc ngang ng b.................................................................................15

4.1.3

Trc dc ng b.....................................................................................17

4.1.4

Cch tnh thi gian ca tn hiu VGA ng b........................................17

4.1.5

Hon tt VGA graphic.............................................................................18

1

4.2

Khi PS2........................................................................................................18

4.3

Khi VGA text................................................................................................21

4.3.1

Font ch...................................................................................................21

4.3.2

Hin th ch.............................................................................................22

4.3.3

Mn hnh gii thiu..................................................................................22

4.3.4

Mn hnh chnh........................................................................................22

4.3.5

Mn hnh kt thc....................................................................................23

4.4

4.4.1

System block diagram..............................................................................23

4.4.2

Schematic................................................................................................23

4.5

V.

S khi......................................................................................................23

Cc khi chnh................................................................................................24

4.5.1

Screen controller......................................................................................24

4.5.2

PS/2 block................................................................................................25

4.5.3

FSM.........................................................................................................25

Nhng hn ch v m rng ca ti..................................................................26

5.1

Hn ch........................................................................................................... 26

5.2

Hng m rng ca ti..............................................................................26

VI.

Ti liu tham kho.............................................................................................26

VII. Kt lun.............................................................................................................26

I.

Gii thiu ti
1.1 Mc ch

Nng cao kh nng lp trnh bng ngn ng HDL.

Lm quen vi quy trnh thit k mt h thng hon chnh.
Giao tip thnh tho vi cc thit b ngoi vi thng dng (VGA, PS/2).
Nng cao cc k nng mm (lm vic nhm, thuyt trnh,).

1.2 M t ti
Thit k h thng kha ca s s dng kit FPGA v bn phm my tnh thng
thng vi cc chc nng c th sau:
di mt khu: 4 ch s.
C chc nng ci t mt khu ban u khi cha tn ti mt khu.
Thi gian ca hon ton m v hon ton kha 3s.
C th thay i mt khu
C nt reset khng thuc bn phm. Khi bm reset, h thng chuyn sang trng
thi STORE nhp li mt khu.
Yu cu: c bin m m bo di chui mt khu nhp vo, tn hiu bo hin
trng thi gi nt (khi m hay kha), tn hiu bo hiu d liu hp l.
1.3 Yu cu
1.3.1 Phn cng
Thc hin trn KIT DE1 ca ALTERA.
Mn hnh hin th VGA 640x480 pixels.
Bn phm chun PS/2.
1.3.2 Cc yu cu v thng s
- Tn s hot ng ca ton h thng t nht l 50MHz, cng nhanh cng tt.
- p ng ca bn phm tt, bt c nhiu phm cng lc, tr nh, khng qu 0.5s.
- Hin th hnh nh vi mn hnh VGA 640x480x60Hz.
- H mu ti thiu 8bits/pixel (256 mu).

II.

M t h thng
2.1 Tin trnh

Mn hnh cho mng: hin th tn h thng, nhm pht trin, ch ngi dng sn sng.
Mn hnh chn ch : ni ngi dng la chn cng vic mun thc hin bao gm
(1) nhp mt khu m hoc kha ca hay (2) thay i mt khu.
Mn hnh nhp mt khu: cho php ngi dng thc hin m hoc kha ca bng cch
nhp ng mt khu c ci t. Hin th mn hnh ny ng ngha ngi dng
chn cng vic (1).
Mn hnh t mt khu: ngi dng t mt khu ti y khi ln u s dng h thng.
Mn hnh ny ch hin th khi ngi dng chn cng vic (2) xong cha tng t mt
khu.
Mn hnh i mt khu: ni ngi dng thay i mt khu t trc . iu ny
ng ngha ngi dng chn cng vic (2) v h thng ghi nhn thnh cng vic ci
t mt khu.
Mn hnh cnh bo: xut hin mn hnh ny ch khi ngi dng nhp sai mt khu
hoc mt khu khng khp nhau trong cc trng hp trn. H thng ng thi cnh
bo ngi dng cn bao nhiu ln nhp li mt khu trc khi khng ghi nhn thm
bt k n lc no na, tc l ngi dng phi quay tr li t u.
Mn hnh kt thc: thng bo cng vic c thc hin v h thng ghi nhn
thnh cng.

2.2 ha
ha gm 6 mn hnh:

 Mn 1: Mn hnh gii thiu

Mn 2: Mn hnh chn ch

Mn 3: Mn hnh t mt khu lc u

 Mn 4: Mn hnh nhp mt khu

Mn 5: Mn hnh i mt khu

 Mn 6: Mn hnh bo thnh cng

III.

Tng qut h thng

3.1 Mn hnh VGA

3.1.1

Gii thiu

VGA(Video Graphics Arrays: mng ha video) c gii thiu bi IBM

PCs c h tr bi phn cng ha PC v mn hnh. Chng ta s thit k mt
giao din gm 12 mu c bn vi phn gii 640x480 cho mn hnh CRT.
3.1.2

C ch hot ng c bn ca mt CRT

S khi:

 Cng tia electron v sng ca cc im c quyt nh bi mc in

th tn hiu video u vo, mono. Tn hiu mono l tn hiu tng t c mc
in th thay i gia 0 v 0,7.
The vertical deflection coil v horizontal deflection coil iu khin hnh trnh
ca dng electron v quyt nh ni m electron u trn mn hnh. Vi cc
mn hnh ngy nay,trm electron c iu khin t tri sang phi t trn
xung di.
3.1.3

Cch qut VGA

Khi in p c a vo the honrizontal deflection coil v tng mt cch

u n th trm electron s di chuyn t gc tri sang gc phi. Sau khi chm
ti gc phi, chm tia s nhanh chng quay tr li gc tri khi in p v 0V
( hsync ). Cho n khi trm electron chm ti y mn hnh th in p s c

a vo the vertical deflection coil, chm tia s c a tr li nh mn hnh (

vsync ) v tip tc qu trnh nh trong hnh.
Tn hiu hsync dng qut mn hnh theo hng v tn hiu vsync dng
qut ton b mn hnh vi tn s 25MHz pixel rate (25 triu im nh c thc
hin trong 1s) c th to ra mn hnh VGA phn gii 640x480.
3.1.4

Cch truyn nhn d liu

c th truyn nhn d liu v hin th ln mn hnh, chng em thit k

mt mch vga_sync gm b m v cc tn hiu ng b. Mch ny c 2 tn
hiu hsync v vsync c ni trc tip n mn hnh, chng dng iu
khuyn s qut ngang v dc mn hnh. Hai tn hiu ny c gii m bi mt
b m c sn trong mch v u ra ca 2 tn hiu ny l pixel_x, pixel_y. Hai
tn hiu u ra ny ch ra quan h gia v tr qut v v tr hin ti ca im nh.
Mch c mt tn hiu video_on iu khuyn tt hay bt s hin th.

3.1.5

Khi iu khin VGA

Mt mch to ra 3 tn hiu video c gi chung l tn hiu rgb (red green

blue) c u vo l pixel_x v pixel_y, video_on. Gi tr ca mt mu c hin

10

th trn mn hnh ph thuc vo v tr im nh hin ti (pixel_x v pixel_y) v

tn hiu data v iu khin bn ngoi.
3.2 Bn phm PS2

3.2.1

S chn PS2

S dng chun kt ni PS2 kt ni keyboard vi KIT DE1

Pin 1 +DATA Data
Pin 2 Not connected
Pin 3 GND Gr
Pin 4 Vcc +5 V DC at 275 mA
Pin 5 +CLK
Pin 6 Not connected

3.2.2

Scan code

Mt bn phm bao gm mt ma trn cc phm v mt vi x l nhng kim

tra nhng hot ng ca phm v gi scan code ph hp.

11

 Hot ng ca bn phm
Khi 1 phm c n th the make code ca phm c truyn i.
Khi 1 phm c gi lin tc, trng thi c bit nh l typematic th the
make code c truyn i lin tc vi mt tc nht nh. ch mc
nh, mt PS2 keyboard truyn make code vo khong 100ms sau khi 1
phm c gi trong khong 0.5s.
Khi 1 phm c nh ra th the break code (0xF0) c truyn i sau l
make code ca phm nhn bit phm no va c nh.
Cch truyn nhn d liu
Mt thit b PS2 (bn phm) kt ni vi KIT DE1 v trao i d liu
thng qua 2 ng l data v clock.

12

 ng data gm 11 bit

ng clock c mang trong mt tn hiu clock ring bit.

D liu s c truyn i khi xung clock c s thay i v ang tch cc
mc thp (falling-edge).
3.3

B nh ROM

Trong project ny, chng em s dng ROM 1 PORT lu tr font ch v hnh

nh. Bng cch ny, s lng total logic elements s gim i ng k.

13

IV.

Thit k chi tit

4.1 Khi VGA Controller
4.1.1

Gii thiu v mn hnh CRT 648 480

640x480 l s im nh v ng c th hin th c trn mn hnh. Mi

ng ngang gm 640 im nh, 480 l s ng dc cn qut nhng thc t l
mi ng ngang gm 800 im nh v s ng dc cn qut l 525. S im
nh v ng khng c hin th c gi l black border (bin en). Tn s
hot ng l 25MHz.

4.1.2

Trc ngang ng b

Trc ngang c 800 im nh c chia lm 4 vng

14

 Dislay: vng m cc im nh thc c hin th c di 640px.

Retrace: vng m trm electron quay tr li gc tri, tn hiu video nn c
tt, c di 96px.
Right border (bin phi): vng to thnh bin phi ca vng hin th c gi
l front porch (cng trc), tn hiu nn c tt,c di 16px.
Left border (bin tri): vng to thnh bin tri ca vng hin th c gi l
back porch (cng sau), tn hiu nn c tt,c di 48px.
di ca left and right border c th thay i gia cc mn hnh khc nhau.
Tn hiu hsync cn c thm b m 800 im nh v mt mch gii m. Khi
bt u vic hin th th b m cng bt u m v tn hiu ra hp thnh tn
hiu pixel_x. Tn hiu hsync mc thp khi tn hiu ra ca b m nm trong
khong 656 va 751.
Chng ta s dng tn hiu video_on iu chnh hin th/khng hin th khi
b m c gi tr nh hn 640.
Mn hnh CRT nn c en bin tri v phi v trong sut qu trnh
retrace.

15

4.1.3

Trc dc ng b

Trong sut qu trnh qut dc, chm electron di chuyn u n t u ti

cui cng mn hnh, sau li quay tr li u mn hnh. S ging nhau ny
yu cu mt khong thi gian lm ti mn hnh. Cu trc ca vsync tng
t vi hsync.
Mt chu k ca tn hiu vsync l 525 ng v c chia lm 4 khu vc
ging nh hsync.
Cc c im ca tng khu vc cng tng t nh hsync:

Tn hiu vsync cn 1 b m 525 dng v mt mch gii m. Bt u m

khi bt u khu vc hin th.tn hiu u ra ca b m l pixel_y. Tn hiu
vsync mc thp khi b m dng dng 490 hoc 491.
Cng nh hsync,chng ta s dng video_on hin th/khng hin th khi b
m c gi tr nh hn 480.
4.1.4

Cch tnh thi gian ca tn hiu VGA ng b

phm vi project ny chng ta s dng tn s l 25MHz. S la chn ny l

do cu hnh phn cng ca mn hnh. Vi vic s dng tn s qut ny th mn
hnh mi hin th c cc k t v hnh nh, nu nhanh hn hoc chm hn th
s khng hin th c.

16

4.1.5

Hon tt VGA graphic

trn chng ta thit k 2 b m. Vn thit k y l KIT DE1 ch

h tr tn s 50MHz m yu cu l 25MHz. V vy do yu cu thit k chng ta
to ra 1 b 25MHz cho php nh du tm dng hoc cho php vic m. Tn
hiu p_tick l mt tn hiu ra thc hin cng vic ny v phi hp vi s hot
ng ca mch the pixel generation.
S dng 2 tn hiu h_end v v_end kim tra vic hon thnh qut ngang
v dc.
Ngoi ra trnh khi tnh trng nhiu chng ta cn s dng thm nhng b
m c chn thm vo cc tn hiu hsync v vsync.
4.2 Khi PS2

PS2 gm 2 ng truyn : clk, data

Thng tin c truyn nh 1 gi gm 11 bit: 1 bit start , 8 bit data, 1 bit
parity, 1bit stop.
Tn hiu clock c chu k trong khong t 60 n 100 ps (10KHz ti 16,7
KHz), v tn hiu ps2d phi n nh t nht l 5 us trc v sau sn ln v
xung ca tn hiu ps2c.

Khi nhn d liu (PS2_rx)

c s dng lc nhiu v c cc bit ca 1 phm
u ra cung cp cho khi FSM.

17

Ta c s khi ca mch nhn :

S khi mch nhn d liu

c th hiu c ch nhn d liu ca PS2 ta xt lu sau:

18

ASMD chart of PS2 port receiver

Khi c tn hiu cho php nhn rx_en v tn hiu tch cc sn xung th trng
thi s dch n start bit v di chuyn n trng thi dps.
19

K t khi d liu c nhn trong mt khi c kim tra, chng ta s

dch li 10bit trong mt trang thi ring hn l s dng cc trng thi ring
bit nh l data, parity, stop.
Sau mch s chuyn ti trng thi load trong c mt chu k tn hiu
clock thm c phn phi hon thnh qu trnh dch n bit stop, v tn hiu
rx_done_tick c chn vo sau 1 chu k thng bo khi nhn xong d
liu.
4.3 Khi VGA text
4.3.1

Font ch

Mi k t c kch thc 8 8 (tng ng vi 8 pixel mi chiu khi hin

th). Tt c c lu trong mt file .mif v c truy cp bng cch s dng
ROM 1 PORT trong LPM.
V d, hin th k t A:

a ch ca mi k t c lit k trong bng sau:

20

4.3.2

Hin th ch

Trong h thng, chng em s dng 2 kch c ch: 32 32 v 16 16.

iu chnh kch thc, chng em da trn gi tr ca cc tn hiu bit_addr v
pixel_x. Bit_addr l s ct trong mt mu font ch. Gi tr ca pixel_x(4
downto 2) hoc (3 downto 1) l s hng trong mu font ch.

4.3.3

Mn hnh gii thiu

Trong mn hnh ny, chng em hin th cc ch:

H THNG KHA CA S vi kch c 32 32
PRESS SPACE TO CONTINUE vi kch c 16 16.
4.3.4

Mn hnh chnh

Chng em lu tr hnh nh ca mi vt trong ROM s dng ROM 1 PORT

LPM trong Quartus II. Da trn tn hiu iu khin ca tng vt, mu sc ca
mi im nh s c ch nh bi u ra RGB t ROM tng ng.
Chng em hin th cc vt trn mt lp v sp xp cc lp chng ln nhau.
Th t ca cc lp s c quyt nh bi th t ca lnh hin th.

21

4.3.5

Mn hnh kt thc

Trong mn hnh ny, chng em hin th ch CONGRATULATION vi

kch c 32 32.
4.4 S khi
4.4.1

System block diagram

4.4.2

Schematic

22

4.5 Cc khi chnh

4.5.1

Screen controller

23

4.5.2

PS/2 block

4.5.3

FSM

24

V.

Nhng hn ch v m rng ca ti
5.1

Hn ch

Do dung lng logic elements ca kit DE1 hn ch cng nh cha ti u ti a

c code nn nhm cha pht trin c nhiu tnh nng hn.
5.2

Hng m rng ca ti

gii quyt vn dung lng logic elements ca kit DE1 hn ch, ta s ghi
data vo RAM sau khi cn th c cc khi t RAM ra.
B sung m thanh cho h thng.

VI.

Ti liu tham kho

[1] http://www.eewiki.net/pages/viewpage.action?pageId=15925278
[2] http://www.youtube.com/user/LBEbooks?feature=watch
[3] http://www.cs.columbia.edu/~sedwards/classes/2011/4840/
[4] http://www.fpga4fun.com/
[5] FPGA Prototyping by Verilog Examples - Xilinx Spartan-3 Version Pong P.Chu.

VII.

Kt lun

Sau mt thi gian thc hin, nhm chng em hon thnh ti H thng kha
ca s. H thng demo chy c v kh hon chnh. Tuy nhin cn mt vi vn
v m rng h thng cha hon thin. Qua y, chng em hon thin hn v ngn
ng HDL, cch m phng testbench, cch lm vic nhm v thuyt trnh.
Chng em chn thnh cm n thy v cc anh hng dn v ch bo chng em
trong thi gian qua! Chng em s c gng hon thin h thng hn trong thi gian ti.

25