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THIT K NG DNG PAINT TRN NN FPGA

Trng Phong Tuyn1, T Duy Thng1, Lu Tioni1 v Lng Vinh Quc Danh1
1

Khoa Cng ngh, Trng i hc Cn Th

Thng tin chung:

Ngy nhn: 19/12/2014
Ngy chp nhn: 17/08/2015

Title:
Implementation of an FPGAbased Paint application
T kha:
Altera DE2-115, ha my
tnh, DE2-Paint, FPGA, h
thng nhng
Keywords:
Altera DE2-115, computer
graphics, DE2-Paint, FPGA,
embedded systems

ABSTRACT
Nowadays, designing embedded systems on FPGA technology has proven
to be an effective solution for various applications because of its
noteworthy benefits such as high speed, high performance and low power
comsumtion. The project Design and implementation of an FPGA-based
Paint application, therefore, aims to create an embedded application on
FPGA to perform some fundamental computer graphics algorithms.
Importantly, further research into computer graphics and embedded
systems on FPGA will be started out based on these results.
TM TT
Hin nay, cc h thng nhng trn nn FPGA vi nhiu u im vt tri
nh tc , hiu sut x l cao v tiu hao nng lng thp ang nhn
c s quan tm nghin cu v ng dng ngy cng tng. Nghin cu
Thit k ng dng Paint trn nn FPGA c thc hin vi mc tiu thi
cng mt ng dng nhng s dng FPGA thc hin mt s gii thut
ha my tnh c bn. Nhng kt qu ca nghin cu ny s l c s cho
vic tip tc pht trin cc ng dng nhng v ha v gii tr a
phng tin trn nn FPGA.
ngnh K thut My tnh. Trong thi gian khong
4 thng thc hin, nghin cu tp trung vo vic
pht trin mt h thng nhng c kh nng thc
hin cc gii thut ha c bn nh v v t mu
on thng, a gic, hnh trn,... Cc gii thut
ha c ci t, minh ha di giao din
chng trnh tng t nh ng dng Microsoft
Paint trn h iu hnh Windows.

1 GII THIU
Vic pht trin cc h thng nhng cho cc ng
dng ha my tnh khng cn l lnh vc qu
mi m vi mt s quc gia pht trin. Nhiu cng
ty, trng i hc ni ting trn th gii c
nhng nghin cu nguyn cu thnh cng, cho ra
i nhiu sn phm ni ting trong lnh vc ny.
Tuy nhin ti Vit Nam, chng ta ch mi tng
bc tip cn vi lnh vc ny khong vi nm tr
li y.
T thc t trn, mc tiu ca nghin cu Thit
k ng dng Paint trn nn FPGA c thc hin
trn board DE2-115 Development and Education
ca Terasic nhm bc u nghin cu v pht
trin mt h thng nhng phc v cc ng dng
ha my tnh. Qua gp phn b sung vo ngun
t liu tham kho cho cc nghin cu v pht trin
ng dng nhng tip theo ca sinh vin chuyn

2 PHNG PHP THC HIN

2.1 Tng quan v h thng
2.1.1 Phn cng
H thng c thit k v cu hnh trn board
DE2-115 ca Terasic bng cch s dng b cng
c SOPC Builder trong phn mm Quatus II ca
Altera. H thng c kh nng giao tip vi chut
qua cng PS/2 cho php x l v hin th hnh nh
ln mn hnh (Terasic Technologies Inc, 2013).

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Hnh 1: S khi h thng

nh cn phi c np vo b nh Pixel Buffer.
Khi cc thnh phn h thng s thc hin vic
chuyn i nh dng hnh nh v hin th ra mn
hnh nh b iu khin VGA (Adam Chapweske,
2003), (Altera Corporation, 2010).
2.1.2 Phn mm

Cc thnh phn chnh ca h thng:

Nios II processor: khi x l trung tm m
nhim x l cc lnh thc thi trn h thng (tn s
hot ng 50MHz). Vi x l Nios II s dng
SDRAM trn board DE2-115 lm b nh d liu
truy xut thng qua li iu khin SDRAM.

Phn mm c thit k, bin dch v ci t

da trn b cng c Nios II trong gi phn
mm Altera Quartus II (Altera Corporation, 2007).
V chc nng, phn mm bao gm cc gii
thut chnh:

Avalon Switch Fabric: bus (32-bit) c

nhim v lin kt cc thnh phn ca h thng.
Pixel Buffer: s dng mt phn vng nh
SRAM (ti a 2MHz) lu tr d liu hnh nh.
Cc khi x l hnh nh (Pixel Buffer DMA
Controller, RGB Reasample, VGA Dual Clock
FIFO): thc hin cc cng vic c hnh nh t b
nh, chuyn i nh dng, khng gian mu ca
hnh nh.

Giao tip vi mn hnh v chut thng qua

chun VGA v PS/2.
Thao tc trn cc pixel (xa pixel, thit
lp/ly gi tr pixel, )
V on thng v hnh hc ( hnh trn/elip,
cc a gic, )

Khi VGA Controller: Thc hin giao tip

vi module VGA-DAC hin th hnh nh ln
mn hnh.

T mu, x l, hin th k t,
2.2 Thit k h thng nhng
2.2.1 Thit k h thng trn phn mm SoPC
Builder

P/S2 Controller: Thc hin giao tip vi

thit PS/2 (chut/ bn phm).
hin th hnh nh ln mn hnh VGA, hnh

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Hnh 2: H thng nhng c thit k

Hnh 2 l kt qu thit k phn cng ca h
thng s dng cng c SOPC Builder c tch
hp trong gi phn mm Quatus II ca hng Altera.
Cc thnh phn ca h thng trn c Altera cung
cp hu ht di dng cc li IP (Intellectual
Property core). xy dng h thng, ngi
thit k cn tin hnh la chn v cu hnh cc li
IP mt cch hp l p ng cc yu cu t ra
nh sau:
Nios II processor (CPU)
Nios II processor l mt li (core) vi x l 32
bit c ti u cho cc ng dng ca hng sn xut
Altera. B x l ny m nhim x l cc lnh
thc thi, iu khin hot ng ca cc thnh phn
phn cng trong h thng. Trong ti ny, h
thng SoPC s dng phin bn NiosII/s (phin bn
chun), phin bn ny yu cu ti nguyn thp trn
chip FPGA m vn m bo p ng tt cc yu
cu t ra (Altera Corporation, 2011).

Hnh 3: Cu hnh khi Pixel Buffer

Pixel Buffer DMA Controller
Khi Pixel Buffer DMA Controller c xem
nh l khi c s dng nh x d liu t b
nh Pixel Buffer lm d liu u vo cho cc
khi x l tip theo. khi Pixel Buffer DMA
Controller c th c chnh xc d liu hnh nh
lu trong khi Pixel buffer, cn thit lp cc thng
s v phn gii ca hnh nh (640x480 pixel),
nh dng khng gian mu (16 bit-RGB), a ch
bt u c d liu 0x08000000 tng ng vi d
liu hnh nh lu trn khi Pixel Buffer (Hnh 4)
(Altera Corporation, 2010).

Pixel Buffer
Khi Pixel Buffer s dng mt phn vng nh
SRAM trn board DE2-115 lu tr cc gi tr
pixel ca hnh nh (c phn gii 640x480 pixel,
nh dng 16bit-RGB). Trong h thng SoPC,
ngi thit k cn cu hnh cho li SRAM/SSRAM
Controller hot ng nh mt b Pixel Buffer
tng thch vi board DE2-115 nh Hnh 3. Khi
Pixel Buffer trong h thng c a ch t
0x08000000 n 0x081FFFFF (Altera Corporation,
2010).
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Hnh 4: Cu hnh khi Pixel Buffer DMA Controller

VGA Resampler

Hnh 5: Cu hnh khi RGB Resampler

Controller, 640x480 pixel, 30-bit RGB nh Hnh 5
(Altera Corporation, 2010).

D liu hnh nh lu trong b nh Pixel Buffer

c phn gii 640x480 v c nh dng 16 bitRGB. V vy, cn phi s dng khi VGA
Resampler chuyn i nh dng ng vo
(incoming format) 16-bit RGB thnh 30-bit RGB
ng ra (outgoing format). nh dng ny thch hp
vi nh dng d liu u vo ca khi VGA

VGA Dual Clock FIFO

Hnh 6 l hnh nh thit lp cc thng s ca
VGA Dual Clock FIFO. y l mt b m d liu
v gip ng b cho qu trnh vn chuyn d liu
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gia thnh phn c 2 ngun xung clock khc nhau.

Trong h thng, khi VGA Controller s dng
xung clock 25 MHz, trong khi cc thnh phn khc
ca h thng hot ng xung clock 50MHz. Khi
VGA Dual Clock FIFO m bo vic giao tip

gia khi VGA Resample v khi VGA Controller

c ng b vi nhau. Trong h thng ny khi
VGA Dual Clock FIFO c nh dng khng
gian mu ca hnh nh 30 bit RGB, 10 bit cho mi
mu (Altera Corporation, 2010).

Hnh 6: Cu hnh khi Dual Clock (DC) FIFO

VGA Controller

thng v gii thut t mu (Donald Hearn, M.

Pauline Baker, 1986; Lm Th Ngc Chu, 2003;
L Tn Hng, Hunh Quyt Thng, 2000).

Li VGA Controller cung cp d liu hnh nh,

ng thi to ra cc tn hiu nh thi cho module
VGA-DAC trn broad DE2-115. Ngoi ra, VGA
Controller cng to ra c tn hiu ng b ngang v
dc s dng cho vic qut hnh nh trn mn hnh.
Li VGA Controller cung cp bi nh sn xut c
th to ra tn hiu nh thi tn s 25MHz (Altera
Corporation, 2010).

Gii thut v on thng Bresenham

Xt phng trnh on thng:
y = kx + m
(1)
vi k = (y2 y1)/( x2 x1) v m = y1 kx1
Trong k c gi l dc hay h s gc
ca on thng v m c gi l on chn trn
trc y.

PS/2 Controller
Li PS/2 qun l s nh thi ca giao thc
truyn d liu ni tip PS/2 (PS/2 Serial Data
Transmission Protocol). Trnh iu khin thit b
c th giao tip vi b phn ny bng cch c v
ghi d liu cng nh iu khin cc thanh ghi. Li
PS/2 Controller s dng trong h thng vi 256word FIFO lu tr d liu nhn c t thit b
PS/2 (bn phm/ chut). a ch ca li iu khin
PS/2 trong h thng t 0x10000100 n
0x10000107 v c dng giao tip vi chut
PS/2 thc hin cc thao tc v nh (Adam
Chapweske, 2003; Altium Corporation, 2009;
Andries Brouwer, 2009).
2.2.2 Phn mm

T phng trnh c th xy dng qu trnh v

cc on thng khi cho x bin thin theo cc
khong x v kt qu ta c th thu c gi tr ca
bin y thay i vi cc khong y tng ng (y =
kx).

Vic thc hin cc gii thut ha d n

gin hay phc tp v c bn u c thao tc trn
tng pixel. Trong nghin cu ny, nhm tc gi s
dng 02 gii thut in hnh l gii thut v on

Hnh 7: Minh ha gii thut Bresenham

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im seed (im bt u t mu) duyt qua 4 im

hoc 8 im lng ging (im ln cn) ca im
seed. Nu im cha c t th s t mu im
. im ny tr thnh im seed mi. Qu trnh
lp li cho n khi ton vng c t mu.

Xt gii thut Bresenham, gi s bc th i, ta

xc nh c ta (xi, yi), nh vy chng ta
cn xc nh ta (xi+1, yi+1) cho bc k tip.
Vi gi tr xi+1 = xi + 1, gi tr ca yi+1 c th c
chn mt trong hai gi tr yi v yi+1. Cch chn
c m t nh sau:
d1 = yi+1 yi = k(xi + 1) + m - yi

(2)

d2 = yi + 1 yi+1 = yi + 1 k(xi + 1) m

(3)

t Di = d1 d2
Nu: Di 0 d1 d2 ta chn S : yi+1 = yi

Hnh 9: Minh ha gii thut t mu loang

Di > 0 d1 > d2 ta chn P : yi+1 = yi +1

Hnh 8: Lu gii thut v on thng Bresenham

Trong lu Hnh 8, mt vng lp c s

dng duyt theo trc x t u n cui on
thng (x1xn). Vi mi gi tr xi ta tnh gi tr Di
tng ng, t xc nh gi tr ca yi. Vic ny
gip ta chn c cc ta (xi,yi) nguyn (tng
ng vi cc pixel) gn vi ng thng cn
v nht.
Gii thut t mu

Hnh 10: Lu gii thut t mu loang

Hnh 10 trnh by lu gii thut t mu
loang cho mt vng vi 4 lng ging. Bt u t 01
pixel trong vng cn t mu, gii thut t mu
loang s c p dng t mu cho 04 pixel lng
ging. Vic t mu trn s lp li cho n khi tt c
cc pixel trong vng cn t u c t mu.

T mu mt vng l thay i mu sc ca cc
im v nm trong vng cn t. Mt vng cn t
mu thng c xc nh bi mt ng khp kn
no gi l ng bin (vin). Hm t mu mt
vng a gic bt k s dng gii thut t mu
loang (Flood Fill). Gii thut loang l mt gii
thut quy da trn tng: xut pht t mt

KT QU V NH GI

Ni dung nghin cu tp trung vo vic thit k

v thc hin mt h thng nhng trn FPGA c
kh nng thc hin v hin th mt s gii thut
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ha my tnh (v on thng, cc a gic, hnh

trn, lip, nhp k t, ).

v cc ngoi vi c ng b v hot ng tt.

Ton b h thng c cu hnh trn chip FPGA
Cyclone IV EP4CE115F29 vi s ti nguyn c
s dng nh Hnh 11.

V phn cng, cc thnh phn trong h thng

Hnh 11: Tng s ti nguyn h thng s dng trn chip FPGA

Hnh 12: Giao din chnh ca chng trnh

nh hin th trn mn hnh c phn gii 640x480
pixel, nh dng khng gian mu RGB 16-bit.

H thng s dng vi x l Nios II vi tn s

xung nhp 50MHz, b nh SDRAM 128MB, giao
tip vi mn hnh LCD v chut my tnh. Hnh
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Phn A: Khoa hc T nhin, Cng ngh v Mi trng: 39 (2015): 48-56

(a)

(b)

Hnh 12: (a) Phn cng thit k s dng board FPGA DE2 ca hng Altera; (b) Cc thao tc vi ng
dng Paint chy trn phn cng c thit k
www.cs.columbia.edu/~sedwards/classes/20
08/4840/qts_qii5v4.pdf, ngy truy cp
15/09/2014.
3. Altera Corporation, 2010. Media Computer
System for the Altera DE2-115 Board. URL:
ftp://ftp.altera.com/up/pub/Altera.../DE2115_Media_Computer.pdf, ngy truy cp
15/09/2014.
4. Altera Corporation, 2010. Video IP Cores
for Altera DE Series Boards. URL:
ftp://ftp.altera.com/up/pub/Altera_Material/
9.1/University_Program_IP_Cores/Audio_
Video/Video.pdf , ngy truy cp
15/09/2014.
5. Altera Corporation, 2011. Nios II Processor
Reference Handbook. URL:
www.altera.com/literature/hb/nios2/n2cpu_
nii5v1.pdf, ngy truy cp 15/09/2014.
6. Altium Corporation, 2009. PS2 Commands.
http://techdocs.altium.com/display/FPGA/P
S2+Commands, ngy truy cp 15/09/2014.
7. Andries Brouwer, 2009. Keyboard scancodes.
http://www.win.tue.nl/~aeb/linux/kbd/scancodes
-13.html, ngy truy cp 15/09/2014.
8. Donald G. Bailey, 2011. Design for
Embedded Image Processing on FPGAs.
John Wiley & Sons Pte Ltd. 352 pp.
9. Donald Hearn, M. Pauline Baker, 1986.
Computer Graphics. Prentice-Hall, Inc.
Englewood Cliffs. New Jersey. 352 pp.
10. H Nguyn t, 2009. H thng nhng:
hng i mi ca Vit Nam. Thi bo Vi
tnh Si Gn,
http://tbvtsg.com.vn/show_article.php?id=16
049&ln_id=101, ngy truy cp 15/09/2014.

Phn mm c lp trnh bng ngn ng C vi

giao din c thit k cho php thc hin c tt
c cc thao tc v, t mu v lu nh nh vi ng
dng Microsoft Paint thng thy trn h iu
hnh Microsoft Windows (Hnh 12). Bn cnh ,
h thng cng b sung tnh nng nhp bn phm o
cho php nhp vn bn t vic click chut hoc
thng qua mn hnh cm ng. B tr h thng trong
thc nghim v hnh nh minh ha mt s thao tc
trn h thng nh Hnh 12. Mt on video clip
trnh by kt qu ca nghin cu c th xem ti
ng link http://goo.gl/MRkyHZ.
4 KT LUN V XUT
Nghin cu c bn t c cc yu cu t
ra v thit k mt phn cng nhng trn nn FPGA
cho php thc hin cc gii thut ha c bn.
Cc gii thut ha ny c minh ha thng
qua mt ng dng v v t mu n gin tng t
nh ng dng Paint ca Microsoft. Mc d vy,
trong qu trnh thc hin do kh nng x l ca h
thng cn hn ch nn mu sc ca hnh nh hin
th cha tht sng ng, i lc cn b tr. Tuy
nhin, vi nhng kt qu t c nu trn cho
thy mt hng nghin cu ng n v y s l
ngun tham kho hu ch cho sinh vin ngnh K
thut my tnh v Cng ngh thng tin trong lnh
vc thit k h thng nhng cho cc ng dng
ha my tnh.
TI LIU THAM KHO
1. Adam Chapweske, 2003. The PS/2 Mouse
Interface. URL: http://www.computerengineering.org/, ngy truy cp 15/09/2014.
2. Altera Corporation, 2007. Quartus II
Handbook Volume 4: SOPC Bulder. URL:
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Phn A: Khoa hc T nhin, Cng ngh v Mi trng: 39 (2015): 48-56

thong-nhung-thoi-ky-hau-may-tinh/ , ngy
truy cp 15/09/2014.
15. Ranjani Chandrasekar, Manu Jain, 2007.
FPGA Paint, Advanced Microcontrollers Final
Projects.http://people.ece.cornell.edu/land/cou
rses/ece5760/FinalProjects/f2007/rc437_mj28
8/rc437_mj288/rc437_mj288/index.html, ngy
truy cp 15/09/2014.
16. Terasic Technologies Inc, 2013. DE2-115
User Manual.
http://www.terasic.com.tw/cgibin/page/archive_download.pl?Language=E
nglish&No=502&FID=cd9c7c1feaa2467c5
8c9aa4cc02131af, ngy truy cp
15/09/2014.

11. Lm Th Ngc Chu, 2003. K thut

ha. Khoa CNTT&TT. Trng i hc Cn
Th. 159 trang.
12. L Tn Hng, Hunh Quyt Thng, 2000.
K thut ha. Nh xut bn Khoa hc v
K thut. H Ni. 355 trang.
13. MathWorks, Inc, 2014. MatLab Image
Processing Toolbox 6 Users Guide.
http://www.mathworks.com/help/pdf_doc/i
mages/images_tb.pdf, ngy truy cp
15/09/2014.
14. Phm Thng Ct, 2005. H thng nhng
Thi k hu my tnh. Th gii my tnh
http://www.pcworld.com.vn/articles/kinhdoanh/giai-phap/2005/06/1187654/he-

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