GEORGIA INSTITUTE OF TECHNOLOGY MICROELECTRONICS RESEARCH CENTER “REDEFINING THE LEADING EDGE” CLASS HANDBOOK Course EE / ChE 4752 Microelectronics Processing Laboratory Sine ae 894.2520DEAR STUDENT: REPRODUCTION OF COPYRIGHTED MATERIAL, WITHOUT PERMISSION OF THE COPYRIGHT OWNER, PARTICULARLY IN AN EDUCATIONAL SETTING, IS AN ISSUE OF CONCERN FOR THE ACADEMIC COMMUNITY. UNFORTUNATELY, THE IMPROPRIETY OF MUCH UNAUTHORIZED COPYING IS ALTO OFTEN OVERLOOKED BY USERS IN AN EDUCATIONAL SETTING. ALTHOUGH COPYING ALL OR PART OF A WORK WITHOUT ORTAINING PERMISSION MAY APPEAR TO BE AN EASY AND CONVENIENT SOLUTION TO AN IMMEDIATE PROBLEM, SUCH UNAUTHORIZED COPYING CAN FREQUENTLY VIOLATE THE RIGHTS OF THE AUTHOR OR PUBLISHER OF THE COPYRIGHTED WORK, AND I DIRECTLY CONTRARY TO THE ACADEMIC MISSION TO TEACH BESPECT FOX IDEAS AN FOR THE INTELLECTUAL PROPERTY THAT EXPRESSES THOSE IDEAS. WITH THAT IN MIND, GEORGIA TECH HAS SOUGHT PERMISSION AND PAID ROVALTIES WHERE APPLICABLE FOR ALL MATERIALS ENCLOSED. THE PRICE OF YOUR CLASS NOTES REFLECTS THOSE NECESSARY COSTS. ‘Note:, This material comes from Questions and Answers on Copyright for the Campus Community, Copyright 1991 National Association of College Stores, Inc. and the Association of American Publishers.GEORGIA INSTITUTE OF TECHNOLOGY Microelectronics Research Center ‘Microelectronics Processing Laboratory LABORATORY SAFETY: The chemicals and equipment used in this Inboratory are not toy. They are af research level and quality, and must be used with intelligence and respect. Instruction sheets for the operation of major pieces of equipment have becn provided. Refer to these handouts as necessary whea using the equipment. Any machines that are not used by the course should not be handled by unqualified users, ‘Chemical safety is also very important, The majority ofthis handout is dedicated to chemical cones, Depending on your background, these notes will either be a reminder of past concerns, or new material ‘which you may have never seen before. In either case, read them carefully, such that you fully understand them, Ifyou have any questions, please ask your instructor. ‘The lb facility is small for the number of users, Therefore, it isimporlant ta respect other's workspace in the lab, As there will be up 10 six or more students in each lab group, the class must be especially concerned. ‘The course shares the lab space with advanced undergraduate and graduate student researchers. ons important to follow Safety as well as cleanliness requires the use of protective clothing, These should be wom at al! hmes while in the laboratory: ‘Lab Coat Bouffint Cap Shue Covering (booties) ‘Safety glasses —- Prescription cyeglasses are acceptable. Wearing of contact lenses is discouraged. Contact lenses greally increase the likelihood of permanent eye damage should # chemical splash contact the eye, as the chemical can become trapped between the lens. and the eye. If you do wear contact lenses, be sure to notify your instructor, so that proper care can be given if necessary, A supplemental handout describes the safety guidelines in the “researc” clean room downstairs. Be sure ‘that you review that document as well as these handouts, as many af the safety guidelines and concerns areGEORGIA INSTITUTE OF TECHNOLOGY Microelectronics Research Ceater Microelectronics Processing Laboratory SAFETY GUIDELINES: i ‘NO OPEN-TOE SANDALS, BARE FEET, or SHORTS allowed inthe lb. All work with acids and sotvents must be done under an exhaust hood, This includes opening of botties. ‘Never pour excess chemicals back into the original bottle. Discard any excess acid into the sinks with the tap running, and discard organic solvents into the solvent waste bottle ‘under the fume hood, ‘Pexsons handling chemicals shoutd wash hands after use, Food or beverages are not allowed inside the laboratory. Never use laboratory glassware as drinking glasses. Clean up your work area during and after use, DO NOT leave hazards for others. ‘Material Safety Data Sheets are available in the lab for all chemicals used. The instructor ‘will be familiar with these, in case of accidental contact. You should be familiar with safety procedures in case of a spill of a particular chemical. Familiarize yourself with the location of cheraical showers and eye washes. Emergency procedures are posted near the telephone inthe lab. To reach CAMPUS POLICE DIAL 4.2500, Report ALL safety violations and hazards to your instructor.GEORGIA INSTITUTE OF TECHNOLOGY Microelectronics Research Center ‘Microelectronics Processing Laboratory ACID HANDLING: In case of accidental contact with any acid, flush immediately with copious quantites of running water. All bums must be report to your instructor tmmediatcly. ‘When mixing solutions containing acids, always pour acid into water, NEVER the reverse. Begin pouring acids slowly, Excessively violent reactions may occur if mixed incorrectly. ‘This is especially true when mixing Sulfurfe Acid ( H280¢ ). ‘After mixing acid solutions, allow solutions to coat thoroughly before capping, Heat is ‘generated after mixing which can cause pressure in a capped bottle. After use, always cap acid bottles tightly, All chemicals poured into a sink will mix in the piping — please run lois af water between chemicals, and always before and after dumping any chemical into the sink. Keep in mind that while other chemical fuses are strong irritants or corrosive, hydrofluoric acid { including buffered oxide etch, BOE ) is lethal if inhaled, DANGER. HYDROFLUORIC ACID (UE Hydrofluoric acid does not produce overt tissue burns like most acids. However, HF does diffuse through tissue and will dissolve bone, Whereas other acids, bases, and solvents are strong irritants, cumulative poisons, or carcinogenic, HF fumes can be faial, For these reasons, particular caution should be exercised when handling HF. Immediately report any possible contact to your instructor.GEORGIA INSTITUTE OF TECHNOLOGY ‘Microelectronics Research Center Microclectronics Processing Laboratory SOLVENT HANDLING: ‘Organic sotvents, such as acetone and trichloroethylene, will react with acids or other strong, oxidizing materials such as hydrogen peroxide. DO NOT MIX THEM. A mixture of nitric acid and acetone, for example, is highly explosive, Solvents should be poured into the waste solvent botile located in the furne hood. |. Most solvents present some degree of toxic hazards when their fumes are inhaled over a prolonged period. Always work with solvents in an exhausted hood. Avoid getting solvents onto the skin. Solvents are readily absorbed through the skin and into "the bloodstream. Some solvents, suchas trichloroethylene, are carcinogenic. Solvents are generally quite flammable. Though there are few ignition sources in the lab, always be cautious of solvents near any source of a spark. ;. Photoresist conizins organic solvents as past of its makeup. These solvents can be as ‘hazardons or more so than the other solvents used in the faboratory. Avoid skin contact or breathing the fumes of photoresist. room temperature, and i highly toxic. Notify your instructor if you break a ‘Mercury evaporates: ‘thermometer or spill mercury. UV light sources ( present in the mask aligners } are normally quite safe. However, when these lamps approach thelr useful end, they can ovecheat and explode. ‘This releases toxic mercury fumes into the room. Should this happen, immediately leave the area and notify your instructor. After turning off a norma! UV lamp, it must cool for 30 minutes before restarting. Failure to do this may ‘result in a bulb explosion,GEORGIA INSTITUTE OF TECHNOLOGY ‘Microelectronics Researcit Center (CLEANROOM PROCEDURES: In order to preserve the integrity of work in a semiconductor processing facility, a number of “clean” practicas must be followed. Dirt, dust, fingerprints, perfume, hair sprays, sneezes, ec, ae the scourge of ‘the semiconductor industry. Steps must be taken to protect your devices from contamination, or fabricated devices will at function as desired. Itis important to keep wafers covered except when processing. Also, ‘keep your tweezers and other objects used for handling wafers clean. Follow all cleaning procedures carefully, and once cleaned, transfer wafers without delay to the next process. The written procedures are esigned to minimize contaminants if followed. 1 2 Always wear all of your protective clothing. ‘Do not bring pencils into clean ream, . Remain in clean arcas only when processing, No visitors without permission. |. NEVER pat your head in laminar Slow, especially over wafers. |. Move hands stowly in and out of laminar flow. |. Avoid tapping feet or running in clean areas. 7. Never touch wafer holders without gloves. - Always uso complete cleaning procedures, ). Never handle wafers with metal tweezers after an RCA clean. ), NEVER touch metal tweezers to quartz fumace boats. . Do not allow furnace pushrods and thermocouples to touch anything except designated ‘furnace tubes, boats and holders.2 %. 10. SAFETY QUIZ - GEORGIA INSTITUTE OF TECHNOLOGY Microelectronics Research Center CHE 4762 / EE 4752 Microelectronics Processing Laboratory Should you add acid to water or water to acid, why? If someone is not following the safety procedures, give two possible actions you could take? 1.) 2) Name 3 pieces of safety clothing for this lab: 1 2) oo? 3) Give two reasons why HF is dangerous: 1) 2) Give two reasons why solvents should be used in a hood: 1) 2) You are about to use the mask aligner and someone turned it off, what should you do before restarting it? What do you do if someone spills acid on their clothes? What do you do if someone spills acid on their face? Why shoutd you not mix acids and solvents? What is the emergency phone number?GEORGIA INSTITUTE OF TECHNOLOGY ‘Microclectronics Research Center ‘Microelectronics Processing Laboratory SUBSTRATE CHARACTERIZATION PROCEDURE: Itisnecessary to charnctetize the starting material in a semiconductor process, a the material dopant type and amount must be correct for a certain process to work as designed. ‘This lab process requires wafers of the following characteristics: © Nee (Phosphorous dopant ) © 10410 cm? ‘Dopant concentration © <100> Crystal Orientation + $200m ‘Wafer Resistivity ‘The first set of mensureaoents isto veify that the starting material has these necessary characteristics. The tests are destructive, so the coutiol wafer used here is not processed. 1. Oncontrol wafer, C, determine the earier type (nor }using the hot probe, 2. Measure dhe wafer thickness with the micremeter, 3, Measure the wafer sheet resistivity in O/ square, using the 4-pt probe, Multiplying by ” the thickness will yiold the bulk resistivity, Given that the mobility of electrons is 1800 cm 7/ Vs, what is the dopant concentration? 4. Check location of wafer flats to verify crystal orientation. The secondary flat opposite the primary fat, signifies ntype < 100>, Other dopant types and orientations have ifferent locations forthe secondary flat. 5, Using a diamond serie, or sharp tweezers, itis possible to break a wafer cleanly slong the orientation plane, After other characterizing measurements have been taken, brealc 1p the wafer in onder to cbserve the single-crystal nature ofthe substrates.GEORGIA INSTITUTE OF TECHNOLOGY Microelectronics Research Center Microelectronics Processing Laboratory .TION OF Ci TYPE: Ahot probe may be used to determine the majority carvier type of a semiconductor with resistivity less than 10000-cm, Two sharply-pointed metal probes are used to contact the sample, One of the probes is heated while the other remains at room temperature. A galvanometer is used to detect rhe direction of current flow between the two probes: {energy moves away) toad [more are left behing] "ake ‘substrate under test “The majérity carriers under the heated probe have greater thermal energy than those in the cooler portions ‘ofthe wafer, These higher energy carriers diffuse away from the probe leaving 2 net fixed charge at the ‘hop probe with polarity opposite to majority carsier type. Am electric ficld is then established in the semlcondactor between the majority carrier type. An electric field is then established in the semiconductor between the majority carers diffusing away from the hot probe aud the fixed charges left behind. ‘The potential Cus generated is detectable at the probes using an electrometer, Alternately, the flux of ruajority carriers can be measured using an ammeter. A positive potential implies n-type material while a negative potential implies p-type material.( SHOULD BE DONE IN ORDER ) ORGANIC CLEAN 8) 0-2 15 min, BUBBLER RINSE 5 min. HF, DP 15 sec, BUBBLER RINSE -~----reeseessevernosererere 3) S80. TONIC CLEAN —-v~onerncereenwereeeeeenanee 8) 0C mip. BUBBLER RINSE 15 min. N2 DRY CLEANGEORGIA INSTITUTE OF TECHNOLOGY ‘Microelectronics Research Center Microclectronies Processing Laboratory ‘RCA PROCEDURE: ‘This is cleaning procedure that should be done of wafers that will goin any of the high temperate fumaces, ‘Wafers to be cleaned should have a Si, S10, or SizN, surface, and not have gone through & i. This handout is intended to serve only as a guideline; 2 MUS dnstroctortovuse the cleaning station, you wish to devi fom tis procedure or have ay queslins, ‘consult with your laboratory instructor. NOTES = Wear poly gloves while working in clean station Due to safety seasons, keep hood sash down when not in use. © Use the white Teflon wafer carricr for the clean. . «Use fresh chemicals for each clean. . ‘© Chasmicals should net be brought oa boll, as this causes rapid decomposition of #03, . i i i.c., organic or ionic ) beaker, graduated ‘© Allways place carrier handle and TEFLON tweezers in solutions and rinses with carrier and wafers. A. Start-Up 1, Tum on DI water flow to the rinse station. The knob is tocated in the front of the station . Take care that the knob is not opened too far, as this could cause overflowing of the station. Consult your laboratory instructor if you are unfarailiar wilh the setup. 2. Tum on Ngflow knob to the rinse station. Thisis done by adjusting the regulator knob located. next to the DI knob in front of the sink. When correctly adjusted, ere should be a genlle ‘bubbling of nitrogen through the rinse station. 3. All cleaning solntion should be made af the same time to minimbe delay in processing, Thus, as soon as the organic semoval solution hes been made and is eating, start on the fone solution,B. ORGANIC CLEAN Prepare solution for organic clean Tn quartz tank marked (0), ‘Add: 1000 ml DI(H,0 ) 200 mi HO; 200 ml NELOH . Tum Heft hot plate switch ON and adjust the hot plate temperature to 350, The solution should ‘heat for 15 minutes, in order to reach 80°C, |. Sobunerge wafers into the warning solution as soon as possible, }. Duting heating time, prepare sofutions for Ondde Stripping and lonie Removal (see below}. 5. When the organic solution begins to bubti, immerse the wafer carrer with your wafers for 15, minntes, Remove carer and wafers from left tank, and immediately place inthe bubblicr rinse tank for S sminntes. |. Tum off hot plate and allow solution to cool to room tertperature, C. OXIDE STRIPPING 1 3. To be done during step #4 above: “The following HF solution will be prepared by the baratory instructor: Inthe left polypropylene vat marked HF TANK, a 50:1 HF dip as follows: ‘Add: 4500 ml DUH (tank is racked to the required level ) $0 mi HF Remove the cartier and wafers from the bubbler rinse, and carefully submerge it into the °50:1” HF solution agitating inthe direction ofthe wafers for 15 seo. ‘Transfer the: carrier to the bubblier for 30 seconds. (This should not be any longer, as to avoid ‘reformation of a hydrous oxide film). |. Immediatcly transfer to Hot Ionic Clean ( right quartz vat).D. IONIC CLEAN 1. Tobe done during step #4 of Organic Clean: Prepare solution for ionic clean in quartz marked (1), ‘Add: = 1000 ml DI(H,0) 200 mal 02 200 ml HC 2. To be done during step #4 of Organic Clean: ‘Tum left hot plate switch ON and adjust the hot plate temperature to 350. The solution should heat for 15 minutes, in order to reach 80°C, 3. Submerge the still wet wafers from the HF Rinse into the Hot Ionic Cleaning sotution, 4, Maintain wafers in 80°C solution for 15 minutes. 5. After 15 minutes has elapsed, transfer wafers directly to the bubbier rinse. 6. Tum off hot plate and let solution cool to room temperature. E, FINAL RINSE AND DRY 1. Rinse the wafers in the bubblier rinse tank for 15 minutes. 2. After wafers have rinsed for 15 minutes, remove from bubblier rinse and place wafer carrier in black box, transfer to wafer dryer using standard procedure 3. Tum off DI water and No flow to rinse tank. 4. Afier completing drying cycle, carefully remove wafer carrier back into the black box replace cover, transfer to furnace boat loading area, and immediately load wafers into the furnace. 5. After hot solutions have cooled to room temperature, empty and rinse the cleaning tanks with DI water,GEORGIA INSTITUTE OF TECHNOLOGY Microelectronics Research Center Microelectronics Processing Laboratory FIELD OXIDATION PROCEDURE: ‘This process will thermally oxidize the silicon substrate. The oxide grown will bea thick field oxide to isolate the devices and define the source and drain regions for subsequent diffusion. 1 RCA clean device wafers and control wafer C2. Refer to RCA Clean handout for procedure in substrate cleaning station, During the cleaning, continue with the next three items, preparing the oxidation furnace. ‘Verify that the gases flowing through the furnaces are in the IDLE CONFIGURATION: Note that in the idle configuration, nitrogen gas is flowing through all three Furnaces. ‘Tum on the oxidation furnace and adjust it to 900°C. This is accomplished by adjusting the furnace controller in the back of the furnace clean hood. Fill bubble flask with DI water and tum the controller dial to 50, then immediately back to 25. This will start heating the water in the bubblier to a temperature between 90 and 100°C. ‘At the completion of the RCA clean, remove the quartz boat from the fumace using, appropriate push rod and quartz boat loader. fare gloves when handlir ‘DO NOT hold push rod in front of mark ‘onred, Keep the boat in the boat loader and set the boat loader down in front of the furnace tubes, taking care that holder and boot remain in laminar flow. Place the RCA ~ cleaned wafers, stl in their carrer, into the carrer box, and transport them to the fumace loading station. Load wafers onto quartz boat using Teflon or Teflon tipped tweezers, Avoid passing arms or head over cleaned wafers. ‘With boat loades, retum wafers on boat to oxidation furnace. Slowly push boat into the mouth of the famace with push rod, to avoid wafer fracturing due to thermal stress, Push ‘the quartz rod in just to the point where the mark on the push rod is even with the metat door to the furnace, This will place the center of the boat at the center of the fumace. ‘The fietd oxidation process is to be carried out at 1100° C, The process is: Load in; (Idle gas) Dy $ minutes Wet O2 120 minutes Dry 02 5 minutes Unload in, . (Idle gas) pao ep10, 11. 17. 18. 19. Ramp the furnace controller up to the oxidation temperature of 100°C. Lock in ramp mode. Wait until the temperature has stabilized (about 10 minutes ). Begin dry oxygen flow through the tube. >> tum oxide furnace valve to O2 >> valve to Dry or Wet should be facing Dry Dry oxygen is now flowing through the tube ADJUST the flow rate to 94.70 scom, (standard cubic centimeter minute ). ‘When 5 minutes have elapsed, begin WET oxygen flow through the tube. >> tum valve from DRY to WET Wet oxygen ( .e., a combination of oxygen and steam ) is not flowing through the tube. Note that oxygen is flowing through the bubblier mounted in the back of the furnace. ‘When 120 minutes have elapsed, start DRY oxygen flowing through the tube. >> tum valve from WET to DRY ‘Tum OFF HEATER to the wet oxidation bubblier. ‘When 5 minutes have elapsed, start nitrogen flowing through the tube, Le. return the gas delivery system to its DLE CONFIGURATION: >> tum oxide furnace valve to Nz Set furnace to 900° C, lock in ramp mode and wait 10 minutes for it to cool to approximately 900° C. Pull wafer boat slowly to the mouth of the fumace with push pull rod. Let wafers cool briefly before completely removing boat from furnace. Make sure that the wafers stay in laminar flow hood at all times. Allow wafers to cool completely in boat before removing and storing in Nz dry box. With boat loader, return boat to oxidation furnace. Slowly push boat into fumace with ‘push rod, approximately 14 of the way into the furnace tube. Loosely replace end cap and store boat holder inside the metal furnace door. Estimate the thickness of the grown oxide using the color charts as well as your calculation of approximately how thick the grown oxide should be. ‘Mcasure grown oxide thickness of control wafer using Ellipsometer, referring to Ellipsometer procedure ( this may be deferred to later lab for time reasons }.GEORGIA INSTITUTE OF TECHNOLOGY Microclectronics Rescarch Center Microelectronics Processing Laboratory ‘LAYER THICKNESS MEASUREMENTS, Color: Both silicon dioxide and silicon nittide layers exhibit different colors on the wafer. We know that silicon dioxide is transparent ( glass is silicon dioxide), yet it has a color ona wafer. The color is actually the result of an interference phenomenon, the same phenomenon that creates the colors of rainbows. ‘The silicon dioxide layer on a silicon wafer is actually a thin transparent film on a reflecting substrate. ‘Some of the light rays impinging on the wafer surface reflect off of the oxide while others pass through the transparent oxide and reflect off of the mirrored wafer surface, When the light rays exit the film, they combine with the surface-reflected ray, resulting in a color. ‘The exact color is f function of three factors. One, which is a property of the transparent film material, is the Index of Reftaction, A second factor is the viewing angle (rotate an oxidized wafer and the surface color will change ), The third factor is the thickness of the film. ‘The color of a thin transparent film becomes an indication of the thickness when the nature of the viewing light is specified (ic. daylight, fluorescent ), along with the viewing angle. The classic color vs. thickness chart is a regular feature at oxidation and diffusion stations. Color alone is not an exact indication of thickness, due to the consequences of the interference phenomenon. As the film gets thicker the color changes ina specific sequence and then repeats itself. Each repetition of the coloris called an order, To determine the exact film thickness, a knowledge of the color order is necessary. A principle use of color charts is for process control. ‘Each oxidation or silicon nitride process is designed to produce a specified thickness. Naturally the thickness will vary run torun. Operators quickly become sensitive to the usual color, When a variation ‘occurs, quick check of the chast will indicate if the film thickness is out of specification. Rarely isa. ‘process so far off that the film thickness is a whole order (same cofor, different thickness } ont of specification, The accuracy of color chart thickness determination is imited to the accurate perception of the colors ( what exactly is red-orange). A typical chart is accurate to 300 angstroms. Bllipsometers: Buipsometers are film thickness instruments that use a laser light souree. ‘The laser light source is polarized, The effect of polarization is to create a wave that is traveling in only one plane. Polarization ccan be imagined by considering looking into the beam of a flashlight. Tn an ordinary beam light rays come to your eyes in many planes, like an arrow with many feathers. A polarized beara has al ofthe light in only one plane, or an arrow with only one feather, Inthe ellipsometer the polarized beam is directed to the oxide covered wafer at an angle, The beam enters the transparent film and reflects off of the reflective wafer surface. During its passage through the film the ‘angle of the beam plane is rotated. The amount of rotation of the beam is a function of the thickness and index of refraction of the film. A detector in the instrument measures the amount of rotation and an on- ‘board computer calculates the thickness and index of refraction. Ellipsometers are used to measure thin oxides ( 50 to 1200 angstroms ). ‘Their accuracy in this range is unequalled by other techniques.Table 7.4 Color Chart for Thermally Grown $10, Films Observed Perpendicularly Under Daylight Fluorescent Lighting? Film Film ‘Thickness ‘Thickness : 4 Color and Comments (am) _,.__ Color and Comments 0.05 Tan 063 Violet red ©.07. Brown 0.63 “Bluish" (Not blue but ~ ©.10 Dark violet to red violet borderline between violet O12 Royal blue and blus green. It spears O.1S |. Light blue to metallic Blue wort Hike a mixture O.17 Metallic to very light between violel red and blue yellow green etn and looks grayish) 0.20 Light gold or yellow— 0.72 Blue green to green (quite slightly metallic broad) 0.22 Gold with slight yellow 0.77 Yellowish" orange - 0.80 © Orange (rather broad for 0.25 © Orange to melon orange) 0.27 Red violet 0.82 Salmon 0.30 Blue to violet blue ©.83 Dull. Hight red violet 0.31 Blue 0.86 > Violet . 0.32 Blue todlue green 0.87 Blue violet 0.34 Light green 089 Blue 0.35 Green to yellow green 0.52 Blue green 0.35 Yellow green 0.55 Dull yellow green 0.37 Greeo yellow 097 "Yellow to “yellowish 0.39 = Yellow 0.99 Orange 0.41 Light orange . 1.00 Carnation pink 0.42 Carnation pink 1.02 Violet red 0.44 Violet red 1.05 Red violet. 0.45 Red violet 7 1.06 Violet 0.47 Violet 1.07 Blue violet 0.48 “Blue violet 1.10 Green : 049° Blue 1.11 Yellow green 0.50 Blue green 1.12 Green 0.52 Green (broad) 1.48 Violet 0.54 = Yellow green “LAS Red violet 0.56 - Green yellow 4.21 Violet red 0.57 Yellow to “yellowish"’ (not. 1.24 Carnation pink to salmon yellow but is in the position 4.25. Orange : where yellow is to be 122 “Yellowish expected. Al times it 132 Sky blue to green blue + «appears to be fight creamy re way oF metallic) 143 Viviet 0.53 Light orange or yellow to 5.45 Blue violet pink borderline 1 Blue 0.6) _Carmation pink 1.54 Dull yellow green * See reference 57,138 VLSI Teanciocy ‘Tadle 1 Rate constants for wet oxidation of silicon Pricer Leer ee romero Aun Boxtn Fate 70) 1x0 00s 0720 Hw o 10 on | 0510 4h © 1000 02% 8 60287 127 © = 050 | (O28 0.406 © palecof s 3 Gefined nF J 14 rust be used. Table 2 lists the values of rate constants for dry oxidation of silicoa* Examination of Eq. 1b reveals that B $s expected to be proportional to C*, which, acconding to Henry's law, is proportional to the parti: Frrsrare oF the ena. ing species. However, A should be Independent of the partial pressure. ‘This has indeed been confirmed experimentally for both wet ard dry oxidations®-* in the tem- eer ana Desens beeen Oe ee ‘The pressure "pendence of A means that the linear rate constant BVA has the same Tinear pres- sure Uepensence as B. Figure 31 shows the effect of temperanure* on the parabolic rate constant B for ‘both dry and wet oxygen at 640 Tort and for wet oxygen normalized to 760 Torr using the linear pressure Gependence. As might be expected from Eq. 14, the temperature Gependence of B is similar to that of D, that is, B increases exponentially with tem- perature. For dry oxygen the activation energy for B is 1,24 eV, which fs comparable to the value of 1.17 eV for the diffusivity of oxygen through fused silica (similar in ‘structure to thermal Si0;). The wet oxygen activation entrgy (0.7) eV) also com- pares favorably with the activation energy for the diffusivity of water in fused silicon ©.80eV). Figure 3b shows the temperature Gependence of the linear rate constant B/A for ‘berh dry and wet oxygen at 640 Torr and for wet oxygen normalized to 760 Torr. Once again an exponertisl dependence is observed with activation energies 1.96 and 2.0 eV for wet and dry oxidation, respectively. Deal and Grove‘ show that these ‘Table 2 Rate constants for dry oxidation of silicon 100 200 OS wiz O07 nc 000 == (Oar 030 0.076 0 ©.165 0.0117 0071 037 2.0019 0.0208 10CMOS Fabrication Process 6 Mask Design Mask # 1 P-Well Mask # 2 P* source/drain Mask # 3N’ source/drain Mask # 4 gatelcontact Mask # 5 contact, Mask # 6 reverse fieldMicroelectronics Research Center 4751 CMOS Integrated Circuit Design EI (pel faPHOTORESIST THICKNESS: THE PHOTORESIST THICKNESS IS ACTUALLY DETERMINED BY SEVERAL RESIST-RELATED FACTORS AND TWO SPINNER-RELATED FACTORS, THE PHOTORESIST FACTORS, INCLUDING SURFACE TENSION, SOLIDS CONTENT AND VISCOSITY GOVERN THE DEGREE OF "SPREAD" OF THE RESIST PUDDLE AS THE WAFER IS AGGELERATED TO HIGH SPEED. SURFACE TENSION AND SOLIDS GONTENT ARE CONSTANT FOR A GIVEN RESIST, WHILE THE VISCOSITY IS THE PROCESS VARIABLE, ACGELERATION AND FINAL SPIN SPEED ARE THE TWO SPINNER FACTORS. GENERALLY, THE SPINNER ACCELERATION IS SET ATA CONSTANT, REACHING 5000 RPM IN ‘ABOUT 4.5 SECONDS. PHOTORESIST THICKNESS CAN ALSO BE INFLUENCED BY THE AMOUNT OF PHOTORESIST APPLIED AND THE TIME OF THE SPIN, BUT ONLY IF . THESE FACTORS VARY IN THE EXTREME. FORTUNATELY, BOTH OF THESE FACTORS HAVE WIDE RANGES AND ARE NOT NORMAL PROCESS VARIABLES IN DETERMING RESIST THICKNESS. FOR A GIVEN VISCOSITY, THE FILM THICKNESS WILL DECREASE WITH INCREASING SPIN SPEED. INCREASING THE VISCOSITY FOR THE SAME SPIN SPEED WILL INCREASE THE FILM THICKNESS, THE COMBINATION OF ALL THREE FACTORS RESULTS IN A FAMILY OF CURVES AS ILLUSTRATED; Resist ©@ So =2— alm,” gum) Insulfictent Complete Resist . Excessive Resist Coverage Coverage oon C) | Spin Example of Resist Coverage{a} Positive & negetive resist exposure characteristics 1 “PERCENT RESIST REMAINING AFTER. + + - EXPOSURE & DEVELOP. MENT L0G EXPOSURE ENERGY [mJfem4 [b)FesIst images alter devetopinent vy bey yoy NEGATIVE RESIST : POSITIVE | RESIST EXPOSURE RADIATION RESIST: Resists may be either negative or positive. Negative resists becomes less soluble in developer when they are exposed to radiation, and positive resists become more soluble after exposure. The typical negative and positive resist exposure response curves. At low-exposure energies the negative resist remains completely soluble In the developer solution. As the exposure Is increased above a threshold energy Ey, more of the resist iilm remains after development. At exposures two or three times the threshold energy, very little of the resist film Is dissolved. For positive resists, the resist solubility In Its developer Is finite even at zero-exposure energy. The solubility gradually Increases until, at some threshold, It becomes completely soluble. Response curves such as these are affected by all the resist-processing variables: Initial resist thickness, spectral distribution of the exposure radiation, prebake conditions, developer chemistry, developing time, and so on. These curves éan therefore be used to characterize the complete photoresist process. Positive resists usually require niore exposure energy (longer exposure times) than negative resists to form resist images. Exposure tool throughput is therefore less when positive resists are used.Correct Develop ere giit iy) mural vii vi VFA . _ Severe, Overdevelop) Mier Develop . Tee Photoresist development Process and Problems;_ After the wafer completes the alignment and exposure step, the device or clrcult pattern is coded in the photoresist as regions of exposed and ‘unexposed resist. The pattern Is “developed” in the resist by the chemical dissolution of the unpolymerized resist regions. Development techniques are designed to leave In the resist layer an exact copy of the pattern that was on the mask or retlole. Problems resulting from a poor developing process are underdevelopment, which leaves the hole incompletely developed to the correct dimensions, or a coved sidewall. In some cases, the development wiil not be long enough (Incomplete) and will leave a layer ofresist in the hole. The third problem is overdevelopment, which . removes too much resist from the Image edge or top surface. Negative and positive resists have different developing characteristics and require different chemicals and processes,GEORGIA INSTITUTE OF TECHNOLOGY Microelectronics Research Center ‘Microelectronics Processing Laboratory “This procednre outlines the operation of the Karl Suss Mask Aligner, Wafers to be exposed in the aligner should have the resist properly softhaked, to prevent damage to the aligner. Al? users MUST have explicit permission to use the aligner. SAFETY NOTE: ‘The aligner uses a mercury arc lamp, Follow proper procedures, to avoid possible explosion and exposure to mercury vapors, Once lamp is on, do not torn off uatil the end af the day. IFit is tumed off, it must cool for 30 minutes before restarting A. STARTUP ‘Note: The aligner may already be on when you come Inio the lab. If so, proceed dircclly to part B. 1, ‘Tumon ths toggle valve located on the gas control panel. Verify proper flows on gauges, reading 4 bar, 2 bar, and 1 bar from left io right. These values are noted just below each gauge. 2. Flip toggle on bulb power supply ON. Allow power supply to warm up a few minutes. 3. Press button labeled ‘start’ to start Hg arc lamp, Tt will take 10-15 minutes for the bulb to come up to its final reading of approximately 200 watts. 4, Turm on power to aligner itself by pressing the zed button marked ‘pawer’ on the aligner panel, Verify that the ‘soft contact” and ‘ST” fights are lit. B. LOADING MASK 1. Remove mask holder from Jocation in sligner by loosening thumb screws and sliding out to the fen, 2, Place mask pattem (etmulsion or ctome } side up on underside of mask frame, Center mask over vacuum groove, aligning it square with the frame. ‘Hint: "The mask is square and can therefore go into the mask holder in aay one of four artentations, “Always put the mask onto the holder inthe seme orientation (i.g., words on mask pointing “north” ); this ‘vill save you an enormous amount of grief when aligning subsequent masks. 3, Push ‘Vacuum Mask’ button and verify that the mask is held in place, 4. Turing mask frame over, reload into nligner sliding it all the way to the right. The mask should be underneath, with the pattern side now facing down: Tighten thumbscrews lightly, holding mask frame and mask in placs.‘To view mask, and eventually wafer, the microscope light must be tumed on. The control for this light is located on a small box to the left af thealigner. To manipulate the. microscope objective as needed, use the handle { joystick } that hangs from the left of the aligner. Ithas two buttons on it, which when depressed release air brakes that hold the microscope head fixed in position, One releases the x direction, the other the y direction, C, WAFER LOADING 1. 4 Place wafer on chuck, Ifthe wafer is whole, place it such that primary flat of wafer is pointing in one preferred direction (e.g,, to the left}. Be consistent; sec “hint” in section Babove. ‘Depress the small silver bation on the stage, drawing a vacuum on the wafer. Hold ‘bution while sliding stage into aligner. Slide it just until it stops; there is no need to force it ‘On the left side of the aligner there are. two levers. (a) Separation Lever ‘This lower one slides forward and back ina plane parallel to the table, This lover is for bringing the wafer just out of contact with the mask in order to perform any necessary alignment, (>) ContactLever - 5 “The lever on top has a range of motion through 180° in a ptane parallel to the ‘side of the atigner. The function of this lever is to bring the wafer chuck up into contact, from the lowered position it occupies when first entering aligner. ‘Using the Contact Lever, move it through 180° counterclockwise, raising wafer into ‘contact, Looking through te microscope, shadows should appear, then disappear, as the ‘wafer comes into contact with the mask. This contact should occur with the lever having ‘passed through % of its motion. Any adjustment to this height is made with the variable ‘thickness control an the lower front ofthe aligner ( if such adjusiment is necessary, alert ‘your laboratory instructor), If this is the first mask step, and no alignment is necessary, continue with Exposure Procedure section E below. Otherwise, continue with Part D. D, ALIGNMENT “Alignment is probably one of the most difficult jobs that you will do in this fab. Tc takes a few tries to become ‘expert’; don't get discouraged. 1 ‘With the wafer in contact, focus the microscope on the mask and wafer. Use a low power objective. Put the wafer into the separation pasition, by moving the Separation Lever all the way towards the front of the machine. ‘The contact light will go out.3. Rotate ona of the alignment micrometers to verify freedom of motion of the wafer. This will be difficult if there is no wafer patter in view, It is possible that the wafer will not move freely duc to a spot of resistor soie other reason. If this is the case, put it back into contact, then drop wafer out of contact with Contact Lever, slightly lower stage with variable thickness adjustment, and return wafer to contact. Remember to alert your instructor before you use the variable thickness adjustment. 4 To performatignment, find alignment marks near the center of the mask. Then move microscope, searching wafer underneath for alignment marks. Once found, use the xand y manipulators to bring alignment marks together. Each micrometer has both a course anda fine adjustment. The course ( which should primarily be used ), is the smaller knot in the middle of each micrometer. 3. ‘Now that alignment marks oa both wafer and mask are visible together, adjust © as necessary. Do the best you can to align this one set of marks. 6. Move microscope objective to one side ofthe wafer, releasing it in only the « direction. Observe alignment at thisend. Do not expect ito be great. Now: a ‘Move wafer 4 way in to alignment using y manipulator. Bb. Use © manipulator to adjust alignment as well as possible in the yy direction. ¢. Adjust x manipulator to achieve ‘perfect” alignment, 7. Move objective to opposite side of wafer. Again check alignment, and repeat previous sequence of steps. 8 Iterate back and forth until satisfactory alignment is achieved. Tt may take many iterations, depending on the amount of care taken at each step. 9. Move Separation Lever to its rear position, relighting the contact light, 10. Thealignment can now be checked using a higher power objective if desired. Le it is unsatisfactory, retum to Separation, and (widdle aligament more. E, EXPOSURE WARNING!!! During exposure, ultraviolet light floods the wafer surface. Invariable, some light will escape. As ultraviolet light is damaging to your eycs, DO NOT LOOK AT THE LIGHT DURING EXPOSURE 1. Set exposure timer fo correct value for your application (in seconds ). 2, Verify that bulb power supply is reading approximately 200 W. 3, Onbulb power supply, swiich to Cl by depressing bution. The display should now switch to zero, indicating the UV exposure energy at the surface of the wafer, ~ 4, Before exposing, check: a, Waferisin contact, as displayed by light. b. ——_Timeris set correctly,Move head away from microscope, and depress EXPOSURE button. The bulb readout should read approximately calibrated mW per square centimeter, While resist is being exposed, DO NOT LOOK ATLIGHT, ‘When exposure is complete, unload the wafer by rotating the Contact Lever 180° clockwise to the front. Slide the transport slide carefully to the right, and remove wafer from the chuck, F, DEVELOPMENT Note: Wafer development is to be done in the fume hood. 1 2. 3. Pour 500 ml of Developer 354 into a first clean beaker. Pour 600 ml of deionized water into a second clean beaker. Place exposed wafer into a wafer holder and agitate lightly in the developer for 30 seconds, Remove from developer and quickly place wafer in deionized water for 30 seconds, Agitate lightly. Hold wafer over sink and lightly spray with deionized water from the water gun for 30 seconds. ‘Dry wafer using nitrogen gun, Inspect under microscope to determine how successful the photolithographic process has been, Ifthe pattems do not come out, you may have to start all over again ( see photoresist application procedure ). Tf pattems are well defined, postbake the wafers for 30 minutes at 120°C,3. Field ‘Oxidation 4. Mask #1 5.6. B.O. Etch PR removal 8. P-Welll Predeposition 9, Boron glass removal 11, P-Well dsive in 12. Mask #2 13.14, B.0, Eteh PR removal CMOS process cross-section view schematic ‘SiOz N-sub PR -——si0, Ne-sub S10, N-sub + F SiO; Nesub ‘SiO; PR SiO; N-sub moo SiOz Well16. P+ Predeposition 17. Boron glass removal 19. Field ‘Oxide for N+ diffusion 20. Mask #3 21. 22. B.O. Etch PR removal 24. N+ Predeposition 25. Phos plus glass removal 26. Mask #4 tee ee eee dd Boron (P+) deposition | -—~si0, cus }———Si0, ‘N-sub, tty + ET VEE EF Phosphoms av deposition t—sio,27. B.O. Etch PR removal Gate SiO, a | ~~(Gate + Field) SiO, P+: drive in 30. Gate” Oxidation PR (Gate + Field) SiO, 31, Mask #5 32, 33. B.O. Etch PR romoval Al 35, Metallization |__ _o=m a }___ (Gate + Field) SiOz 36. Mask #6 37. B.O. Etch PR removal ~40.GEORGIA INSTITUTE OF TECHNOLOGY ‘Microclecironics Research Conter Microctectronics Processing Laboratory BORON DIFFUSION PROCEDURE: ‘This lab introduces the solid-source method for dopant diffission. In this case, a Boron ( p-type ) diflusion ‘will dope the source / drain regions which are defined by gaps in the ficld oxide. Methods for evaluation of the diffused layer will be performed later, The boron source is a ceramic wafer of boron nitride ( BN ), which has been oxidized in a 1000° C 25% 0, abnosphere resulting in a surface layer of B203 glass. ‘During this infinite — source or pre-deposition step, this glass slowly evaporates from the BN wafer and ‘condenses on the silicon wafer. This thin layer of B203 provides elemental boron for diffusion into the Silicon via the. “ 2B203 +Si >4B4+3Si0, After the desired amount of boron is depasited on the silicon wafer, the BN source wafers are removed the boron is diffused into the silicon wafer during a high temperature drive-in step. In our process, the drive-in ‘will occur during the subsequent GATE OXIDATION STEP. 1 RCA Clean device and contro! wafers ( refer ta RCA clean handout ). Check that the Boron diffusion tube is idling at 600° C with nitrogen flowing through the tube. Before cor during the clean, the instructor will prepare source wafers as necessary suing the following procedure, . . ‘Oxidize BN wafers at 900° C in 25% 02 for approximately six hours. This is not necessary for every use, as the source are compromised if oxidized too frequently. After oxidation, the BN wafers need to be stabilized in N? in the furnace for at Jeast 30 minutes, ‘The source wafers should then be stored at the mouth of fumace tube, to avoid hydration. 2. At completion of RCA clean, load wafers into boat with sources. ‘The wafers should be inserted such that the device side of cach is facing a BN source wafer. There arc two wafer slots between sources, allowing for a device wafer facing out to both sides. 3. Load the boat into the mouth of the furnace for the pre~deposition diffusion © 4. ‘Check that the gas system is in the JDLE CONFIGURATION: >> Oxide Furnace valve is facing Ne Note that in the idle configuration, nitrogen gas is flowing through all three furnaces. 5. Tum the fumace controller up to the deposition temperature of 935° C. Wait unull the temperature has stabilfzed ( about 10~ 15 minutes )10. 11. 12, 1s. Begin appropriate nitrogen flow through the tube. >> Adjust the flow rate to 87.11 sccm ( 1000 / standard cubic centimeter per min). Wafers should be loaded in the wafer boat, between each solid source of boron and placed in the mouth of the furnace tube, Push the wafers into the center of the tube ata continues movement until you reach ‘center zone using the pushrod. ‘When 30 minutes have elapsed, boron deposition is completed. ‘Using pushrod retum wafers back to the mouth of the furnace using the same procedure as in step 8. ‘Tum the temperature controller down to 600° C. Allow the wafers to coof down in the mouth of the tube for a least 5 minutes before removing ‘Remove the boat from the furnace and allow the wafers to continue to cool before removing them from the wafer carrier, ‘The wafers are now covered with borosilicate glass, which served to dope the exposed source / drain regions and the polysilicon. Other areas of the wafer surface were masked from diffusion by the field oxide, . ‘When wafers are cool, place them in the RCA wafer carrier and dip them back into the HF bath for 15 seconds and rinse for 2 minutes, This is to remove outer boron film from ‘surface that is no longer needed. NOTE: The sheet resistance will increase when the Boron is removed from the surface because the boron doping tends to increase conductivity ( and therefore reduce resistivity ). When this boron is removed, the conductivity decreases and the resistivity (as well as sheet resistance ) goes up.PHOS PLUS High Purity Planar Dopant Sources PhosPlus Planar Dopant Sources Have Widespread Uses. PhosPlus planar diffuston sources represent e significant edvancement in the field of phosphorus dopant materia's. Thair ability to easily and uniformly dope large-diameter slicon wafers in a safe manner accounts for thelrincreasing popularity in the semfeonductor industry. in genersl, PhosPlus sources offer ell the advantages tradifonally associated with planar sources plus they possess a number of additional improvements which make them the most desired phosphorus source available to the diffusion engineer. ‘Three PhosPlus Sources Provide Versatility. Three PhosPius sources are avatable to meet the many silicon processing requirements of the semiconductor industry. The following temperature ranges are normally recommended for thelr use: [- Source Type | _ Recommended | Approximate Sheet _ [temperature Range Resistivity —_| "__1P-470 _-_915-1150°C LnP Oy +P,054 ANPOs)y--PAIPO,+P,054 — LaPgOyy ‘Several thin radial slots are cut into the sources to ensure that they will not fracture when rapidly heated in the diffusion fumnece, The slots have no effect on the uniformly of the doped sitlcon wafer. The TP-380 and TP-470 Sources also conlein TayOx to adjust tei thermat expansion cosficients and make them extremely resistant to thermal shook. Are Safe to Use.TTT CLL PHOS PLUS High Purity Planar Dopant Sources PhosPlus Sources Show Long Lifetimes. Industrial experience has shown thet PhosPlus sources normally exhibit ifeimes in the range of 200-500 use hours, The setualifeimes of PhosPlus sources used in typical plant production, however, depend upen many factors, such as temperature of use, care in handling, device being manufactured, the sensiiviy of the process to the eventual decrease in the P20. evalution rats, etc, ‘The potential lifetime of a PhosPlus souro can be estimated by periodically doping a silicon wafer with the sourca being held in diffusion furnace and observing how the resulting sheet resistivity varies with time. Figure 1 shows the average sheet resistivity oblained on the slicon wafers doped for 60 minutas at 1020°C with TP-470 sources ‘when used in a typicel production environment. Litle change in sheet resistivity was observed forthe first 600 hhours of use. The shee! resistivity then began to slowly increase es the Po. evolution rates was gradually decreasing. AGITIME ‘WEIGHT LOSS VERSUS USE TINE ee a FORTRAZOSOURCES: Cennreoncestcn a se2S'E Veer caer) "30 200 DOD AD oon el Tan EOE BoE STN oD Users) frigate ‘Asecond method of estimating the lifetime of 2 source is to measure the amount of weight a source loses at @ use temperature as the PO evolves. Weight loss data for the TP-470 sources (Figure 2) indicates a continuing process of PO, evolution over hundreds of use hours. Figures 3 and 4 show similar sheet cesisthity and weight loss date for the TP-260 sources. This deta also Indicates that hundreds of hours of use can be obtained from a set of TP-250 PhosPlus sources.YL LLL PHOS PLUS High Purity Planar Dopant Sources, Doping Properties of PhosPlus Sources. Single Grystal Silicon; Typical sheet resistivity versus deposition time ourves for the three PhosPlus sources ace plotted in Figures 6,6 and 7. The curves are different for each source because the sheet resistivity of the silicon water for a given deposition cycle depends somewhat upon tie thickness of the deposited glassy film. The thicker the glassy fim, the lover the sheet resistivity. Figure & shows how the deposited film thicknass varies with the type of source being used. ‘SHEET RESIaTIVITY VERSUSDEPOSTIONTINE ‘SHEET RESISTIVITY VERSUS DEPCSTION TAME ‘CURVES AT VARIOUS TEMPERATURES ‘CURVES ATVARIOUS TEMPERATURES. "FOR TP-4705URCES ‘FORTP-980 SOURCES 2 pravage St Beye tome) ncennsenn =" Es) Beaton Time thus) aa ‘SHEET RESISTIVITY VERGUE DEPOSITION TIME ‘CURVESAT VARIOUS TEMPERATURESFOR, "TP2S0BOURCES 0 DIPOSTEDOLASEFHLUZHICKMESS VERSUS ‘DEPOSITION FIUE ANDTEMPERATURE TORPhes Phos SOURGES. ed é 5 & Giasstim ewes 3 28 g & ‘AvarageSheeMenatveyfanmet) a g é 2 88 8Atypical deposition time for a solid-source diffusion system is about 45 minutes, This time is usually long enough for the sources to uniformly dope the sliicon wafers. At the same time, itis short enough to be compatible with most semiconductor process parameters. Figure 9 shows the sheet resistivity and junction depth that is obtained from a 45-minute deposition with the TP-470 PhosPlus sources at various deposition temperatures. ‘SHEET RESISTIVITY AND. JUNCTION DEPTH SHEET RESISTIVITY OF POLYSILICON {VERSUS DEPOSITION TEMPERATURE DEPOSITED GLASS PLM THIGRNESS Sane ee 8 % Pa oe ie Ba i: i 3 a i: : : veya ie ‘0 yooo 1050100 HBO vol = so00h ELI aes Sea ee re a Polysilicon: The minimum sheet resistivity that can be obtained from polysilicon wafers that are seturated with phosphorus partilly depends upon the thickness ofthe polyslicon layer. These sheet resistives are about ¥2ohimlsq for 800A of polysiicon and about 32ohmisq for 2500A, and they occur when the deposited phosphorus glassy film exceeds about 600 to 600A. Glassy films that are less than 500A can also be uniformly deposited on the polysilicon wafers from the PhosPlus sources to produce higher sheet resistitles for special applications. Figure 10 can be used as a guide to determine the approximate thickness that is required for diferent sheet resistivities. Sheet resistivities at or above the saturation of phosphorus in polysilicon can be obtained from any ofthe three phosphorus sources, The appropriate deposition cycle can be selected from the curves showm in Figures 11, 12 and 13,“YP-280 PhesPios SHEET RESISTIITY VERSUS DEPOSITION TIME i mica Foe wo Se poeeaeee Untformities: When the various processing conditions are optimized, uniformities of 2% across the silicon, 3% across tne bost and 4% rundown or Beto can ganeraly be oblanad on shle-crystlslicon, A ola! vation of ‘2bout 3% can be achieved on high-quality polysilicon wafers doped to their minimum sheet resistivities (saturation with phosphorus). ‘These uniformities are quite typical of the planar diffusion system and tend to be indepancient of the diameter of the wafer and the number of silicon wafers being processed during a run. This Independence can result in an increase in silicon throughput compared to the number of silicon wafers often processed in gas system. It can also significantly Increase production yes by impcaving process contro! as demonstrated by the decrease in bela variation when TP-470 PhosPlus sources are used for an emitter difusion instead of POCI3 (Figure 14). PhosPius® is a registered trademark of Techneglas, Inc.GEORGIA INSTITUTE OF TECHNOLOGY ‘Microelectronics Research Center ‘Microelectronics Processing Laboratory DRY OXIDATION PROCEDURE: _{ GATE REGION ) ‘This process step will thermally oxidize the silicon substrate, The oxide grown will be a thin gate oxide, ‘approximately 100A, 1 RCA clean device wafers and control wafer. Refer to RCA Clean Handout for procedure in substrate cleaning station. During the cleaning, continue with the next three items, ‘preparing the oxidation furnace, ‘Verify that the gases flowing through the furnaces are in the IDLE CONFIGURATION: ‘Note that inthe idle configuration, nitrogen gas is flowing through all four furnaces. Ramp oxidation furnace and set itto 900° C. This is accomplished by adjusting the fumace controller in the side of the firmaces. At the completion of the RCA clean, semove the quartz boat from the fiumace using the ‘appropriate push rod and quartz boat loader. ‘hold push rod in front of mark ‘onzod. Keep the boat in the boat loader and set the boat loader down in front of the furnace tubes, taking care that holder and boat remain in laminar flow. Place the RCA — clean wafezs, still in their cartier, into the cartier box, and transport ‘them to the furnace loading station, Load wafers into quartz boat using Teflon of Teflon. tipped tweezers. Avoid passing arms or head over clean wafers. ‘With boat loader, return wafers on boat to the mouth of the oxidation furnace. Slowly ‘push boat into the mouth of the furnace with push rod, to avoid wafer fracturing duc to thermal stress, Note during this procedare there is no stopping point until wafers have been loaded in the ‘mouth of the furnace. ‘The dry oxidation process is to be carried out at 1100° C, The procedure is: a LeadinN, — (idle ges) b Dry: 45 minutes ©. ‘Unload inN, (idle gas) Ramp the furnace controller up to the oxidation temperature of 1100°.C, Wait until the temperature has stabilized, (ramp mode is set at 20°/ per min. ) ‘Begin dry oxygen flow through the tube: >> tum oxide fumace valve to 0; >> valve to Dry or Wet should be facing Dry Day oxygen is now flowing through the tube, ADJUST the flow rate to 94.7scom ( which is equivateat to 1000 sccm flow ), sct time for 45 minutes.i 12, 13, 4. 15, When 45 minutes have elapsed, turn oxide furnace valve to N2. The gas delivery system is back to IDLE CONFIGURATION Retum furnace setting to 900° C, lock in ramp mode and wait to cool down. Pull wafer boat slowly to the mouth of the fumace with push rod. Let wafers cool briefly before completely removing boat from furnace, Make sure that the wafers stay in laminar flow hood at all times. . Allow wafers to cool completely in boat before removing and storing in N, dry box. ‘With boat loader, return boat to oxidation furnace. Slowly push boat into furnace with push rod, approximately 4 of the way into the furnace tube. Loosely replace end cap and store boat holder inside the metal furnace door. " Bstimate the thickness of the grown oxide using the color chart as well as well as your calculation of approximately how thick the grown oxide should be, ‘Measure grown oxide thickness of control wafer using Ellipsometer, referring to Ellipsometer procedure ( this may be deferred to later lab for time reasons),METAL FILM DEPOSITION WORKSEET DATE: ; WAFER #: 1 Film Material : : (Single Run) Distance between Source /Wafer: ys. Deposition rate: __ Monitor reading: ae eae Tencor reading: , Notes / Comments; ee ee SSGEORGIA INSTITUTE OF TECHNOLOGY Microclectronics Research Center ‘Microelectronics Processing Laboratory INTRODUCTION TO METALLIZATION Scmiconductor device structures require a munber of differen layers or films, These layers can be Gieteotrics, semiconductors or conductors and are placed on the wafer by a variety of techniques. During the past several years there has been a dramatic increase in the uses and number of these layers. Deposited conductors are an integral part of every device, in the ole of surface wiring. Conductors also provide other functions in 1.C, structures, such as fuses and back side electrical contact for the packaged dle, Metaliizationis the general term used to describe this segment of semiconductor processing, ‘Conductors: ‘Metal films are used in semiconductor technology to wire together the various components formed in the ‘wafer surface. The wiring is accomplished by the deposit ofa thin (10 to 15 thousand angstroms ) layer of metal on the wafer. This metal layer, aller being paltemed through a rhotomasking process, connects the devices as required by the circuit operation. ‘The metal strips on the wafer surface are called Jeads or datercoanects. Generally, a wafer beating slop called ally follows depocition to insure good electrical contact between the metal and the wafer surface. Pattemed conductive films serve two other roles in device structures. They function as the gate electrodes in MOS structures, and are used 28 electrodes in thin film capacitors. Wising ‘The following metals and alloys are used for theee purposes: 1 2. 3. 4, Doped Polysilicon 5, Refiactory Metals and their Silicldes 6 Gold Thin Film Wiring Aluminum and Aluminum Alloys: ‘Aluminum has been the traditional “wiring” metal, In fact the development of thin film alumizwm technology has been one of the major contributions to planar technology. Alurainum achieved this status because it meets the requirements that a motel must have to be compatible with silicon technology. 1, Good Current carrying Density 2. Superior Adhesion to SiO 3, Ease of Patteming 4. High Purity 5. Good Electrical contact with Siticon ‘Aluminom meets all of the above requirements. It has good conductivity, adheres very well to silicon dioxide, can be patterned with conventional photomasking techalques and is obtainable in high purity. ‘Aluminum has to be purified to between 99.9999 and 99.99999% for semiconductor use. Blectrical contact of aluminum with silicon, while adequate for LSI level technology has reached its limits in the VLSI era.GEORGIA INSTITUTE OF TECHNOLOGY Microcicetronics Research Center Microelectronics Processing Laboratory ‘DEPOSITION METHODS: ‘Metaltization techriques; tke the other fab processes, have undergone improvenient and evohition in. ‘response to the demands of the nevr circuits. The mainstay of metal deposition techniques was and is vacuura evaporation Aluminum, gold and te fuse metals are deposited by evaporation. The newer metal systems as well asthe dielectrics and semiconductors can be deposited by sputtering. ‘This technique offers, ‘Supecior film composition and thickness control and will become the dominant deposition method by the end of the century. ‘The two systems are similar in construction and operation. Each a soutce of the material to be deposited, a ‘method to convert the source to atoms and / or molecules, wafer holders to insure even film deposition, an, ‘evacnated chamber and a pumping system vo remove the air. Evaporation Theory: ‘The evaporation of metal onto wafers relies on the same process by which water will evaporate aut of a glass, Atthe liquid air interfice some of the water atoms have enough internal energy to break the surface ‘and escape into the air, Overtime, enough atoms will escape fram the water and remain in the air, reducing the volume of the water. ‘This same evaporation process canbe made to occur in a solid, When athe temperature Is raised high enough, atoms of the solid material wil melt and “evaporate” into the aumosphere. Ce ee ee ae 21 . . 1, Filament 2. Ebeam 3. Flash richrome, each of the elements in the alloy will evaporate al adifferentrate, Each rate is characteristic of he evaportion mite of the eloment atthe particular temperature of the filament. In the case of nichrome, the composition of the nickel and chromium on the wafer will differ from the composition inthe source alloy. ~suTTT { wetter ra Vif ——— @- \wemn ‘Crucible - Water Cooler Evaporation Methods ?Flash System: ‘This method is used primarily to evaporate aluminum / silicon alloys. The source is a wire ofthe alloy. A mechanical feeder automatically pushes the wire onto a hat plate. Upon contact the end of the wire very quickly evaporates or “flashes” into the gas slate. Since all ofthe elements in the wire are evaporated instantaneously the composition ofthe film on the water is very clase to the source composition Evaporation Chamber: ‘The evaporation must take place in an evacuated chamber. If the evaporation took place in air, the high ‘energy aluminum would combine with the oxygen in the air to form Al,Os,an insulator, The chamber itself is made of heavy wall quartz or stainless steel to withstand the low pressures that are ( 5X16” torr, or 0,00005 mm Hg ). (Chamber design is either the familiar bell jar or the refrigerator style configuration, Bell jars have the advantage of maximum strength and good vacuum sealing from the bottom circular gasket, but the disadvantage of slower productivity due to the time required toraise and lower thé jar. The front opening styles have the opposite advantages and disadvantages. a Bell Jar (Quartz or Stainless Stee) Planetary Water Holder High Vacuum 5x 10° torr ® 1x Wort Heater Evaporation Source Mechanical and High Vacuum Pumps * Vacuum Evaporator32 Via Plugs Mi +First Metal = M2 = Second Metal figure 132 | Gross section of typical planarized two-level metal VES! fracture showing range of via de anarlzation. (Courtesy eid State Peano) ™ Next comes a layer of some dielectric material, called an intermetallic dielectric. This dielectric may be a deposited oxide, silicon nitride, or a polyimide film. This layer receives a masking step that etches contact holes, called vias, down to the first-level metal. The whole process is repeated, with the final structure having two or three levels of metal connected to each other and protected by a final passivation layer. In some schemes the via holes are filled with metals other than the main conducting material. The particular metals for via filling are dis- cussed in the following pages. A multilevel metal system is more costly, of lower yield, and re- quires greater attention to planarization of the wafer surface and in- termediate layers to create good current-carrying leads. In the role of surface conductor, a metal must meet the following criteria: ® Good electrical current-carrying capability (current density) * Good adhesion to the top surface of the wafer (usually SiO2) « Ease of patterning « Good electrical contact with the wafer material = High purity © Corrosion resistance ® Long-term stability ™ Capable of deposition in uniform void- and hillock-free films Fuses The development of thin-film fuse technology allowed creation of the programmable read-only memory (PROM) circuit. The fuse allows field programming of data in the memory section of the chip, In this role the fuse is not a protective device, as in most electrical circuits, but is included specifically to be “blown” or disabled.‘GEORGIA, INSTITUTE OF TECHNOLOGY ‘This Should Be Handled with Safety in Mind: lL Pour a generous amount of Pan Etch in a petri dish 2. Heat solution to 40°C to 45°C 3, Carefully immerse wafer alurninum side up with tweezers 4 ‘Begin to geal rtate wafer in soliton to prevent bes fram faring ax np srace of NOTE: Bubbles may prevent the etch from removing the aluminum 5. Aluminum should begin to react immediately and remove all the exposed aluminum + depending on the thickness of the deposition. 6, ‘When the sluminm is etched, carefully remove the wafer and place a petr dish filled with DI water. 7. Load wafer in wafer carrier and continue to rinse for several minutes both front and back NOTE: Pan Etch tend to leave a cleat residue 8. Dry with, gun 9. Inspect under microscope for clear, clean, patternsGEORGIA INSTITUTE OF TECHNOLOGY Microelectronics Research Center Microelectronics Processing Laboratory ‘TECHNICS PLASMA ETCHING PROCEDURE: Oxygen tank in ON ‘Main Power to Technics Machine is ON AUTOMATIC: Lift chanber lid up ‘Load the wafer to be treated Carefully bring down the chamber Hid Push to Start /Stop button, This will start the Systems Automatic Sequence ‘THE SEQUENCE WILL BEGINBY ‘Pumping the chamber down to the low setpoint Once the low setpoint has been reached Gas #1 ‘Will tum on the Flow Controller ‘After a time delay of approximately 30 seconds the sequence will begin ‘When the timer reaches 00,0 minutes the RF power and the gases will tum OFF, The chamber will pump down and the system will give off and andible alarm With the chamber vented, lift chamber Iid up and remove your wafer ‘Tum OFF Vent Valve mTorr Pressure: ‘Watt Power: Time:GEORGIA INSTITUTE OF TECHNOLOGY ‘Microelectronics Rescarch Center Microelectronics Processing Laboratory SINTER/ ANNEAL PROCEDURE: Verify that the Gas Flowirig through the Sinter / Anneal furnace is Nz Note: ‘That in the Idle Configuration the gas valve is turned facing the Nz 10. Gas flow regulator should be set at 87.11 sccm ( approximately 1000 sccm ) Set temperature to furnace controller marked sintering / anneal at 400° C, Remove quartz boat from mouth of furnace using sinter push ro ‘Carefully slide boat onto boat carrier and place on table under laminar hood. ‘Load wafers tobe sintered on wafer carrier Slide mounted wafers carefully into mouth of furnace. ‘Wail afew seconds for wafer to adjust to furnace temp. Slide boat using quartz rod up to marked line flushed with metal doorway, this will place wafer carrier to center of furnace. Set timer to 30 MINUTES. ‘When time has expired slide quartz boat back to mouth of furnace. Wait for the wafers to cool, approximately 5 minutes, remove and unload wafers.