Chapter 1 Exercise Solutions

1.1

There are 14 nodes in the circuit. Thus, there are 142 = 28 single stuck-at faults.
For multiple stuck-at fault, it has (2 + 1)14 1 = 4782968 multiple stuck-at faults.
For collapsed single stuck-at fault:
Number of collapsed faults = 2(number of POs + number of fanout stems)
+ total number of gate (including inverter) inputs
total number of inverters
Here number of POs = 1, number of fanout stems = 3, total number of gate inputs = 10, number of
inverter = 2. Therefore, the number of collapsed faults = 2(1 + 3) + 10 2 = 16.

1.2
A feedback bridging fault will transforms a combinational circuit into a sequential one, as the
following figure shows:

1.3
To detect all single stuck-at faults of the n-input NAND, we need n+1test vectors. In fact, in order
to detect the s-a-1 fault at the inputs, the following patterns are needed:

VLSI Test Principles and Architectures

Ch. 1 Introduction P. 1/2

(011111), (101111), (110111), (111011), (111101), , (111110)

In addition, (11111) is required to detect the inputs s-a-0 faults and the output s-a-1 fault.

1.4
Four patterns are enough to exhaustively test each gate in the parity checker independent of n.
They are as follows.
(000), (111),(0111), and (1000).

1.5
k

= i ,
i =1

MTBF =

i =

1000
6
4
. Thus, = 10 500 = 5 10
9
10

= 2 10 = 2000 hours.
3

1.6

t = T (1 System _ availability )
= 1 365 24 60 60 (1 99.999%) = 315.36sec
1.7
(1 0.9)

Defect level = 1 0.5

= 1 0.933 = 6.7%

VLSI Test Principles and Architectures

Ch. 1 Introduction P. 2/2