library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity jkc is
Port ( clock : in std_logic;
reset : in std_logic;
count : out std_logic_vector(3 downto 0)
);
end jkc;
architecture rtl of jkc is
COMPONENT jkff
PORT(
clock : in std_logic;
reset : in std_logic;
j
: in std_logic;
k
: in std_logic;
q
: out std_logic
);
END COMPONENT;
signal temp : std_logic_vector(3 downto 0) := "0000";
begin
d0 : jkff
port map (
reset => reset,
clock => clock,
j
=> '1',
k
=> '1',
q
=> temp(3)
);
d1 : jkff
port map
reset
clock
j
k
q
);

(
=>
=>
=>
=>
=>

reset,
temp(3),
'1',
'1',
temp(2)

d2 : jkff
port map
reset
clock
j
k
q
);

(
=>
=>
=>
=>
=>

reset,
temp(2),
'1',
'1',
temp(1)

d3 : jkff
port map
reset
clock
j
k
q

(
=>
=>
=>
=>
=>

reset,
temp(1),
'1',
'1',
temp(0)

);
count(3)
count(2)
count(1)
count(0)
end rtl;

<=
<=
<=
<=

temp(0);
temp(1);
temp(2);
temp(3);