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VHDL Implementation For A Fuzzy Logic Controller
VHDL Implementation For A Fuzzy Logic Controller
ABSTRACT
This paper describes the implementation for a basic fuzzy logic controller in Very High
speed integrated-circuit Hardware-Description Language (VHDL). It is not intended as
an introduction to fuzzy logic control methodology; instead, we try to demonstrate the
implementation of a fuzzy logic controller through the use of the VHDL code. Use of the
hardware description language (HDL) in the application is suitable for being
implemented into an Application Specific Integrated Circuit (ASIC) and Field
Programmable Gate Array (FPGA). The main advantages of using the HDL approach are
rapid prototyping, and allowing usage of powerful synthesis tools such as Xilinx ISE,
Synosys, Mentor Graphic, or Cadence to be targeted easily and efficiently.
2. FUZZIFICATION
There are numerous different types of membership functions. Among them, the two most
commonly used in practice are the triangular and trapezoidal membership functions (triangular
membership function being a special case of the trapezoidal function). For this application we use
a trapezodial function.
Each trapezoidal membership function is defined by two points and two slope values. The
entire membership function can be divided into three segments: 0, 1 and 2 as shown in Figure 1.
The Y axis shows the degree of membership () as a value between 0 and 1. The X axis shows
the universe of discourse and is divided into three segments. The degree of membership depends
on the location of the input value with reference to these three segments. Figure 1 shows how
trapezoidal input membership functions are formed in the fuzzification process [8, 9, 10].
The calculation of the degree of membership (() can be categorized into three different
segments: (a) in segment 0: = 0, (b) in segment 1: slope is upward from left to right, therefore:
(1)
(2)
and
Since the input value of 10 ($0A) is greater than Point 2 and lies in segment 2, therefore:
= $FF (Input value point 2) * slope 2 = $FF ($0A - $09)*$55 = $AA
(3)
In VHDL, each membership function is defined by four 8-bit values, two points and two
slope values using record type declaration as follow [11]:
type membership is (term, none);
type mfs is record
linguistic: membership;
point1: std_logic_vector(7 downto 0);
slope1: std_logic_vector(7 downto 0);
point2: std_logic_vector(7 downto 0);
slope2: std_logic_vector(7 downto 0); end record;
type membership_functions is array(natural range <>) mfs;
constant linguistic_name : membership_functions :=((linguistic => term, point1 => x"04",
slope1 => x"7F", point2 => x"09", slope2 => "55"), linguistic => none, point1 => x"FF",
slope1 => x"FF", point2 => x"FF", slope2 => x"FF"));
3. RULE EVALUATION
A rule usually takes the form of IF-THEN statement as follow:
IF x is A AND y is B THEN z is C
(4)
AND is a fuzzy operator which is the minimum operation between the two antecedents. In
VHDL, the following minimum function is used to obtain the result of each rule evaluation
between two variables:
function minimum(a, b: std_logic_vector) return std_logic_vector is
variable min: std_logic_vector(7 downto 0) := (others => '0');begin
if a < b then min := a; else min := b; end if; return min; end minimum;
There is also an implied OR operation between successive rules when more than one rule is
involved with the same output. The linguistic rule, IF (x1 is A1 AND y1 is B1) OR (x2 is A2 AND
y2 is B2) THEN z is C , can be implemented by taking the maximum value of all the results with
the same consequent block. In VHDL code, a function of taking the maximum of two input
variables to determine the final result of all rules with the same output can be written as:
function maximum(a, b: std_logic_vector) return std_logic_vector is
variable max: std_logic_vector(7 downto 0) := (others => '0'); begin
if a > b then max := a; else max := b; end if; return max; end maximum;
By combining the minimum and maximum functions, the truth value for each rule can be
obtained as:
C <= maximum( minimum(A1, B1), minimum(A2, B2));
4. DEFUZZIFICATION
During the defuzzification process, each fuzzy output is multiplied by its corresponding
singleton position. The sum of this product is divided by the sum of all fuzzy output to obtain the
result of the final output. In VHDL, this is implemented as:
For i = 1 to n do begin product = (s(i) f(i)) + product; sum = f[i] + sum; end for loop;
output = product / sum;
Although several types of membership functions, such as singleton, trapezoidal etc., could be
used to describe the output using VHDL, the defuzzification calculation are not the same, some
are more complicated than others. If trapezoidal shapes are used, finding the center of gravity
and overall area of the membership functions are considerably more complicated than the
calculation on singletons, and the results are not necessary effective or better [8].
The membership functions for TE consists of seven fuzzy logic ranges that can be defined
using the linguistic terms as Cold, Cool, Mild, Warm, and Hot. Table 1 shows the partitions for
the variable temperature. In this case, the ranges are subjectively chosen for demonstrating the
fuzzification process in VHDL.
The graphical representation of the member-ship function of TE is depicted in Figure 3. The
triangular and trapezoidal shapes of membership function will be used throughout this application
because of their simplicity and efficiency of implementation in VHDL code.
The values of the x-axis of the membership function have been scaled as an 8-bit
hexadecimal value representing the actual reading from the temperature sensor. Similarly, the yaxis for the grade of the membership function starts from $00 (false) to $FF (completely true).
Table 1. Range of the
Variable Temperature
Fuzzy Set
Range (C)
Cold
-55 to +5
Cool
-25 to +35
Mild
+5 to 65
Warm
+35 to +95
Hot
+65 to +125
Cold
Cool
Mild
Warm
Hot
($FF) 1.0
$A5
0.8
0.6
$5A 0.4
0.2
($00) 0.0
65
95 125
5
($7F) ($AA) ($DA) ($FF)
TE
75
5
-25
($55
($00 ($2A)
-55
Cold : Point1 = -55 ($00), Slope1 = 255, Point2 = -25 ($2A), Slope2 = 6
Cool : Point1 = -25 ($2A), Slope1= 6, Point2 = 5 ($55), Slope2 = 6
Mild : Point1 = 5 ($55), Slope1 = 6, Point2 = 35 ($7F), Slope2 = 6
Warm : Point1 = 35 ($7F), Slope1 = 6, Point2 = 65 ($AA), Slope2 = 6
Hot : Point1 = 65 ($AA), Slope1= 6, Point2 = 95 ($FF), Slope2 = 255
Since the 75C vertical line intersects two membership functions, warm and hot respectively,
the degrees of these two membership function intersections can be calculated using the three
segment information as described above to obtain the grade of each membership intersection.
The following calculation shows how the grade of the membership is calculated for the
temperature value of 75C:
The vertical line is in segment 2 of the warm label, therefore:
Grade = $FF ((Input value point 2) * slope 2)
= $FF ((75 65) * 6) = 255 (10*6) = 195 = $C3
(7)
(8)
The following declaration defines the data structure description of the TE membership
function in VHDL:
type te_type is (cold, cool, mild, warm, hot, none); type te_ membership is record term: te_type;
point1: std_logic_vector(7 downto 0); slope1: std_logic_vector(7 downto 0);
point2: std_logic_vector(7 downto 0); slope2: std_logic_vector(7 downto 0);end record;
type te_membership_functions is array(natural range <>) te_membership;
constant te_mfs: te_membership_functions :=
((term => cold, point1 => x"00", slope1 => x"FF", point2 => x"2A", slope2 => x"06"), (term
=> cool, point1 => x"2A", slope1 => x"06", point2 => x"55", slope2 => x"06"), (term =>
mild, point1 => x"55", slope1 => x"06", point2 => x"7F", slope2 => x"06"),
(term => warm, point1 => x"7F", slope1 => x"06", point2 => x"AA", slope2 => x"06"),
(term => hot, point1 => x"AA", slope1 => x"06", point2 => x"D5", slope2 => x"FF"),
(term => none, point1 => x"FF", slope1 => x"FF", point2 => x"FF", slope2 => x"FF"));
The second input variable to the temperature fuzzy controller is the rate of change of
temperature with respect to time. This calculation results in the rate of temperature change per
time interval as fined below:
(present temperature reading) (previous temperature reading)
rate =
(9)
time between temperature reading
0.0
($00)
20%
40%
AC
60%
80% 100%
($FF)
Fuzzification():
Set n = number of membership function; Set = array of degree of membership function;
Set membership = array of membership function; For i = 1 to n do begin
if input value < membership[i].point 1 then [i] = 0;
else if input value < membership[i].point 2 then
[i] = (input value membership[i].point 1) membership[i].slope 1;
else [i] = 255 - (input value membership[i].point 2) membership[i].slope 2;
end if; end for loop;
TE
Cold Cool Mild Warm Hot
Rule 1
Rule 2
Rule 3
Rule 4
Cold
Cold
Cool
Mild
Rule 5
Warm
Rule 6
Warm
0.0
AND
0.0
AND
0.0
AND
0.0
Rule 7
Hot
Rule 8
Hot
AND
0.8
AND
0.8
AND
0.2
AND
0.2
AND
Fast
Slow
Moderate
Slow
Slow
Moderate
0.3
= 0.0
0.0
= 0.0
0.75 = 0.0
0.0
= 0.0
0.0
= 0.0
0.75 = 0.75
Slow
Fast
0.0
= 0.0
0.3
= 0.2
1C/s
75C
Figure 6. Rule Evaluation Example
Understanding the evaluation of these rules in the fuzzy inference stage, the set of rule
evaluation in VHDL can be described as follow:
Rule 1: very_high <= minimum(cold, fast);
Rule 2: high <= minimum(cold, slow);
Rule 3 and Rule 4: medium <= maximum( minimum(cool, moderate), minimum(mild, slow));
Rule 5 and Rule 6: low <= maximum( minimum(warm, slow), minimum(warm, moderate));
Rule 7 and Rule 8: very_ low <= maximum( minimum(hot, slow), minimum(hot, fast));
9. DEFUZZIFICATION MODULE
After the output grade of each rule has been determined, the next step is to combine all the
output grades into a single value that can be used to control the heater operation. In the
defuzzifier process, Center-of-Gravity (COG) [8, 9, 10] deffuzifiction technique will be used to
obtain the final system output. In this application, singleton variables are used as the output
membership functions. Defuzzification involves taking the weighted average of all the fuzzy
outputs. Each fuzzy output is multiplied by its corresponding singleton value, then the sum of
these products divided by the sum of all the fuzzy outputs to obtain the final single output
variable. The following pseudo-code illustrates the procedure of this defuzzification process:
Defuzzification():
Set n = number of output membership function; Set s = array of singleton of output
membership function; Set f = array of result of all rule evaluations; Set sum = 0
For i = 1 to n do begin product = (s(i) f(i)) + product; sum = f[i] + sum; end for loop;
output = product / sum;
CONCLUSION
The design of a typical fuzzy logic controller using VHDL is presented in this paper. Once
the basic design of the fuzzy logic control system has been defined, the implementation of the
fuzzy logic controller is very straight forward by coding each component of the fuzzy inference
system in VHDL according to the design specifications. The availability of different synthesis
tools for the programmable logic devices such as FPGA and CPLD have made it easier for the
designers to experiment their design capabilities. By simply changing some parameters in the
codes and design constraint on the specific synthesis tool, one can experiment with different
design circuitry to get the best result in order to satisfy the system requirement.
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