HEF4518B

HEF4518B
Dual BCD counter

Rev. 7 21 November 2011
Product data sheet
1. General description
The HEF4518B is a dual 4-bit internally synchronous BCD counter. The counter has an
active HIGH clock input (nCP0) and an active LOW clock input (nCP1), buffered outputs
from all four bit positions (nQ0 to nQ3) and an active HIGH overriding asynchronous
master reset input (nMR). The counter advances on either the LOW-to-HIGH transition of
the nCP0 input if nCP1 is HIGH or the HIGH-to-LOW transition of the nCP1 input if nCP0
is LOW. Either nCP0 or nCP1 may be used as the clock input to the counter and the other
clock input may be used as a clock enable input. A HIGH on nMR resets the counter (nQ0
to nQ3 = LOW) independent of nCP0, nCP1. Schmitt trigger action in the clock input
makes the circuit highly tolerant of slower clock rise and fall times.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2. Features and benefits
Tolerant of slow clock rise and fall times

Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from 40 C to +85 C
Complies with JEDEC standard JESD 13-B
3. Applications
Multistage synchronous counting
Multistage asynchronous counting
Frequency dividers
4. Ordering information
Table 1.
Ordering information
All types operate from 40 C to +85 C
Type number
Package
Name
Description
Version
HEF4518BP
DIP16
plastic dual in-line package; 16 leads (300 mil)
SOT38-4
HEF4518BT
SO16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
HEF4518B
NXP Semiconductors
Dual BCD counter
5. Functional diagram
1Q0 3
1 1CP0
1Q1 4
2 1CP1
1Q2 5
1Q3 6
7 1MR
2Q0 11
9 2CP0
2Q1 12
10 2CP1
2Q2 13
2Q3 14
15 2MR
001aae698
Fig 1.
Functional diagram
Q0
Q1
Q
CP1
CP0
Q2
FF1
FF2
T
CD Q
FF3
T
CD Q
Q3
FF4
T
CD Q
CD Q
MR
001aae700
Fig 2.
Logic diagram for one counter
HEF4518B
Product data sheet
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
2 of 15
HEF4518B
NXP Semiconductors
Dual BCD counter
6. Pinning information
6.1 Pinning
HEF4518B
1CP0
16 VDD
1CP1
15 2MR
1Q0
14 2Q3
1Q1
13 2Q2
1Q2
12 2Q1
1Q3
11 2Q0
1MR
10 2CP1
VSS
2CP0
001aae699
Fig 3.
Pin configuration
6.2 Pin description

Table 2.
Pin description
Symbol
Pin
Description
1CP0, 2CP0
1, 9
clock input (LOW-to-HIGH triggered)
1CP1, 2CP1
2, 10
clock input (HIGH-to-LOW triggered)
1Q0, 2Q0
3, 11
output
1Q1, 2Q1
4, 12
output
1Q2, 2Q2
5, 13
output
1Q3, 2Q3
6, 14
output
1MR, 2MR
7, 15
master reset input
VDD
16
supply voltage
VSS
ground supply voltage
HEF4518B
Product data sheet
3 of 15
HEF4518B
NXP Semiconductors
Dual BCD counter
7. Functional description
Table 3.
Function table[1]
nCP0
nCP1
nMR
Mode
counter advances
counter advances
no change
no change
no change
no change
nQ0 to nQ3 = LOW
[1]
H = HIGH voltage level; L = LOW voltage level; X = dont care; = positive-going transition; = negative-going transition.
10
11
12
13
14
15
16
17
18
nCP0
nCP1
nMR
9
nQ0
nQ1
nQ2
nQ3
001aae703
Fig 4.
Timing diagram
HEF4518B
Product data sheet
4 of 15
HEF4518B
NXP Semiconductors
Dual BCD counter
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VDD
supply voltage
0.5
+18
IIK
input clamping current
VI
input voltage
10
mA
0.5
VDD + 0.5
IOK
output clamping current
10
mA
II/O
input/output current
10
mA
IDD
supply current
50
mA
Tstg
storage temperature
65
+150
Tamb
ambient temperature
40
+85
750
mW
VI < 0.5 V or VI > VDD + 0.5 V
total power dissipation
Ptot
P
power dissipation
VO < 0.5 V or VO > VDD + 0.5 V
DIP16 package
[1]
SO16 package
[2]
per output
[1]
For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.
[2]
For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
500
mW
100
mW
9. Recommended operating conditions

Table 5.
Recommended operating conditions
Symbol
Parameter
Conditions
Min
VDD
supply voltage
VI
input voltage
Tamb
ambient temperature
in free air
40
t/V
input transition rise and fall rate
VDD = 5 V
Typ
Max
Unit
15
VDD
+85
3.75
s/V
VDD = 10 V
0.5
s/V
VDD = 15 V
0.08
s/V
10. Static characteristics

Table 6.
Static characteristics
VSS = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter
VIH
VIL
HIGH-level input voltage
LOW-level input voltage
HEF4518B
Product data sheet
Conditions
IO < 1 A
IO < 1 A
VDD
Tamb = 40 C
Tamb = 25 C
Tamb = 85 C
Max
Min
Min
Max
Min
Unit
Max
5V
3.5
3.5
3.5
10 V
7.0
7.0
7.0
15 V
11.0
11.0
11.0
5V
1.5
1.5
1.5
10 V
3.0
3.0
3.0
15 V
4.0
4.0
4.0
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HEF4518B
NXP Semiconductors
Dual BCD counter
Table 6.
Static characteristics continued
VSS = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter
VOH
VOL
IOH
IOL
Conditions
HIGH-level output voltage IO < 1 A
LOW-level output voltage
5V
Tamb = 25 C
Tamb = 85 C
Min
Max
Min
Max
Min
Max
4.95
4.95
4.95
Unit
V
10 V
9.95
9.95
9.95
15 V
14.95
14.95
14.95
5V
0.05
0.05
0.05
10 V
0.05
0.05
0.05
IO < 1 A
15 V
0.05
0.05
0.05
HIGH-level output current VO = 2.5 V
5V
1.7
1.4
1.1
mA
VO = 4.6 V
5V
0.52
0.44
0.36 mA
VO = 9.5 V
10 V
1.3
1.1
0.9
LOW-level output current
mA
VO = 13.5 V
15 V
3.6
3.0
2.4
mA
VO = 0.4 V
5V
0.52
0.5
0.36
mA
VO = 0.5 V
10 V
1.3
1.1
0.9
mA
VO = 1.5 V
15 V
3.6
3.0
2.4
mA
15 V
0.3
0.3
1.0
5V
20
20
150
10 V
40
40
300
15 V
80
80
600
7.5
pF
Extrapolation formula
Min
Typ
Max
Unit
93 ns + (0.55 ns/pF)CL
120
240
ns
10 V
44 ns + (0.23 ns/pF)CL
55
110
ns
15 V
32 ns + (0.16 ns/pF)CL
40
80
ns
5V
48 ns + (0.55 ns/pF)CL
75
150
ns
10 V
24 ns + (0.23 ns/pF)CL
35
70
ns
17 ns + (0.16 ns/pF)CL
25
50
ns
93 ns + (0.55 ns/pF)CL
120
240
ns
44 ns + (0.23 ns/pF)CL
55
110
ns
32 ns + (0.16 ns/pF)CL
40
80
ns
10 ns + (1.00 ns/pF)CL
60
120
ns
10 V
9 ns + (0.42 ns/pF)CL
30
60
ns
15 V
6 ns + (0.28 ns/pF)CL
20
40
ns
II
input leakage current
VDD = 15 V
IDD
supply current
IO = 0 A
CI
Tamb = 40 C
VDD
input capacitance
11. Dynamic characteristics

Table 7.
Dynamic characteristics
VSS = 0 V; Tamb = 25 C; for test circuit see Figure 6; unless otherwise specified.
Symbol
tPHL
Parameter
HIGH to LOW
propagation delay
Conditions
VDD
nCP0, nCP1 to nQn;

see Figure 5
nMR to nQn;
see Figure 5
5V
[1]
15 V
tPLH
LOW to HIGH
propagation delay
nCP0, nCP1 to nQn;

see Figure 5
5V
[1]
10 V
15 V
tt
transition time
HEF4518B
Product data sheet
nQn; see Figure 5
5V
[1]
6 of 15
HEF4518B
NXP Semiconductors
Dual BCD counter
Table 7.
Dynamic characteristics continued
VSS = 0 V; Tamb = 25 C; for test circuit see Figure 6; unless otherwise specified.
Symbol
Parameter
Conditions
tW
pulse width
nCP0 input LOW;

minimum width;
see Figure 5
recovery time
trec
set-up time
tsu
maximum
frequency
[1]
Extrapolation formula
Min
Typ
Max
Unit
5V
60
30
ns
10 V
30
15
ns
15 V
20
10
ns
nCP1 input HIGH;

minimum width;
see Figure 5
5V
60
30
ns
10 V
30
15
ns
15 V
20
10
ns
nMR input HIGH;

minimum width;
see Figure 5
5V
30
15
ns
10 V
20
10
ns
15 V
16
ns
5V
50
25
ns
10 V
30
15
ns
15 V
20
10
ns
5V
50
25
ns
10 V
30
15
ns
15 V
20
10
ns
5V
50
25
ns
10 V
30
15
ns
15 V
20
10
ns
nMR input; see Figure 5
nCP0 to nCP1;
see Figure 5
nCP1 to nCP0;
see Figure 5
fmax
VDD
nCP0, nCP1;
see Figure 5
5V
16
MHz
10 V
15
30
MHz
15 V
20
40
MHz
The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
Table 8.
Dynamic power dissipation PD
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf 20 ns; Tamb = 25 C.
Symbol
PD
Parameter
dynamic power
dissipation
VDD
5V
Typical formula for PD (W)

PD = 750 fi + (fo CL) VDD
Where:
2
10 V
PD = 3300 fi + (fo CL) VDD2
15 V
PD = 8000 fi + (fo CL) VDD2
fi = input frequency in MHz;

fo = output frequency in MHz;
CL = output load capacitance in pF;
VDD = supply voltage in V;
(fo CL) = sum of the outputs.
HEF4518B
Product data sheet
7 of 15
HEF4518B
NXP Semiconductors
Dual BCD counter
12. Waveforms
VI
VM
nCP0 input
0V
VI
nCP1 input
VM
0V
0V
tsu
tsu
VI
nMR input
VM
0V
tPHL
tPLH
VOH
nQn output
tPHL
90 %
VM
10 %
VOL
tt
tt
001aae702
a. nCP0 and nCP1 set-up times, propagation delays and output transition times
1/fmax
VI
nCP1 input
(nCP0 = LOW)
VM
0V
tW
VI
nCP0 input
(nCP1 = HIGH)
VM
0V
tW
VI
VM
nMR input
0V
tW
trec
001aae701
b. nMR recovery time, minimum nCP0, nCP1, and nMR pulse widths and maximum frequency
Measurement points are given in table Table 9.
The logic levels VOH and VOL are typical output voltage levels that occur with the output load.
Fig 5.
Waveforms showing measurements for switching times
HEF4518B
Product data sheet
8 of 15
HEF4518B
NXP Semiconductors
Dual BCD counter
tW
VI
90 %
90 %
negative
pulse
VM
VM
10 %
0V
10 %
tf
tr
tr
tf
VI
90 %
positive
pulse
90 %
VM
VM
10 %
0V
10 %
tW
001aaj781
a. Input waveforms
VDD
VI
VO
DUT
RT
CL
001aag182
b. Test circuit
Test data is given in Table 9.
Definitions for test circuit:
DUT = Device Under Test;
CL = Load capacitance including jig and probe capacitance;
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
Fig 6.
Test circuit for switching times
Table 9.
Measurement points and test data
Supply voltage
5 V to 15 V
HEF4518B
Product data sheet
Input
Load
VI
VM
tr, tf
CL
VDD
0.5VI
20 ns
50 pF
9 of 15
HEF4518B
NXP Semiconductors
Dual BCD counter
13. Package outline

DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
ME
seating plane
A2
A1
c
e
w M
b1
(e 1)
b2
MH
16
pin 1 index
E
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
min.
A2
max.
b1
b2
D (1)
E (1)
e1
ME
MH
Z (1)
max.
mm
4.2
0.51
3.2
1.73
1.30
0.53
0.38
1.25
0.85
0.36
0.23
19.50
18.55
6.48
6.20
2.54
7.62
3.60
3.05
8.25
7.80
10.0
8.3
0.254
0.76
inches
0.17
0.02
0.13
0.068
0.051
0.021
0.015
0.049
0.033
0.014
0.009
0.77
0.73
0.26
0.24
0.1
0.3
0.14
0.12
0.32
0.31
0.39
0.33
0.01
0.03
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
ISSUE DATE
95-01-14
03-02-13
SOT38-4
Fig 7.
EUROPEAN
PROJECTION
Package outline SOT38-4 (DIP16)
HEF4518B
Product data sheet
10 of 15
HEF4518B
NXP Semiconductors
Dual BCD counter
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
A
X
c
y
HE
v M A
Z
16
Q
A2
(A 3)
A1
pin 1 index
Lp
1
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
D (1)
E (1)
HE
Lp
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.01
0.019 0.0100 0.39

0.014 0.0075 0.38
0.039
0.016
0.028
0.020
inches
0.010 0.057
0.069
0.004 0.049
0.16
0.15
0.05
0.244
0.041
0.228
0.01
0.01
0.028
0.004
0.012
8o
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
Fig 8.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT109-1
076E07
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Package outline SOT109-1 (SO16)
HEF4518B
Product data sheet
11 of 15
HEF4518B
NXP Semiconductors
Dual BCD counter
14. Revision history

Table 10.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
HEF4518B v.7
20111121
Product data sheet
HEF4518B v.6
Modifications:
Table 6: IOH minimum values changed to maximum

Figure 6: added DUT = Device Under Test
HEF4518B v.6
20091210
Product data sheet
HEF4518B v.5
HEF4518B v.5
20090727
Product data sheet
HEF4518B v.4
HEF4518B v.4
20090703
Product data sheet
HEF4518B_CNV v.3
HEF4518B_CNV v.3
19950101
Product specification
HEF4518B_CNV v.2
HEF4518B_CNV v.2
19950101
Product specification
HEF4518B
Product data sheet
12 of 15
HEF4518B
NXP Semiconductors
Dual BCD counter
15. Legal information

15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term short data sheet is explained in section Definitions.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
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damages are based on tort (including negligence), warranty, breach of
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Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customers own risk.
Applications Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customers sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customers applications and
products planned, as well as for the planned application and use of
customers third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customers applications or products, or the application or use by customers
third party customer(s). Customer is responsible for doing all necessary
testing for the customers applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customers third party
customer(s). NXP does not accept any liability in this respect.
Limiting values Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
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products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
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applying the customers general terms and conditions with regard to the
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Right to make changes NXP Semiconductors reserves the right to make

changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
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authorized or warranted to be suitable for use in life support, life-critical or
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Export control This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
HEF4518B
Product data sheet
13 of 15
HEF4518B
NXP Semiconductors
Dual BCD counter
Non-automotive qualified products Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
NXP Semiconductors specifications such use shall be solely at customers

own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors
standard warranty and NXP Semiconductors product specifications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
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Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
HEF4518B
Product data sheet
14 of 15
HEF4518B
NXP Semiconductors
Dual BCD counter
17. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12
Legal information. . . . . . . . . . . . . . . . . . . . . . . 13
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Contact information. . . . . . . . . . . . . . . . . . . . . 14
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section Legal information.
NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 21 November 2011
Document identifier: HEF4518B

HEF4518B

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Dual BCD counter

Product data sheet

2. Features and benefits

Tolerant of slow clock rise and fall times

plastic dual in-line package; 16 leads (300 mil)

plastic small outline package; 16 leads; body width 3.9 mm

Dual BCD counter

Logic diagram for one counter

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 21 November 2011

NXP B.V. 2011. All rights reserved.

Dual BCD counter

6.2 Pin description

clock input (LOW-to-HIGH triggered)

clock input (HIGH-to-LOW triggered)

master reset input

ground supply voltage

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 21 November 2011

NXP B.V. 2011. All rights reserved.

Dual BCD counter

nQ0 to nQ3 = LOW

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 21 November 2011

NXP B.V. 2011. All rights reserved.

Dual BCD counter

input clamping current

output clamping current

VI < 0.5 V or VI > VDD + 0.5 V

total power dissipation

VO < 0.5 V or VO > VDD + 0.5 V

For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.

For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.

9. Recommended operating conditions

Recommended operating conditions

input transition rise and fall rate

10. Static characteristics

HIGH-level input voltage

LOW-level input voltage

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 21 November 2011

NXP B.V. 2011. All rights reserved.

Dual BCD counter

HIGH-level output voltage IO < 1 A

LOW-level output voltage

HIGH-level output current VO = 2.5 V

LOW-level output current

input leakage current

11. Dynamic characteristics

nCP0, nCP1 to nQn;

nCP0, nCP1 to nQn;

Product data sheet

nQn; see Figure 5

All information provided in this document is subject to legal disclaimers.

Rev. 7 21 November 2011

NXP B.V. 2011. All rights reserved.

Dual BCD counter

nCP0 input LOW;

nCP1 input HIGH;