DP] Cu iowa Sto) ULOOET Service Manual CONTENTS ‘SPECIFICATIONS GENERAL........ TRANSMITTER, RECEIVER. CIRCUIT DISCRIPTION 1). Receiver System DR-135. 2) Transmitter System DR-135.. 3) PLL Synthesizer Circuit DR-135. 4) Receiver System DR-435.. 5) Transmitter System DR-435. 6) PLL Synthesizer Circuit DR-43 7) CPU and Peripheral Circui 8) Power Supply Circuit... 9) M3826BMCAO75GP (XA1130).... SEMICONDUCTOR DATA 1) NUM780BFA (XA0102 2) TC4S66F (XA0115). 3) AN8O10M (xAO119) 4) BU4052BCF (XA0236). 5) TCAWS3EU(KA0348)....sne 6) TA31136FN (XA0404)..0 9) 10) L8@MSOSTLL (XANES). 11) S-B1GASOAMC (KA0925)....... 12) LM2904PWR (XA1103).. 13) LM2902PWR (XA1108)...... 14) MB1SEO7SR (XA1107) sence 415) RAGOH1317M1 (XA1108)...... 16) S-AUB2L (XA1142), i 17) Transistor, Diode and LED Outline Drawing. 18) LCD Connection (TTR3626UPFDHN)....... EXPLODED VIEW 1). Top and Front View. 2) Bottom View. 3) LOD Assembly... PARTS LIST CPU Unit... MAIN Unit DR-135, MAIN Unit DR-435, Mechanical Parts. 2 Packing Parts. 2 ACCESSORIES ....... 2 ‘ACCESSORIES (SCREW SET)... TNC (Ev41U). ‘TNC (EJ41U) Packing Parts.. 34 4 DR-135 ADJUSTMENT 5 1) Adjustment Spot. 2) VCO and RX Adjustment Specifcation.. 7 3) TX Adjustment Specification. 7,8 4) RX Test Specification, 8 5) TX Test Specification. 9 10-12 DR-435 ADJUSTMENT 1) Adjustment Spot. 2) VCO and RX Adjustment Specification 13 3) TX Adjustment Specification. 43 4) RX Test Specification. 435) TX Test Specification 14 PC BOARD VIEW ‘CPU Unit Side A DR-135 (UPO536 ‘CPU Unit Side B DR-135 (UPO536 18 3) CPU Unit Side ADR-435 (UP0543).... 48 4) CPU Unit Side B DR-435 (UP0543). 45 5) MAIN Unit Side ADR-135 (UP0536)... 46 6) MAIN Unit Side B DR-135 (UP0536).. 46 7) MAINUnit Side ADR-435 (UPO543). MAIN Unit Side B DR-435 (UP0543).... })_TNC Unit Side A (UPO402) (option).. 48 10) TNC Unit Side A(UP0402) (option). 20 SCHEMATIC DIAGRAM 21 1) CPU Unit DR-36...... 2) CPU Unit DR.436.. 3) MAIN Unit DR-135. 22 4) MAIN Unit DR-435., 23 8) TNC Unit (option). 24 BLOCK DIAGRAM 4) DR436. 25,26 2) DR-436. 26-29 29-32 ALINCO we.SPECIFICATIONS m_General Frequency coverage: DR-135, DR-435, 116.000 ~ 135.995MHz (AM RX) | 360.000 ~ 511.995MHz (RX) TM«ill 196.000 ~ 173.995MHz (RX) | 430.000 ~ 449,996MHHz (TX) 144,000 ~ 147.995MHz (TX) E Mill 144,000 ~ 145.995MHz (RX,TX) | 430.000 ~ 439,995MHz ( RX,TX) ‘Operating mode FiM_TeKOFSE (Wide mode) 8KS0FSE (Narrow mode ) Frequency resolution 5, 8.33, 10,125, 15,20, 25, 30,50 kHz Number of memory 100 Channels ‘Antenna impedance ‘S0ohm unbalanced Power requirement T3.BV DC +/- 15% (11.7 ~ 15.8 V) ‘Ground method Negative ground Current drain Receive OBA(max.) _0.4A( Squelched ) Transmit ‘Approx, 12.0 A max. ‘Operating temperature 10°C ~ 60°C Frequency stabil +25 ppm Dimensions 742 (w) x40(h)x174(d)_mm (42 x 40 x 188 mm for projection included) Weight ‘Approx, 1,0 Kg _ @ Transmitter Output power Hi 50W, 35W Mid 20W 20W Low ‘Approx. 5 W Approx. 5 W Modulation system Variable reactance frequency modulation Maximum Frequency + 5kHz (Wide mode) +/- 2.5kHz ( Narrow mode ) deviation Spurious emission = 60 dB ‘Adjacent channel power =60 dB Noise and hum ratio = 40 dB (Wide mode) - 34 dB (Narrow mode ) Microphone impedance 2kohm Receiver Sensitivity = 14 dBu for 12 dB SINAD _] Receiver circuit Double conversion super-heterodyne Intermediate frequency 4st 21.7 MHz_2nd 450KHz ‘Ast 30.85 MHz 2nd 455kHz ‘Squelch sensitivity = 18 dBu ‘Adjacent channel selectivity = 65 dB (Wide mode) _- 55 dB (Narrow mode ) Inter-modulation rejection 60 dB ratio. ‘Spurious and image rejection 70 dB ratio ‘Audio output power 2O0W (ohm, 10% THD) ! NOTE : All specifications are subject to change without notice or obligation.CIRCUIT DESCRIPTION 1) Receiver System DR- 135 The receiver system is a double second IF. 41. Front End 2. 1F Circuit 3. Demodulation Circuit 4. Audio Circuit super-heterodyne system with a 21.7MHz first IF and a 450kHz The received signal at any frequency in the 136.000MHz to 173.995MHz range is passed through the low-pass fiter (L118, L115, L114, L113, C204, €203, C202, 6216 and C215) and tuning circult (L108, L104 and D105, D104), and amplified by the RF amplifier (107). The signal from Q107 is, then passed through the tuning circuit (L103, L102, and variable capacitor D103, D102) and converted into 21.7MHz by the mixer (Q106), The tuning Circuit, which consists of L105, L104, variable capacitor D105 and D104, L103, L102, variable capacitor D103 and D102, is controlled by the tracking voltage from the VCO. The local signal from the VCO is passed through the buffer (Q145), end supplied to the source of the mixer (Q106). ‘The radio uses the lower side of the super-heterodyne system. The mixer mixes the received signal with the local signal to obtain the sum. of and difference between them. The crystal filter (XF102, XF101) selects 21.7 MHz frequency from the results and eliminates the signal of the unwanted frequencies. The first IF amplifier (105) then amplifies the signal of the selected frequency. After the signal is amplified by the first |F amplifier (105), itis input to pin16 of the demodulator IC (IC 108). The second iocal signal of 21.25MHz {shared with PLL IC reference oscillation), which is oscillated the external oscillator X102 (VCTCXO), is input through pin 1 of IC408, Then, these two signals are mixed by the internal mixer in 1C108 and the resutt is ‘converted into the second IF signal with a frequency of 450kHz. The second IF signal is output from pin 3 of IC108 to the ceramic filter (FL102, or FL101), where the unwanted frequency band of that signal is eliminated, and the resulting signal is sent back to the IC108 through pin. 5. The second IF signal input via pin 5 is demodulated by the internal limiter amplifier and quadrature detection circutt in IC 108, and output as an audio signal through pin 9, ‘The audio signal from pin 9 of IC 108 is amplified by the audio amplifier (1C120:A), and switched by the signal switch IC (IC111) and then inputit to the de-emphasis circuit ‘And is compensated to the audio frequency characteristics in the de-emphasis circuit (R203, R207, R213, R209, C191, C218, C217) and amplified by the AF amplifier (IC120:B). The signal is then input to volume (VR1). The adjusted signal is sent to the audio power amplifier (10117) through the pin 1 to drive the speaker.5, Squelch Circuit ‘The detected output which is outputted from pin 9 of 1C108 is inputted to pin 8 of IC108 after it was been amplified IC120:A and itis outputted from pin 7 after the noise component was been eliminated fram the composed band pass fiter in the builtin antpiier of the IC, then the signal is rectified by the internal diode in IC 108 to convert into DC component. The adjusted voltage level at VR101 is delivered to the comparator of the CPU. The voltage is led to pin 2 of CPU and compared with the setting voltage. ‘The squeich will open ifthe input voltage is lower than the setting voltage. During open squelch, pin 30 (SQC) of the CPU becomes *L” level, AF control signal is begin controlled and sounds is outputted from speaker. Pee ccetan eae When the freat within 118.000 ~ 135.995MHz, Q113 automaticall frequency is within 118.000 ~ tz, Q118 automatically (T version only) tums on, pin 5 of IC 121 becomes “H’ level and the condition becomes in AM detection mode. The receiver signal passed through the duplexer is let to the antenna switch (D107, D101). After passing through the band-pass fitter, the signal is amplified by RF amplifer Q112. Secendly the signal is mixed withthe signal from the first local oscillator in the firs!-mixer Q106, then converted into the first IF. Its unwanted signal Ig let to pin 16 of IG108, Then corwerted into the second IF. And is demadulated by AM decoder of 118, and is output from Q108 as the AF signal. 7. WIDE/NARROW Switching circuit The second IF 450kHz signal which passes through fiter FL101 (wide) and FL102 (narrow) during narrow, changes its width using the width control switching D116 and D116. 2) Transmitter System DR- 135 1, Modulator Circuit The audio signal is converted to an electrical signal by the microphone, and input it to the microphone amplifer (Q6). Amplified signat which asses through mic-mute control IC109 is adjusted to an appropriate mic-Volume by means of mic-gain adjust VR108, IC114D and C consists of two operational amplifiers; one amplifier (pin 12, 13 and 14) is composed of pre-emphasis and IDC circuit and the other (pin 8, 9 and 10) is composed of a splatter filter. The maximum frequency deviation is obtained by VR107. And input to the signal switch (IC113) (9600 bps packet signal input switch) and input to the cathode of the variable capacitor of the VCO, to change the electric capacity in the oscillation circuit. This produces the frequency modulation. 2. Power Amplifier Circuit ‘The transmitted signal is oscillated by the VCO, amplified by the younger amplifier (Q115), end input to the final power module (IC110). The signal is, then amplified by the final pawer module (IC110) and led to the antenna switch (D410) and low-pass fiter (L113, L114, L115, L146, C216, C216, €202, C203 and C204), where unwanted high harmonic waves are reduced as needed, and the resulting signal is supplied to the antenna. 3. APC Circuit Part of the transmission power from the low-pass filter is detected by D111, convertad to DC. The detection voltage is passed through the APG circuit (IC114:A, IC114:B), then it controls the APC voltage supplied to final power module IC110 to fix the transmission power.3) PLL Synthesizer Circuit DR- 135 1. PLL 2. Reference Frequency Circuit 3. Phase Comparator 4, PLL Loop Filter 5. VCO Circuit 6. VCO Shift Circuit uit The dividing ratio is obtained by sending data from CPU (IC1) to pin 10 and sending clock pulses to pin 9 of the PLL IC (IC116). The oscillated signal from the VCO is amplified by the buffer (Q134 and Q136) and input to pin 8 of IC116. Each programmable divider in IC116 divides the frequency of the input signal by N according to the frequency data, to generate a comparison frequency of 5 or 6.25 kHz. The reference frequency appropriate for the channel steps is obtained by dividing the 21.2 MHz reference oscillation (X102) by 4250 or 3400, according to the data from the CPU (IC1). When the resulting frequency is & kHz, channel step of §, 10, 18, 20, 25, 30 and 60 kHz are used. When it 18 6.26 kHz, the 12.5 kHz channel step is used. The PLL (IC116) uses the reference frequency, 5 or 6.25 kHz. The phase comparator in the IC116 compares the phase of the frequency from the VCO with that of the comparison frequency, 5 or 6.25 kHz, which is obtained by the internal divider in IC116. If a phase difference is found in the phase comparison between the reference frequency and the VCO output frequency, the charge pump output (pin 5) of IC116 generates a pulse signal, which is converted DC voltage by the PLL loop filter and input to the input to the variable capacitor of the VCO unit for oscillation frequency control. ‘A Colpitts oscillation circuit driven by Q131 directly oscillates the desired frequency. The frequency control voltage determine in the CPU (IC1) and PLL circus input to the variable capacitor (D122 and D123). This change the oscillation frequency, which is amplified by the VCO buffer (134, Q145) and output from the VCO area During transmission or the AIR band Reception (118 ~ 136 MHz), the VCO shift circuit tums ON Q138, change control the capacitance of L123 and safely oscillates the VCO by means of H signal from pin 42 of IC1 4) Receiver System DR- 435 The receiver system is a double super-heterodyne system with a 30.85MHz first IF and a 455kKHz second IF. 41. Front End ‘The received signal at any frequency in the 430.000MHz to 439.996MHz range is passed through the low-pass filter ( L115, L114, L116, C204, 203, C202, C216 and C215) and amplified by the RF amplifier (2107). The signal from Q107 is then passed through the BPF circuit (L103, L102) and converted into 30.85MHz by the mixer (106). The local signal from the VCO is passed through the buffer (134, Q145), and supplied to the source of the mixer (Q106). The radio uses the lower side of the super-heteradyne system.2. 1F Circuit 3. Demodulation Circuit 4. Audio Circuit 5. Squelch Circuit 6. WIDE/NARROW Switching circuit The mixer mixes the received signal with the local signal to obtain the sum of and difference between them. The crystal filter (XF101) selects 30.85 MHz frequency from the results and eliminates the signal of the unwanted frequencies. The first IF amplifier (105) then amplifies the signal of the selected frequency. ‘After the signal is amplified by the first IF amplifier (108), itis input to pint of the demodulator IC (IC108). The second local signal of 30.395MHz (Crystal oscillator) is input through pin 1 of IC108. Then, these two signals are mixed by the internal mixer in IC108 and the resutt is converted into the second IF signal with a frequency of 455kHz. The second IF signal is output from pin 3 of IC10B to the ceramic fiter (FL101 or FL102), where the unwanted frequency band of that signal is eliminated, and the resulting signal is sent back to the [C108 through pin 5. ‘The second IF signal input via pin 5 is demodulated by the internal limiter amplifier and quadrature detection circuit in IC 108, and output as an audie signal through pin 9. The audio signal from pin 9 of IC 108 is amplified by the audio amplifier (1C120:A), and switched by the signal switch IC (IC111) and then input it to the de-emphasis circuit. ‘And is corapensated to the audio frequency characteristics in the de-emphasis circuit (R203, R207, R213, R209, C191, C218, C247) and ‘amplified by the AF amplifier (IC120:B). The signal is then input to volume (VR1). The adjusted signal is sent to the audio power amplifier (IC117) through the pin 1 to drive the speaker. The detected output which is outputted from pin 9 of 1C108 is inputted to pin 8 of [C108 after it was been am outputted from pin 7 after the noise component was been eliminated from the composed band pass filter in the built in amplifier of the IC, then the signal is rectified by the internal diode in 1C108 to convert into DC component. The adjusted voltage level at VR101 is delivered to the comparator of the CPU. The voltage is led to pin 2 of CPU and compared with the setting voltage. The squelch will open if the input voltage is lower than the setting voltage. During open squelch, pin 30 (SC) of the CPU becomes “L” level, AF Control signal is begin controlled and sounds 1s outputted from speaker. The second IF 455kHz signal which passes through filter FL101 (wide) and FL102 (narrow) during narrow, changes its width using the width control switching D146 and D118.5) Transmitter System DR- 435 4. Modulator Circuit 2. Power Amplifier Circuit 3. APC Circuit The audio signal is converted to an electrical signal by the microphone, ‘and input it to the microphone amplifier (Q6). Amplified signal which passes through mic-mute control IC109 is adjusted to an appropriate mmic-volume by means of mio-gain adjust VR106. IC114:D and C consists of two operational amplifiers; one amplifier (pin 12, 13 and 14) is composed of pre-emphasis and IDC circuit and the other (pin 8, 9 and 10) is composed of a splatter fer. The maximum frequency deviation is obtained by VR107. And input to the signal switch (IC113) (9600 bps packet signal input switch) and input to the cathode of the variable capacitor of the VCO, to change the electric capacity in the oscillation circuit. This produces the frequency modulation, The transmitted signal is oscillated by the VCO, amplified by the crive amplifier (Q138) and younger amplifier (Q115), and input to the final power module (IC110). The signal is then amplified by the final power module (IC110) and fed to the antenna switch (D110) and low-pass filter (L116, L114, L115, C215, C216, C202, C203 and C204), where unwanted high harmonic waves are reduced as needed, and the resulting signal is supplied to the antenna, Part of the transmission power from the low-pass filter is detected by D111, converted to DC. The detection voltage is passed through the APC circuit (IC114:A, 1C114:B), then it controls the APC voltage supplied to the final power module IC110 to fix the transmission power. 6) PLL Synthesizer Circuit DR- 435 4. PLL 2. Reference Frequency ‘ircuit 3, Phase Comparator Circuit 4, PLL Loop Filter Circuit The dividing ratio is obtained by sending data from CPU (IC) to pin 10 and sending clock pulses to pin 9 of the PLL IC (IC116). The oscillated signal from the VCO is amplified by the buffer (0134 and Q135) and input to pin & of IC116. Each programmable divider in IC116 divides the frequency of the input signal by N according to the frequency data, to generate a comparison frequency of 5 or 6.25 kHz. The reference frequency appropriate for the channel steps is obtained by dividing the 21.25 MHz reference oscillation (X102) by 4250 or 3400, according to the data from the CPU (IC1), When the resulting frequency is ‘5 kHz, channel step of 5, 10, 16, 20, 25, 30 and 60 kHz are used, When it, i 6.25 kHz, the 12.5 kHz channel step Is used. The PLL (IC116) uses the reference frequency, 5 or 6.25 kHz. The phase ‘comparator in the C116 compares the phase of the frequency from the VCO with that of the comparison frequency, 5 or 6.25 kHz, which is obtained by the internal divider in 1C116. If @ phase differenice Is found in the phase comparison between the reference frequency and the VCO output frequency, the charge pump output (pin 5) of [C116 generates @ pulse signal, which is converted DC voltage by the PLL loop filer and input to the input to the variable capacitor of the VCO unit for oscillation frequency control5. VCO Circuit 7) CPU and Peripheral 1. LED Display Circuit 2. Dimmer Circuit 3. Reset and Backup 4. S (Signal) Meter Circuit 5. DTMF Encoder 6. Tone Encoder 7. DCS Encoder 8. CTCSS, DCS Decoder A Colpitts oscillation circuit driven by Q131 directly oscillates the desired frequency. The frequency control voltage determine in the CPU (IC1) and. PLL circuit is input to the variable capaciter (0122 and 0123}. This change the oscillation frequency, which is amplified by the VCO buffer (A134, Q145) and output from the VCO unit. cuits ‘The CPU tums ON the LCD via segment and common terminals with 1/4 the duty and 1/3 the bias, at the frame frequency is 64 Hz. The dimmer circuit makes the output of pin 13 of CPU (IC1) into “H” jevel at set mode, s0 that Q9 and Q3 will turn ON to make the lamp control resistor R84 short and make its illumination bright. But on the other hand, if the dimmer circuit makes pin 13 into °L" level, 29 and Q3 will turn OFF, 4's illumination will Become dimmer as its hang on voltage falls down in the working LED (011, D2, D5, 03 and D6). ‘When the power ftom the DC cable inoreases from Circuits 0 V to 2.5 V or more, "H’ level reset signal is output from the reset IC (IC4) to pin 33 of the CPU (IC1), causing the CPU to reset. The reset signal , however, waits at 100, and dose not enter the CPU until the CPU clock (X1) has stabilized. ‘The DC potential of IF IC is input to pin 1 of the CPU (IC'1), converted from an analog to a digital signal, and displayed as the S-meter signal on the Lop. ‘The GPU (IC1) is equipped with an internal DTMF encoder. The DTMF signal is output from pin 10, through R35, R34 and R261 (for level adjustment), and then through the microphone amplifier (IC114:A), an sent fo the variable capacitar of the VCO for modulation. At the same time, the monitoring tone passes through the AF circuit and is output from the speaker. The CPU (IC1) is equipped with an intemal tone encoder. The tone signal (67.0 to 250.3 Hz) is output from pin 9 of CPU to the variable capacitor (D122 and D123) of the VCO for modulation. The CPU (IC1) is equipped with an internal DCS code encoder. The code (023 to 754) is output from pin 9 of CPU to the voltage control pin of VCTCXO (X102) of the PLL reference oscillator. When OCS is ON, DCS MUTE circuit (Q126-ON, 2133-ON, Q132-OFF) works. The modulation activates in X102 side only. The voice band of the AF output signal from pin 1 of [C120:A is cut by sharp active filter IC104:A, B and C (VCVS) and amplified, then led to pin 4 of CPU. The input signal is compared with the programmed tone frequency code in the CPU. The squelch will open when they match. During DCS, Q108 is ON, C479 is working and cut off frequency is jowered.8) Power Supply Circuit ‘When power supply is ON, there is a "L” signal being inputted to pin 39 (PSW) of CPU which enables the CPU to work. Then, "H’ signal is outputted from pin 44 (C5C) of CPU and drives ON the power supply switch contro! Q8 and Q7 which tums the 5VS ON. 5VS turns ON the PLL IC ((C116), main power supply switch Q127 and Q122, ‘AF POWER IC117 and the 8V of AVR (IC115). During reception, pin 29 (R5) of CPU outputs “H’ level, Q124 is ON, and the reception circuits supplied by 8 V. While during transmission, pin 28 (T5) of CPU outputs *L” level which is reverse by Q11 so that the output in Q728 will be "level, Q123 is ON, and the transmission circuit is supplied by 8 V. Or, in the case when the condition of PLL is UNLOCK, “H” level is outputted from pin 14 of PLL IC, UNLOCK switch Q128 Is ON, transmission switch Q128 is OFF which makes the transmission to stop. 4. ACC External Power Supply Terminal When optional power supply cord EDC-37 etc. is connected to the external power supply terminal JK101, with ACC power supply ON, switch Q101 will tum ON, & V of AVR IC10% pin 2 (STB) becomes “L* which makes CSV to turn ON. With this, it can turn the power supply of the radio ON.9) M38268MCLO75GP (XA1130) CPU Terminal Connection (TOP VIEW) 10No Signal_|_VO_| Description 1 ‘SMT 1 | Ssmeter input 2 Sat 1 | Noise level input for squelch 3 BAT 1 Battery voltage input 4 TIN’ |__| CTCSS tone input / DOS code input 5 _| POSISCLK22/AN3 | __BP1 1 [Band plan ¢ 6 | PO2/SCLK2V/AN2 | BP2 1 | Band plan 2 7_| PevSOUTZIANT | DCSW_| 0 __| DCS signal mute | PSO/SINZ/ANO [REZ 1 | Rotary encoder input 9 | PSTIADTIOA2 | TOUT | _O | CTCSS tone output / DCS tone output 10 |__ PS6IDAt OUT [0 _ | DTMF output 11 | PSsIGNTRI_| SCL ‘© _| Serial clock for EEPROM 12 | PS4iCNTRO | TBST | _O | Tone burst output 13 | PSaiRTPI BP4__|/O_| Band plan 4//lamp dimmer HI/LOW switch 14 |__PS2/RTPO MUTE [VO | Microphone mute / Seourty alarm SW ae 15 | PSiiPWMt CLK ‘© __| Serial clock output for PLL, scramble : 16 | PS0/P WMO DATA | VO _| Serial data output for PLL scramble / PLL unlock signal input 17_[Pa7isRbYi__ | TSTB_ | VO | Trunking board detection / Strobe signal to trunking board 18 | PaB/SCLKA STB (© _| Strobe for PLL IC 7 19 | PasirxD UTX__| | UART data transmission output 20 | Paa/RXD RIX |__| VART data reception output 21_| _PasigiTOUT | BEEP | VO | Beep tone / Band plan 3 22 |__Paannt2 SEC [Security voltage input 23_|__Pavdintt REt |__| Rotary encoder input 24 PaO Ds@ [Digital squelch input 25 P77 PIT 1_ [PTT input 26 P76 SSTB__| 0 _ | Strobe signal to scramble IC / Security mode 27 P75 WIN (© Wide Narrow SW 28 P74 i ‘0 [TX power ON / OFF oulput 29 P73 RS: ‘0 [RX power ON / OFF output 30 P72 sac__[ 0 [SQL ON/OFF 31 P71 os ‘© | Digital scramble ONT OFF 32_|___PronNTO BU 1 | Backup signe! detection input 33 RESET RESET |__| | Reset input 34 XCIN Xcin - 35 XCOUT Xeout_| = |= 36 XIN Xin = _| Main clock input 37 XOUT Xout =| Main clock output 38 vss GND = [GPU GND 38 P27 PSW. 1 [Power switch input 40 P26 ‘SDA__| 0 _ | Serial data for EEPROM 41 P25 5G © | C8V power ON OFF oulput 2 Pad AIR © | Air band SW//Tx middle power 43 P23 tow [0 | Txlow power 44 P22 EXP (© [Trunking / Packet data SW a5 Pat SWw6 1 [Key sw 6 (SQL) 46 P20 'SW5 1__[Key sw 5 (CALL) a7 PIT swa |_| Key sw 4 (TSa) [43 PI6 'sw3 |_| Key sw3 (MHz) 49 | P1S/SEG39 ‘sw 1 | Key sw 2 (VIM [50 | P1a/sEGse ‘Swi 1__ [Key sw 1 (FUNG) 4No. |___ Terminal Signal_[ VO Description si | PisiseGs7__| DOWN 1 [tic down input [52 | Pi2iseG36 DUD 1 ~/ Digital unit detect [53 | PriSeG3s SCR 1 [Scramble IC ready signal / PTT input for 9600bps 54 | PIOISEGa4 UP T [Mic up input 55_|_ PO7ISEG33 833) ° |_56 POSISEG32 $32 oO 57 | POSISEG31 S31 ° 58 | Poa/SEG30 S30 oO _| 59 | PO3/SEG29 S29 ° 60 | Po2IsEG28 S28 o_| 61 | POvseGa7 ‘S27 ° 62 | POOISEG26 S26 ° 63 | P37ISEG25 S25 ° [ea | P3esEG24 S24 ° 65_| P3siSEG23 823 o | 66 | P34/SEG22 "$22 ° 67 |__P33/SEG21 ‘S21 ° | 68 | P32/SEG20 $20 ° 60 | P3t/SEGi9 ‘S19 0 70 | P30ISEGi8 S18 oO 7A SEGIT si 0 oo ee oe | LED segment signe 73 ‘SEGI5 S15, 0 [74 ‘SEGI4 St o 75 SEGIS S13 0 76 ‘SEGI2 S12 o 77 SEGIt Sit ° |_78 SEGIO S10 0 79 SEGO 89 oO [80 ‘SEGB 88 ° 81 ‘SEGT ST oO 2 ‘SEG 86 © 83 SEGS: 85 oO 84 ‘SEG4 S4 0 85 SEG $3 ° 86 SEGZ S82 ° [a7 SEGI St ° 88 SEGO ‘SO ° 89, veC VDD. =__| CPU power terminal 20 VREF Vief = [AD converter power supply 31 ‘AVSS. Avs = [AD converter GND 92 coms coM3_| 0 | LCD COMS output 93 coma come [0 [LCD COW? output 4 comi comt_| © [LCD COM# output 95 ‘como CoMo_[ 0 | LCD COMO output 96 Vi3 Ws =| LED power supply 97 Viz Viz = [LCD power supply 98 C2. i ol 99 ct ci oe 100 vit vit T [LC power supply 2SEMICONDUCTOR DATA 1) NIM7808FA (XA0102) 8V (1A) Voltage Regulator 7a08h | 4. INPUT, JRC based 2. COMMON 3, OUTPUT 123 2) TC4S66F (XA0115) Bilateral Switch 5 4 cag 4.IN/OUT 2 OUT/IN | co 3.Vss ere 4. CONT fede 5. VDD 3) AN8010M (XA0119) 10V (50mA) Voltage Regulator EEE PEE IEE =< * 4, OUTPUT o * 2. COMMON 3, INPUT 123 4) BU4052BF (XA0236) ‘Analog Multiplexer / De-multiptexer oof _ [aw Beeee QA CONT | Function (N-OUT) B L_| Disconnect (HiZ) | 7 H__| Connect (2800hm 4 ooo ¢ 2.) 123 vEHe © 2 vomon [31 tyro 1 EH Iyour vB Fi] wevorr (BH, is ve TH my vss] ae innigiT | A [8 [| COMMON | ON SWITCH ce fele Xoo ufaie xt¥4 uc [ttw) xy X2¥2 c_tulea XB ¥3 Ht NONE | * Don't care5) TC4WS53FU (XA0348) Multiplexer / De-muitiplexer 8768 4. COMMON 2. INH EC 2m Sonic input | "ON channel ANF init ti ot ; tA ch Bort eile Sone a * NONE Zech o * Don't care 1234 6) TA31136FN (XA0404) Narrow Band FM IF IC 9 WENO a EOee Rd 8. AF OUT i ARE 2OSCOUT — 10. QUAD 3. MIX OUT 14. IF OUT 4. Voc 12. RSSI S.IFIN 18. N-DET 6 DEC 14, NREC 7. FIL OUT 15. GND. 8. FILIN 16. MIX IN 16|—{i5}_f14}-_[13} f12| {11} 10} 9 te T tur Wier RS Rssi r Noise Conparator t hae oe ‘utter r] [eae Filter Aro eal IF Aa. sci INator7) LA4425A (XA0410) 5W Audio Power Amplifier Qa 4. Input 2 Sal signal GND Laas 8. Lerge signal GND baad 4. Output 5. Vee 12345 8) BR24L32FJ (XA06042Z) 32K-Bit EEPROM 87165 1.80 AAAA 7 ni av i is lO) tee : PHS iy 1234 9) S-80845ALMP (XA0620) 4.5V Voltage Detector 5 4 41, GND Ho 2.Vn B66 axe Tag Pr See 10) L88MSO5TLL (XA0675) Test Cirouit Veo=13, 2 Rl=dohn Po=5H Gain=45d8 User Configurable Chip Select Ground Serial Address / Data / VO Serial Clock WP) ‘Write Protect Input Veo 42.5 ~ 6.0V Power Supoly 5V (500mA) Voltage Regulator with On/Off Function 4.¥in 2sTB 88405 3B meet 4.Cn 5. Vout U T234511) S-816A50AMC (XA0925) External Transistor Type 5V Voltage Regulator with On/Off Function 5 4 AA BAZ* gua 123 4. EXT 2.Vss_ 3. ONIOFF 4. Vin 5. Vout . 412) LM2904PWR (XA1103) Dual Operational Amplifiers 43) LM2 8765 * * Oo L2904 Output A Inverting Input A Non-inverting Input A. GND Non-inverting Input B Inverting Input B Output B 8.Vec 902PWR (XA1106) Quad Operational Amplifiers 4131211109 8 L2 oO * 0 sk: o*: ¥¥O x¥¥N 1234567 Output A Inverting Input A Norvinverting Input A Veo Non-inverting Input B Inverting Input 8 Output B Output C Inverting Input C Non-inverting Input GND 2. Non-inverting Input D 43. Inverting input D 14, Output D 1 | pe j14) MB15E07SR (XA1107) PLL Synthesizer 16 15 14 13 1211 109 E07SR seb eK 12345678 4.08C IN 9. Clack 2N.C, 10. Data 3. Vp. 11.LE 4. Veo 12.PS 5.Do BNC. 6. GND 14, LD /fout 7. xfin 15.N.C. 8 fin 46.N.C. (ata Referee Binary Fee Tose act ator zeterene conte ate Lue toten | —_ paar osal ier | nar To wane detector 7 itt ae ssleotor loot eh ; etch | itis late 4 Fie | ears ate eee ‘lor | | teopramble Sine | "sancr coatno (Veo = 2,7 to 5.0V, Ta = -40°C to +850C ) Parameter ere Condition min. | Typ. | Max | unit | Power supply voltage. Veo = 27 | 375 | 50 | Vv 500M Hz Power supply current lec eves Tal. 80 mA TPF supply vollage Ve = Vee [= 55 |v OOM to 0OMHz | -6 "2 Local oscilator input level | vin | /00MH2 to S00MFiz |S 22 | apm Tocal oscillator Taput aun fin : 100 |_| 2500 | ie Xin input evel Vain : 05 Vec_| Vpn Xin input frequehg Fxin_| 5 3 40 [MHz 715) RAGOH1317M1 (XA1108) 144 ~ 146MHz 60W RF Power Module [OUTLINE oRAWig Ht ABSOLUTE MAXIMUM RATING ( Te = 25% Unless otherwise noted ) LOOK DIAGRAW tia. OF trout Pied @ Gate Voltare (N66), Power contro! @ drain Voltage (VOO), Battery © FF Osteut Pout) © RF Ground (Case) Simbel Parameter Conditions Ratings Unik ‘voo | Drain Vallage VGG<5V,26 = ZL = Stonm 17 Vv ‘VGG___| Gate Voltage VoD < 12.5, Pin=s0mW 35 Vv. 1DD | Drain Current 2G =2L.= 50chm 16. A Pin | Input Power f= 135 ~ 175 MHz, Pin=SomW 700 mW Pout | Outpit Power 2G = 2 = 500hm 30 Ww Tease (OP)_| Operation Case Temperature “B0i0 110 alg] Storage Temprature =4010 +110) ° ELECTRICAL CHARACTERISTICS (Te = 25°C, unless otherwise noted ) Ratings ; Symbol Parameter Conditions Tin er Un t Frequsney Range 135 175 | Wz Pout | Output Power 60 WH aT | Total Efficiency Neate 45 %_| 2fo 2 Harmonit eae aoa ia -60_| “ape Pin [Input VSWR ait - | 16G__| Gate Current 7 mA, Stability VSD=10.0-18.2V, Pir=25-7OmW, No parasitic : Pout<70W (VGG control), Load ‘oscillation : VSWR=3:1 Load VSWR VOD=16.2V, Pn=6OmW, Pou=6OW | No degradation or - Tolerance (VGG contra), destroy L_ Load VSWR=6:1 : 816) S-AU8: 430 ~ 450MHz 60W RF Power Module 2L (KA1142) ‘OUTLINE DRAWING ns a, | | @@ mo e 10a 8 g & Si DF input ® Gate Voitege (VO), Power Con @® Drain Yo (ie) | @aF ovtput Pout) ABSOLUTE MAXIMUM RATING (Te = 25°C, unless otherwise noted ) +@ rtrol | ‘tage (YOO), Battery l © RF Ground (Franee) Symbol Parameter Conditions Ratings Unit ‘von | Drain Voliage VEG <5V,Pi= 50mW, Po <60W 165 Vv VEG | Gate Voltage 7 55 Vv ¥GG___ Gate Voleas_ VOD < 12.8, Pin=5omw 55 ¥ Pin | Input Power VOD <72.5V, VGG<5V, 700, mW, Pout | Output Power Mee tere 80 w ‘Tease (OP)_| Operation Case Temperature “301 +700__| °C “Tsig___| Storage Temprature SS ~a0to +100} °C ELECTRICAL CHARACTERISTICS ( Tc = 25°C, unless otherwise noted ) symbol Parameter Conditions Pail Unit | iMin_| Typ | Max [FF Frequency Range 400 470 | MHz Pout | Output Power 60 nT | Total Efficiency 40 fo 2™ Harmonic, -30 Pin _| Input VSWR 3.0 16G___| Gate Current 7 Stabilty VODHO5-16BV, VGG=05V, Pin=6OmW, | Allsprious output - Poute60W (VGG control), Load VSWR=3"1 | than 6008 below | - ALL PHASE desired signal Toad VEWR (0.5-16 BV, VGG=O8V Pin=50mW, | No degradation 7 Tolerance Pout=60W (VGG contro), Load VSWR=20:1 ALL PHASE = : 1917) Transistor, Diode and LED Outline Drawing 20 Top View M407 isvais | 18v237 WAT28 xp0395__| " x00400 x90402 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(rrssse loner leruaceiioux 1 lreze |rrzezs ovr |erucenioxx 1 Ini |reasas Jonpr — |eroevioix 1 Jes Jarssts joapr — |enoocsasmx : Inizs frrasse fowpe — eruoceviozx 1 eas anscse |onpr — eneaezevte : Inv fovasst fompa — leruacestx ‘ lr arseor Jenpr. —|erveccanane 1 Ins facseso |onpe — lenocevionx : Jeo Jarssse Jompr — feruosenozx 1 Jnvzo |reseso |ompm — eruocevtowx ‘ Jeo arsesr Jonpr — |emsaceriax 1 Jno [arassa Jompa. — leruacevioux : Jrao Jarsece ompr — eruaccierx 1 leisy farssse forpm — leruscevioax ‘ Inst Jarscso |omon — croezmsios ‘ Intze frrasso lonpa — leuoceviow: : Jneze Jrracas Jonpr —Jensaoerorx 1 Jars: |reasor fompe — enaceseanx ‘ leewe |rescas fonpr — |erazccinozx 1 Jnise frrcess lonpe — lerusceviesx t Jase Jarcess |onpn —|erveeisoax 1 Jntze farast Jenpa — eruacexerix : Jn farses |onpr — ensoceroxx 1 Inver frnsoso lonpm — erucestoox ‘ lees Jansest Jowpr — lenuocesiasx : late frrsore loupe leruacevrax ‘ nes Jaraeas ompR |eriocevionx ‘ lates |arasee fonpa — eruoceax : Jee Jrescse ompR eniocevioux 1 Jntes frxssee lonpe —ensaceiooex : Jes Jrxaeso Joner —eruecesioax ‘ lates frrcess Jowpe — leruscensax ‘ Jno araese ompR. |enocevioxx ‘ Jats frrasse Jonpa — eruocessax : leat Jeraeso Jonpr: — feruosevsoxx 1 Inver |rcaso lonpr —erusoevtoax 4 Jew Jaraeee Jonpn — |eraccverax : Jateo frrsese loupe — eruacextozx : Jas Jarasso |onpr — |erooeisoax ‘ Ins anasse Jonpm —leruzcesioux : leat Jresees Jonpr — leruaseisex 1 Jno |rrsors |ompe — eniogeuerax 4 Inas Jaraese Jonpr. — enlacevtaxx 1 later farssso loupe etuacezoax : nas Jarsses Jonpn — |eroceuerax : Ini frrasso fonpa — |eruocesoax 4 leew Jreseso Jonpr. — fenvaseuvo ‘ Ins frrsesn |onpr —leniocevoax : leowe Jaraero Jompr — |eraocurax : Ini frrcsst lonpm — leruocenaax 4 Jaw Jarssra Jonpn — feruoceuerax 1 nies frrssse fonpe — enloceurax i ass Jaraess onpe — |eriaceizax 1 Jas fanssse |owpr. — lenuaceutoux 4 jez Jarsero foun |eruosexrax ‘ Jee |araea> Jonpr —enlooeverox 4 ras Jarscsr Jonpr. — feruoceison : Ini ferasro Jowpr — leruocexerax : Ina Jarsesr |onpe. — erizcessoax 1 Ineo |rrcase lorem leriacevtoax ' as farses Jone lenaceurax i nice frrcsse Jonpe — leriaoenoax 4 fess Jarseas Jonpr — femiascivorx : lee ferase: lonpr erueseisomx : er Jansess Joups. — leniogeusrx : ies Jrcets leben funestne : fase fcsar lenpm — [emnoeioont 1 Ines ferssrs |owpe. — ftugcesomx : fess fosest lenpn. fenlsevaae i lai [rrassa lompm — lercevtax : ct recess Jonpe. —leminccvzase 4 Jie farssst lonpe — eruzcesiax i fece Jarscoo fonpe, —leruacesoex 4 Javea fevasst Jompa — [etuoceasx : ee Jreaess Jonpe — leruncevsoox ‘ Jae frnssso lonpa — jeriogevvozx ‘ Jrass fraser fonom —|/endacestoox : Jaz frnsese |onpe lerugcexrax : acs Jreseco Jonpn — lersceivoxe : Jams fressse |oope — jerocexoux : cr Jarsere Jonpe — leniageuarax 4 laze |rnsese Jonpe — endacevtoax ‘ Jes frseso [eno —eningeinomx ‘ laiza frncace Jompe — eruacexorx : co recess Jonpa — |enusceuvoat : ini |resote lonpm — eruacesrax 4 et Jaeacon Jeonpe, — lemurewrwy : Javma frase Jonpe — eruacessix i feta |ressso omen (eniacciroxx 4 Jarra fressse Jompe — lenuocesrax : fers Jrrseee Jonpe. — (enasesiox 1 Jao |rrcest loope — eniaceverix 4 fre Jreseso Jonpe, — lercesrx 4 lave: frrcsse Jompe — fenlaceizax 3 revs fsso Jonpe — femiacevsx ; lave frrssee Jonpa — |eroceszozx : liste freaese [enon — eningeverix ‘ lates frrcess Jonpr — eniaoessocx 4 jaar fuser [onan — leninoemzax : Jae frases Jompe — leruacenorx : lazra frusees [enon — lenuoaesiorx 1 Ines frrsoro lonpa —|erueceserex 4 lnsre faaoes fonon © facrasczruar2 ‘ Irie |rcsse loop x i jase fracese [oman — |ennngeioax ler |rrasse fonpre : lazer frasosr fonom — facrasezravec Ineo |rrasee [onpe ‘ Jrses |receeo lorem — leniocestone : ea |rvasie [ene __[epiouectoox H [rvs [recess [one RET :fa] eana [onsen | ronan |e raowore |v ed fear freee m7 m fam fics foo exmocurin 1 Moen ; leer fsee lowe |enaoeir i frcsiecears | 3 fm fos lope (enmscir : IMeswacirs |S fim Joo [owen torent i erste : je use lowe lenwocias : fearesee : fi fies fee eka : feossicene : Jase fase [owe lentoeiaon 1 Frere i fs nese [oes iekncarat : feorsicue : Jess fuses [oon |emosenn : Feecrcs i fis fuse [ome letmccioa : iSecienr : lest fase [owe lenmoeiann } fesercne i face fenaociane i feeererar : ese fete 1 eeekicteverse | | eee fenmoetoie i sera ar ! ese fetes : foie fone faces [sundae |! eee fenimosene : fre: fewet Pierte fineatmsincs |! foe femmecieer : Jremer lewsor'” feustonowss i leer fenocwrs } cos [sme fovosmnconso | i eee (etaeeceat : fee [eines feicon ouren : ese (etieeiant : foe [Reo [ensue i face fens i eee fenworss : for lenioetiee i MAIN Unit DR-435 eee lenis ; fave] rotna [ owcrin | ronan [ov [ve fee lenge i leo ope rE ese (eteeemane i Ee feereero| | leoe —enaoeisun } fs fwesxcraree | | fee jenaecient : fe lmeaseceraoro| | fase fenmecte i fs Fecweacranee | | eee fenaeert : ee lewresaceaore| | eee fetoem : fe fstcramerrones | | ese fucmatioe : ss Karas] | fase [etmocizas i Es : leer (enact : fs : Eee feces: | fs : pe (eta i Es i ese lensoctany i Ke : eer fenaeetont i is : face fenmoctzm ee Fewrsecrcacr | | leer (enact ee emericeoare| | Jobe fetecert ie : rer fener Ei lsercsrntcaaoo| | eon (ett : Ee lemusisiieatore| free fenwocieas : Es fewnsecitices| | fee feocisnt : Bea lScnerioae| | ck fennocienx : Es ements | 1 leer fenaoesia : Ee lewesccternssto| | fcr fect : Kee lSaneriterawe| | lace fenaocican : Ee lewsionmicaare| 1 lace fengoctiay : Ee lewnsectranco| | eee fenaoctens : ie leans | | fcr fenaoeion : Ee lewnsisrwenare| 1 ese fete : Ete lewsecmenees| | eee (emcee : Ee ewcesnecerae |} lace fenaocize : Eis fewer : ese (eta : Es Jetestettacoro| | Jee (enor: : Ee: feweveseae | leer fenaoctane : Es leerernencrre | fcr fengecting Est leensemeczcsro| | leer fenmoeieay Es Fsensiectneoo| | eee fenascieat : Es feersieiteaaee| 1 een fenscrs : ks freedcreie| 3 fee fenaectims : tt forsee eer fener ae frerseersaaoa'o free enwozteue : se estonia) fcr fengocta : e eer cane oer naar, : a Frenette | face feriocien } 3 lserseracnacre| | fre fenoctan, : Er lensecterens| | ck enaoctase : 3 lewnsserimcearo| free fennoein: : Ene lewrswcrccusro| | fer — fenaoeton, i Eins restore |} foe fenmosmane : fers scree | 3 fer fenostnne : fens lscesieenccrs| | free ferneesnne i fine jourcstavcwacts| lace fensostine i fe leersievtrenaa'o| jeer (eter : fet ecierireacors| | free fenoumene i ewe] 3 ese (eee : : [oon _lesabeian : :30 ‘ lsrunsesriissnaoio] 1 Iasxarsuai lersusszcreretapoo| 1 lernagsarsarxcnoso [Srussocimsonanio) 1 fers fescaase |Srotemsum frauarssoror lsrursssttceraraio| 4 lero fusnate foamecor ” Poensosrs lowousteraacras ‘ Jewion|uscasa \Eouaaor eros tear owns i Jewiosfuscase feowecsr res |cteoucresovee vs ‘ Jens fuacaaay fuss cronies feroowarssae : lens |uccata ssncsce lease lessiss lene ' ler fuecons pasa fsza2 fousess lenpo: lammssarimeaaoio| | Jeo |uecoet [rsesorxvs lesss fesoct enpiomaen [racraseseaurne : lo fueeaet fp2sscou lesse feusstt fenpe lexmmssccrrooeeso | lower fxoonet ssvzarteas) fees feusess fence. fonmssorirnomaora | sce jrocase ssseoter? fess feunses fénpe. foramasicsranccamo] ies ronan jvozrae sta fczso Icusses fenpe: fonwiseornnacznaoro | lar Peoore svzarreos.) lczro Jeusowr fence: feveonmneraserse i see fronase [32300 ter? lesa [esi00. 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frnscsa fowpe — femuzcesiose : jureosr08 1 Inia [races foupe — emiacevioox ; lunsczsres : Inst |rcsso owe — feriacenoax : luna saree 3 Inge [vases owe — ercesoax ; Keswrncroom. 3 faces exszoesione 4 Invszrezzsers : fasee exuzoezae : lkaososrenen } asst enuzeeszae ; leconesrenaad : asso lexacelurax ; lsio-a00 ; vssce lewzcesox : Laos esios i eases leszcesosx : Ikaosecrrensst i leasoe lexizcesonx : fentrenaeivery ‘ Jos frcronezreen 4 lansiomevire.s) i Jrasre forse — [eecesrose 1 lEwooran : Jrrasee fenoe — fercesosk } frnnionevres 4 Jarsses fener fences bscszeertesst) : lrcasse fonoe — fenacencox 3 Fescearesr) ; Jrasse fence fences 4 fascsaress ; Jrasss fener fenacenone 4 rwriomevie) : frcsso fence fermceneax 1 lesoaenie 5 Inicsee fener fensacemenx 4 faspocaiet i Jrcsez loner lenmcencox 4 frost) : Jrcse fehpe — Jenvecesicox 1 lsscasaeri nas) ; fricses fener — fenmcenioce 4 lewcoraa ‘ frase fener — Jensscesoox : Jevtionervrey : Inscs fener fersacesoex : bras TOE 3 jncsas fonpe — fensasestone 4 Hsxrowic reo : eso lene — |enisczserax i lasccon cen : frome Jove [eruroerese : fanrroareosie) : lcs oven ferizocrox i : fas: \enpa: — [etuzcesrone : : Incsis Jena [enincevione : serous r1coa 1 frcsse fore — femuzoerioax 4 fssoreaat 1 frcsoe fonee — feruscerione 4 leosrzn 1 lrcasis fonpe — lEnincerioox fawticrtrvry 1 lcs fone —fenizoenrax fasczom icon 1 frase fener — jenmcsnoa faxiterarvaresy 3 frasio Jonpe — jenscuernsn faniieatessu) 3 fase owe lence : Jasiicaresstr) i Irose Joner — |eRiacelzznx pezsroe i imasro fone lenacesrax faxtionervir) i fase Joon — [erizoeiczee lesttorarvics) 5 Jrccoas fener Jeescerseriv fscesdswrtesst ' Jacses fener enacesssox fesciarerttesa.r) 1 fraser forse — lenacessoax fwiteu 4 Jrcocs fener jemoceriton fastonsevooc 4 Jrrooes fener |enceeimaoy fscazaerieaoy ; frases feren — Jenansisae soar rare ; frcsss fener — feniaociorx scacat riost 1 Jace: forge fenvaceseax rxatonervereay i frcse fener — fervaaszex Jrntiowresscr 4 factors fenpe — ferverzaou scsoa T1058 : frcioas fonpe — fenzeinowy pscsoesvrensy : frcss fener — feniacevex sacra 1 frescos [orp [emceniaax lewosran : frcsos fener fenszcemsrx frcaressir : frcaoes fener — |eaoaezrstse 4 ierueveey 1 vcoso_[empe___cnoserest03 3132 Parvo, | Owsoston | __Parelene ey [wr] [rere] rote ov [ver Roa [oTpR ERENT fer po frase foun — |rmiacenaxx ; Feat fucse 3 Jrcaesa fone fersravaar 4 Jrsz2 fpooice ‘ Ireoseo fener — fenvaceenx : Irs. fraser ; lrcasos fenpe — fensacenionx ; fraae frrcore i lrcsoo fonpe — fensecesarx : fs frase : lasso fonpe. — fensaceuenx : fre. freasee ; Jrcos fonpe — |uctoseznsce 4 for fcoce i Imo: Jeno ferszceoncor ‘ frezs fposors : Irasss fowpr fences 4 fre frases i frosso foe fenacesane 1 frst frrssse ‘ Ince fener — lenaecieme t frase frases i fro fenpe — ucmaearivas 1 tas farses i lrrosca fone lenscenroe : i lrrssia [oupn — eniaeevcox : t lrrsose fener. enucesnane 4 : Ineass: fener Jenacevraae 4 i lrcssos forse exstoesone : i Ireasea Jenene. |enszoestooe 1 ; lncsso owe eRszoes:coe 1 i Jacssse Jowpr. — [enszoesicax : | Irasso lew — fenizoenene : ; lacases Jonpe, [enizoesczne : Jerioesaak 1 Ireasce fonpe — ferizceviaas 1 leaoeviosx 4 Iiaéve Jens: Jemuzcesirax 1 ences 3 asco jones erizcevroax 1 lsasezax 1 Inmasre [one fenizoesir ‘ Jenioevoon 4 Insooa |oupa jcoaer i 1 lerer —ferszaesioo 4 Irrasio [Supe ferizceno 1 leren —ferszsestaox 4 Jnrasoe fompa — feruzceazae ‘ lsren: — fensaaeiene 4 lraasro shoe feeizoevoa 1 lover ferszsesroe 1 Incase [ome feruzcesaeoe 1 Jeter feriacenrox 4 lncacsr [ompe — feruzceinene : Jere fersaaeoeese 1 lresse |onpe — feeuzcessrax 1 leven fenszoesseox : Jrcaas ome — ferizceston 1 lsren — ferszaesrooe 4 lnesoe Jowoe — ferssceserne 1 leven. femzosineae 1 Inessr Jospe — feeuzoesaeon 1 leror — ferszoesteax 1 Jeesso |Gcpe — ferszoenteoe ‘ lcien — fenszaetza0e 4 frxssse fospe — fenvcoeizex 1 lenox. femizasseroe 1 lrcsoa fompe — fenaoeoaan 1 cre ferizoesrcox 4 lncssr: fener fenvaoesseax ‘ loon fenszamsoe 1 frrsis foe — fenecesoan 4 lever. ferzoemese : jricsss foe fenacencox ‘ ston fenizoesteae 1 frncsso fewer femmes 1 lever. ferszoeineoe 1 lriasoe foe fenoesron 1 leven ferszoemzee + Jricsso foe fenmcentene ‘ lsten — femszsesraoe 4 lrncsso foe ferscoescen ‘ lower fenszaesrzse 1 Jrrasso fompe — fensacesenn 1 lees ferizoeneae 1 Jrncooe foe — feanawnurw : lore ferszaerrooe 4 lrnssso foe fenocucon 1 lesen ferszaemoax 4 Jricsso fee fenmcenten 1 lorek — feriacerieae : Jricsso fone fermoeoene 1 love fervzoesteoe 1 lrrssso [oer fenaocrarx : lone fersacemoax 1 jacssee fomoe — fenmocraon ‘ lores: feracesron : lrnsszz [ope fenvacession 4 lcner — fenzovroe 1 Jrxsoce fone fucneanvre 4 leren —fersaaestooe 1 Jaaor farsacr Jomo — crasezasiee : lero fenizcestoox 1 lrass farsose Joven — |ucrasearsice + [sexe Age oneanr 4 Jaace fanssre Jowor — fenmacerroxx 4 lrnmarc. froracroua tree : lrass forse lemon — lensoceverix : lrmars. [Fessetooa tea 4 lncor farssre Jmon — envaceserox i lose farecisemiesars 3 jaaoa farssso own |emiocestosx 1 lose utereaanscsr S| 1 Jnasa frrsoee fonor — lemaceiox : Frnmorr. fanosoxctex 1 Jnzoo farasse |tmr — [enaceizaee 4 fromarn. fue 3 Jasot farssse tor — feeiocezerx i Jrroz29 firmer Janozoicucx 1 Jreze |rtaiae Jeon — ferceierox : fricosa [rar anoseisioe 4 Jase frrsste Jowor — feriaceseax i frccoss [ina 4 Jraas forme |Gor — ferncenea : Fricass [mae 4 lass fanseee Jaron — lenacenx 4 favozes [mare : lesor |trase Jowor — fenncensx frvcazs [roma 1 lnaoo frvsste |G — jensaceneax : fricass [ronar : lnsor favasse Jeno — jeameesieax 4 bicorrs vercxo fosuesza vom 1 [reas |iasea |onpk —fervageserox 4 frccnsez fel |e soon 1 ram |rcea owe — fersocevezox 4 poorer feclemer fpeusza stocinc. ‘ least frases [ener — fenmceiscon 1 FFceaso” [SPtcvanon [oecuston oats 4 lor frases lensacesecx ; Jrsossr fownan Jusetowontas 1 soo [aso feruzcesenx 4 Jsboox« [Steg lexpsenneoass0 1 lea fresco fewer — enmcenex : |izso fourear|sutcon vunren 3 Insts Jreasse [one — fenusceviox 4 Kireses_|resonno [pnswe, Jes frase four fewacesteox 4 lnsis Jrcasse [ono — fenizcevsecx 4 Jets fer [ener [enuotineox : Instr |reaco: fewpe — ferugoeonoox ; Inst races foupr — feniooessoax jas [moses [enor lesuacesesxee rani aT eee. || [vrs F190, 1 Beira | § fe fl Lee era ene en ise) feces, | | feces” | | feral | | Reems | | erasers cree ae. |G Kirsten, | | lemsuseeres) 3 | 3 | a feet tL Y Packing Parts RET a RT ay hiss. fas. frome | 3 | hiss: birvereimcrsae™ | 2 | bet fesstosaraceo| it | ti] « BR betnw Poco) | Frere farms femwwe| | 1 bere ee SSome| 2 | 2 Fee foe freemen! 7] 7" fee ie ene | ACCESSORIES es oe [ee Le fee fewer fecoamuase |! | 3 He foot Gearon] | $ Bete Bes Semtsumn| 5 | ? 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Fie fin fescatonse |S | fe" Pi ie i: fess fee EL 3334 TNC (EJ41U) fratno] pants | Oowpan | Peaname ‘oy [ee] [re] torte | Oommen | Porshe of] rm [as a + fr A —_|NORCEZPTOS T fer" fesaxo Jenoteaan fucvoorsurar : se [eacos Ireaezrite : lea fescro Jowtoraur Jrecaeaniesree ; feo fae Icresezrsts 1 les fevsose Jone fotsoessttoacrs : frat frvsose Icresezriis 1 lex faust Jone etsamsreroact-ns 4 fez esse Itreaezraes 1 les fevsore owe — |eseivsrcroar a i fezs fnsooo Iiceosezrois 1 lcs fessow lee — feteouanincoerns : lace faxaart Icresezr is : ler fevsosr femps — fersoustinaotns 4 Knes|rsooo Itcresezrvi : lee fousssr [omc fetsonsteroncrs 1 fase frnsoso Icroseerois 1 lcs, feusost [ere fereonsrnazanrns lear |ansoon Inesezrii8 : lero fous owe |teoesteroncras ‘ laze fenaoea Icrosezries Jor fevstts owe — |otonesreroucras ' © [Resiea IMenesezriis : lesa feuaote Jone — feamenvcreaura ‘ faso sone IMeneseani 4 lors fovsosr omc feteousinzzoer-ns 1 fase Irae creer 1 Jere fovaos owe fersousmeracrns ‘ Jass |rxaaea IMcnoseanio : lets fous Jems — fersossnnezantns 1 fase resect Menezes : Jers fouscs: ome — fctoousmczserns : fas fansost Icrosezevies 1 ler feuans Jose — |ereouarneanerns ‘ Ios frvaaoe ose : lets fovsois [orc fetsoustusaonrns : last feraost recess t lero fevsor eee — etsousurenerns : fase frraces fcnesezesins 4 lczo fous Jomee — fesarsierosmrn 1 loo frnccco lucrozsca ; leer fous Jere |etoonisrecoucras 1 Inco fersost lucrasezeuizs 4 leza fovome owe — |eteonsswneners : Inet fresose Inenoaconszs : lees fous feme S08 18K AS 1 Ince frnaont fucnose esse t lesa fousoo Jone [etonecrrosoorns | 1 Ines fanaone hecnaez0e ‘ leas foun Jose etsanonranerans : lees faracao lucnosezoizet t leas fouscce Jone — ormiescorzarsanio] + Inee |recosr hucrosezeises ‘ lear feuoces Jonpe — |etenacnnrorsras ‘ ler Fanaa Imcnosezni03 ‘ leas fousser Jone letsanereroacrvs : Ineo fans Iucnoaezia3 ‘ leoo fevers Jonpe — |eteceveretoncens ‘ eam ec hicessezrlara ‘ jeso foussst Jenbe — [etemipretoacras ‘ leo frase lwcnoaeznsic2 ‘ less fousoe2 |omec. —ctsoucnnscourus 3 lest frnaoe acre zr ' less fovsrss Jone [etevercroncras 1 lace fanaa hacreseoros ' [ess festa [onpacaum (rucsatcsosurar : lass frcose hicreaezrizs ‘ lesefestase [onp nam (raciaavertee 1 Ise Janaso hicresezhiovo ‘ less fourm Jonge fevemietoucras : fs cosa Iicresezrsvoe 1 jess feusoie lonwc —[ctsmecanaarosrns 3 lee |cone facresezrise ' icsr [evans Iohpe — (eteceuemeracras 1 sr fresos hicresezrivs : less [evs fenpe — |etecasceroncras : fsa Joo Icresezrsis t Jess Jeusow |onpe —|etecavermronerns : lca frescor hicesezrooo : fezo fevaoes [énpc. — [etscsvnananrns : fea frucoee Icecsezrse ‘ lect fevacs: Jewpe — feraravormarir.ns : fret faxsast Itceesezra0 ‘ lee |evane [onnc — [eaoteiercsoare ; Inca frnsooo Ineneoecres ‘ fess jeuaowe [ense —fetacamsrazanras + Jnes frucoce Icnoseziet : leat fevsosr fenpe. — feteoasrrazantons : Ines frrcose Iscresezres : fess fevsow [ésne — fetecasshoearre ; Ines fro Icnesearoas : less eum Jos — feteesorcrs laos frxcose lwcnesezrsse : leas evs [ee — [ctecusrerannrns lrer frncoco fucroseze cs : Newt [oe5102 |Eerreaor fren france Icosezraos : lor" ome fowceo Ineo frnsoee lucrosezras Jos prune fen tes Ivo feraoeo frenaeien : joc frtcoss Yoiete0 fewcstoerres fare fawcoce ' los fposzst [erase fuauraseor Inve fansoeo : loc roast [Ero bea fares fers fcr : ice Perowes fe aresssecees.r Ie fansoee ' ies featsre friar Irs Janene ' ice fracas fe Haneda nes are fare fanaa 1 Hes fiteme fe fenasosteTet ares fre |etcse : [2 féscow tres facteoneas loo frase 1 lat fereose Jone Scala TR ler Jrnsose : lar frroose Jon —_fasavsrea icon Irea |aaee owe — ucrevezrinse 1 las frroose Jone fasavaren cen Ines |rcors Jomo — (wcreoezrois ‘ fax frroose Jomo fasarsrearicon fea |racoso fonpe — fvenoaezemnes : fas fremors Jim faskrsaorn Ines Jraose fonpm — enaaezrsare : loc frrooss ome faseacer rico Iner_|rccost [Ono crasezrae ‘ far fruoore Jon esartooe nea Jnaoer Jomo fvcnosezpstoe : fae frrooes |émp ——_ascacer ricer juetfrncree [Tense fvrasioerensos 1 fos frrooes Jom fasaroroa ricer jira frsoree [Tuners Iourazicerenion : lato frraoss Joc [asccer ricer jv furvass [esmeser vine we : lars frroces ap faseaon: ieee hs froorae fear bisa arom } Int’ frusoee omen. croseznvie luroate Jeceorna Jesu ine ons Ina fruaoee |oape — orosezrvio Irooss fusneno’ \ve.cron , las fruaoes |ESbe — weraseznioe roan [osenon [Soeacer cusnion 2 lea fruaaee oe — wcrosezrasee [rote fruitoe raga a 01809 1 jas fruaose |omom — uorosezruars jizsee |owmeer —fotuconoourensou | lnc frnaase [ono — ucrosezuars Wzsist [rape is ec 2 ley frame oro worosearusrs lee fanaa Jorn ucrosezriso: les frrsme own — enosezparce lato frraace |OoR — cnoseansies Jair faraoee [on wonosezpize laie frramse ome — (Momaepice lata favame Jorn — ucnosezritea Jere frusose fone crosezmice fais frame Jonpe — furcrosearisee lic fans fine Monosezrtee ;TNC (E,44U) Packing Parts fein] ease | Omayion | Patenane [rararoerlorror T renew Jeusnce — (seeaer cussion 1 facser [pesons — fremcanton est 4 a) [Pasteseg [eas scans 4 Jeroen retztog [axtaoxzco : Jracst [sneer Jocaesny : Joes eae [everpcaner i sass June: Ygrrucnowesey 4 sess ines! fnstoise es : fies lo Die i 35DR-135 ADJUSTMENT 1) Adjustment Spot Power Supply Voltage 13.8V Output of SSG is all EMF indication. If without instruction, WIDE mode. without instruction, SSG output is MOD 1KHz WIDE DEV 3.SKHZ/DEV, NARROW DEV 1.75KHz/DEV. Standard modulation is also based above. Speaker load is 8 ohm and output is 50 ~ 100 mV. ball2) VCO and RX Adjustment Specification 3) TEM CONDITION | UNIT [ ADJ. SPOT ADJUSTING MRTHOD. Adjustment | 145.90MHz MAIN | VRII0 ‘Adjust so that Tx Frequency becomes Frequency _| TX within 145.90MHz +/- 100Hz ‘veo 146. 00MH2, MAIN [L123 ‘Adjust so that PD vollage becomes 2.7 Adjustment __| RX ‘veo 173.992 MAIN ‘Confirm if PD voltage becomes less than Confirmation _| RX 7.3V Rx Signal —_| 146 05NHz MAIN” | L105, L104 | Repeatedly adjust so that the Rx sensitivity Sensitivity L403, 1102 | becoms in maximum’. ‘Adjustment Confirm: 196.05MHz At=7dBu SINAD more than 120B 446.05MHz At~8dBu SINAD more than 1248 473.95MHz_ At-SdBu SINAD more than 1248 ‘Squeich 146.05MHZ MAIN | VR101 ‘Adjust so that the squelch stops at Adjustment | SSG OFF perfectly close tocation indicate 04 ‘S Meter 146.05MHZ WAIN | VRI02 ‘Adjust so that all the Indicator appears Adjustment | SSG 20dBu 1KH2 indicate 04 TX Adjustment Specification TEM CONDITION | UNIT | ADJ. SPOT ‘ADJUSTING MRTHOD HIPOWER | 446.00MHz MAIN | VR103, ‘Adjust to 50.0 +/- LOW Adjustment, HI POWER, MID POWER | 146.00MHz WAIN | VRt04 ‘Adjust to 20.0 4- 10W Adjustment___| MID POWER LOW POWER | 146.00MH2 WAIN Confirm fit becomes 5.0 +/- 1.0W Confirmation _| LOW POWER Maximum 1146. 00MH2 WAIN, | VR107 45 ¥- O-AKHEIDEV Deviation MoD Adjustment | 1kHz 40mVemf WIDE Maximum 1146, OGRA MAIN | VRI05 22 41-0.1KHRDEV Deviation MOD Adjustment — | 1KHz 40mVenf NARROW. fe : Mic Gain 146,00MHZ MAIN | VRT06 3.0 +/- 0.1KH/DEV Adjustment — | MOD AKHz 4mVent WIDE CTCsS 146, 00MHZ MAIN 800 + 200HZ/DEV Modulation | 88.5Hz ‘KHz LPF ON Level Confirmation DCs 148,002 MAIN | VRT08 800 +/- SOHZIDEV Modulation | 255 Code ‘akHz LPF ON Level Adjustment 1750H2 46. 00MHZ MAIN [VR108 30 ¥- O.SKHZIDEV Modulation | 1750Hz Level Adjustment OTME 146. 00MHZ WAIN 3.0 ¥- O.SKHZ/DEV Modulation | DTMF 1 Level Press the VIM key Confirmation __| during TX os 374) RX Test Specification 38 TESTITEM | CONDITION | ADJ. STANDARD | TEST STANDARD NOTE RX Signal 736.05MHz | Lessthan-7oB8u | Lessthan~6dBu | 72dB SINAD Sensitivity 446.05MHz | Less than-8dBu | Less than -7dBu 173.98MHz | Less than—6dBu | Less than ~5dBu 446,06hiHz [Less than -8dBu | Less than =7dBu NARROW 1a506NHz | Less than SdBu Less than 70dBu [AM 10dB Si” RX Distortion | 146.05MHz ‘SSG Output 30080 WIDE Less than 4% Less than 5% NARROW, RX SIN 1a6.05MH2 |More than 40dB | More than 38dB | SSG Output 30dBu WIDE, 0.3 ~ 3KHz BPF OFF 746,00MH2 | More than 340B | More than 326 NARROW ‘Squeich 146.08MHz | Squeich Open ‘Squeich Open ‘SSG Output 1006 Sensitivity Indication 02_ | Squetch Close ‘Squelch Close ‘SSG Output OFF S Meter 146.05MH2 | All appears at ‘All appears at Decrease SSG level and | 4KHz 20d8u 28dBu decrease S Meter level 3.5KHZ/DEV AF Output 446,05MHz | More than 207 ‘More than SW ‘SSG Output 30a CTCSS 146.05MHz | Open at ‘Open at ‘SSG Output OdBu Sensitivity WIDE___| 500Hz/DEV. S00Hz/DEV 88.5Hz 146,05Hz | Open at Open at NARROW | 250H2/DEV 250Hz/DEV DES Sensitivity | 146.05MHz | Opens when Test | Opens when Test | 255 Code WIDE, Equipment is in TX_| Equipment is in TX 146,05MHz | Opens when Test | Opens when Test NARROW | Equipment is in TX_{ Equipment is in TX Drain Current | 146,05MHz | Less than 0.654 | Less than 0.65A _| Max volume | Power of Current | 746.05MHz | Less than 10mA | Less than 10mA | Power off Howling 446.05Mn2 | Don't occur Don't occur ‘SSG Output 60dBu Mod off, Max volume5) TX Test Specification TESTITEM | CONDITION | ADJ. STANDARD | _TEST STANDARD NOTE Tx Output 748,00MHz 30 1-3 HI POWER 146.00MHz | 50 +/-1W 50 4/- 30 448.00MHz 50 + 3W Tx Output 146.00MHz a a rays 20+ 4W 20+ 20 Tx Output |746.00MHZ | S+- 1W 3-6W LOW POWER Drain Curent [146.00MHz | Less than 711A Less than 172A Frequency 746.00MHz | Within +/-0.1KH2 | Within +7 0.3KHz Deviation Spurious 744.00MHz |More than 65d8 | More than 60dB__| MID and LOW standard 146.00MHiz | More than 658 | More than 608_—_| power is also the same 148.00MHz_| More than 65d8__| More than 6048 __| as of Hl power level Modulation Level | 146.00MH2 | 3.0 +/- 0.1KH2/DEV [3.0 #/- 0.2KH2/DEV | MIC in TKHz 4mVernf WIDE. 45 41- O.AKHZ/DEV | 45 +/- 0.2KH2/OEV | MIC in 1KHz 40mVemt 146.00MHz | 2.2 ¥/- O.1KHZ/DEV | 2.2 #/- 0.2KHa/DEV | MIC in 1KHz 40mVemf NARROW. CTCSS 146.00MHz | 800 ¥/- 200HZ/DEV | 600 + 200HZ/DEV | 88.5Hz Modulation Level_| WIDE 3khiz LPF ON Des 746.00MHz | 800 ¥/- 200HIDEV | 800 +7 200HZIDEV | 255 Code Modulation Level | WIDE. 3KiHz LPF ON 146.00MHz [450 ¥- 100HZIDEV | 450 +7 T00HZIDEV —| NARROW — 1750H2 446.00MHz [3.0 #- O.SKHz/DEV | 3.0 #/- 0.SKH2/DEV Modulation Level_| WIDE DTMF 146.00MHZ [3.0 +7 0.SKHZIDEV | 3.0 ¥/- 0.SKHZIDEV | Press the VIM key during Modulation Level_| WIDE ™ | Modulation 146.00MHz | Less than 3% Tess than 4% Distortion WIDE TXSIN 146.00MHz | More than 400B | More than 38d [0.3~ SKHz BPF ON. WIDE, 146.00MHz | More than 3408 | More than 3208 NARROW. 39DR-435 ADJUSTMENT 1) Adjustment Spot 40 Power Supply Voltage 13,8V Output of SSG is all EMF indication. If without instruction, WIDE mode. If without instruction, SSG output is MOD 1KHz WIDE DEV 3.5KHz/DEV, NARROW DEV 1.75KHz/DEV. ‘Standard modulation is also based above, Speaker load is 8 ohm and output is 50 ~ 100 mV. vill) 5) [¢4* =Ol L a 1 i Ile 6 | ao m aici oO sol vw wee ae a6 wo ele al ewe2) VCO and RX Adjustment Specification [Tew CONDITION | UNIT | ADJ. SPOT ADJUSTING MRTHOD Adjustment — | 430. 90MHz MAIN |VRII0 “Agjust so that Tx Frequency becomes Frequency __| TX within 439, 90MHz +/- 100Hz veo 425.00MHz MAIN [L123 ‘Adjust so that PD voltage becomes 2.0V Adjusiment_| RX veo 514 9OMHZ MAIN Confirm if PD voltage becomes less than | Confirmation | RX gov H Rx Signal | 440.05MHz MAIN | TO103, itis a Wacking generator from an antenna Sensitivity TC102 connector. ~30d8m is inputted. And when Adjustment L103, L102. | CN109 is seen with @ spectrum analyzer, by the maximum gain, it becomes as itis shown in the following figure, and ‘appearance adjustment is carried out. 430,00MHz 450,00MHz 430,05MHz 440,05MHz ‘At-T.5dBu SINAD more than 12¢B 450.05MHz ‘At=7.5dBu SINAD more than 1248 l Ef At~7.$cBu SINAD more than 1248 ‘Squeich 440,05MHZ MAIN. | VRi01 ‘Adjust so that the squelch stops at Adjustment | SSG OFF perfectly close location Indicate 04 'S Meter “440, 05MHZ MAIN | VRI02 ‘Adjust so that all the indicator appears: Adjustment | SSG 20dBu 1KHz Indicate 01 | a3) TX Adjustment Specification 42 Tem | CONDITION UNIT [ ADJ. SPOT ADJUSTING MRTHOD HIPOWER | 440.00MHz MAIN | VRI03, ‘Adjust to 35.0 +/- TOW Adjustment | HIPOWER __ MID POWER | 440.00MH2 MAIN’ [VRi04 ‘Adjust to 20.0 +7 10W Adjust ment___| MID POWER LOW POWER | 440.00MH2 MAIN Confirm Fit becomes 5.0 +/- 1.0W Confirmation _| LOW POWER ‘Maximum “440,00MH2 MAIN [VRI07 45 4. OAKHeIDEV Deviation MoD Adjustment | 4KHz 40mVemnt WIDE. Weximum “440.00MHz MAIN | VR105 22 ¥- D.KHZDEV Deviation MoD Adjustment | 1KHz 4omVemf NARROW. Mic Gain 440.00MH2 MAIN | VRI06 30 +7 0. 1KHZIDEV Adjustment | MOD KHz 4mVemt WIDE pre CTCss “440, 00M WAIN 800 +/- 200HZIDEV Modulation — | 88.5Hz ‘3kH2 LPF ON Level Confirmation Dcs 440.002 MAIN | VRI08 ‘800 +/- SOHB/DEV Modulation | 255 Code 3KHz LPF ON Level Adjustment 4750Hz 440.002 MAIN | VRI08 3.0 7 O.5KAZIDEV Modulation — | 1750Hz Level Adjustment ‘DIME “440 00MH2 MAIN 30 #7 O.BKHEIDEV Modulation — | DTMF 1 Level Press the VIM key Confirmation _| during TX4) RX Test Specification TEST ITEM CONDITION | ADJ. STANDARD | TEST STANDARD NOTE RX Signal 350.05MHZ Less than —1.0dBu | Less than +0.0dBu | 12dB SINAD Sensitivity 430.08NH42 | Less than -7.54Bu | Less than -6.5dBu 440.05MHiz | Less than -7.54Bu_| Less than ~6.5dBu 450,05MHz Less than -7.5dBu | Less than -6.5dBu 514.95MHzZ Less than +1.0dBu__| Less than +2.0dBu 440,05MHZ [Less than -8aBu | Less than -7dBu NARROW. RX Distortion 440,05MHz SSG Output 40dBu WIDE Less than 4% Less than 8% NARROW. RXSW 440.05MHZ | Moré than 40B | More than 3848 | SSG Output 40dBu WIDE 3 ~ 3kHz BPF OFF 440.00MHz More than 34dB ‘More than 32dB [NARROW sHEee ‘Squelch ‘440.05MHz__| Squelch Open ‘Squelch Open ‘SSG Output 1oaBu Sensitivity Indication 02 ['Squelch Close. ‘Squelch Close SSG Output OFF ‘S Meter ‘440.05MHz All appears at All appears at Decrease SSG level and AKHz 20dBu 25dBu decrease S Meter level ‘3.5KHz/DEV ‘AF Output |440.05MHz__| More than 2W___| More than 20. ‘SSG Output 30dBu cTcss 440.05MHz ‘Open at Open at ‘SSG Output OdBu Sensitivity WIDE | SOOHZ/DEV. S00HZ/DEV 88.5Hz ‘440.05MHz | Open at ‘Open at | NARROW 250H2/DEV 250H2/DEV_ DCS Sensitivity 440.05MHz_ Opens when Test Opens when Test (255 Code. WIDE Equipment is in TA_| Equipment is in TX. 440.05MHZ [Opens when Test | Opens when Test NARROW _| Equipment is in TX_| Equipmentis in TX Drain Current | 440.05MHZ Less than 0.658 | Less than 0.65A | Max volume Power off Curent | 440.05MH2 [Less than 10mA [Less than 70mA | Power off Howing 7'440.05MHz | Don't occur Don't occur SSG Outpt 6060 i ___| Mod off, Max volume 435) TX Test Specification 44 [_TESTITEM | CONDITION [ ADJ. STANDARD _| TEST STANDARD. NOTE Tx Output '430.00MH2 35+ BW HIPOWER 440.00MHz | 35 +/-1W 35 4/.3W 450.00MH2 : 35 4/-5W Tx Output 440.00MHz MID POWER 20+ 1W 20 +-2W Tx Output ‘440,00NH2 | 547 1W 3-6W LOW POWER Drain Current |'440,00MH2 | Less than 11A Less than 124 Frequency 440.00MHz | Within ¥7- 0.1KHe | Within +- 0.3KHz Deviation | Spurious 430.00MH2 |More than €5dB_——_| More than 6008 | MID and LOW standard 440,00MHz | More than 65dB | Morethan 60dB —_| power is also the same 450.00MHz_| More han 65dB__| More than 60d8__| as of Hl power ievel Modulation Level | 440.00MHz | 3.0 +/- 0.1KHZ/DEV [3.0 +/- 0.2KHZ/DEV | MIC in 1KHz 4mVemf WIDE 4.5 +- O.AKHZ/DEV | 4.5 +/-0.2KHz/DEV_| MIG in 1KHz 4omVemt “440.00MH2 | 2.2 +/- 0.1KH2IDEV | 2.247 0.2KH/DEV | MIC in 1KHz 4OmVemf NARROW. cress 440,00MH2 | 800-¥/- 200H2/DEV | 600 ¥/- 300HZ/DEV | 88 5Hz Modulation Level_| WIDE kHz LPF ON Des 440.00MH2 [80047 200HZIDEV | 800 +7 200HZIDEV | 255 Gode Modulation Level. | WIDE. 3KHz LPF ON “440.00MH2 | 450 +- 100H2/DEV | 480 +7- T00HZ/DEV NARROW 750, 440.00MHz — | 8.0 + O.SKHZIDEV | 3.0 +/- 0.KHZ/DEV Modulation Level | WiDE___ DTMF 440.00MHZ [3.0 +/-O.SKH2/DEV [3.0 ¥- 0.5KH2/DEV | Press the VIM key during Modulation Level_{ WIDE. ™ Modulation “440.00MH2 | Less than 3% Tess than 4% | Distortion WIDE TX SIN “440,00MH2 | More than 40dB | More than 38dB | 0.3~ KHz BPF ON WIDE. 440,00MHz | More than 344B | More than 3248 LNARROWBLOCK DIAGRAM oupooyjwsuest = avto0y > 1 = 0 =a > OE = - TUES EEE 7 Heh LEH pee He serud (b+ i pee eee ee eee SUL ger-ud (zALINCO, INC. Head Office: Shin-Dai Building 9th Floor 2-6, 1-Chome, Dojimahama, Kita-ku, Osaka 530-0004, JAPAN: Phone: +81-6-4797-2136 Fax: +81-6-4797-2157 E-mail: expart@alinco.co.ip Dealer/Distibutor ‘Copyright Anco, no. Osaka Japan M0089 Printed in Japan FNFNNJ-NJ / AES555PC BOARD VIEW 1) CPU Unit SIDE A DR-135 (UP0536) Bas «(Cp rosy a a Bonding a AY al tec ak a a | a Sy. a0 g & am = if a = 5 3880 = ® DoooooonpoNg0onDD oat) soa) fi gmnm G8 ae Fo Gunn CA Goo Be 2 7 & a a a B ok Ue. ty a8 »oftek R13 R16 JP3 IDR135TMk3|_ = NC 0 JUMPER IDR135EMk3| 0 NC |JUMPER3) CPU Unit SIDE A DR-435 (UP0543) age 2 (i fe Or S Bonding [- : 8 88 oe Ce q Gp x 3830 ae ee a 3 a soma + : 1 a @ ee ae z [Seen gee eM oe 7 ae gos0 Saf x0 = fgets nae @ 2 fF 2B s Bab @ 3 0 ee 30 = ekallegite 8 us Ris | Rie | UPS DR435TMk3| NC. 0 [JUMPER DR435EMK3| 0 Nc | JUMPER6) MAIN Unit Side B DR-135 (UP0536) 5) MAIN Unit Side A DR-135 (UP0536)7) MAIN Unit Side A DR-435 (UP0543) 8) MAIN Unit Side B DR-435 (UP0543) ae mig PL GF a 29 a ou fi ) } 7 a 8 abe e in @ oh ® a a . ie ag nm oa i, fy Gl 40 59 ao spon = a Se op aes 3 ae ihre uaa co ar * Sa, ae Bee Sepereaapt T9) TNC Unit Side A (UP0402) OPTION unit (EJ41U) 10) TNC Unit Side B (UP0402) OPTION unit (EJ41U) 212 ys [oh cot 2D Liboar Paper fg Ged EPO Et uae oO say of ait @ Boot wo 169 wise 39s lover {samo {cow oss ox ox Fewasa @ << 120056 SILICON QUNPER 4aU | T | c SOLOS FF@@335 VELCRO A YZ0131 wu u a a S a = a © 3 Ss A a a & Y a NL ressee urn saree cur, 5. y<— YZ0131 49SCHEMATIC DIAGRAM 1) CPU Unit DR-135 GEIS ‘Selll) afd) sa) silo eisseh senge: Peerits | pis [ R16 | JP3 DR135Fx | NG 0 |JUMPER DR135FXE] 0 Nc | JUMPER 502) CPU Unit DR-435 EEE AVOSEERR ERD eR RpeRht ESSE Bealielowet paguanesagesnagen os (piviersrinnrene tress | a bs He tee fa J ste R13 R16 JP3 IDR435TMk3| = NC 0 JUMPER |DR435EMk3} O NC |JUMPER 5t3) MAIN Unit DR-135 aOR =! Eh ang HELP HBR 824) MAIN Unit DR-4355) TNC Unit 54 OPTION Unit (EJ41U) ces_PTT peta conte cima 2600bpet« Ler 002038 vated race