P T - 9 0 Neat Chassis: Modification Reserved

SERVICE MANUAL
SERVICE MANUAL
SERVICE MANUAL
SERVICE MANUAL
SERVICE MANUAL
SERVICE MANUAL
SERVICE MANUAL
SERVICE MANUAL
SERVICE MANUAL
SERVICE MANUAL
SERVICE MANUAL
SERVICE MANUAL
SERVICE MANUAL
SERVICE MANUAL
SERVICE MANUAL
SERVICE MANUAL
SERVICE MANUAL
SERVICE MANUAL
SERVICE MANUAL
SERVICE MANUAL
SERVICE MANUAL
SERVICE MANUAL
SERVICE MANUAL
SERVICE MANUAL
SERVICE MANUAL
SERVICE MANUAL
SERVICE MANUAL
SERVICE MANUAL
SERVICE MANUAL
PT-90
NEAT
CHASSIS
Modification reserved
PT 90 NEAT Service Manual
CONTENTS
PAGE
Assembling/Disassembling
Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1. Technical Specs. Connectors
and Chassis Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2. Safety Instructions and Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4. Supply Voltage Diagram
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
5. I-C Bus Interconnection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

6. Fault Tracing Diag. for Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
7. Chassis Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
8. Service Menu And Basic Adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
8.1 Option Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
8.2 Geometry Adj. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
8.3 G2 Adjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
8.4 Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
8.5 Tune / IF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
8.6 Hotel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
8.7 System Voltage Adj.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
9. DVD Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

9.1 Safety And Handling Precautions
9.2 Mech. And Elec.
. . . . . . . . . . . . . . . . . . . .17
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
10. Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

TV Chassis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
DVD Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
11. Description Of Ics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
TV Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
DVD Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
ASSEMBLING /
DISASSEMBLING PROCEDURE
Disassembly procedure is explained as below. Before disassembling the TV set please read the safety instructions
and warning parts of the service manual.
CRT drive module must be grounded via mass

cable.
Grounding must be completed between loader and
chassis via soldering cable between tuner and loader.
Front AV must be connected to SS05 and line out
should be connected to SS09 via 9P and 5P sockets,
respectively.
Place the back cover back to its place.(6 screws)
Plug the mains in.
Turn on the TV.
Grounding must be completed between loader and
chassis via soldering cable between tuner and loader.
Front AV must be connected to SS05 and line out
should be connected to SS09 via 9P and 5P sockets,
respectively.
Place the back cover back to its place.(6 screws)
Plug the mains in.
Turn on the TV.
Turn off TV and plug the mains out

Remove screws (6 pieces) to dismount the back cover
Remove 2 connection cables between chassis and back
cover. Front AV and lineout sockets should be disconnected.
Cut the tie, which fixes DVD cables together.
Disconnect the following sockets to take the chassis out ;
Loader,
IR receiver
Deflection cable
Degaussing coil
Speaker cable
Power cable
Remove the ground cable localised between tube module, chassis and mass cable.
Remove the CRT drive module from picture tube.
Desolder the ground cable of loader from tuner.
Remove anode cable localised on the picture tube.
Slide out the chassis through the guides (no screws,
straps or other fixing).
Please follow the assembly instructions

explained below;
Be sure that all of the loader cables are free. If necessary
fix the cables firmly to avoid any kind of squeezing
while inserting the chassis back.
Before inserting the chassis into guides, check the control buttons in front of the chassis. In case of misplacement of control buttons place them into correct position.
Slide the chassis into guides until the connection cables
could be reached to their sockets.
Plug in the sockets coming from led PCB, 5P to KL01
and 4P to KL02
Plug in the sockets coming from loader, 4P to SS03, 6P
to SS13 and 12P (blue one pointing to right) to SS18.
Plug in the power cable socket to AC01.
Plug in the degauss cable socket to KP02.
Plug in the speaker cable socket to HS03.
Place the CRT drive module on picture tube.
Slide the chassis completely on its place. Be careful
about control buttons.
Plug in the deflection cable socket 4P to KD01 and 2P to
SD21.
Place the anode cable to picture tube. Be careful about
high voltage!
1. TECHNICAL SPECIFICATIONS, CONNECTIONS AND

CHASSIS OVERVIEW
1.1. Technical Specifications
1.1.1 Reception
Tuning System
Color Systems
Sound Systems
A/V Connections
Channel Selections
IF Frequency
Aerial Input
:
:
:
:
:
:
PLL
PAL SECAM NTSC
B/G D/K L/L
SCART AND FRONT AV
AIR, CABLE : The entire band via frequency search
B/G, D/K, L : 38.9 MHZ
L:
33.4
I:
39.5MHZ
: 75 OHM
1.1.2 Miscellaneous
Audio Output (RMS)
Mains Voltage
Mains Frequency
Ambient Temperature
Maximum Humidity
Power Consumption
Standby Power Consumption
: 2 x 2.5 W
: 220-240 V ( 10 %)
: 50/60 Hz ( 5 %)
:
:
: 50 W
:4W
1.2 Connections
A/LA/R PCM
EURO AV
Rear Connections
VIDEO L AUDIO R
Side Connection
EURO SCART
I- Audio output 1. right channel 0.5 VRMS/<l k 0
2- Audio input 1. right channel 0.5 VRMS (connected to No.6)
3- Audio output 2. left channel 0.5 VRMS (connected to No.1)
4- GND (audio)
5- GND
6- Audio input 2. left channel 0.5 VRMS/>10k 0
7- RGB input, blue (B)
8- Switch signal video (status)
9- GND
10- Reserved for clock signals (not connected)
11- RGB input, green (G)
12- Reserved for remote control (not connected)
13- GND
14- GND switch signal RGB
15- RGB input, red (R)
16- Switch signal RGB
17- GND (video)
18- GND19- Video output 1 Vpp/75 ohm
20- Video input 1 Vpp/75 ohm
21- Shield
11 13 15 17 19 21
8 10 12 14 16 18 20
14 NEAT CTV 001
CHASSIS OVERVIEW
14 NEAT CTV 002
1- FRONT CABINET 002

2- PICTURE TUBE
3- PICTURE TUBE SCREW
4- SPEAKER
5- SPEAKER SCREW
6- DVD DRIVER
7- DVD DRIVER SCREW
8- EJECT BUTTON 001
9- EJECT BUTTON 001 SCREW
10- MULTIBUTON LEFT
11- MULTIBUTON LEFT SCREW
12- MULTIBUTON RIGHT
13- MULTIBUTON RIGHT SCREW
14- ON-OFF BUTON
15- ACYRILIC WINDOW 001
16- INFRA LED PCB
17- INFRA LED PCB SCREW
18- REFLECTOR
19- REFLECTOR SCREW
20- DVD HEAD
21- CHASSIS RAIL RIGHT
22- CHASSIS RAIL LEFT
23- MAIN CHASSIS
24- BACKCOVER
25- BACKCOVER SCREW
26- STYROPHOR
1- FRONT CABINET 002

2- PICTURE TUBE
3- PICTURE TUBE SCREW
4- SPEAKER
5- SPEAKER SCREW
6- DVD DRIVER
7- DVD DRIVER SCREW
8- EJECT BUTTON
9- EJECT BUTTON SCREW
10- MULTIBUTON LEFT
11- MULTIBUTON LEFT SCREW
12- MULTIBUTON RIGHT
13- MULTIBUTON RIGHT SCREW
14- ON-OFF BUTON
15- ACYRILIC WINDOW 002
16- INFRA LED PCB
17- INFRA LED PCB SCREW
18- REFLECTOR
19- REFLECTOR SCREW
20- DVD HEAD
21- CHASSIS RAIL RIGHT
22- CHASSIS RAIL LEFT
23- MAIN CHASSIS
24- BACKCOVER
25- BACKCOVER SCREW
26- STYROPHOR
27- AVPCB
28- AVPCB HOLDER
KEYBOARD
All the keys on the keyboard are used same as the relevant keys on the RC. But navigation in menus is quite different. In order to open Main Menu from keyboard V+ and V- keys must be pressed together. After displaying the
menus P+ and P- keys will be used as Navigation Up and Navigation Down keys. There is no enter key on the keyboard so V+ or V- will be used as Menu Right key if a submenu item is highlighted on the menu. These two keys will
also be used as Navigation Left and Navigation Right keys in order to change any highlighted options right side
value. To return previous menu V+ and V- keys should be pressed together.
2. SAFETY INSTRUCTIONS AND WARNINGS

SAFETY INSTRUCTIONS FOR SERVICE
REPAIRS
laser beam is highly dangerous and it may cause permanent damages.
1. Use only the original spare parts with the same specifications for replacement.
2. Only the original fuse value should be used.
3. Safety components, indicated by the symbol, should
be replaced by components identical to the original ones.
4. Main leads and connecting leads should be checked for
external damage before connection. Insulation must be
checked.
5. Parts contributing to the safety of the product must not
be damaged or obviously unsuitable. This is valid especially for insulators and insulating parts.
6. Thermally loaded solder pads are to be sucked off and
re-soldered.
7. Ensure that the ventilation slots are not obstructed.
8. Potentials as high as 25 KV are present when this
receiver is operating. Operation of the receiver outside the
cabinet or with back cover removed involve a shock hazard
from the receiver.
9. Servicing should not be attempted by anyone who is not
thoroughly familiar with precautions necessary when working on high voltage equipment. Perfectly discharge the
high potential of the picture tube before handling it. The
picture tube is highly evacuated and if broken. Glass fragments will be violently expelled. Always discharge the picture tube anode to the receiver chassis to keep of the
shock hazard before removing the anode cap.
10. Keep wire away from the high voltage or high temperature components.
11. When replacing a wattage resistor, keep the resistor
10mm away from the circuit board.
12. Fast heating up (e.g. by bringing the Combi from a cold
place into warm and humid room) can result in moisture
condensing on the pickup lens of the DVD Module, thus
influencing the playability for a certain time. Before checking the performance, the DVD Loader should be stabilized
for at least 4 hours.
13. Never try to repair DVD module when it is ON. The
HANDLING THE MOS CHIP COMPONENTS

MOS circuit requires special attention with regard to static
charges. Static charges may occur with any highly insulated plastics and can be transferred to persons wearing
clothes and shoes made of synthetic materials. Protective
circuits on the inputs and outputs of MOS circuits give protection to a limited extend only due to time of reaction.
Please observe the following instructions to protect the
components against ESD.
1. Keep MOS components in conductive package until they
are used. Most components must never be stored in styropor materials or plastic magazines.
2. Personnel must not touch the MOS components to avoid
electrostatic discharging.
3. Hold the component by the body touching the terminals.
4. Use only grounded instruments for testing and processing purposes.
5. Remove or connect MOS Ics when operating voltage is
disconnected.
6. Personnel in charge must make sure that they are connected with the same potential as the mass of the set by a
wristband with resistance.
X-RAY RADIATION PRECAUTION

1. Excessive high voltage can produce potentially hazardous X-RAY radiation. To avoid such hazard, the high
voltage must not be above the specified limit. The nominal
value of the high voltage of this receiver is 25KV at zero
beam current (minimum brightness) under 220 V AC power
source. The high voltage must not under any circumstance,
exceed 30KV. It is recommended the reading of the high
voltage to be recorded as a part of the service record. It is
important to use an accurate and reliable high voltage
meter.
2. The primary source of X-RAY radiation in the TV receiver is the picture tube. For continued X-RAY radiation protection, the replacement tube must be exactly the same
type tube as specified in the part list.
8
SC_I
13
A-8
A2
-2
A7-1
A2-5
CVBS
A2-3
A-1
A2-7
SDA
SCL
A 1 -2/A2-2/A7-2
A4
A2
-6
A 7 -1/A2-1/A1-1
AC IN
-1
24C08
IC02
SCART1
SS01
17 11
21 15
19
5
9
20
16 14
18
12 10
CLI
FBEXT
A5 POWER SUPPLY
KEYB
A11
KEYBOARD
AV_STATUS
A2 -1
A3 SCART
A4
-2/A2-2
SD-1/A2-3
CL
-4
10
-5
11
A1 TUNER
SC_IN -2
AV STATUS A3-1
-1
TDA16846
IP01
11
14
A-5
-7
R -6
FBEXT
28
27
26
25
20
CV BSEXT A3-4
B -8
13
A-3
14
11
A-5/A1-56
AGC
CVBS
A-5/A1-52
IF2 -4
IF1
IF1
L/L -8
WP0
ICV1
STV2246/47/
AUDOUT A8 -1
34
35
36
37
42
44
A-2
A7-6
A6-3
B_OSD
G_OSD
A7-5
A7-4
R_OSD A-3
FB_OSD A7-10
V_AMP
CVBSOUT
BCL
VERT -1
47
46
HOUT A-2
A6-1/A7-7
48
49 HEATER
51 SCL A7-2/A1-2/A4-2
52 SDA A7-1/A4-1/A1-3
55
A2 VIDEO PEOCESSOR
A8-2
-8
A2-3
A2-4
A2-5
12V
16
110
25
19
18
17
16
15
13
12
11
IC01
ST92195/921
34
33
40
41
43
42
56
BCL A2-3
HEATER
HOUT A2-2
9
FBT
A6 HORIZONTAL
SCL
A2-2/A4-2/A1-2
SDA
A2-1/A4-1/A1-1
FB_OSD
A2-10/A7-5
R OSD
G OSD
B OSD
TV/DVD
L/L
MUTE_DVD
A8-10/A8-1/A10
-1
CLI -1
A7 -CONTROLLER
DVD SB
-1
-1
HEATER
12 V
24 V
FB_OSD
A7 -5/A2-10
CVBSOUT
A2-6
A2-7/A6-1
V_OSD A-1
VOL
KEYB
-1
A2
-1
IA03
12
I060
LM358
V_AMP A2 -2
ID41 TDA177
R_DVD
A10
-3
CVBS_DVD
A8-5
14
15
16
DOUT
MUTE
L DVD R DVD
A8-4 _DVD A7- A8-2
A8-3
1/A8
-1
12
SS08
18
A10 AV INTERFACE
CONN.
V_OSD A7-1
VERT A2-1
3B
1MN405
A9 VERTICAL
L DVD A10-2
MUTE_DVD
A8-10/A10
-1/A7-1
AUDOUT
VOL
IA01
TDA7057
A8 AUDIO AMPLIFIER
3. BLOCK DIAGRAM
10
A9
16V
110V
A6
TDA1 8
771
FBT
RD28
RD44
RD40
8V
RD12
RD56
RD45
24V
12V
24V
RD15
8V
12V
RV06
8V
5V
SS08
A10
RV57 TV05
DV10
12
14
8V
RV54
SS05
RV03
TV01
8V TO SS05/4
19
A3
33V
RT01
RT03
LT01
5V
A4
5V
5V
A1
C011
EEPROM
1
TUNER
5V
5V
5VA
5VD
A7
R013
R012
R032
R007
R010
R011
T003
A5 POWER SUPPLY
26
25
21
20
19
14
13
12
IA03
MN4
053
DV20
DV21
DV22
DV23
LV03
LV01
ST92195/92185
A8
8V
5V
A2
11
16
28
27
26
25
17
12
31
33
39
34
40
41
43
45
46
54
55
56
45
53
D004
D005
D001
D002
5VA
5VA
5V
5V
8V
5V
5VA
5V
5V
12VDVD
5VDVD
RA09
R081
R080
T001
R028
R057
R008
R002
8V
5V
LV01
LV01
8V
+12V TO RA10
R052
RS58
RA11
VIDEO
PROC.
STV2246/47/48
SA02
LV07
4. SUPPLY VOLTAGE DIAGRAM
TUNER
A1
SCL
SDA
RT
RT
A2
11
RV33
SCL
SDA
52
VIDEO
PROC.
51
RV34
A4
R048
SCL
SDA
EEPROM
R049
SCL
SDA
A7
20
19
R012
u-CONTROLLER
R013
+5V
SCL
SDA
5. I2 BUS INTERCONNECTION DIAGRAM
6. FAULT TRACING DIAGRAM-POWER SUPPLY

Switched mode power
supply defective, +110V
is missing or level is wrong
DP01 - 04
CP01 - 04
CP06, TP01
YES
Fuse
F1 defective
NO
RP 07, RP 05
open and
short circuit
NO
Voltage at drain
TP 01
YES
YES
RP 06
Voltage at
IP01
PIN 11
< 1V
NO
YES
RP 11, DP 07
Start-up voltage
(6)
PIN 14
< 8V
NO
YES
TP 01
Start-up voltage
varies ca. 8V
NO
IP 01
Measure
NO
VAP 1, RP 03
+115V
adjustable with
VAP 01
YES
Control range of
switched-mode
power supply
12
7. CHASSIS DIAGRAM
FRONT AV
TDA 7057
2 X 2W
TDA1771
CVBS
AUDIO
STV224X
DVD
BOARD
ST92195
DVD
LOADER
V.YOKE
+5V
24C08
RC
H.YOKE
RGB
SCART
BU508D
PLL TUNER
+110V
+12V
+16V
IR
13
POWER
8.
SERVICE MENU AND BASIC ADJUSTMENTS

SERVICE MODE IS ACTIVED BY PRESSING THE DIGIT 1923
AT FEATURES MENU
8.1
OPTION BYTES
OPTION 1:
b0:
b1:
b2:
b3:
b4:
b5:
b6:7
OPTION 2:
b0:
b1:
b2:
b3
b4:
b5:
b6:
b7:
b6:
b7:
0:
0:
0:
0:
0:
0:
not available
APR OFF
Pin 8 16:9 switching mode
not used
Keyboard without menu
Brightness full range available
FEATURE CONFIGURATION
1: AV2 mode available

1: SVHS mode available
1: Volume linear
1: Search mono audio ident available
1: DVD picture in SVHS mode
1: Headphone available
1: No Subwoofer
1: 4/3 Picture tube
OPTION 3:
b0:
b1:
b2:
b3:
b4:
b5:
MODEL CONFIGURATION
1: L Avaialable
1: APR ON
1: no Pin 8 16:9 switching mode
1: Turn on with AV button
1: Keyboard with menu
1: Brightness half range available
Main Tuner
00 : Samsung
01 : Temic
10 : Philips UV1316
11 : Thomson/Orega
0:
0:
0:
0:
0:
0:
0:
0:
not available
not available
Volume Logaritmic
not available
DVD picture in RGB mode
not available
Subwoofer available
16/9 Picture tube
VIDEO/AUDIO FEATURE CONFIGURATION
1: One Crystal application (4.43 Mhz)

0:Two cystal application (for NTSC playback)
1: Intercarrier application
0: QSS application
1: STV2248E
0: Normal video IC
1: OSD contrast control ON
0: OSD contrast control OFF
1: Blue screen enable
0: disable
1: AVC Automatic Volume Correction (MSP Stereo) AVL(Mono 22XX)
0: not available
1: DVD available
0: not available
1: Standby after power on
0: No Standby after power on
Reserved bits must be set to 0

You will need following equipments to carry out the adjustment procedures;
a- PLL Pattern generator for Secam L'
b- PLL Pattern generator PAL BG
c- Patern generator for white pattern
d- Color Analyzer (CA100)
14
8.2 GEOMETRY ADJUSTMENT

a. V.S
b. V.S
c. V.S
d. V.S
e. V.P
f. H.P
4/3 50H
16/9 50H
4/3 60H
16/9 60H
Enter service menu and select the GEOMETRY settings

Standart geometrical adjustments carried out by V.S, V.P and H.P settings. V.S 16/9 50h setting have to be carried
out until 3 cm distance between upper and lower parts of the screen.
Same adjustments for 60H for 16/9 and 4/3.
Press menu button to leave service menu
Menu button to leave service menu.
8.3 G2 ADJUST
>
<
increase normal decrease

Enter the G2 menu in the service mode
Turn the G2 potentiometer on FBT until you reach the : sign
< indicator means to decrease
> indicator means to increase
8.4 VIDEO
1
2
3
4
5
RED
GREEN
BLUE
RED COFF
GREEN COFF
Apply Dark gray pattern (at 10 IRE)

Contrast 70%, brightness middle, color saturation middle.
By changing the R COF and G COF Adjust to obtain the necessary values for x and y.
Apply white pattern (at 100 IRE)
Set the contrast to 70%, brightness and color saturation to middle.
Place the color analyzer.
(R,G,B), it is possible to modify the peak white.
Adjust to obtain the necessary values for x and y.
Remark: It may be necessary after low light alignment to check and to re-align the high light and to repeat several
times the procedure to obtain good alignment for both low and high light.
15
8.5 TUNER/ IF
1.
2.
3.
4.
5.
AGC
PC
PF
P C.L
P F.L
PIF adjustment for BG/DK/L systems:

38.9 MHz PAL BG signal applied Tuner via tuner output (IF output).
Leave the channel settings menu and enter service menu. Enter TUNER IF menu in the service mode.
Choose the PIF COARSE and PIF FINE item and adjust the setting until the : indicator (displayed as > : <)
turns in red color by pressing < and > on remote control.
Press Menu button to leave service menu.
PIF adjustment for L' system:
33.9 MHz SECAM L' signal applied Tuner via tuner output.
Leave the channel settings menu and enter service menu. Enter TUNE IF menu in the service mode.
Choose the PIF COARSE L and PIF FINE L item and adjust the setting until the: indicator
(displayed as > : < ) turns in red color by pressing < and > on remote control.
Press Menu button to leave service menu.
8.6 HOTEL MODE

Installation and Child Lock Menus are omitted in Hotel Mode. You can not search any channel when the
Hotel Mode is activated.
Volume level cannot be increased higher then certain level in Hotel Mode. The volume limiting level is a predefined value in service menu.
Hotel mode activated from service menu.
8.7 SYSTEM VOLTAGE ADJUSTMENT

Switch the TV in AV mode by pressing AV button on remote control unit. (Minimum beam current condition)
Adjust the VAP2 potentiometer until 110Vdc measured on cathode pin of DP08 diode.
16
9. DVD MODULE
9.1 SAFETY AND HANDLING PRECAUTIONS
1. DO NOT use and store the Loader in dusty, high temperature or high humidity environments.
2. To avoid damage to the Loader by electrostatic dischargers, measuring equipment and operators should be
grounded during handling. The user of this unit takes all necessary precautions to avoid ESD (Electro-Static
Discharge) failures during handling and assembly of this unit into the end product.
3. Contamination of the PCB might influence the performance. Avoid fingerprints and stains on the PCB and
handle the Loader in a clean environment.
4. The mechanism of the Loader has been adjusted carefully during manufacturing. High shocks on this unit
may damage and should be avoided.
5. Fast heating (e.g. by bringing the Loader unit from a cold place into a warm and humid room) can result in
moisture condensing on the pickup lens, thus influencing the playability for a certain time. Before checking
the performance the Loader unit should be stabilized for at least 4 hours.
6. DO NOT disamble the loader to avoid ESD failures and to prevent from contamination.
AC Source Supply:
The Voltage Fluctuation : 110/220 V 10% tolerance
The Impulse Noise
: 110/220 V 10% tolerance
Applicable Discs Format

Disc Type
DVD-5 (Single Layer)
DVD-9 (Double Layer)
DVD-10 (Single Layer Double Side)
DVD-18 (Double Layer Double Side)
Description
IS09660
UDE
DVD BOOK
Disc Format
IS09660
RED BOOK (CD-DA)
WHITE BOOK (Video-CD)
BLUE BOOK (CD Extra)
YELLOW BOOK (CD-ROM)
ORANGE BOOK (CD-RW, R)
CD
Disc Capacity
Disc Diameter
Disc Thickness
Disc center
Aperture
Track Gap
DVD-5
DVD-9
DVD-10
DVD-18
CD
4.70 GB
8.54 GB
9.40 GB
17.0 GB
656 MB (Mode 1)
748 MB (Mode 2)
12 cm/8 cm
1.2 mm
DVD/CD
15 mm
0.74 m, DVD
1.6 m, CD
17
Functions
Data Transfer Rate:
DVD 2600kB/sec (max)
CD
870kB/sec (max)
Data Buffer Capacity
256KB (DVD/CD)
Error Rate
10e -15 MAX (DVD), 10e -12 MAX (CD)
Reading Time
Starting procedure (Less than 15seconds)
Stopping procedure (Less than 2 Seconds)
Laser Specifications
Laser wavelength
Laser power
Object
lens
Focus
Searching
DVD
650-665nm
0.5mW
CD
790+20nm
0.7mW
Non-spherical lens
Lens
Length of Ray
Coil
0.6mm
Moving Range 1.71mm
Phase difference detection
0.47mm
1.35mm
Astigmatism
Three spot tracking
Disc Loading Mode

Motor- driven front-loading tray
Disc Fixing
Beam magnetic fixation
Reliability
Mean Time Between Failure (MTBF): Not less than 2,000 hours
Mean Time To Repair (MTTR): 0.5 hours
Working Environment
Temperature and Humidity
Operating temperature
5 to 45
Storage temperature
- 20 to 60
Operating temperature varying
11/hour(max)
Storage temperature varying
20/hour(max)
Operating humidity
10% to 70%
Storage humidity
5% to 80%
Vibration
Reading data state
0.2g 10-30Hz sine wave
Playing CD audio state
0.15g 10-30Hz random
Standby
2.4g 10-30Hz random
Striking
Standby state 100kg 6ms half sine-wave (in X,Y and Z directions)
Noise
Not more than 45dB in one meter away
18
9.2 MECHANICAL AND ELECTRICAL

1. CONNECTORS
Integrated Connectors
1.
2.
3.
4.
5.
DC power jack
IDE interface
Master/slave mode jumper set (not applicable as the loader configured for player)
Analog audio output (not applicable as the loader configured for player)
Digital Audio output (not applicable as the loader configured for player)
Pin Definitions
Power Jack
ITEM
PIN NO.
DC Power Jack
DESCRIPTION
+12V
GND
GND
+5V
ATAPI Interface
Signal
Pin No.
Pin Type
Description
CSIEX-
37
Driver Chip Select 0
CS3EX-
38
Driver Chip Select 1
DA0
35
Driver Address Bus-Bit 0
DA1
33
19
DA2
36
DASP-
39
I /O
Driver Activity/Driver I Present
DD0
17
I /O
Driver Data Bus-bit 0
DD1
15
I /O
DD2
13
I /O
DD3
11
I /O
DD4
I /O
DD5
I /O
DD6
I /O
DD7
I /O
DD8
I /O
DD9
I /O
DD10
I /O
DD11
10
I /O
DD12
12
I /O
DD13
14
I /O
DD14
16
I /O
DD15
18
I /O
DIOR
25
Driver I/O Read
DIOW-
23
Driver I/O Write
DMACK-
29
DMA Acknowledge
DMARQ-
21
Driver Request
INTRQ
31
Driver 16Bit I/O
IOCS16
32
Driver Interrupt
IORDY
27
I/O Channel Ready
PDIAG-
34
I/ O
Passed Diagnostics
RESET-
Driver Reset
CSEL
28
Cable Select
KEYPIN
20
Keying Pin on Interface Connector
20
2. KEY COMPONENTS
Items
Model No.
Spindle Motor
CCM03-042R1-2
Loading Motor
FC8A30T28_4A DM2429A
Sled Motor
FC8A30T18_2 DM2428
Laser Pick-up
PVR-520T-HR-0101
Actuator Drive
BA5954FP
Loading Motor Drive BA6287F
RF Amp.
SP3721A
Servo DSP
M5705
Maker
MORETECH
SANKO TRICORE
SANKO TRICORE
MISTSUMI
Rohm
Rohm
TI
ALI
3. MECHANICAL DIMENSIONS
21
Location
China
China Taiwan
China Taiwan
Japan
Japan
Japan
U.S.A
Taiwan
10- BLOCK DIAGRAMS
TV CHASSIS
A 1 TUNER
22
A 2 VIDEO PROCESSOR
D2
D1
D5
D4
D3
A 3 SCART
A 4 EEPROM
24
E1
A 5 POWER SUPPLY
25
F1
F2
A 6 HORIZONTAL
26
A 7 MICRO CONTROLLER
G2
G1
27
A 8 AUDIO AMPLIFIER
28
H1
H2
A 9 VERTICAL
A10 AV INTERFACE
CONNECTOR
29
A 11 KEYBOARD
A 12 FRONT AV
30
A13 LINE OUT
A14 TUBE MODULE
31
A 15 IR MODULE
32
RFO
RFGND
33
TEI
FEI
SAE
2
2
RFO
FOCUS
TRACK
SLEG
MOTOR
SSBAD
DFCT
XSFGIN
FLAG0
FLAG1
FLAG2
FLAG3
PLCK
SLRF
4 SFGIN
4 SSPDON
2 SCSJ
2 SCLK
2 SDATA
2 SBAD
2 SDFCT
TEXI
2,4 MVREF2
5K1
XSFGIN
XSPDON
R221
R222
R223
FOCUS
TP
SLEG
TP
SSBAD
TP
XSFGIN
TP
FLAG1
TP
FLAG3
TP
C210
R208
XSCSJ
XSCLK
XSDATA
R228
RFGND
L21
0
10
R
33.8688MHz
C225
12P
Y21
C223
12P
100K
R229
3.3V
C224
C
R226
R227
LED1
R237
INSW
AVSS_DS
XSRFIN
XSIPIN
AVDD5-DS
XSDSSLV
XSRSLINT
VDD-3.3
XSAWRC
XSRFGC
XSEFGC
XSFOCUS
XSTRACK
XSSLEG
AVDD5-DA
XSMOTOR
AVSS-DA
XSRFRPLP
XSTELP
XSVREF2
XSRFRP
XSTEXI
AVSS-AD
XSTEI
XSFEI
XSAEI
AVDD5_AD
XSSBAD
GND
XSDFCT
XSCSJ
XSCLK
XSDATA
XSLDC
XSFGIN
XSSPDON
XSFLAG3
XSFLAG2
XSFLAG1
XSFLAG0
XMP1_7
XMP1_6
GND
XMP1_5
XMP1_4
TXD
TP
RXD
TP
VCC
1
2
3
4
MD[0..7]
MWRJ 5
MA10
MA11
2 PI_SIGO
4,5 CRSTJ
5 MPSENJ
6 IDERST
EJECT1
5 MFSCSJ
OUTSW
XSFGIN
XSPDON
FLAG3
FLAG2
FLAG1
FLAG0
DFCT
XSCSJ
XSCLK
XSDATA
SSBAD
SAEI
VC2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
U21
PLLVCC
PLLGND
10K
1
3
5
7
SRN33
RN21
RA[0..9]
RS232
VCC
TX
RX
GND
J21
ALi M5705
XRD3
XRD12
GND
XRD2
XRD13
XRD1
XRD14
XRD0
XRD15
XHD7
XHD8
XHD6
XHD9
XHD5
XHD10
XHD4
XHD11
VDD_3.3
XHD3
XHD12
XHD2
XHD13
GND
XHD1
XHD14
XHD0
XHD15
XHDRQJ
XHIOWJ
XHIORJ
XHIORDYJ
XHDACKJ
XHINTJ
XHCS16J
XHA1
XHPDIAGJ
XHA0
XHA2
XHCS1J
XHCS3J
XHDASPJ
XMA15
XMA14
XMA13
2
4
6
8
MD[0..7] 5
MA12
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
5 A16J
3.3V
FOCUS
TRACK
SLEG
MOTOR
COUNTER
5 EJECT1
5 LED1
4 INSW
4 OUTSW
RFVCC
51K
TRAY_CNTL
BIT1
MP1_
R236
C219
C220 1000P
1000P
C218
0.1U
SLRF
2 LDON
TP
RFO
COUNTER
TP
TP
TRACK
TP
MOTOR
TP
DFCT
TP
FLAG0
TP
FLAG2
TP
33
33
33
RFGND
0.1U
C221
SAEI
R217
3K3
3K3
3K3
3K3
10K
6800P
R209
C211
2 RFRP
2 MIRR
C216
R210
R211
R212
R213
R214
20K
470P 470P 1000P

C217
0.1U
R215
47K
C214 C215
3K3
4K7
0.047U
SSBAD
DFCT
PLCK
TP
R220
R218
R219
R216
0.47U
C213
RFGND
C212
1N4148
D21
R235
C209
1000P
RFGND
2 EFGC
4 SFOCUS
4 STRACK
4 SSLEG
4 SMOTOR
4 TRAY_CNTL
RFO
RFGND
R231
R234
C207
0.1U
R206
5K1
VC2
RFGND
PLLGND
PLLGND
C205
0.1U
C206
47P
C208
0.1U
R207
47K
R230
R205
4K7
3.3V
PLCK
SLRF
2,4 MVREF2
0.1U
BC26
RFVCC
3.3V
C202 R204
0.01U
C203
18P
100K
R203
51K
RA6
RA5
RA4
RA0
RA1
RA2
RA3
RFGND
BC27
0.1U
BC28
RFVCC
C204
0.1U
TC22
47U/16V
0.1U
RFVCC
PLLGND
R234R207C208
AWRC 47K R 10K
Default R 47K 0.1U
RA7
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
C201
0.1U
R201
RA9
RA8
XSAWRCVCO
XSVREFO
XSPDOFTR1
XSVR_PLL
XSFTROPI
XSFDO
AVSS_PL
XSPLLFTR2
AVDD5_PL
XSFDIREF
XSPDIREF
GND
XTSLRF
XTPLCK
VDD_3.3
XRA3
XRA2
XRA1
XRA0
XRA4
XRA5
XRA6
GND
XRA7
XRA10
XRA11
VDD_3.3
XRA8
XRA9
XROEJ
VDD_3.3
XRCASJ
XRRASJ
XRSDCLK
XRWEJ
XRD7
XRD8
XRD6
GND
XRD9
XRD5
XRD10
XRD4
XRD11
PLLGND
RD6
RD8
RD7
XMP1_3
XMFSCSJ
XMP1_2
XGPIO2
XMP1_1
XHRSTJ
XGPIO1
XGPIO0
XCRSTJ
XMPSENJ
VDD_3.3
XMALE
XMP1_0
VDD_3.3
XOSC1
XOCS2
GND
XMD0
XMD1
XMD2
XMD3
XMD4
XMD5
XMD6
XMD7
XMCSJ
XMRDJ
XMWRJ
XMINT1J
XMA11
XMA10
VDD_3.3
XMA9
XMA8
XMA7
XMA6
XMA5
XMA4
XMA3
XMA2
XMA1
XMA0
XMA12
GND
PLLVCC
RD11
RD4
RD10
RD5
RD9
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
TC21
220U/16V
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
3.3V
ROEJ 7
RCASJ 7
RRASJ 7
RWEJ 7
MA[00..15]
RD2
RD13
RD1
RD14
RD0
RD15
RD3
RD12
0.1U
MA[0..15] 5
HDRQ 6
IOWJ 6
IORJ 6
IORDY 6
HDACKJ 6
HINTJ 6
HCS16J 6
HA1 6
HPDIAGJ 6
HA0 6
HA2 6
HCS1J 6
HCS3J 6
HDASPJ 6
XHD1
XHD14
XHD0
XHD15
XHD3
XHD12
XHD2
XHD13
XHD7
XHD8
XHD6
XHD9
XHD5
XHD10
XHD4
XHD11
RD[0..15]
0.1U
0.1U
BC23
3.3V
XHD[0..15]
RD[0..15] 7
0.1U
BC24
3.3V
DECODER.SCH
Title
ALI M5705 (176 PIN) DVD/CD DECODER
3.3V
RA[0..9] 6,7
BC22
3.3V
BC21
3.3V
XHD[0..15] 6
0.1U
BC25
3.3V
DVD MODULE
MA15
MA14
MA13
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
34
Q12
D11
1N4148
TRTR+
FOFO+
PD(MONITOR)
VCC
VR
GND
LD(DVD)
LD(CD)
VR
GND(NC)
PD
GND
RFOUT
C
B
A
D
F
E
VCC
VS(VCC)
GND
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
10UH
L12
RFGND
R122
100
D12
1N4148
SOT89EBC 2SB1132
10UH
HOP-1000 JP24-05M
CN11
DVDLD
CDLD
L11
SOT89EBC 2SB1132
0.1U
100
RFGND
C130
MVREF25
TRACKTRACK+
FOCUSFOCUS+
1000P
C124
1K
R106
100U/16V
TC13
1000P
C106
5K1
R102
100U/16V
R123
PUHRF
C
B
A
D
F
E
CDMDI
DVDLD
CDLD
TRACKTRACK+
FOCUSFOCUS+
DVDMDI
RFGND
R105
10
RFGND
Q11
R101
10
4
4
4
4
D
C
B
A
F
E
MVREF25
RFO
R107
R108
R109
C114
680P
C115
680P
C117
680P
C118
680P
C119
100P
PUHRF
C101
3.3P
1K2
1K2
10K
TC16
100U/16V
0.1U
Vref
2.1V
2.5V
680P
C112
R103
TC11
R134
R135
8K2
R133
1K5
R132
DVDMDI
DVDLDO
CDMDI
CDLDO
C102
0.1U
C104
0.1U
RFGND
1
2
3
4
RFGND
SP3721
V+
BO
BB+
TL3472
AO
AA+
V-
U12
MVREF2
100U/16V
TC14
0
R
RFGND
DVDFRP
DVDRFN
PD1
PD2
A2
B2
C2
D2
CP
CN
D
C
B
A
F
E
4K7
MVREF25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
RFGND
220U/16V
R132 R133
1.5K
8.2KRFGND
0
R
3 LDON
10K
R110
MVREF25
0.1U
C109
MEI-
R134 R135
MVREF2!=MVREF25
0
R
MVREF2=MVREF25
R
0
C129
RFGND
DVDLDO
CDLDO
RFGND
0.1U
BC11
RFGND
0.1U
BC13
8
7
6
5
R118
RFGND
56K
0.47U
C134
33P
10K
C121
0.1U
C123
150P
MEVO
PI
RFGND
PI
RFRP 3
RFGND
PREAMP.SCH
Title
ALI HOP 1000 PRE-AMP CIRCUIT
R114
R113
MVREF2 3,4
MIRR 3
R115
470K
R112
MVREF2
EFGC 3
C110
33P
C111
33P
C113
33P
RFVCC
RFVCC
C122
C
C120
1000P
RFVCC
C116
0.047U
RFVCC
MEVO
MEI-
FEI
RFGND
C125
4700P
C126
1000P
0.1U
100U/16V
TC15
C131
RFGND
R136
0.1U
0.1U
RFVCC
C128
C127
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
RFVCC
SDEN
SDATA
SCLK
LCP
LCN
CE
FE
TE
MEI
MEV
TPH
DFT
PI
MIN
MEVO
MLPF
8K2
U11
C107
0.1U
R104
BC12
C103
0.1U
C105
0.1U
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
CDRFDC
CDRF
ATOP
ATON
AIN
AIP
VPA
SIGO
BYP
RX
DIN
DIP
FNP
FNN
VNA
HOLD1
RFGND
CDTE
VC12
NC
VNB
DVDPD
DVDLD
CDPD
CDLD
LDON
VC
VCI
VPB
MIRR
MP
MB
FDCHG
3
SDFCT 3
SBAD 3
TEXI
SAE
FEI
TEI
SCSJ 3
SDATA 3
SCLK 3
PRE-AMP.
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
3
3
3
ALI HOP-1000
RFGND
TC12
PAGND
0.1U
D71
1N4002
C710
12V
MVCC
PAGND
220U/16V
0.1U
PAGND
TC71
C701
D72
1N4002
FB-1
PAGND
FB-1
L78
MVCC
Q73
(BA05 TO252AA)
5V
+12V
L71
PAGND
0.1U
C706
5V
0.1U
C709
5V
220U/16V
TC75
FB-1
L74
FB-1
L77
IN
OUT
0.1U
C708
3.3V
RFGND
0.1U
C707
RFVCC
PLLGND
0.1U
C704
PLLVCC
M5V
VCC
C703
0.1U
3.3 0805
R701
FB-1
L72
Q72
SOT223 AS1117
TC72
220U/16V
0.1U
1
C702
5V
GND
35
1
12V
100U/16V
TC76
100U/16V
TC73
PLLGND
TP
PLLGND
PLLVCC
TP
PLLVCC
RFGND
TP
RFGND
RFVCC
TP
RFVCC
MGND
TP
MGND
MVCC
TP
MVCC
GND
TP
GND
3.3V
TP
3.3V
ALI HOP-1000
POWER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
VEE
HA2 /AUX4[4]
VEE
AUX[0]
AUX[1]
AUX[2]/IOW#
VSS
VEE
AUX[3]/IOR#
AUX[4]
AUX[5]
AUX[6]
AUX[7]
LOE#
VSS
VCC
LCS0#
LCS1#
LCS2#
LCS3#
VSS
LD0
LD1
LD2
LD3
LD4
VEE
VSS
LD5
LD6
LD7
LD8
LD9
LD10
LD11
VSS
VEE
LD12
LD13
LD14
LD15
LWRLL#
LWRHL#
VSS
VEE
CAMIN0
CAMIN1
LA0
LA1
LA2
LA3
VSS
VEE
LA4
LA5
LA6
LA7
LA8
LA9
VSS
VCC
LA10
LA11
LA12
LA13
LA14
LA15
LA16
VSS
VEE
LA17
LA18
LA19
LA20
LA21
RESET#
TDMDX/RSEL
VSS
VEE
TDMDR
TDMCLK
TDMFS
TDMTSC#
TWS/SEL_PLL2
TSD0/SEL_PLL0
VSS
VCC
TSD1/SEL_PLL1
TSD2
TSD3
MCLK
TBCK
SPDIF/PLL3
NC
VSS
VCC
RSD
RWS
RBCK
NC
XIN
XOUT
AVEE
VSS
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
VSS
HA1/AUX4[3]
HA0/AUX4[2]
HCS3FX#/AUX3[6]
HCS1FX#/AUX3[7]
HIOCS16#/CAMCLK/AUX3[4]
HRD#/DCI_ACK#/AUX4[6]
HWR#/DCI_CLK/AUX4[5]
VEE
VSS
HIORDY/AUX3[3]
HRST#/AUX3[5]
HIRQ/DCI_ERR#/AUX4[7]
HRRQ#/AUX4[0]
HWRQ#/DCI_REQ#/AUX4[1]
HD15/AUX2[7]/IR
HD14/AUX2[6]/SQSI
VCC
VSS
HD13/AUX2[5]/SP
HD12/AUX2[4]/C2PO
HD11/AUX2[3]//IRQ
HD10/AUX2[2]/SQSK
HD9/AUX2[1]/SQSO
HD8/DCI_FDS#/AUX2[0]/VFD_CLk
HD7/DCI7/AUX1[7]/VFD_DIN
VEE
VSS
HD6/DCI6/AUX1[6]/VFD_DOUT
HD5/DCI5/AUX1[5]
HD4/DCI4/AUX1[4]
HD3/DCI3/AUX1[3]
HD2/DCI2/AUX1[2]
HD1/DCI1/AUX1[1]
HD0/DCI0/AUX1[0]
VCC
VSS
HSYNC#/CAMIN7/AUX3[0]
VSYNC#/CAMIN6/AUX3[1]
PCLKQSCN/CAMIN5/AUX3[2]
PCLK2XSCN/CAMIN4
YUV7/CAMIN3
YUV6/VDAC
YUV5/YDAC
VSS
ADVEE
YUV4/RSET
YUV3/COMP
YUV2/CDAC
YUV1/VREF
YUV0/CAMIN2/UDAC
DCLK
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
ES6008/18/28/38
208-Pin PQFP Package
MPEG Board
MPEG Decoder
36
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
VEE
VSS
DSCK
DQM
DCS0#
VEE
VSS
DCS1#
DB15
DB14
DB13
DB12
VEE
VSS
DB11
DB10
DB9
DB8
DB7
DB6
VSS
VCC
DB5
DB4
DB3
DB2
DB1
DB0
VSS
VEE
DMBS1
DMBS0
DRAS#
DWE#
DOE#/DSCK_EN
DCAS#
VEE
VSS
DMA11
DMA10
DMA9
DMA8
DMA7
DMA6
VSS
VEE
DMA5
DMA4
DMA3
DMA2
DMA1
DMA0
11- DESCRIPTION
OF INTEGRATED
CIRCUITS
-TV PART-
37
STV224X
pos: ICV1
Multi Standard TV Processor

STV224X is a fully bus controlled IC for TV including PIF, SIF , Luminance , Chrominance and deflection processing. It is a
bus controlled PAL / SECAM / NTSC single chip TV Processor. For details of STV224X features please refer to the
STV224X datasheet. 110 , 4:3 or 16:9 CRT applications. It integrates both vertical deflection and E-W correction circuit
necessary for design of 110 chassis it allows designing a PAL/NTSC(BGDKIMN) set with very few external components
and no manual adjustment.
SIFIN1
56
FMCAP
SIFIN2
55
AUDIOOUT
54
GNDD
53
V CCD
52
SDA
PIFIN1
51
SCL
PIFIN2
50
SLPF
49
LFB/SSC
IFPLL
48
HOUT
GND IF
10
47
VERT
AM /FMOUT/SC
11
46
BCL/SAF
V CCIF
12
45
V CC1
13
44
CVBSOUT2
14
43
PIFLC1
15
42
PIFLC2
AGCSIFCAP
V REFIF
AGCPIFCAP
TUNERAGCOUT
INTCVBSOUT
EXTAUDIOIN
GND1
X1/VAMP/CHROUT
16
41
CLPF
V CC2
17
40
XTAL1
CVBSIN1
18
39
XTAL2
GND2
19
38
XTAL3/BTUN
CVBSIN2
20
37
FBOSD/HC
BS
21
36
ROSD
Y/CVBSIN3
22
35
GOSD
CHR
23
34
BOSD
APR
24
33
ICATH
BEXT/Cb
25
32
ROUT
GEXT/Y
26
31
GOUT
REXT/Cr
27
30
BOUT
FBEXT
28
29
NTBC/CVBSOUT1
38
STV224X
1.2 PIN DESCRIPTION
Table 1. Pin Configuration
Pin N
STV224XC/8XC
STV223XD
SDIP56
TQFP64
1
8
2
9
3
10
4
11
5
12
6
13
7
14
8
16
9
17
10
18
11
19
12
20
13
21
14
22
15
23
16
24
17
25
18
26
19
27
20
28
21
29
22
34
23
35
37
38
39
40
41
42
30
43
31
44
32
45
33
46
34
47
35
48
36
49
37
50
38
52
39
53
40
54
41
55
42
56
Symbol
Description
SIFIN 1
SIFIN 2
AG C SIFC AP
VREFIF
AGCPIFCAP
PIFIN1
PIFIN2
TUNERAGCOUT
IFPLL
GND IF
AM/FMOUT/SC
VCCIF
INTCVBSOUT
EXTAUDIOIN
PIFLC1
PIFLC2
VCC2
CVBSIN1
GND2
CVBSIN2
BS
Y/CVBSIN3
CHR
U IN
VIN
YIN
YOUT
VO U T
UO UT
BOUT
GOUT
ROUT
I
CATH
BOSD
GOSD
ROSD
FBO SD /HC
XTAL3/BTUN
XTAL2
XTAL1
CLPF
SIF Input
SIF Input
AG C SIF C apacit
or
Voltage Reference Filtering
AGC PIF Capacitor
PIF Input
PIF Input
AGC Tuner Output
IF PLL Filter
IF Ground
AM/FM Mono Sound or Stereo Carriers Output
5 V IF Supply
Internal CVBS Output
External Audio Input
LC Input
LC Input
Video/Luma Supply Voltage (8 V)
Internal Video Input
Video/Luma Ground
External Video Input
Black Stretch Capacitor
Y(SVHS) or CVBS3 External Input
Chroma (SVHS) Input
B-Y In
put
R -Y In
put
Y Input
Y O utput
R -Y O utput
B-Y O utput
Blue Output
Green Output
Red Output
Cathode Current Measurement Input
OSD Blue Input
OSD Green Input
OSD Red Input
O SD Fast Bl
ankingInput /alf
H ont
C rast onSD IP56 package
3.5X M Hz C rystalorC loche Filt
erTuningC apacitor
3.5X MHz Crystal
4.43/3.5X MHz Crystal
Chroma PLL Filter
XTAL1 Control Pin, Vertical Amplitude DAC Output
X1/VAMP/CHROUT
Chroma Reference Signal Output
39
Pin N
STV224XC/8XC
STV223XD
SDIP56
TQFP64
43
57
58
45
59
Symbol
GND1
CVBSOUT1
VCC1
46
61
BCL/SAF
47
48
49
50
51
52
53
54
55
56
62
63
64
1
2
3
4
5
6
7
VERT
HOUT
LFB/SSC
SLPF
SCL
SDA
VCCD
GNDD
AUDIOOUT
FM C AP
Description
Chroma/Scanning Ground
Main Video Switch Output
Chroma/Scanning Power Supply (8 V)
Beam Current Limiter Control Voltage and Safety
(XRAY)
Vertical Output Pulse
Horizontal Output Pulse
Line Flyback Input and Super-Sandcastle Output
Scanning PLL Filter
I C Bus Clock Input
I C Bus Data Input
Digital Supply Voltage (5 V)
Digital Ground
Main Audio Output
FM D em odulati
on C apacit
or
40
41
54
IF 10
GND2
19
V CC2 17
GND1 43
V CC1 45
V REF
51
AUDIO
REF
29 44
38
CLOCHE
TUNING
Mute
CLOCHE
FILTER
11
AVL
AM
Mono
FM
Mono
DEEMP.
AM/FMOUT/SC
14
Mute
SOUND BP
FM DEMOD
XTAL3/BTUN
EXTAUDIOIN
55
VOLUME
LIMITER
PLL Reference
Carrier
Subcarrier
SCL
52
IC BUS
DECODER
AGC
TUNER AGC
Sound
GND
V CCIF 54
GNDD
V CCD 53
AGCSIFCAP
SIFIN2 2
SIFIN1 1
TUNERAGCOUT
PIFLC1
AGC
IFPLL
INTCVBSOUT
AGCPIFCAP
CHR
W/B SPOT
INVERTER
Y/CVBSIN3
18
CVBSIN1
20
CVBSIN2
22
NTBC/CVBSOUT1
23
CVBSOUT2
PIFIN2 7
56
49
HORIZONTAL
2nd LOOP
50
VAMP DC
CONTROL
ICATH SENSE
BCL/SAF
RGB
CONTRAST
APR
HALF
CONTRAST
VERTICAL
SCANNING
HORIZONTAL
1st LOOP
SYNC.
SEP
27
RGB
TO YUV
26
25
SLPF
42
CHROMA
DL
BRIGHT.
DRIVE
CUTOGG
BLANKING
RGB
SWITCH
SAT./CONT
MATRIX
YUV
SWITCH
28
LFB/SSC
X1/VAMP/CHROUT
41
AUTO IDENT.
KILLER
PAL/SECAM/NTSC
DEMODULATOR
BANDPASS
FILTER
ACC & ACC

OVERLOAD
FILTER
TUNING
CHROMA
TRAP
LUMA DL
PEAKING
& CORING
BLACK
STRETCH
21
BS
AFC
FMCAP
13
FBEXT
BEXT/Cb
PIFIN1 6
16
GEXT/Y
PLL
PIFLC2
15
REXT/Cr
STV2248
48 HOUT
47 VERT
30 BOUT
31 GOUT
32 ROUT
33 ICATH
46 BCL/SAF
34 BOSD
35 GOSD
36 ROSD
37 FBOSD/HC
24 APR
CLPF
XTAL1
XTAL2
AUDIOOUT
SDA
MAIN FEATURES
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
I-C bus control (read and write modes),

PIF PLL demodulator, Bus controlled VCO alignment,
IF positive and negative modulation,
Digital AFC,
Tuner delayed AGC output,
White and Black spot cancellation,
SIF with QSS or intercarrier structure,
Built in sound bandpass,
Multistandard PLL FM demodulator (4.5, 5.5,
6.0,6.5MHz),
AM demodulator for France,
FM sound carriers output for Stereo chassis,
Audio switch for external audio input, Mono chassis,
Digital volume control,
Audio Mute,
Video switch, 3 CVBS inputs, 1 CVBS output which can
be used to drive teletext decoder,
SVHS switch, Y input is combined with CVBS3 input,
OSD RGB analog inputs, fast blanking detection on OSD
fast blanking pin, contrast control capability,oversize
blanking capability on OSD fast blanking input,
External analog RGB inputs with contrast and saturation
control (external RGB matrixed in YUV).
Integrated chroma filters (trap, bandpass, cloche) with
automatic alignment,
Integrated luminance delay line,
Adjustable peaking on the luminance signal with coring
function,
Black strech circuit,
PAL / SECAM / NTSC color decoder with automatic identification of standards,
Integrated chroma delay line,
Full integrated SECAM decoder,
Hue control, two selectable matrixes in NTSC mode,
Automatic flesh control circuit with two selectable characteristics (normal and wide),
ACC overload circuit,
Chroma subcarrier output, which could be used to drive
comb filter circuit,
Automatic RGB peak regulation (APR).
Automatic digital cut-off current loop with warm-up detection circuit,
White point and cut-off point adjustments,
Beam current limiter control stage,
High performance synchronization pulses separator,
Horizontal synchronization with two phase locked loops,
Integrated VCO, auto-calibration using the chroma crystal
reference frequency,
Automatic time constant selection for the first PLL, 3
selectable time constants,
l
l
l
l
l
l
l
l
l
42
Video identification circuit (independent from PLL1),

Noise detector circuit,
Vertical countdown circuit,
Automatic 50/60Hz selection circuit,
Blanking and inserted cut-off pulses position adapted to
standard (50 or 60Hz),
Long blanking mode capability in 60Hz (same blanking as
50Hz standard),
Possibility to insert cut-off pulses after a vertical oversize
blanking signal,
De-interlace capability,
Horizontal starting circuit with soft-start capability,
Horizontal and vertical position adjustments, vertical
amplitude control voltage (combined with chroma subcarrier output),
4/3, 16/9 selection voltage.
ELEC TRICAL CHAR A CT ERISTICS

A B SO LU TE MA XIMUM RA TING S
Symbol
Parameter
Value
Unit
V CC _8V
8 V Supply Voltage
10
V CC _5V
5 V Supply Voltage
V ESD
Capacitor 100 pF discharged via

serial
1.5 k resistance (Human Body Model)
2
Toper
Operating Temperature
Tstg
Storage Temperature
kV
0, +70 C
-55, +150C
TH ER M A L DA TA
Symbol
Parameter
R th (j-a)Junction-ambient Thermal Resistance (measured

D = 1 W)at P
SDIP56
TQFP64
Typical
Value
Unit
40
50
C/W
C/W
SU PPLY
(Supplies at Typical Values,
T C, I
C bus register at power-on reset value, autom
amb = 25
mode, unless otherwise specified).
Symbol
V CCIF
V CCD
V CC1
V CC2
ICCIF
ICC5F
ICCI
ICC2
PD
Parameter
Test Conditions
Min. Typ Max.
Unit
IF Circuit Supply Voltage
4.75
5
5.25
Bus & Digital Supply Voltage
4.75
5
5.25
Chroma, Scanning Supply Voltage
7.6
8
8.4
V
Video Supply Voltage
7.6
8
8.4
V
V CCIF Current Consumption
V
=
5
V.
No-load
at
RGB
outputs.
58
m
CCIF
V CC5F Current Consumption
V
=
5
V.
No-load
at
RGB
outputs.
48
m
CCD
V CCI Current Consumption
40
m
CCIV= 8 V. No-load at RGB outputs.
V CC2 Current Consumption
V
=
8
V.
No-load
at
RGB
outputs.
56
m
CC2
V CCI = V
CC2 = 8 V,
TotalPower Dissipation
V CCIF =V CC5V = 5 V
No-load at RGB outputs.
43
1300
mW
ST92195C/D
pos: IC01
48-96 KB ROM HCMOS MCU WITH ON-SCREEN DISPLAY AND

TELETEXT DATA SLICER
General Features:
Register File based 8/16 bit Core Architecture with RUN,
WFI, SLOW and HALT modes
0C to +70C Operating Temperature Range available
C-Compiler, Archiver, Source Level Debugger and hardware emulators with Real-Time Operating System available from third parties
Pin Compatible EPROM and OTP devices available.
Microcontroller+OSD+(Teletext decoder)+VPS/PDC/WS
decoder are embedded in one chip, where there are two
types with the major difference;
ST92185 No-teletext
ST92195 With teletext
The ST92195 microcontroller is developed and manufactured by STMicroelectronics using a pro-prietary n-well
HCMOS process. Its performance derives from the use of
a flexible 256-register pro-gramming model for ultra-fast
context switching and real-time event response. The intelligent on-chip peripherals offload the ST9 core from I/O and
data management processing tasks allowing critical application tasks to get the maximum use of core resources.
The ST92195 MCU supports low power consumption and
low voltage operation for power-efficient and low-cost
embedded systems.
The advanced ST9+ Core consists of the Central Processing Unit (CPU), the Register File and the Interrupt controller. The general-purpose registers can be used as accumulators, index registers, or address pointers. Adjacent
register pairs make up 16-bit registers for addressing or
16-bit processing. Although the ST9 has an 8-bit ALU, the
chip handles 16-bit operations, including arithmetic,
loads/stores, and memory/register and memory/memory
exchanges. Two basic addressable spaces are available:
the Memory space and the Register File, which includes
the control and status registers of the on-chip peripherals.
Power consumption of the device can be reduced by more
than 95% (Low power WFI).
Up to 28 I/O lines are dedicated to digital Input/Output.
These lines are grouped into up to five I/O Ports and can
be configured on a bit basis under software control to provide timing, status signals, timer and output, analogue
inputs, external interrupts and serial or parallel I/O. A set
of on-chip peripherals form a complete system for TV set
and VCR applications:
Voltage Synthesis
VPS/WSS Slicer
Teletext Slicer
Teletext Display RAM
OSD
Up to 24 MHz Operation @ 5V10%

Minimum instruction cycle time: 165nS at 24MHz.
48, 56, 64, 84 or 64K Bytes ROM
256 Bytes RAM of Register file (accumulators or index
registers)
256 to 512 Bytes of on-chip static RAM
2 or 8 Kbytes of TDSRAM (Teletext and Display Storage
RAM)
28 fully programmable I/O pins
Serial Peripheral Interface
Flexible Clock controller for OSD, Data Slicer and Core
clocks running from
a single low frequency external crystal.
Enhanced Display Controller with 26 rows of 40/80 characters
2 sets of 512 characters
Serial and Parallel attributes
10x10 dot Matrix, definable by user
4/3 and 16/9 supported in 50/60HZ and 100/120 Hz
mode
Rounding, fringe, double width, double height,
scrolling, cursor, full Background color, half-intensity
color, translucency and half-tone modes
Teletext unit, including Data slicer, Acquisition Unit and
up to 8K Bytes RAM for Data Storage
VPS and Wide Screen Signalling slicer
Integrated Sync Extractor and Sync Controller
14-bit Voltage Synthesis for tuning reference voltage
Up to 6 External Interrupts plus one non-maskable interrupt
8 x 8-bit programmable PWM outputs with 5V open-drain
or push-pull capability
16-bit Watchdog timer with 8-bit prescaler
1 or 2 16-bit standard timer(s) with 8-bit prescaler
IC Master/Slave (on some devices)
4-channel A/D converter; 5-bit guaranteed
Rich instruction set and 14-Addressing modes
Versatile development tools, including Assembler, Linker,
44
BLOCK
DIAGRAM
Up to 96
Kbytes ROM
256 or 512
bytes RAM
256 bytes
Register File
8/16-bit
CPU
NMI
INT[7:4]
INT2
INT0
MEMORY BUS
Up to 8
Kbytes TRI
TDSRAM
P2[5:0]
I/O
PORT 3
P3[7:4]
I/O
PORT 4
P4[7:0]
I/O
PORT 5
P5[1:0]
16-BIT
TIMER/
WATCHDOG
VPS/WSS
DATA
SLICER
TIMING AND
CLOCK CTRL
REGISTER BUS
SYNC.
EXTRACTION
MCFM
SDA1/SCL1
SDA2/SCL2
I/O
PORT 2
RCCU
SPI
STOUT0
P0[7:0]
DATA
SLICER
& ACQUISITION
UNIT
Interrupt
Management
SDO/SDI
SCK
VSO[2:1]
MMU
ST9+ CORE
OSCIN
OSCOUT
RESET
RESETO
I/O
PORT 0
ADC
SYNC
CONTROL
VOLTAGE
SYNTHESIS
ON
SCREEN
DISPLAY
STANDARD
TIMER 1)
PWM
D/A CONVERTER
IC 2)
TXCF
CVBS1
WSCR
WSCF
CVBS2
AIN[4:1]
EXTRG
VSYNC
HSYNC/CSYNC
CSO
FREQ.
PXFM
MULTIP.
R/G/B/FB
TSLU
HT
PWM[7:0]
All alternate functions

(Italic characters)
are mapped on Ports 0, 2, 3, 4 and 5
Note 1
: One standard timer on ST92195C devices, two standard timers on ST92195D devic
Note 2
: C
I available on ST92195D devices only
45
PIN DESCRIPTION (Cont

d)
Figure 3. 56-Pin Package Pin-Out
INT7/P2.0 1
RESET 2
P0.7 3
P0.6 4
P0.5 5
P0.4 6
P0.3 7
AIN4/P0.2 8
P0.1 9
P0.0 10
CSO/RESET0 /P3.7 11
P3.6 12
P3.5 13
P3.4 14
B 15
G 16
R 17
FB 18
SDA1/SDI/SDO/P5.1 19
SCL1/SCK/INT2/P5.020
V DD 21
JTDO 22
23
WSCF
V PP /WSCR 24
AVDD3 25
TEST0 26
27
MCFM
JTCK 28
56 P2.1/INT5/AIN1
55 P2.2/INT0/AIN2
54 P2.3/INT6/VS01
53 P2.4/NMI
52 P2.5/AIN3/INT4/VS02
51 OSCIN
50 OSCOUT
49 P4.7/PWM7/EXTRG/STOUT0
48 P4.6/PWM6
47 P4.5/PWM5/SDA2
46 P4.4/PWM4/SCL2
45 P4.3/PWM3/TSLU/HT
44 P4.2/PWM2
43 P4.1/PWM1
42 P4.0/PWM0
41 VSYNC
40 HSYNC/CSYNC
39 AVDD1
38 PXFM
37 JTRSTO
36 GND
35 AGND
34 CVBS1
33 CVBS2
32 JTMS
31 AVDD2
30 CVBSO
29 TXCF
RESET Reset (input, active low). The ST9+VSYNC

is iniVertical Sync. Vertical video synchro
tialised by the Reset signal. With the deactivation
tion input to OSD. Positive or negative
of RESET, program execution begins from
the
HSYNC/CSYNC
Horizontal/Composite sync. HoriProgram memory location pointed to by thezontal
vectoror composite video synchronisatio
contained in program memory locations 00h
and
OSD.
Positive or negative polarity.
01h.
PXFM Analog pin for the Display Pixel F
R/G/B Red/Green/Blue. Video color analog DAC
Multiplier
outputs.
AVDD3 Analog V DD of PLL. This pin must be t
FB Fast Blanking. Video analog DAC output. to V externally.
DD
VDD Main power supply voltage (5V10%, digital)
GND Digital circuit ground.
WSCF, WSCR Analog pins for the VPS/WSS slicAGND Analog circuit ground (must be ti
er . These pins must be tied to ground or
not to
connally
digital GND).
nected.
CVBS1 Composite video input signal for t
VPP: On EPROM/OTP devices, the WSCR pin is
text slicer and sync extraction.
replaced byPP Vwhich is the programming voltage
CVBS2 Composite video input signal for t
pin. PP
V should be tied to GND in user mode.
WSS slicer. Pin AC coupled.
MCFM Analog pin for the display pixel frequency
AVDD1, AVDD2 Analog power supplies (must
multiplier.
tied externally to AVDD3).
OSCIN, OSCOUT Oscillator (input and output).
Analog pin for the Teletext slicer
These pins connect a parallel-resonantTXCF
crystal
(24MHz maximum), or an external source CVBSO,
to the JTDO, JTCK Test pins: leave float
on-chip clock oscillator and buffer. OSCIN is the
TEST0 Test pins: must be tied to AVDD2.
input of the oscillator inverter and internal clock
JTRST0 Test pin: must be tied to GND.
generator; OSCOUT is the output of the oscillator
inverter.
46
PIN ASSIGNMENT
Pin No.
1
3
4
5
6
7
8
9
10
11
12
13
14
28
30
32
42
43
44
45
46
47
48
49
53
54
55
56
Pin Name
INT7/P2.0
P0.7
P0.6
P0.5
P0.4
P0.3
AIN4
P0.1
P0.0
CSO/RESET0/P3.7
P3.6
P3.5
P3.4
JTCK
CVBSO
JTMS
P4.0/PWMO
P4.1/PWM1
P4.2/PWM2
P4.3/PWM3
P4.4/PWM4
P4.5/PWM5
P4.6/PWM6
P4.7/PWM7/EXTRG/STOUT
P2.4/NMI
P2.3/INT6/VS01
P2.2/INT0/AIN2
P2.1/INT5/AIN1
I/O Function
IR INT. IN
DVDDATAOUT
STOP
N.C.
N.C.
N.C.
AV.STATUS
N.C.
N.C.
MUTE_DVD
L/L'
TV/DVD
STDBY
N.C.
N.C.
N.C.
DVD_STD_BY
VOL
N.C.
DVD POWER +5V
DVD POWER +12V
N.C.
N.C.
N.C.
N.C.
LED CONTROL
DVDDATAIN
KEYBOARD INPUT
47
24C08
pos: IC02
Non-Volatile Memory
These I_C-compatible electrically erasable programmable memory (E_PROM) is organized as 1024 x 8 bit and operate
with a power supply of 5 V. The memory behaves as a slave device in the I_C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a START
condition, generated by the bus master. The START condition is followed by a Device Select Code and RW bit terminated
by an acknowledge bit.
DC Characteristics
70 20 to C85or 40 toC;
85 CC
V = 3V to 5.5V, 2.5V to 5.5V or 1.8V to 5.5V
(TA = 0 toC,
Symbol
Parameter
ILI
Input Leakage Current
ILO
Output Leakage Current
ICC
Supply Current (ST24 series)

Supply Current (ST25 series)
ICC1
ICC2
ICC3
ICC4
Supply Current (Standby)

(ST24 series)

(ST25 series)

(ST24C08R)

(ST24C08R)
V IL
Input Low Voltage (SCL, SDA)
V IH
Input High Voltage (SCL, SDA)
V IL
Input Low Voltage

(E, PRE, MODE,
WC)
V IH
Input High Voltage

(E, PRE, MODE,
WC)
Test Condition
Max
Unit
mA
V
0V
IN VCC
0V VOUT VCC
SDA in Hi-Z
V CC = 5V,C f
= 100kHz
(Rise/Fall time < 10ns)
CC
V C =f 100kHz
= 2.5V,
V,
V IN = V
SS or CC
V CC = 5V
V IN = V
V,
SS or CC
= 100kHz
V CC = 5V,C f
V IN = V
V,
SS or CC
V CC = 2.5V
V IN = V
V,
SS or CC
V CC = 2.5V,
C =f 100kHz
V,
V IN = V
SS or CC
V CC = 3.6V
V IN = V
V,
SS or CC
V CC = 3.6V,
C =f 100kHz
V IN = V
V,
SS or CC
V CC = 1.8V
V IN = V
V,
SS or CC
V CC = 1.8V,
C =f 100kHz
CC
mA
100
300
50
20
60
10
20
0.3
CC
0.3 VV
0.7 VVCC + 1
0.3
V CC 0.5
Output Low Voltage (ST24 series)

I CCV = 5V
OL = 3mA,
V OL
Min
0.5
V
CC
+ 1
0.4
V
V
V
V
Output Low Voltage (ST25 series)

I
OL = 2.1mA,
CCV = 2.5V
0.4
Output Low Voltage

(ST24C08R)
0.3
IOL = 1mA, CCV = 1.8V
48
TDA1771
pos: ID41
VERTICAL DEFLECTION CIRCUIT

DESCRIPTION
The TDA1771 is a monolithic integrated circuit in SIP10 package.
It is a full performance and very efficient vertical deflection circuit intended for direct drive of a TV picture tube in Color and
B & W television as well as in Monitor and Data displays.
.
.
.
.
.
.
.
RAMP GENERATOR
INDEPENDENT AMPLITUDE ADJUSTEMENT
BUFFER STAGE
POWER AMPLIFIER
FLYBACK GENERATOR
INTERNAL REFERENCE VOLTAGE
THERMAL PROTECTION
SIP10
(Plastic Package)
ORDER CODE : TDA1771
ESCRIPTION
he TDA1771 is a monolithic integrated circuit in
IP10 package.
t is a full performance and very efficient vertical
eflection circuit intended for direct drive of a TV
icture tube in Color and B & W television as well
s in Monitor and Data displays.
10
9
8
7
6
5
4
3
2
1
FLYBACK GENERATOR
VS
INVERTING INPUT
BUFFER OUTPUT
RAMP GENERATOR
GROUND
HEIGHT ADJUSTMENT
TRIGGER INPUT
OUTPUT STAGE V S
POWER OUTPUT
1771-01.EPS
PIN CONNECTIONS (top view)
LOCK DIAGRAM
2
VOLTAGE
REGULATOR
FLYBACK
GENERATOR
10
R3
CLOCK
PULSE
RAMP
GENERATOR
POWER
AMP.
BUFFER
STAGE
THERMAL
PROTECTION
49
-02.EPS
TRIGGER IN
ABSOLUTE MAXIMUM RATINGS

Parameter
Value
Supply Voltage
VS
V1 ,
2V
30
Flyback Peak Voltage

Trigger Input Voltage
V8
Amplifier Input Voltage
I0
Output Peak to Peak Current (non repetitive t = 2ms)
20
I0
Output Peak to Peak Current

st > 10
Pin 10 DC Current1 at
< V
9V
I10
Pin 10 Peak to Peak Current

t
fly< @1.5ms
V
V
6
100
mA
Total Power Dissipation

= T
60
C
tab @
JT
GND
to V
S
I10
P tot
65
V3
TS ,
Unit
1771-01.TBL
Symbol
W
40, + 150
C
Storage and Junction Temperature
THERMAL DATA
R th
Parameter
(j-tab)Thermal
R th
(j-a)
Value
Resistance Junction-tab
Thermal Resistance Junction-ambient
Unit
Max.
10
C/W
Max.
70
C/W
Max.
Unit
1771-02.TBL
Symbol
ELECTRICAL CHARACTERISTICS (Tamb = 25

C unless otherwise specified)
Symbol
Parameter
Test Conditions
Min.
Typ.
DC (VS = 30V)
I2
Pin 2 Quiescent Current
= 0,
I
10 I= 0
16
36
mA
I9
Pin 9 Quiescent Current
= 0,
I
10 I= 0
15
30
mA
Ramp Generator Bias Current
= 0
V
Ramp Generator Current
=V 0, 4 =I 20
A
Ramp Gener. Linearity
= V0 to 15V,
20
IA
4 =
= R
30k
, R
, V
b = 10k
S = 30V
dI6/I
6
Quiescent Output Voltage
V1
, R
, V
R a = 6.8k
b = 10k
S = 15V
18.5
Out Saturation Voltage

to V
S
Reference Voltage
V4
17.8
18.6
7.5
7.8
0.5
1.4
1I = 0.5A
1.1
1.6
1I = 1.2A
1.6
2.2
= I20
A
6.3
6.6
Reference Voltage Drift Versus

V S V= 10V to 30V
S
Reference Voltage Drift 4Versus
I4 =
I 10
A to 30
A
1.5
Vr
Internal Ref. Voltage
4.26
Gv
Ouput Stage Open Loop Gain
f = 100Hz
V fs
V9
= 1.2A
I
V 10
Pin 10 Scanning Voltage
V3
Trigger Input Threshold
I3
Trigger Input Bias Current
t3
Trigger Input Width
7.2
dV4/VS
10Saturation Voltage
dV4/dI
17.0
I1 = 1.2A
V 1H
0.5
21.5
0.2
Out Saturation Voltage to GND 1 = 0.5A

I
V 1L
20
10
10
= I
20mA
(see note 1)
IN
mV/V
mV/A
2
4.40
4.54
60
1.5
1.7
2.6
= V
0.2V
3 V
(see note 2)
6.9
dB
2.5
V
3.0
30
20
3.4
60 S th
1171-03.TBL
6I
6I
Notes : 1. The trigger input circuit can accept, with a metal option, positive and negative going input pulses.
1.2 tS
2. th=
whereS tis the vertical period
and
ramp
V amplitude at Pin 6
PP is
V PP
50
ELECTRICAL CHARACTERISTICS (Tamb = 25

C unless otherwise specified) (continued)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
DC (VS = 24V)
Operating Supply Voltage Range
I1
Peak-to-peak Operating Current Range
IS
Supply Current
=I 2.4A
pp
315
V1
Flyback Voltage
=I 2.4A
pp
51
V7
Sawtooh Pedestall Voltage
TJS
Junction Temp. for Thermal Shutdown
10
30
0.4
2.5
mA
V
1.85
145
1771-04.TBL
VS
APPLICATION CIRCUIT
+VS
0.1F
470F
1N4001
100F
35V
VOLTAGE
REGULATOR
FLYBACK
GENERATOR
10
POWER
AMP.
R3
CLOCK
PULSE
RAMP
GENERATOR
2.2
330
BUFFER
STAGE
YOKE
0.22
F
THERMAL
PROTECTION
Ry = 9.6
Ly = 24.6mH
Iy = 1.2App
2.4k
4
180k
1.2k
1500F
1k
47nF
22F
220k
1.2
51
1771-03.EPS
TRIGGER IN
TDA 16846
pos: IP01
Controller for Switch Mode Power Supplies Supporting Low Power

Standby and Power Factor Correction
Features
Description
Line Current Consumption with PFC

Low Power Consumption
Stable and Adjustable Standby Frequency
Very Low Start-up Current
Soft-Start for Quiet Start-up
Free usable Fault Comparators
Synchronization and Fixed Frequency Facility
Over- and Undervoltage Lockout
Switch Off at Mains Undervoltage
Temporary high power circuit (only TDA 16847)
Mains Voltage Dependent Fold Back Point Correction
Continuous Frequency Reduction with Decreasing
Load
Adjustable and Voltage Dependent Ringing Suppression Time
The TDA 16846 is optimised to control free running or

fixed frequency flyback converters with or without Power
Factor Correction (Current Pump). To provide low power
consumption at light loads, this device reduces the
switching frequency continuously with load, towards an
adjustable minimum (e. g. 20 kHz in standby mode).
Additionally, the start up current is very low. To avoid
switching stresses of the power devices, the power transistor is always switched on at minimum voltage. A special circuit is implemented to avoid jitter. The device has
several protection functions: V CC over- and undervoltage, mains undervoltage, current limiting and 2 free
usable fault comparators. Regulation can be done by
using the internal error amplifier or an opto coupler feedback (additional input). The output driver is ideally suited
for driving a power MOSFET, but it can also be used for
a bipolar transistor. Fixed frequency and synchronized
operation are also possible. The TDA 16846 is suited for
TV-, VCR- sets and SAT receivers. It also can be good
used in PC monitors. The TDA 16847 is identical with
TDA 16846 but has an additional power measurement
output (pin 8) which can be used for a Temporary High
Power Circuit.
Pin Configuration (top view)
Pin Definitions and Functions

Pin
DTC
PCS
Symbol
Function
OTC
Off Time Circuit
PCS
Primary Current Simulation
RZI
Regulation and Zero Crossing Input
14
VCC
13
OUT
RZI
12
GND
SRC
Soft-Start and Regulation Capacitor
SRC
11
PVC
OCI
Opto Coupler Input
OCI
10
FC1
FC2
Fault Comparator 2
FC2
REF
SYN
Synchronization Input
SYN
N.C./PMO
N.C./PMO
Not Connected (TDA16846)
REF
Reference Voltage and Current
10
FC1
Fault Comparator 1
11
PVC
Primary Voltage Check
12
GND
Ground
13
OUT
Output
14
VCC
Supply Voltage
52
Short Description of the Pin Functions
Pin
Functions
A parallel RC-circuit between this pin and ground determines the ringing suppression time
and the standby-frequency.
A capacitor between this pin and ground and a resistor between this pin and the positive
terminal of the primary elcap quantifies the max. possible output power of the SMPS.
This is the input of the error amplifier and the zero crossing input. The output of a voltage
divider between the control winding and ground is connected to this input. If the pulses at
pin 3 exceed a 5 V threshold, the control voltage at pin 4 is lowered.
This is the pin for the control voltage. A capacitor has to be connected between this pin
and ground. The value of this capacitor determines the duration of the softstart and the
speed of the control.
If an opto coupler for the control is used, it's output has to be connected between this pin
and ground. The voltage divider at pin 3 has then to be changed, so that the pulses at pin
3 are below 5 V.
Fault comparator 2: If a voltage > 1.2 V is applied to this pin, the SMPS stops.
If fixed frequency mode is wanted, a parallel RC circuit has to be connected between this
pin and ground. The RC-value determines the frequency. If synchronized mode is wanted,
sync pulses have to be fed into this pin.
Not connected (TDA16846). / This is the power measurement output of the Temporary
High Power Circuit. A capacitor and a RC-circuit has to be connected between this pin
and ground.
Output for reference voltage (5 V). With a resistor between this pin and ground the fault
comparator 2 (pin 6) is enabled.
10
Fault comparator i: If a voltage > 1 V is applied to this pin, the SMPS stops.
11
This is the input of the primary voltage check. The voltage at the anode of the primary
elcap has to be fed to this pin via a voltage divider. If the voltage of this pin falls below
1 V, the SMPS is switched off. A second function of this pin is the primary voltage dependent fold back point correction (only active in free running mode).
12
Common ground.
13
Output signal. This pin has to be connected across a serial resistor with the gate of the
power transistor.
14
Connection for supply voltage and startup capacitor. After startup the supply voltage is
produced by the control winding of the transformer and rectified by an external diode.
53
TDA16846 Block Diagrams

PVC
11
Fold Back Point Correction
R4
D4
SYN
R6x1/3
Primary
Voltage
Check
KSY
R7
5V
30k
R8
PVA
R6
OTC
G1
RZI
3.5V
ED2
CS1
R2
+
-
6
+
FC2
ErrorFlipflop
D2
Eror
Amplifier
REF
N.C.
G4
RSTC/RSTF
5V
VCC
+
-
3.5V
Off Time
Comparator
5V
1V
15k
75k
Control Voltage
Limit
1.5V
R3
D5
FC2
1.2V
R
D3
Buffer for
Control Voltage
4
SRC
OCI
+
+
-
R1
PCS
&
On Time
Comparator
20k
2
5V
Output
Driver
G3
G2
13
&
OUT
I1
ED1
Zero Crossing
Signal
1.5V
D1
Startup
Diode
VCC
GND
<25mV
14
12
16V
Supply Voltage
Comparator
Overvoltage
Comparator
+
-
+
-
15.8V
1) The input with the lower voltage becomes operative
54
FC1
1V
10
TDA7057AQ
2 x5 W stereo BTL Audio Output Amplifier with DC Volume Control
FEATURES
GENERAL DESCRIPTION
DC volume control
Few external components
Mute mode
Thermal protection
Short-circuit proof
No switch-on and switch-off clicks
Good overall stability
Low power consumption
Low HF radiation
ESD protected on all pins.
The TDA7057AQ is astereo BTL output amplifier with DC

volume control. The device is designed for use in TV and
monitors, but are also suitable for battery-fed portable
recorders and radios.
Missing Current Limiter (MCL)

A MCL protection circuit is built-in. The MCL circuit is
activated when the difference in current between the
output terminal of each amplifier exceeds 100 mA (typical
300 mA). This level of 100 mA allows for headphone
applications (single-ended).
QUICK REFERENCE DATA

SYMBOL
PARAMETER
VP
Pout
supply voltage
output power
Gv
voltage gain
GC
Iq(tot)
THD
gain control
total quiescent current
total harmonic current
CONDITIONS
Vp = 12 V; RL = 16
Vp = 12 V; RL = 8
Vp = 12 V; RL =
Pout=0.5w w
TYPE
TYP.
MAX.
UNIT
4.5
3.0
39.5
3.5
5.3
40.5
18
41.5
V
W
W
dB
68.0
73.5
22
0.3
25
1
dB
mA
%
PACKAGE
NUMBER
NAME
TDA7057AQ
DBS13P
SYMBOL
MIN.
PIN
DESCRIPTION
VERSION
Plastic DIL-bent-SIL power package; 13 leads (lead length 12 mm)

DESCRIPTION
VC1
DC volume contol 1
n.c.
VI (1)
VP
VI (2)
SGND
VC2
OUT2+
PGND2
OUT2OUT1PGND1
OUT1+
2
3
4
5
6
7
8
9
10
11
12
13
not connected
voltage input 1
positive supply voltage
voltage input 2
signal ground
DC volume contol 2
positeve output 2
power ground 2
negative output 2
negative output 1
powwer ground 1
positive output 1
vc1
n.c.
VI(1)
VP
VI(2)
SGND
VC2
OUT2
PGND2
OUT2
10
OUT1-
11
PGND1
12
OUT1+
13
SOT141-6
TDA7057AQ
Pin Configuration
55
handbook, full pagewidth

(1)
100 nF
220 F
V P = 12 V
TDA7053AQ
13
470 nF
input 1
I+ 1
(2)
1
R s = 5 k
I 1
11
TEMPERATURE
MCL
PROTECTION
STABILIZER
10
470 nF
input 2
R s = 5 k
I 1
5
7
(2)
I+ 1
DCvolume
signal
ground
12
power
ground
(1) This capacitor can be omittedFifelectrolytic

the 220
capacitor is connected close to pin 5.
(2) RL = 16 .
FUNCTIONAL DESCRIPTION
citors can be used which results in cost reductions.
The TDA7057AQ is a stereo output amplifiers with two

DC volume control stages. The device is designed for TV
and monitors, but also suitable for battery-fed portable recorders and radios.
In conventional DC volume control circuits the control or
input stage is AC coupled to the output stage via external
capacitors to keep the offset voltage low.
In the TDA7057AQ the two DC volume control stages are
integrated into the input stages so that no coupling capacitors are required and a low offset voltage is still maintained. The minimum supply voltage also remains low.
The BTL principle offers the following advantages:
Lower peak value of the supply current
The frequency of the ripple on the supply voltage is twice the signal frequency.
Consequently, a reduced power supply with smaller capa
For portable applications there is a trend to decrease the

supply voltage, resulting in a reduction of output power at
conventional output stages. Using the BTL principle increases the output power.
The maximum gain of the amplifier is fixed at 40.5 dB.
The DC volume control stages have a logarithmic control
characteristic. Therefore, the total gain can be controlled
from +40.5 dB to -33 dB. If the DC volume control voltage
falls below 0.4 V, the device will switch to the mute mode.
The amplifier is short-circuit protected to ground, Vp and
across the load. A thermal protection circuit is also implemented. If the crystal temperature rises above 150 oC the
gain will be reduced, thereby reducing the output power.
Special attention is given to switch-on and switch-off
clicks, low HF radiation and a good overall stability.
56
74HC4053B
pos:IA03
Analog Multiplexer/Demultiplexer
.
.
.
.
.
.
.
.
.
.
.
4053B
QUIESCE NT CURREN T SPECIFIED TO 20V

FOR HCC DEVICE
LOW ON RESISTANCE : 125 (typ.) OVER
15V p.p. SIGNAL-INPUT RANGE FOR VDD V EE = 15V
HIGH OFF RESISTANCE : CHANNEL LEAKAGE 100pA (typ.)DDV VEE = 18V
BINARY ADDRESS DECODING ON CHIP
VERY LOW QUIESCENT POWER DISSIPATION UNDER ALL DIGITAL CONTROL INPUT
AND SUPPLY CONDITIONS : 0.2 W (typ.),
V DD VSS = V DD VEE = 10V
MATCHED SWITCH CHARACTERISTICS :
R ON = 5 (typ.) for
VEE = 15V
DD V
WIDE RANGE OF DIGITAL AND ANALOG SIGNAL LEVELS : DIGITAL 3 TO 20V, ANALOG TO
20V p.p.
5V, 10V, AND 15V PARAMETRIC RATINGS
INPUT CURRENT OF 100mA AT 18V AND
25C FOR HCC DEVICE
100% TESTED FOR QUIESCENT CURRENT
MEETS ALL REQUIREMENTS OF JEDEC TENo
TATIVE STANDARD N
13A, STANDARD
SPECIFICATIONS FOR DESCRIPTION OF B
SERIES CMOS DEVICES
EY
F
(Plastic Package)(Ceramic Frit Seal Package)
M1
C1
(Micro Package) (Plastic Chip Carrier)
ORDER CODES :
HCC40XXBF
HCF40XXBM1
HCF40XXBEY
HCF40XXBC1
DESCRIPTION
TheHCC 4051B, 4052B and4053B (extended temperature range) and
HCF4051B, 4052B and4053B
(intermediate temperature range) are monolith
tegrated circuits, available in 16-lead dua
plastic or ceramic package and plastic microp
age. HCC/HCF4051B, HCC/HCF4052B, and
HCC/HCF4053B analog multiplexers/demult
plexers are digitally controlled analog switc
ing low ON impedance and very low OFF leakage
FUNCTIONAL DIAGRAMS AND TRUTH TABLES (continued)

4053
Inhibit
A or B
or C
ax or bx or cx
ay or by or cy
X = Dont care.
57
None
LM317
pos: IP02
1.2V TO 37V Voltage Regulator

GENERAL DESCRIPTION
FEATURES
The LM117 series of adjustable 3-terminal positive voltage regulators is capable of supplying in excess of 1.5A
over a 1.2V to 37V output range. They are exceptionally
easy to use and require only two external resistors to set
the output voltage. Further, both line and load regulation are better than standard fixed regulators. Also, the
LM117 is packaged in standard transistor packages
which are easily mounted and handled.
In addition to higher performance than fixed regulators,
the LM117 series offers full overload protection available only in ICs. Included on the chip are current limit,
thermal overload protection and safe area protection. All
overload protection circuitry remains fully functional
even if the adjustment termi-nal is disconnected.
Normally, no capacitors are needed unless the device is
situ-ated more than 6 inches from the input filter capacitors in which case an input bypass is needed. An optional output capacitor can be added to improve transient
response. The adjustment terminal can be bypassed to
achieve very high ripple rejection ratios which are difficult to achieve with stan-dard 3-terminal regulators.
Besides replacing fixed regulators, the LM117 is useful
in a wide variety of other applications. Since the regulator is floating and sees only the input-to-output differential voltage, supplies of several hundred volts can
be regulated as long as the maximum input to output differential is not ex-ceeded, i.e., avoid short-circuiting the
output. Also, it makes an especially simple adjustable
switching regulator, a programmable output regulator,
or by connecting a fixed resistor between the adjustment pin and output, the LM117 can be used as a precision current regulator. Sup-plies with electronic shutdown can be achieved by clamping the adjustment terminal to ground which programs the out-put to 1.2V
where most loads draw little current. For applications requiring greater output current, see LM150 series (3A)
and LM138 series (5A) data sheets. For the negative
complement, see LM137 series data sheet.
l
l
l
l
l
l
l
l
l
58
Guaranteed 1% output voltage tolerance (LM317A)

Guaranteed max. 0.01%/V line regulation (LM317A)
Guaranteed max. 0.3% load regulation (LM117)
Guaranteed 1.5A output current
Adjustable output down to 1.2V
Current limit constant with temperature
P + Product Enhancement tested
80 dB ripple rejection
Output is short-circuit protected
LM358
Dual Operational Amplifier
pos: I060
PIN CONNECTIONS
FEATURES
INTERNALLY FREQUENCY COMPENSATED
LARGE DC VOLTAGE GAIN : 100dB
WIDE BANDWIDTH (unity gain) : 1.1MHz (temperature
compen
sated)
VERY LOW SUPPLY CURRENT/OP (500mA) ESSENTIALLY INDEPENDENT OF SUPPLY VOLTAGE
LOW INPUT BIAS CURRENT : 20nA (temperature compensated)
LOW INPUT OFFSET VOLTAGE : 2mV
LOW INPUT OFFSET CURRENT : 2nA
INPUT COMMON-MODE VOLTAGE RANGE INCLUDES
GROUND
DIFFERENTIAL INPUT VOLTAGE RANGE EQUAL TO
THE POWER SUPPLY VOLTAGE
LARGE OUTPUT VOLTAGE SWING 0V TO (VCC
1.5V)
1
2
3
4
- Output 1
5 - Non-inverting input 2
- Inverting input 1 6 - Inverting input 2
- Non-inverting input7 1- Ouput 2
- CC
V8 - CC
V+
and all the conventional op-amp circuits, which now can be

more easily implemented in single power supply systems.
For example, these circuits can be directly supplied with
the standard + 5V, which is used in logic systems and will
easily, provide the required interface electronics without
requiring any additional power supply. In the linear mode
the input common-mode voltage range includes ground
and the output voltage can also swing to ground, even
DESCRIPTION
These circuits consist of two independent, high gain, internally frequency compensated which were designed specifically to operate from a single power supply over a wide
range of voltages. The low power supply drain is independent of the magnitude of the power supply voltage. Application areas include transducer amplifiers, dc gain blocks
LM7805
pos: IP03
3-Terminal 1A Positive Voltage Regulator
Features
Description
The MC78XX/LM78XX/MC78XXA series of three terminal positive regulators are available in the TO-220/DPAK package and with several fixed output voltages,
making them useful in a wide range of applications.
Each type employs internal current limiting, thermal
shutdown and safe operating are protection, making it
essentially indestructible. If adequate heat sinking is
provided, they can deliver over 1 A output current.
Although designed primarily as fixed voltage regulators,
these devices can be used with external components to
obtain adjustable voltages and currents.
Output Current up to 1A
Output Voltage of 5,6,8,9,10,12,15,18,24 V
Thermal Overload Protection
Short Circuit Protection
Output Transistor Safe Operating Area Protection
59
DESCRIPTION OF INTEGRATED CIRCUITS

-DVD PARTES6018
DVD PROCESSOR SOLUTION
DESCRIPTION
Built on ESSs proprietary and flexible Programmable Multimedia Processor architecture, the Vibratto TM series of
DVD processors combine audio/video stream data processing, system control and housekeeping functions, video postprocessing, and display format encoding, enabling various
DVD-based multimedia electronics to be built with minimal
external components. The Vibratto series includes new features for DVD-Audio support, progressive scan video output, and built-in TV encoder and video DACs.
All of the Vibratto DVD processors each include two parallel
processing units, a RISC processor, a vector engine, and
supplemental hardware resources for implementing specialized encoding and decoding tasks in the device architectures. All of these resources are interconnected with two
separate data buses, each with its own DMA unit and interface to external memory. The processing units enable
simultaneous parallel execution of system commands and
data processing.
Both the RISC processor and vector engine are independently programmable. Each has its own on-chip cache
memory. The RISC processor and its associated hardware
units perform bit stream parsing, control audio data output,
transfer video and audio data to the vector engine and service system control and housekeeping functions. The vector
engine and associated hardware units perform audio and
video microcode processing required by A/V standards such
as Dolby Digital TM, DTS TM, MPEG and JPEG. These
processing tasks include audio DSP, video motion compensation and estimation, loop filtering, discrete cosine transforms (DCT) and inverse DCT, quantization and inverse
quantization.
The Vibratto DVD processors support both JPEG/MP3
audio playback and the Kodak PictureCD JPEG display format. These new features allow Picture CDs created with
images and voiceovers from digital cameras to be enjoyed
in a DVD player or Home Theater System. All of the Vibratto DVD processors support both parallel and serial DVD
loader interfaces for system MPEG A/V data stream input,
industry standard-I 2 S bus for audio data input and output,
direct system EPROM and SDRAM access for high-speed
command fetching and audio/video data buffering and processing. The Vibratto DVD processors are available in 208pin Plastic Quad Flat Pack (PQFP) device packages.
FEATURES
60
Dedicated core and I/O power supplies for low-power

operation; integrated 32-bit RISC processor for system
host, eliminating requirements of an external host CPU
Supports DVD-Video, DVD-Audio, VideoCD 1.1, 2.0, and
3.0, Super VideoCD (SVCD), CD-DA, MP3, and Kodak
Picture-CD
Supports parallel and serial interfaces to ATAPI, Compact
Flash, DCI, IDE and UDF DVD loaders
Direct interface of 8- or 16-bit SDRAM of up to 128-Mb
capacity at a variety of speed grades
Direct interface of up to 4 banks of 8- or 16-bit EPROM or
Flash EPROM; automatic firmware updating of Flash
EPROM through DVD loader
Video
Built-in NTSC/PAL encoder includes field-adaptive de
interlacing for progressive scan video output for clearer
and more stable display (ES6028 and ES6038 Only)
Macrovision 7.1 and Macrovision AGC 1.03 compliant
video outputs for 480-pixel progressive scan and for
NTSC/PAL interlaced video
Four built-in 10-bit Video DACs provide simultaneous
video outputs of composite and S-video, or composite and
YUV; supports selectable 8-bit CCIR 601 4:2:2 YUV outputs
8-bit On-Screen Display (OSD) controller with 3-bit blending provides display with 256 colors in 8 degrees of transparency
On-chip Subpicture Unit (SPU) decoder supports karaoke
lyric, subtitles, and EIA-608 compliant Line 21 Captioning
Video error concealment, motion zoom and pan and
NTSC to PAL and PAL to NTSC conversion supported
Audio
Dolby Digital (AC-3), DVD-Audio, Pro Logic, DTS, MPEG1 layer 2 and 3 Audio (MP3), and High-Definition Compatible Digital.... (HDCD) decoding
On-chip Dolby Digital (AC-3) and DTS 5.1 channel decoding and output (ES6018/28/38 Only)
Dolby Digital and DTS S/PDIF digital audio output.
Dolby Digital Class A, DTS, and HDCD certified
Meridian Lossless Packing.... (MLP) decoding and Linear
PCM for DVD-Audio (ES6038 Only)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
VEE
HA2 /AUX4[4]
VEE
AUX[0]
AUX[1]
AUX[2]/IOW#
VSS
VEE
AUX[3]/IOR#
AUX[4]
AUX[5]
AUX[6]
AUX[7]
LOE#
VSS
VCC
LCS0#
LCS1#
LCS2#
LCS3#
VSS
LD0
LD1
LD2
LD3
LD4
VEE
VSS
LD5
LD6
LD7
LD8
LD9
LD10
LD11
VSS
VEE
LD12
LD13
LD14
LD15
LWRLL#
LWRHL#
VSS
VEE
CAMIN0
CAMIN1
LA0
LA1
LA2
LA3
VSS
VEE
LA4
LA5
LA6
LA7
LA8
LA9
VSS
VCC
LA10
LA11
LA12
LA13
LA14
LA15
LA16
VSS
VEE
LA17
LA18
LA19
LA20
LA21
RESET#
TDMDX/RSEL
VSS
VEE
TDMDR
TDMCLK
TDMFS
TDMTSC#
TWS/SEL_PLL2
TSD0/SEL_PLL0
VSS
VCC
TSD1/SEL_PLL1
TSD2
TSD3
MCLK
TBCK
SPDIF/PLL3
NC
VSS
VCC
RSD
RWS
RBCK
NC
XIN
XOUT
AVEE
VSS
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
VSS
HA1/AUX4[3]
HA0/AUX4[2]
HCS3FX#/AUX3[6]
HCS1FX#/AUX3[7]
HIOCS16#/CAMCLK/AUX3[4]
HRD#/DCI_ACK#/AUX4[6]
HWR#/DCI_CLK/AUX4[5]
VEE
VSS
HIORDY/AUX3[3]
HRST#/AUX3[5]
HIRQ/DCI_ERR#/AUX4[7]
HRRQ#/AUX4[0]
HWRQ#/DCI_REQ#/AUX4[1]
HD15/AUX2[7]/IR
HD14/AUX2[6]/SQSI
VCC
VSS
HD13/AUX2[5]/SP
HD12/AUX2[4]/C2PO
HD11/AUX2[3]//IRQ
HD10/AUX2[2]/SQSK
HD9/AUX2[1]/SQSO
HD8/DCI_FDS#/AUX2[0]/VFD_CLk
HD7/DCI7/AUX1[7]/VFD_DIN
VEE
VSS
HD6/DCI6/AUX1[6]/VFD_DOUT
HD5/DCI5/AUX1[5]
HD4/DCI4/AUX1[4]
HD3/DCI3/AUX1[3]
HD2/DCI2/AUX1[2]
HD1/DCI1/AUX1[1]
HD0/DCI0/AUX1[0]
VCC
VSS
HSYNC#/CAMIN7/AUX3[0]
VSYNC#/CAMIN6/AUX3[1]
PCLKQSCN/CAMIN5/AUX3[2]
PCLK2XSCN/CAMIN4
YUV7/CAMIN3
YUV6/VDAC
YUV5/YDAC
VSS
ADVEE
YUV4/RSET
YUV3/COMP
YUV2/CDAC
YUV1/VREF
YUV0/CAMIN2/UDAC
DCLK
SYSTEM BLOCK DIAGRAM
ROM/Flash
Video
8 MB
SDRAM
Audio
Vibratto
DVD drive
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
61
TV
5.1 Audio
DAC
Audio S/PDIF Out

or DTS
ES6008/18/28/38
208-Pin PQFP Package
Speakers or
A/V Receiver
EEPROM
VFD
Driver
VFD Panel
ATAPI
TVM
Compact FlashUDE
VSTEM
DCI
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
VEE
VSS
DSCK
DQM
DCS0#
VEE
VSS
DCS1#
DB15
DB14
DB13
DB12
VEE
VSS
DB11
DB10
DB9
DB8
DB7
DB6
VSS
VCC
DB5
DB4
DB3
DB2
DB1
DB0
VSS
VEE
DMBS1
DMBS0
DRAS#
DWE#
DOE#/DSCK_EN
DCAS#
VEE
VSS
DMA11
DMA10
DMA9
DMA8
DMA7
DMA6
VSS
VEE
DMA5
DMA4
DMA3
DMA2
DMA1
DMA0
ES60X8 PIN DESCRIPTION
Table 1
Name
ES60x8 Pin Description

Number
I/O
Definition
VEE
1,18, 27, 59, 68,I

75, 92, 99, 104,
130, 148, 157,
159, 164, 183,
193, 201
I/O power supply.
VSS
8, 17, 26, 34, 43,

I
52, 60, 67, 76,
84, 91, 98, 103,
112, 120, 129,
138, 147, 156,
163, 171, 177,
184, 192, 200,
208
Ground.
LA[21:0]
VCC
RESET#
23:19, 16:10,O
7:2, 207:204
9, 35, 44, 83, I
121, 139, 172
24
Device address output.

Core power supply.
Reset input, active low.
TDMDX
TDM transmit data.
RSEL
ROM Select.
25
RSEL
0
1
Selection
16-bit ROM
8-bit ROM
TDMDR
28
TDM receive data.
TDMCLK
29
TDM clock input.
TDMFS
30
TDM frame sync.
TDMTSC#
31
TDM output enable.
TWS
Audio transmit frame sync.
SEL_PLL2
System and DSCK output clock frequency selection is made at the

RESET#. The matrix below lists the available clock frequencies an
PLL bit settings.
32
TSD0
SEL_PLL0
O
33
TSD1
SEL_PLL1
I
O
36
SEL_PLL2
SEL_PLL1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
SEL_PLL0 Clock Type

0
1
0
1
0
1
0
1
VCO off.
DCLK
Bypass mode
DCLK x 2
DCLK x 4.5
DCLK x 3
DCLK x 3.5z
DCLK x 4
Audio transmit serial data port 0.

Refer to the description and matrix for SEL_PLL2 pin 32.
Audio transmit serial data port 1.
Refer to the description and matrix for SEL_PLL2 pin 32.
TSD[2]
37
Audio transmit serial data output 2.
TSD[3]
38
Audio transmit serial data output 3.
62
Table 1
Name
ES60x8 Pin Description (Continued)

I/O
Definition
MCLK
Number
39
I/O
Audio master clock for audio DAC.
TBCK
40
Audio transmit bit clock.
S/PDIF output.
SPDIF
SEL_PLL3
Clock source select.
41
SEL_PLL3
0
1
NC
42, 48
Clock Source
Crystal oscillator
DCLK input
No connect pins. Leave open.
RSD
45
Audio receive serial data.
RWS
46
Audio receive frame sync.
RBCK
47
Audio receive bit clock.
XIN
XOUT
AVEE
DMA[11:0]
49
50
Crystal input.
51
Crystal output.
Analog power for PLL.
66:61, 58:53
DRAM address bus [11:0].
DCAS#
69
DRAM column address strobe.
DOE#
70
DRAM output enable.
DSCK_EN
DWE#
71
DRAM clock enable.
DRAM write enable.
DRAS#
72
DRAM row address strobe.
DMBS0
73
SDRAM bank select 0.
74
SDRAM bank select 1.
DMBS1
DB[15:0]
DCS[1:0]#
96:93, 90:85,I/O
82:77
97,100
DRAM data bus [15:0].

SDRAM chip select [1:0].
DQM
101
Data input/output mask.
DSCK
102
Output clock to SDRAM.
DCLK
105
YUV0
I
O
CAMIN2
UDAC
27 MHz clock input to PLL.

YUV0 pixel output data.
Camera input 2.
Video DAC output.
106
Y:
C:
U:
V:
Mode
YDAC
A
B
C
D
Y
Y
Y
Y
UDAC
VDAC
C
Composite
Composite Composite
U
Composite
U
C
CDAC
C
C
V
V
Luma component for YUV and Y/C processing.

Chrominance signal for Y/C processing.
Chrominance component signal for YUV mode.
Chrominance component signal for YUV mode.
63
Table 1
ES60x8 Pin Description (Continued)
Name
Number
I/O
Definition
YUV1
107
VREF
YUV2
CDAC
108
YUV3
109
COMP
YUV4
Internal voltage reference to video DAC. Bypass toFground

capacitor.
with
110
RSET
Video DAC output. Refer to description and matrix for UDAC pin 1
Compensation input. Bypass to ADVEE with

F capacitor.
0.1
DAC current adjustment resistor input.
ADVEE
111
YUV5
113
YDAC
YUV6
114
VDAC
YUV7
115
CAMIN3
PCLK2XSCN
I
I/O
117
Camera YUV 4.
13.5-MHz video output pixel clock.
Camera YUV 5.
118
I/O
119
I/O
CAMIN6
HSYNC#
Camera YUV 6.
HD[5:0]
I/O
127:122
AUX1[5:0]
HD[6]
I/O
DVD channel data I/O [5:0].

Aux1 data I/O [5:0].
I/O
VFD_DOUT
HD[7]
I/O
DCI[7]
AUX1[7]
VFD_DIN
Host data I/O [6].

DVD channel data I/O [6].
Aux1 data I/O [6].
VFD data output.
I/O
131
Host data I/O [5:0].
I/O
I/O
128
Horizontal sync, active low.

Camera YUV 7.
I/O
DCI[6]
AUX1[6]
Vertical sync, active low.
CAMIN7
DCI[5:0]
27-MHz video output pixel clock.
CAMIN5
VSYNC#
Camera YUV 3.
116
CAMIN4
PCLKQSCN
Analog power for video DAC.
I/O
I
Host data I/O [7].

DVD channel data I/O [7].
Aux1 data I/O [7:0].
VFD data input.
HD[8]
I/O
Host data bus 8.
DCI_FDS#
I/O
DVD input sector start.
AUX2[0]
132
VFD_CLK
HD[9]
AUX2[1]
I/O
I
I/O
133
I/O
SQSQ
HD[10]
I/O
AUX2[2]
SQSK
134
I/O
I
Aux2 data I/O 0.

VFD clock input.
Host data bus line 9.
Aux2 data I/O [1] when selected.
Subcode-Q data.
Host data bus line10.
Aux2 data I/O [2] when selected.
Subcode-Q clock.
64

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SERVICE MANUAL

PT 90 NEAT Service Manual

5. I-C Bus Interconnection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

9. DVD Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

10. Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

PT 90 NEAT Service Manual

CRT drive module must be grounded via mass

Turn off TV and plug the mains out

Please follow the assembly instructions

PT 90 NEAT Service Manual

1. TECHNICAL SPECIFICATIONS, CONNECTIONS AND

PT 90 NEAT Service Manual

PT 90 NEAT Service Manual

14 NEAT CTV 001

14 NEAT CTV 002

1- FRONT CABINET 002

1- FRONT CABINET 002

PT 90 NEAT Service Manual

2. SAFETY INSTRUCTIONS AND WARNINGS

laser beam is highly dangerous and it may cause permanent damages.

HANDLING THE MOS CHIP COMPONENTS

X-RAY RADIATION PRECAUTION

PT 90 NEAT Service Manual

PT 90 NEAT Service Manual

4. SUPPLY VOLTAGE DIAGRAM

PT 90 NEAT Service Manual

5. I2 BUS INTERCONNECTION DIAGRAM

PT 90 NEAT Service Manual

6. FAULT TRACING DIAGRAM-POWER SUPPLY

PT 90 NEAT Service Manual

PT 90 NEAT Service Manual

SERVICE MENU AND BASIC ADJUSTMENTS

1: AV2 mode available

VIDEO/AUDIO FEATURE CONFIGURATION

1: One Crystal application (4.43 Mhz)

Reserved bits must be set to 0

PT 90 NEAT Service Manual

8.2 GEOMETRY ADJUSTMENT

Enter service menu and select the GEOMETRY settings

increase normal decrease

Apply Dark gray pattern (at 10 IRE)

PT 90 NEAT Service Manual

PIF adjustment for BG/DK/L systems:

8.6 HOTEL MODE

8.7 SYSTEM VOLTAGE ADJUSTMENT

PT 90 NEAT Service Manual

Applicable Discs Format

PT 90 NEAT Service Manual

Phase difference detection

Disc Loading Mode

PT 90 NEAT Service Manual

9.2 MECHANICAL AND ELECTRICAL

Driver Chip Select 0

Driver Chip Select 1

Driver Address Bus-Bit 0

Driver Address Bus-Bit 1

PT 90 NEAT Service Manual

Driver Address Bus-Bit 2

Driver Activity/Driver I Present

Driver Data Bus-bit 0

Driver Data Bus-bit 1

Driver Data Bus-bit 2

Driver Data Bus-bit 3