1.2.

H thng OFDM

H thng ofdm bao gm b: scrambler / descrambler, reed-solomon encoder / decoder,

convolutional encoder / decoder, interleaver / de-interleaver, constellation mapper / demapper, inverse fast fourier transform / fast fourier transform, addition / removal of
cyclic prefix.
D liu sau khi qua b trn c a qua b m ha knh.y l khi c nhim v sa
li bit trong qu trnh truyn d liu.b m ha sa sai c s dng l convolutional
encoder v , reed-solomon encoder. sau d liu c a vo khi an xen gip phn
tn d liu trnh trng hp li cm u thu Sau , cc bit d liu c chuyn tun
t vo khi nh x chm sao (constellation mapper). Php iu bin c s dng l
QPSK theo m Gray.,t y d liu c a qua b fast fourier transform nhm t
c tnh trc giao ca sng mang tn hiu trc khi truyn i c chn thm tin t lp
vng pha u thu thc hin qu trnh ngc li nhm ly thng tin ban u.
1.2.1 SCRAMBLER / DESCRAMBLER.

Bit d liu c a vo b scrambler,chui bit sau khi qua b ny s tr thnh chui

bit ngu nhin. iu ny c thc hin lm cho cc chui u vo phn tn nhiu
hn nh vy m ph cng sut ca tn hiu u vo trn thc t trong qu trnh truyn d
liu c th c loi b [ 2 ] .
Ti u thu De-scrambler ch n gin l khi phc d liu bit t d liu b scrambler.
1.2.2 REED-SOLOMON ENCODER / DECODER
D liu sau khi qua b trn s i vo b m ha reed-solomon, reed-solomon l mt
phn ca FEC. N l 1 k thut m ha sa sai.d liu u vo c ly mu v bit parity
c tnh ton v thm vo on d liu gc[3].m reed-solomon c m t bng
RS(n,k) vi
N=2m-1
K=2m-1-2t
y m l s bit m ha 1 symbol,k l s symbol d liu u vo b m ha, n l
tng s symbol(data+ parity) trong t m RS v t l s symbol ln nht c th sa
cha.ti u thu symbol reed Solomon c khi phc bng cch loi b parity.
1.2.3. CONVOLUTIONAL ENCODER / DECODER
D liu sau khi m ha Reed-solomon tip tc i vo b m chp (convolutional).y
l loi m.trong k thut ny mi m bit symbol c chuyn i thnh n bit symbol;m/n
c gi l t l m. S bin i m bit symbol ny thnh n bit symbol ph thuc vo k
symbol k c gi l di hn ch(constraint length) ca m chp[4].
Thut ton Viterbi c s dng cho gii m ti pha thu vi k<10.
1.2.4. INTERLEAVER / DE-INTERLEAVER
an xen c thc hin nhm bo v d liu trnh trng hp li khi(burst errors) trong
qu trnh pht.v mt khi nim khi bit ti c sp xp li cc bit lin k tch xa
nhau ,phn tn bit.d liu c chia thnh cc khi v cc bit trong 1 khi c ti sp
xp li[5].
Ti pha thu n li sp xp li nh ban u ca khi d liu.
1.2.5. CONSTELLATION MAPPER / DE-MAPPER
Qu trnh nh x chm sao v c bn l qu trnh nh x hay sp xp d liu vo sng
mang ph(sub-carriers).c nhiu k thut iu ch c th s dng

( QPSK,QAM,BPSK) Cho sng mang ph. d liu c trch xut t symbol iu ch

ti my thu.
1.2.6. INVERSE FAST FOURIER TRANSFORM / FAST FOURIER TRANSFORM
y l khi quan trng nht trong h thng OFDM.n s dng k thut IFFT v c bn
n s to ra cc sng mang con trc giao.IFFT bin i ph(bin v pha )ca mi
thnh phn tn hiu trong min thi gian.n chuyn i d liu l im s phc thnh d
liu trong min thi.Tng t nh vy,FFT c nhim v ngc li chuyn d liu t
min thi gian v min tn s.
1.2.7. ADDITION / REMOVAL OF CYCLIC PREFIX.
Nhm m bo tnh trc giao v c lp ca sng mang trong OFDM.mt khong bo
v c thm vo. di ca khong bo v ph thuc vo s lng mu trong OFDM
1.4.2 ng dng.
Do kh nng ti cu trc n gin v s hu mt khi ti nguyn logic ln FPGA c th
c ng dng cho nhiu cc lp bi ton x l tn hiu s c ln m cc cng ngh
trc khng lm c hoc lm c nhng vi tc v hiu sut thp. Cc lp ng
dng l:
- Cc ng dng chung v x l s nh lc tn hiu, tm kim, phn tch, gii m, iu ch
tn hiu, trn tn hiu
- Cc ng dng v m ha, gii m ging ni, nhn dng ging ni, tng hp ging ni.
X l tn hiu m thanh bao gm lc nhiu , trn, m ha, gii m, nn, tng hp m
thanh
-ng dng trong x l nh s, nn v gii nn, cc thao tc bin i, chnh sa, nhn
dng nh s
- ng dng trong cc h thng bo mt thng tin, cung cp cc khi gii m v m ha
c th thc thi vi tc rt cao v d dng tham s ha hoc iu chnh.
- ng dng trong cc h thng thng tin nh cc h thng Voice IP, Voice mail. Modem,
in thoi di ng, m ha v gii m truyn thng trong mng LAN, WIFI trong
truyn hnh KTS, radio KTS
- ng dng trong iu khin cc thit b in t: cng, my in, my cng nghip , dn
ng, nh v, robots.
Ngoi ra cn rt nhiu ng dng khc.

1.4.3 Ngn ng v mi trng lp trnh cho FPGA

Thit k trn FPGA thng c thc hin bi cc ngn ng HDL v hu ht cc dng
FPGA hin ti h tr thit k theo hai ngn ng chnh l Verilog v VHDL, tt c nhng
thit k trong ti ny u c thc ha trn FPGA bng mt quy trnh n gin.
Ngoi HDL, thit k trn FPGA cn c th c thc hin thng qua h nhng ngha l
bng ngn ng phn mm (thng l C/C++). Mt phng php na thng dng trong
cc bi ton x l s tn hiu l s dng System Generator mt chng trnh kt hp ca
Matlab vi phn mm thit k FPGA ca Xilinx. Hin nay cng ngh FPGA ang c
pht trin rng ri bi nhiu cng ty bn dn khc nhau. Dn u l Xilinx vi cc dng
sn phm nh Virtex 3, 4, 5, 6 v Spartan3, 6, Altera vi Stratix, Cyclone, Arria, Bn
cnh cn c sn phm ca Lattice Semiconductor Company, Actel, Achronix, Blue
Silicon Technology
1.4.4 Ngn ng verilog.
Verilog c ra i vo u nm 1984 bi Gateway Design Automation. Khi u, ngn
ng u tin c dng nh l mt cng c m phng v kim tra. Sau thi gian u
ngn ng ny c chp nhn bi ngnh cng nghip in t, mt cng c m phng,
mt cng c phn tch thi gian, v sau ny vo nm 1987, cng c tng hp c xy
dng v pht trin da vo ngn ng ny. Gateway Design Automation v nhng cng c
da trn Verilog ca hng sau ny c mua bi Cadence DesignSystem. T sau ,
Cadence ng vai tr ht sc quan trng trong vic pht trin cng nh ph bin ngn
ng m t phn cng Verilog.Vo nm 1987, VHDL tr thnh mt chun ngn ng m t
phn cng ca IEEE. Bi do s h tr ca B quc phng (DoD), VHDL c s dng
nhiu trong nhng d n ln ca chnh ph M. Trong n lc ph bin Verilog, vo nm
1990, OVI ( Open Verilog International) c thnh lp v Verilog chim u th trong
lnh vc cng nghip. iu ny to ra mt s quan tm kh ln t ngi dng v cc
nh cung cp EDA ti Verilog.

1.3. Gii thiu phn mm Quartus 12.1

Quartus II l cng c phn mm pht trin ca hng Altera, cung cp mi trng

thit k ton din cho cc thit k SOPC (h thng trn 1 chip kh trnh - system on a
programmable chip). y l phn mm ng gi tch hp y phc v cho thit k
logic vi cc linh kin logic kh trnh PLD, FPGA ca Altera, gm cc dng APEX,
Cyclone, FLEX, MAX, Stratix...Quatus ii cung cp cc kh nng thit k sau:
Mi trng thit k gm cc bn v, s khi, cng c son tho cc ngn
ng: AHDL, VHDL, v Verilog HDL.
Thit k LogicLock.
L cng c mnh tng hp logic.
Kh nng m phng chc nng v thi gian.
Phn tch thi gian.
Phn tch logic nhng vi cng c phn tch SignalTap II.
Cho php xut, to v kt ni cc file ngun to ra cc file chng trnh.
T ng nh v li.
Kh nng lp trnh v nhn din linh kin.
Phn mm uartus II s dng b tch hp NativeLink vi cc cng c thit
k cung cp vic truyn thng tin lin mch gia Quartus vi cc cng c thit k
phn cng EDA khc.
Quartus II cng c th c cc file mch (netlist) EDIF chun, VHDL v
Verilog HDL cng nh to ra cc file netlist ny.
Quartus II c mi trng thit k ha gip nh thit k d dng vit m,
bin dch, sot li, m phng...
Vi Quartus c th kt hp nhiu kiu file trong 1 d n thit k phn cp. C th
dng b cng c to s khi (Quartus Block Editor) to ra s khi m t
thit k mc cao, sau dng cc s khi khc, cc bn v nh: AHDL Text
Design Files (.tdf). EDIF Input Files (.edfh VHDL Design Files (.vhd). and Verilog HDL
Design Files to ra thnh phn thit k mc thp.Quartus II cho php lm vic vi
nhiu file cng thi im, son tho file thit k trong khi vn c th bin dch hay chy
m phng cc d n khc. Cng c bin dchQuartus II nm trung tm h thng, cung
cp quy trnh thit k mnh cho php ty bin t c thit k ti u trong d n.
Cng c nh v li t ng v cc bn tin cnh bo khin vic pht hin v sa li tr
nn n gin hn. Sau khi ci Quartus II, giao din nh hnh v:

1.4. Gii thiu v FPGA.

1.4.1 khi nim.

FPGA l cng ngh vi mch tch hp kh trnh (PLD Programmable Logic Device)
trnh mi nht v tin tin nht hin nay. Thut ng Field Programmable Get Array ch
qu trnh ti cu trc IC c th c thc hin bi ngi dng cui, trong iu kin thng
thng thng, hay ni mt cch khc l ngi k s lp trnh IC c th d dng hin
thc ha thit k ca mnh s dng FPGA m khng l thuc vo mt quy trnh sn xut
hay cu trc phn cng phc tp no trong nh my bn dn.
Vi mch FPGA c cu thnh t cc b phn:
-cc khi logic c bn c th lp trnh c(logic block).
-h thng mch lin kt lp trnh c.
-khi vo/ra(I/O pads).
-phn t thit k khc nh DSP slide,RAM.ROM,nhn vi s l..

FPGA ra i hon ton l mt cng ngh mi ch khng phi l mt dng m rng

ca cc chip kh trnh kiu nh PAL,PLA... S khc bit th nht nm c ch ti cu
trc FPGA, ton b cu hnh ca FPGA thng c lu trong mt b nh truy cp ngu

nhin (thng thng SRAM), qu trnh ti cu trc c thc hin bng cch c thng
tin t RAM lp trnh li cc kt ni v chc nng logic trong IC. C th so snh c ch
lm vic ging nh phn mm my tnh cng c lu tr trong RAM v khi thc thi
s c np ln lt vi x l, ni cch khc vic lp trnh li cho FPGA cng d dng
nh
lp
trnh
li
phn
mm
trn
my
tnh.
Nh vy v mt nguyn tc th qu trnh khi ng ca FPGA khng din ra tc th m
cu hnh t SRAM phi c c trc sau mi din ra qu trnh ti cu trc theo ni
dung thng tin cha trong SRAM. D liu cha trong b nh RAM ph thuc vo ngun
cp, chnh v vy lu gi cu hnh cho FPGA thng phi dng thm mt ROM ngoi
vi. n nhng dng sn phm FPGA gn y th FPGA c thit k c th giao tip
vi rt nhiu dng ROM khc nhau hoc FPGA thng c thit k km CPLD np
nhng thnh phn c nh, vic tch hp ny lm FPGA np cu hnh nhanh hn nhng
c ch np v lu tr cu hnh vn khng thay i. Ngoi kh nng im th hai lm
FPGA khc bit vi cc PLD th h trc l FPGA c kh nng tch hp logic vi mt
cao vi s cng logic tng ng ln ti hng trm nghn, hng triu cng. Kh nng
c c nh s t ph trong kin trc ca FPGA.