1 2 3 4 5 6

S2ELC REV1
A A

B B

C C

D D

BOARD NAME : SPARTAN-IIE DEVELOPMENT BOARD

BOARD PART NUMBER : DS-BD-S2ELC
BOARD REVISION : 1
E E

SPARTAN-IIE DEVELOPMENT BOARD

TITLE PAGE

<OrgName> Last Modified

Sunday, January 26, 2003
<OrgAddr1> Size Rev
<OrgAddr2> C 1
<OrgAddr3> Designer Sheet
<OrgAddr4> JBE 1 of 8
1 2 3 4 5 6
 10 9 8 7 6 5 4 3 2 1

VOLTAGE INPUT JACK REGULATION LED GROUND TEST LOOPS

5VJACK

H 5V TP5 H

VIN
JP1 SW1
1
1
2
2

(5V)
Barrel Jack SMT + C84
3 330u
+ C56 6.3
5VJACK SPDT Slide 6A 330u

5V

FEET

G 3.3V NE1 Little Rubber Feet -Thick G

5V

U1 TPS75733KTT NE2 Little Rubber Feet -Thick

R1
1
EN 330 NE3 Little Rubber Feet -Thick
2
IN
3 3A 6
GND HS

3.3V
4
C1 OUTPUT NE4 Little Rubber Feet -Thick
5
2.2u FB/PG DS1
+ C2 GREEN
330u
LABEL = 3.3V

MOUNTING HOLES
F 3.3V F
NE6 Mounting Hole (.125)
2.5V
5V NE7 Mounting Hole (.125)

U2 TPS75725KTT
NE8 Mounting Hole (.125)
R2
1
2 EN 330
IN NE9 Mounting Hole (.125)
3 3A 6
GND HS

2.5V
4
C3 OUTPUT
5
2.2u FB/PG DS2
+ C4 GREEN NE5 Mounting Hole (.100)
330u
LABEL = 2.5V
E E

2.5V

3.3V

R3
330

D 5V DS3 D
GREEN
U3 TPS75718KTT
LABEL = 1.8V
1 3
2 EN Q1
IN

1.8V
3 3A 6
GND HS
4
C5 OUTPUT
5
2.2u FB/PG
R1
+ C6 1.8V 1
330u

R2

BCR133
C 1.8V 2 C

B B

SPARTAN-IIE DEVELOPMENT BOARD

A A
POWER

MemecBoard Last Modified

Sunday, January 26, 2003
<OrgAddr1> Size Rev
<OrgAddr2> C 1
<OrgAddr3> Designer Sheet
<OrgAddr4> Jim Elliott 2 of 8
10 9 8 7 6 5 4 3 2 1
 10 9 8 7 6 5 4 3 2 1

BANK 0 - P160 LEFT HEADER & RIGHT HEADER BANK 1 - P160 RIGHT HEADER BANK 2 - SAM BANK 3 - GPIO (3.3V ONLY)

VBANK0 VBANK1 VBANK2 3.3V

3.3V

H H

G10

G13
G14

G17
H17

R17

N16
K16

P16
F15
F16

T17
J16
G9
R4

F8
F7
U4A
Bank 0 U4B
Bank 1 U4C
Bank 2 330 U4D
Bank 3
2S300E 2S300E 2S300E 1% 2S300E

VCCO_0
VCCO_0
VCCO_0
VCCO_0

VCCO_1
VCCO_1
VCCO_1
VCCO_1

VCCO_2
VCCO_2
VCCO_2
VCCO_2

VCCO_3
VCCO_3
VCCO_3
VCCO_3
RIO.A8 B11 C8 RIO.A10 SM.CS B20 F14 RIO.A23 SAM.D08 L21 INITn W21 R18
D11 IO_LVDS_DLL_L13N IO_L6P_Y D8 A20
IO_CS_L28P_YY IO
D15 L20
IO_IRDY_L44N_YY
Y22
IO_INIT_L59N_YY
IO_VREF_3_L52N_Y
R19
RIO.A15 IO IO_VREF_0_L6N_Y RIO.A9 SM.WRITE IO_VREF_1_L21P_Y
IO_WRITE_L28N_YY RIO.A34 SAM.IRQ IO_L44P_YY SM.D7 IO_D7_L59P_YY IO_D6_L52P_Y SM.D6
F11 A7 D18 C15 L19 G22 W22 P22
RIO.A17 IO IO RIO.A1 RIO.A40 IO IO_L21N_Y RIO.A33 SAM.RESETn IO IO SAM.D00 GPIO26 IO IO_D5_L51N_YY SM.D5
RIO.A7 A10 B7 LIO.B8 RIO.A39 C18 B15 RIO.B24 SAM.CEn L18 F22 SAM.A02 GPIO25 V21 P21 GPIO17
IO_L12P_Y IO IO IO_L20P_Y IO_L43N_Y IO IO IO_L51P_YY
RIO.A6 B10 C7 LIO.A9 RIO.B40 B19 A15 RIO.B22 SAM.BRDY L17 GPIO11 V19 P20 GPIO3
E11 IO_L12N_Y IO_L5P D7 A19
IO_L27P_Y IO_L20N_Y
E14 K22
IO_L43P_Y
G21 V20
IO_L58N_Y IO P18
RIO.A16 IO IO_L5N LIO.A11 RIO.B38 IO_L27N_Y IO RIO.A22 SAM.D06 IO_L42N_Y IO_L35N SAM.D01 GPIO10 IO_L58P_Y IO_L50N_Y
RIO.A14 C10 E8 RIO.B2 RIO.B36 B18 D14 RIO.A32 SAM.D07 K21 G20 SAM.D14 GPIO24 V22 P19 GPIO4
D10 IO_L11P_Y IO_L4P E7 A18
IO_VREF_1_L26P_Y IO_L19P_Y
C14 K20
IO_L42P_Y IO_L35P
G19 U22
IO_VREF_3_L57N_Y IO_L50P_Y
RIO.A13 IO_VREF_0_L11N_Y IO_L4N RIO.B34 IO_L26N_Y IO_L19N_Y RIO.A31 SAM.A06 IO IO_L34N_Y SAM.D15 GPIO22 IO_L57P_Y
G18 N22 GPIO15
IO_L34P_Y IO_L49N_Y
RIO.B8 F10 A6 LIO.B9 RIO.A38 D17 B14 RIO.B20 SM.D3 K19 E22 SAM.A00 GPIO23 U21 N21 GPIO16
IO IO_L3P_YY IO IO_L18P_Y IO_D3 IO_L33N_Y IO IO_L49P_Y
G RIO.A5 A9
IO_L10P IO_VREF_0_L3N_YY
B6 LIO.B10 RIO.A37 C17
IO IO_L18N_Y
A14 RIO.B18 K18
IO_VREF_2_L41N
IO_VREF_2_L33P_Y
F21 SAM.A03 GPIO8 U20
IO IO
P17 G
RIO.A4 B9 C6 LIO.A13 RIO.B32 B17 E13 RIO.A20 K17 E21 SAM.A01 U18 N19 GPIO2
E10 IO_L10N IO
A5 A17
IO_L25P_YY IO
D13 J22
IO_L41P IO
F20 U19
IO_L56N_Y IO_L48N_YY
N20
RIO.B6 IO IO_L2P LIO.B11 RIO.B30 IO_L25N_YY IO_L17P_Y RIO.A30 SAM.D04 IO_L40N_Y IO_L32N_Y SAM.D12 GPIO9 IO_L56P_Y IO_L48P_YY GPIO1
RIO.A12 C9 B5 LIO.B12 RIO.A25 E16 C13 RIO.A29 SAM.D05 J21 F19 SAM.D13 GPIO21 T21 N18
IO_L9P IO_L2N IO_VREF_1_L24P_YY IO_L17N_Y IO_L40P_Y IO_L32P_Y IO_VREF_3_L55N_Y
IO_VREF_3_L47N_Y
RIO.A11 D9 D6 LIO.A15 RIO.A26 E17 B13 RIO.B16 SAM.A04 J20 F18 GPIO20 T22 N17 SM.D4
IO_L9N IO IO_L24N_YY IO_VREF_1_L16P_Y IO_L39N_Y IO IO_L55P_Y IO_D4_L47P_Y
F9 B4 E15 A13 J19 T20 M22
IO_L8P IO_L1P_Y LIO.B14 RIO.A24 IO IO_L16N_Y RIO.B14 SAM.A05 IO_L39P_Y GPIO6 IO IO GPIO13
RIO.B4 E9 C5 LIO.A17 F13 RIO.A21 SAM.D02 H22 D22 SAM.OEn
IO_L8N IO_VREF_0_L1N_Y IO IO IO_L31N_Y
RIO.A36 D16 D21 SAM.WEn T18 M20
IO_L23P_Y IO_VREF_2_L31P_Y IO_L54N_Y IO_L46N_Y
RIO.A3 A8 A4 LIO.B13 RIO.A35 C16 C12 RIO.A27 J18 E20 SAM.D10 GPIO7 T19 M21 GPIO14
IO_L7P_Y IO IO_L23N_Y IO_L15P_Y IO_L38N_Y IO_L30N_Y IO_L54P_Y IO_L46P_Y
B8 A3 B16 B12 J17 E19 R21 M18
RIO.A2 IO_L7N_Y IO_L0P LIO.B15 RIO.B28 IO_L22P_Y IO_L15N_Y RIO.B12 IO_L38P_Y IO_L30P_Y SAM.D11 GPIO19 IO_L53N_Y IO_L45N_Y
B3 LIO.B16 RIO.B26 A16 D12 RIO.A28 SAM.D03 H21 D20 SAM.D09 GPIO18 R22 M19
IO_L0N C4
IO_L22N_Y IO_L14P_Y
E12 H20
IO_L37N_Y IO
C22 R20
IO_L53P_Y IO_L45P_Y
M17
IO LIO.A21 IO_L14N_Y RIO.A18 SM.D2 IO_D2_L37P_YIO_DIN_D0_L29N_YY SM.D0 GPIO5 IO IO
CLK.GCK3 C11 D5 LIO.A19 F12 RIO.A19 SM.D1 H19 C21 SM.BUSY L22 GPIO12
GCK3 IO IO IO_D1_L36N_Y
IO_DOUT_BUSY_L29P_YY IO_TRDY
39 IO CLK.GCK2 A11 A12 RIO.B10 H18
GCK2 IO_LVDS_DLL_L13P IO_VREF_2_L36P_Y
39 IO 1 CLOCK 36 IO 36 IO
1 CLOCK 2 SM 5 SM 5 SM

BANK 4 - MEMORY B BANK 5 - MEMORY A BANK 6 - USER IO (RS232, VGA, PUSH, LED, SSD, LCD) BANK 7 - P160 LEFT HEADER & USER IO (DIP)
F F
2.5V 2.5V 3.3V VBANK7
U15
U16
T13
T14

T10

G6
U8
U7

R6

N7

H6
P7

K7
T9

T6

J7
U4E
Bank 4 U4F
Bank 5 U4G
Bank 6 U4H
Bank 7
2S300E 2S300E 2S300E 2S300E
VCCO_4
VCCO_4
VCCO_4
VCCO_4

VCCO_5
VCCO_5
VCCO_5
VCCO_5

VCCO_6
VCCO_6
VCCO_6
VCCO_6

VCCO_7
VCCO_7
VCCO_7
VCCO_7
MEM.BA0 Y12 W15 MEM.CSn MEM.D12 AA3 Y8 MEM.A07 M1 R4 VGA.BLUE0 LIO.B17 D3 H2 DIP1
IO_LVDS_DLL_L75P IO_L67N_Y IO_L89N_Y IO IO_TRDY IO IO IO_L112P_YY
W12 V15 AB3 V8 M2 R5 C2 H1
MEM.A06 IO IO_VREF_4_L67P_Y MEM.D14 IO_L89P_Y IO_VREF_5_L82N_Y IO IO LIO.B31 IO IO_L112N_YY DIP2
V12 AB16 MEM.D27 MEM.D15 AB4 W8 MEM.A12 FPGA SERIAL IN TXD M3 T2 LCD.E LIO.B32 C1 J6 LIO.A29
IO_L74N_Y IO IO IO_L82P_Y IO_L104P_Y IO_L96P IO IO
E U12
IO_L74P_Y IO
AB17 MEM.D16 MEM.D13 AA5
IO IO_L81N_Y
AB9 MEM.D05 FPGA SERIAL OUT RXD
M4
IO_L104N_Y IO_L96N
T3 DISPLAY.1E LIO.B33 D2
IO_L119P_Y IO_L111P_Y
J4 LIO.B25 E
MEM.D24 AB13 AA16 MEM.D25 MEM.D08 W5 AA9 MEM.D06 VGA.GREEN2 M5 T4 DISPLAY.1D LIO.B34 D1 J5 LIO.A31
IO_L73N_Y IO_L66N IO_L88N_Y IO_L81P_Y IO_L103P_Y IO_L95P_Y IO_L119N_Y IO_L111N_Y
AA13 Y16 Y5 AB10 M6 T5 E2 J3
MEM.D26 IO_L73P_Y IO_L66P MEM.A01 MEM.D10 IO_L88P_Y IO VGA.GREEN1 IO_L103N_Y IO_L95N_Y LIO.B35 IO_VREF_7_L118P_Y IO_L110P_Y LIO.B26
MEM.A00 Y13 W16 MEM.A10 MEM.D11 AB5 W9 MEM.A08 LED1 N1 T1 LCD.RS LIO.B18 E3 J2 DIP3
IO IO_L65N IO_VREF_5_L87N_Y IO_L80N_Y IO IO_L94P_Y IO_L118N_Y IO_L110N_Y
V16 MEM.D00 AB6 Y9 MEM.A05 LED2 N2 U1 LCD.DB0 LIO.B36 E1 J1 DIP4
W13 IO_L65P IO_L87P_Y IO_L80P_Y IO IO_VREF_6_L94N_Y IO IO
MEM.A03 IO_L72N_Y
V13 AA17 MEM.D18 MEM.CLK Y6 V9 VGA.RED0 N3 U2 LCD.DB1 LIO.A23 F5 K5 LIO.A35
IO_VREF_4_L72P_Y IO_L64N_YY IO IO_L79N_Y IO_VREF_6_L102P IO IO IO_L109P_YY
U13 Y17 MEM.A02 MEM.D09 AA6 U9 VGA.RED1 N4 U3 DISPLAY.1F LIO.B19 F4 K6 LIO.A33
IO IO_VREF_4_L64P_YY IO IO_L79P_Y IO_L102N IO_L93P_Y IO_L117P_Y IO_L109N_YY
MEM.D28 AB14 AB18 MEM.D17 V6 AA10 MEM.D07 VGA.GREEN0 N5 U4 DISPLAY.1G LIO.B20 F3 K3 LIO.B28
IO_L71N IO IO_L86N_YY IO IO_L101P_Y IO_L93N_Y IO_L117N_Y IO_VREF_7_L108P_Y
MEM.D30 AA14 W17 MEMA.LDQM MEM.A13 W6 W10 MEM.A04 VGA.HSYNC N6 V1 LCD.DB2 LIO.B37 F2 K4 LIO.B27
IO_L71P IO_L63N IO_L86P_YY IO_L78N_Y IO_L101N_Y IO IO_VREF_7_L116P_Y IO_L108N_Y
MEM.D31 AB15 V17 MEM.D01 AB7 Y10 MEM.CKE LED3 P1 W1 LCD.DB4 LIO.B38 F1 K2 DIP5
IO IO_L63P IO_VREF_5_L85N_YY IO_L78P_Y IO_L100P_Y IO_L92P_Y IO_L116N_Y IO
MEM.RASn Y14 AA18 MEM.D20 MEM.D02 AA7 V10 LED4 P2 V2 LCD.DB3 LIO.A25 G5 K1 DIP6
IO_L70N IO IO_L85P_YY IO_VREF_5_L77N_Y IO_L100N_Y IO_VREF_6_L92N_Y IO IO_L107P_Y
W14 Y18 Y7 U10 R1 W2 G4 L1
MEM.WEn IO_L70P IO_L62N_Y MEMB.UDQM MEM.A11 IO IO_L77P_Y PUSH1 IO IO LCD.DB5 LIO.B21 IO_L115P_Y IO_L107N_Y DIP8
W18 MEMB.LDQM LIO.B22 G3
U14 IO_VREF_4_L62P_Y V7 U11 P3 V3 IO_L115N_Y L3
IO_L69N IO_L84N_Y IO VGA.RED2 IO_L99P_Y IO_L91P_Y DISPLAY.1A IO_L106P_Y LIO.B30
V14 AB19 W7 V11 P4 V4 G2 L2
IO_L69P IO MEM.D19 MEMA.UDQM IO_L84P_Y IO VGA.BLUE2 IO_L99N_Y IO_L91N_Y DISPLAY.1B LIO.B39 IO_L114P_Y IO_L106N_Y DIP7
MEM.D29 AA15 AA19 MEM.D22 MEM.D03 AB8 W11 MEM.A09 VGA.VSYNC P5 Y1 LCD.DB6 LIO.B40 G1 L4 LIO.B29
IO_L68N_Y IO_L61N IO_L83N_Y IO_L76N IO_L98P_YY IO IO_L114N_Y IO
MEM.BA1 Y15 Y19 MEM.D04 AA8 Y11 MEM.CASn P6 Y2 LCD.DB7 LIO.A27 H5 L5 LIO.A39
IO_L68P_Y IO_L61P AB21
IO_L83P_Y IO_L76P
AA11 R2
IO_L98N_YY IO_L90P_YY
W3 H3 IO IO_L105P_YY
L6
D IO
AB20 AB12
IO
AB11
FPGA.RESETn
R3
IO_L97P_Y IO_L90N_YY DISPLAY.1C LIO.B24
H4
IO_IRDY_L105N_YY
IO_VREF_7_L113P_Y LIO.A37 D
IO_L60N_YY MEM.D21 FPGA.GCLK GCK1 IO_LVDS_DLL_L75N VGA.BLUE1 IO_VREF_6_L97N_Y LIO.B23 IO_L113N_Y
CLK.CAN1 AA12 AA20 MEM.D23
GCK0 IO_L60P_YY
41 IO 40 IO 41 IO 41 IO
1 CLOCK 1 CLOCK

CONFIGURATION BLOCK POWER BLOCK

1.8V
3.3V

3.3V

W19
G15
G16

H16

R16

U17

D19
E18

V18
F17

T15
T16

W4
G7
G8

H7

R7

U6

D4
E5

V5
F6

T7
T8
2S300E
C R5
U4J C

VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
3.3k
R8 A1
R6 R7 3.3k A22 GND
3.3k 3.3k 1% B2 GND A2
GND GND
Configuration B21
GND GND
B1
U4I C3 T11
GND GND
B22 2S300E C20 T12
FPGA.CCLK CCLK GND GND
DONE W20 G11 Y20
DONE GND GND
Mode Pull-ups 0 1 2
PROGRAMn Y21 G12 Y3
PROGRAM GND GND
J9 Y4
Master-serial No M0 GND GND
AA1 J10 AA2
M1 M0 GND GND
Yes U5 J11 AA4
Slave Serial No M2 AB2 M1 J12 GND GND AA21
M2 GND GND
Yes J13 AA22
SelectMAP No GND GND
TCK E6 J14 AB1
TCK GND GND
Yes
TDO.PROM.to.TDI.FPGA C19 K9 AB22
Boundary-scan No A21 TDI K10 GND GND
B TDO.FPGA.to.TDO.PORT TDO GND B
1
3
5

Yes E4 K11
TMS TMS GND
J1 K12
GND
012

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Indicates jumper installed ('0') 2X3
Indicates jumper removed ('1')

M16

M10
M11
M12
M13
M14

N10
N11
N12
N13
N14
K13
K14

P10
P11
P12
P13
P14
L10
L11
L12
L13
L14
L16
2
4
6

M7
M9

N9

P9
L7
L9
NE10 SHUNT-LO-CL

NE11 SHUNT-LO-CL

NE12 SHUNT-LO-CL

SPARTAN-IIE DEVELOPMENT BOARD

A A
FPGA

MemecBoard Last Modified

Sunday, January 26, 2003
<OrgAddr1> Size Rev
<OrgAddr2> C 1
<OrgAddr3> Designer Sheet
<OrgAddr4> Jim Elliott 3 of 8
10 9 8 7 6 5 4 3 2 1
 10 9 8 7 6 5 4 3 2 1

XC18 PROM PROGRAM PUSHBUTTON DONE LED VBANK SELECT

3.3V
3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V

3.3V 2.5V 3.3V 2.5V

3.3V
H R9 JP4 JP8 H
330
C7 C58 C59 C60 C8 C61 C62 1 3 3 1
.1u .1u .1u .1u .1u .1u .1u 2 2
1X3 RA 1X3 RA
R10 DS4
3.3k GREEN

LABEL = DONE VBANK0 VBANK1

3
Q2
PROGRAMn
1 2
SW2
TL1105SP 3.3V 2.5V 3.3V 2.5V
R1
DONE 1
LABEL = PROGRAM JP9 JP10
3.3V 3.3V
4 3 1 3 3 1
G R2
2 2
G
R11
1X3 RA 1X3 RA
PROGRAMn
0 1% BCR133
2

16
26
36

17
35
38
8
44 34 VBANK2 VBANK7
1 33

VCC
VCC
VCC
VCCO
VCCO
VCCO
VCCO
INITn
3 NE13 SHUNT-LO-CL NE15 SHUNT-LO-CL
TDI.PROM TDI
TMS 5 40 SM.D0
TMS D0/DATA
TCK 7 29
JP6 TCK U5 D1 NE14 SHUNT-LO-CL NE16 SHUNT-LO-CL
1 TDO.PROM 31 42
TDO D2
27
XC18V04VQ44C D3
10 9
CF D4
13 25
2 OE/RESET D5
DONE 15
21 CE D6
14
19
CLOCK SELECTMAP PORT
43 CEO D7
F F
GND
GND
GND
GND
3 FPGA.CCLK CLK
1X3 RA
11 23 3.3V 3.3V
12 18 22
28
41
6

C9 C10
.1u .1u

JP2
3.3V 3.3V 1 2
SM.CS CSn DIN/D0 SM.D0
DONE 3 4 SM.D1
NE23 SHUNT-LO-CL DONE D1
FPGA.CCLK 5 6 SM.D2
CCLK D2
INITn 7 8 SM.D3
Y1 Y2 INITn D3
PROGRAMn 9 10 SM.D4
PROGRAMn D4
1 4 1 14 11 12 SM.D5
EN VCC ENABLE VCC 13 NC D5 14
SM.WRITE RDWRn D6 SM.D6

half
15 16
SM.BUSY DOUT/BUSY D7 SM.D7
2 3 CLK.CAN1 4 11 CLK.SOCKET
GND OUT GND OUT
E E

full
SelectMAP RA
100MHz
7 8
GND OUT
CAN

FPGA RESET CIRCUIT JTAG PORT

3.3V 3.3VJ
3.3VJ

3.3V

5
D5 U9 74AHC125 R39
5.1k
D D

VCC
1N5817M 1%
R13 1
3.3k 3.3VJ OE
1% 2 4
IN OUT
1 2 3.3VJ
C11 R83

GND
SW3 .01u R38 4.7k
TL1105SP 6 1k D6 3.3VJ 1% 3.3VJ
0603 1% R84
LABEL = RESET 1N5817M R35 4.7k

5
1% U10 74AHC125 3.3V
4 3

VCC
300 1%
1
R25 R34 OE R27 J2
100 2 4 2 1
FPGA.RESETn IN OUT OBTDI
1% 4 3
C 300 1% 3.3VJ 100 1% 6 5 C
8 7

GND
OBTCK TCK
C52 10 9
OBTDO TDO.FPGA.to.TDO.PORT
C57 U11 5 74AHC125 100p OBTDI 12 11 TDI.PORT.to.TDI.PROM
2.2u VCC 16 14 13
OBTMS TMS

3
0603
JM1 1 2X7 RA
R33 OE R28
1
2 RJ_PROG 2 4
RJ_DIN IN OUT OBTCK
3
4 RJ_TMS 300 1% 100 1%
5 RJ_CTRL 3.3VJ NE19 SHUNT-LO-CL
GND

6 RJ_DONE R37 C53

7 100p NE20 SHUNT-LO-CL
PROM JTAG BYPASS 8 RJ_CLK 3.3VJ 16
300 1% R85 NE21 SHUNT-LO-CL
3

0603
RJ45 4.7k

5
1% U12 74AHC125 NE22 SHUNT-LO-CL
B B
VCC
R36
TDO.PROM
1
OE R29
300 1% 2 4
IN OUT OBTMS
100 1%
JP11 3.3VJ
GND

1
C54
PROM IN CHAIN 100p
5

U13 74AHC125 16
TDO.PROM.to.TDI.FPGA 2 R32
3

0603
VCC

TDI.PORT.to.TDI.PROM 3 PROM BYPASSED

1
100 1% OE R30
4 PROM IN CHAIN 4
OUT IN
2 OBTDO
1X4 RA
R31 100 1%
SPARTAN-IIE DEVELOPMENT BOARD
GND

A C55 A
NE17 SHUNT-LO-CL 100 1% 100p FPGA PERIPHERALS
TDI.PROM
16
NE18 SHUNT-LO-CL Last Modified
3

0603 MemecBoard Sunday, January 26, 2003

<OrgAddr1> Size Rev
<OrgAddr2> C 1
<OrgAddr3> Designer Sheet
<OrgAddr4> Jim Elliott 4 of 8
10 9 8 7 6 5 4 3 2 1
 10 9 8 7 6 5 4 3 2 1

MRAM A

H H
2.5V 2.5V

D3

C7
A9

E7

B3

A7
J9
U6 HYB25L128160AC-8

VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
MEM.A00 H7
H8 A0
MEM.A01 A1
MEM.A02 J8
A2
G MEM.A03 J7
A3
G
MEM.A04 J3 A8 MEM.D00
J2 A4 DQ0 B9
MEM.A05 A5 DQ1 MEM.D01

INFINEON MOBILE RAM

MEM.A06 H3 B8 MEM.D02
H2 A6 DQ2
C9
MEM.A07 A7 DQ3 MEM.D03
H1 C8
MEM.A08 A8 DQ4 MEM.D04
MEM.A09 G3 D9 MEM.D05
A9 DQ5
MEM.A10 H9 D8 MEM.D06
A10 DQ6
MEM.A11 G2 E9 MEM.D07
A11 DQ7
G1 E1
MEM.A12 A12 DQ8 MEM.D08
MEM.A13 E2 D2 MEM.D09
A13 DQ9
D1 MEM.D10
DQ10
MEM.CLK F2 C2 MEM.D11
CLK DQ11
C1 MEM.D12
DQ12
MEM.CKE F3 B2 MEM.D13
CKE DQ13 B1
DQ14 MEM.D14
MEMA.UDQM F1 A2 MEM.D15
UDQM DQ15
MEMA.LDQM E8
LDQM
F G7 F
MEM.BA0 BA0
MEM.BA1 G8
BA1
F8
MEM.RASn RAS
MEM.CASn F7
CAS
MEM.WEn F9
WE
G9
MEM.CSn CS

VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS

C3

D7
A1
E3

A3

B7
J1
E E

MRAM B

2.5V 2.5V

D D

D3

C7
A9

E7

B3

A7
J9

U7 HYB25L128160AC-8
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ

MEM.A00 H7
A0
MEM.A01 H8
A1
MEM.A02 J8
A2
J7
MEM.A03 A3
MEM.A04 J3 A8 MEM.D16
J2 A4 DQ0
B9
MEM.A05 A5 DQ1 MEM.D17
INFINEON MOBILE RAM

MEM.A06 H3 B8 MEM.D18
A6 DQ2
MEM.A07 H2 C9 MEM.D19
C H1 A7 DQ3 C8 C
MEM.A08 A8 DQ4 MEM.D20
G3 D9
MEM.A09 A9 DQ5 MEM.D21
MEM.A10 H9 D8 MEM.D22
A10 DQ6
MEM.A11 G2 E9 MEM.D23
G1 A11 DQ7 E1
MEM.A12 A12 DQ8 MEM.D24
E2 D2
MEM.A13 A13 DQ9 MEM.D25
D1 MEM.D26
DQ10
MEM.CLK F2 C2 MEM.D27
CLK DQ11
C1
DQ12 MEM.D28
MEM.CKE F3 B2 MEM.D29
CKE DQ13
B1 MEM.D30
DQ14
MEMB.UDQM F1 A2 MEM.D31
UDQM DQ15
MEMB.LDQM E8
LDQM

MEM.BA0 G7
BA0
MEM.BA1 G8
BA1

MEM.RASn F8
F7 RAS
B MEM.CASn
F9
CAS B
MEM.WEn WE
MEM.CSn G9
CS
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS

C3

D7
A1
E3

A3

B7
J1

SPARTAN-IIE DEVELOPMENT BOARD

A A
MEMORY

MemecBoard Last Modified

Sunday, January 26, 2003
<OrgAddr1> Size Rev
<OrgAddr2> C 1
<OrgAddr3> Designer Sheet
<OrgAddr4> Jim Elliott 5 of 8
10 9 8 7 6 5 4 3 2 1
 10 9 8 7 6 5 4 3 2 1

FPGA CLOCK INPUT FROM SOCKET

H CLK.SOCKET H
NE24 SHUNT-LO-CL

2
4
NE25 SHUNT-LO-CL FPGA CLOCK INPUT FROM SAM
JP30

2X2
SAM CLOCK INPUT FROM SOCKET

1
3
3.3V FPGA.GCLK 3.3V FPGA & SAM CLOCK INPUTs FROM SOCKET

JP29
1 2
3.3V 3.3V
G TDO.FPGA.to.TDO.PORT 3
TDO GND
4 G
TMS 5 6
TMS CLOCK 2.5V 3.3V 5V
7 8
5V 3.3V 2.5V TDI.PORT.to.TDI.PROM TDI GND
PROGRAMn 9 10 TCK
PROGRAMn TCK 2.5V
11 12
2.5V GND GND
13 14
JX1 P160 Left Header MB SAM.OEn OEn INITn INITn JX2 P160 Right Header MB
SAM.A00 15 16 SAM.WEn
A00 WEn
SAM.A02 17 18 SAM.A01
A02 A01
19 20 SAM.A03
2.5V A03
21 22
SAM.D00 D00 2.5V
A1 B1 SAM.D02 23 24 SAM.D01 RIO.A1 A1 B1
TCK DIN D02 D01 IOA1 GND
A2 B2 SAM.D04 25 26 SAM.D03 RIO.A2 A2 B2 RIO.B2
GND DOUT D04 D03 IOA2 IOB2
A3 B3 SAM.D06 27 28 SAM.D05 RIO.A3 A3 B3
TMS CCLK D06 D05 IOA3 VIN
A4 B4 SAM.D08 29 30 SAM.D07 RIO.A4 A4 B4 RIO.B4
VIN DONE D08 D07 IOA4 IOB4
A5 B5 SAM.D10 31 32 SAM.D09 RIO.A5 A5 B5
TDI INITn D10 D09 IOA5 GND
A6 B6 33 34 A6 B6
GND PROGRAMn SAM.D12 D12 D11 SAM.D11 RIO.A6 IOA6 IOB6 RIO.B6
A7 B7 SAM.D14 35 36 SAM.D13 RIO.A7 A7 B7
TDO NC D14 D13 IOA7 3.3V
A8 B8 LIO.B8 SAM.A04 37 38 SAM.D15 RIO.A8 A8 B8 RIO.B8
3.3V IOB8 A04 D15 IOA8 IOB8
A9 B9 39 40 A9 B9
F LIO.A9
A10
IOA9 IOB9
B10
LIO.B9 SAM.A06
41
A06 A05
42
SAM.A05 RIO.A9
A10
IOA9 GND
B10 F
GND IOB10 LIO.B10 SAM.IRQ IRQ GND RIO.A10 IOA10 IOB10 RIO.B10
LIO.A11 A11 B11 LIO.B11 SAM.RESETn 43 44 SAM.CEn RIO.A11 A11 B11
IOA11 IOB11 RESETn CEn IOA11 2.5V
A12 B12 LIO.B12 DONE 45 46 SAM.BRDY RIO.A12 A12 B12 RIO.B12
2.5V IOB12 DONE BRDY IOA12 IOB12
A13 B13 47 48 A13 B13
LIO.A13 IOA13 IOB13 LIO.B13 FPGA.CCLK CCLK BITSTREAM SM.D0 RIO.A13 IOA13 GND
A14 B14 LIO.B14 49 50 RIO.A14 A14 B14 RIO.B14
GND IOB14 GND GND IOA14 IOB14
LIO.A15 A15 B15 LIO.B15R RIO.A15 A15 B15
IOA15 IOB15 SAM Header IOA15 VIN
A16 B16 A16 B16
VIN IOB16 LIO.B16 RIO.A16 IOA16 IOB16 RIO.B16
LIO.A17 A17 B17 LIO.B17 RIO.A17 A17 B17
IOA17 IOB17 IOA17 GND
A18 B18 LIO.B18 RIO.A18 A18 B18 RIO.B18
GND IOB18 IOA18 IOB18
LIO.A19 A19 B19 LIO.B19 RIO.A19 A19 B19
IOA19 IOB19 IOA19 3.3V
A20 B20 LIO.B20 RIO.A20 A20 B20 RIO.B20
3.3V IOB20 IOA20 IOB20
LIO.A21 A21 B21 LIO.B21 RIO.A21 A21 B21
IOA21 IOB21 IOA21 GND
A22 B22 LIO.B22 RIO.A22 A22 B22 RIO.B22
GND IOB22 IOA22 IOB22
LIO.A23 A23 B23 LIO.B23 RIO.A23 A23 B23
IOA23 IOB23 IOA23 2.5V
A24 B24 LIO.B24 RIO.A24 A24 B24 RIO.B24
2.5V IOB24 IOA24 IOB24
LIO.A25 A25 B25 LIO.B25 RIO.A25 A25 B25
IOA25 IOB25 IOA25 GND
A26 B26 A26 B26
GND IOB26 LIO.B26 RIO.A26 IOA26 IOB26 RIO.B26
LIO.A27 A27 B27 LIO.B27 RIO.A27 A27 B27
IOA27 IOB27 IOA27 VIN
E A28
VIN IOB28
B28 LIO.B28 RIO.A28 A28
IOA28 IOB28
B28 RIO.B28 E
LIO.A29 A29 B29 LIO.B29 RIO.A29 A29 B29
IOA29 IOB29 IOA29 GND
A30 B30 A30 B30
GND IOB30 LIO.B30 RIO.A30 IOA30 IOB30 RIO.B30
LIO.A31 A31 B31 LIO.B31 RIO.A31 A31 B31
IOA31 IOB31 IOA31 3.3V
A32 B32 LIO.B32 RIO.A32 A32 B32 RIO.B32
3.3V IOB32 IOA32 IOB32
A33 B33 A33 B33
LIO.A33R IOA33 IOB33 LIO.B33 5V RIO.A33 IOA33 GND
A34 B34 LIO.B34 RIO.A34 A34 B34 RIO.B34
GND IOB34 3.3V IOA34 IOB34
LIO.A35R A35 B35 LIO.B35 RIO.A35 A35 B35
IOA35 IOB35 2.5V IOA35 2.5V
A36 B36 LIO.B36 RIO.A36 A36 B36 RIO.B36
2.5V IOB36 IOA36 IOB36
LIO.A37 A37 B37 LIO.B37 RIO.A37 A37 B37
IOA37 IOB37 IOA37 GND
A38 B38 LIO.B38 RIO.A38 A38 B38 RIO.B38
GND IOB38 JP7 IOA38 IOB38
LIO.A39R A39 B39 LIO.B39 RIO.A39 A39 B39
IOA39 IOB39 IOA39 VIN
A40 B40 1 2 A40 B40
VIN IOB40 LIO.B40 RIO.A40 IOA40 IOB40 RIO.B40
GPIO1 3 4 GPIO2
GPIO3 5 6 GPIO4
7 8
GPIO5 GPIO6
GPIO7 9 10 GPIO8
GPIO9 11 12 GPIO10
13 14
D GPIO11
15 16
GPIO12 D
GPIO13 GPIO14
GPIO15 17 18 GPIO16
GPIO17 19 20 GPIO18
21 22
GPIO19 GPIO20
GPIO21 23 24 GPIO22
GPIO23 25 26 GPIO24
27 28
GPIO25 GPIO26
29 30

2X15

C GLOBAL CLOCK SELECT JTAG CHAIN C

JTAG PORT

TDO.FPGA.to.TDO.PORT

PROMs FPGA

JP31
LIO.A33R 1 2 LIO.A33
CLK.GCK3 3 EXP1 4
5 EXP3 6
B LIO.A39R LIO.A39 B
2X3 RA
TDO.PROM.to.TDI.FPGA
TDI.PORT.to.TDI.PROM TDI TDO TDI TDO
JP32
LIO.A35R 1 2 LIO.A35
CLK.GCK2 3 EXP1 4
LIO.B15R 5 EXP3 6 LIO.B15
SYSTEM ACE CONTROLLER PROM BYPASS NOT SHOWN NO FPGA BYPASS
2X3 RA

NE26 SHUNT-LO-CL
TCK
NE27 SHUNT-LO-CL

NE30 SHUNT-LO-CL SPARTAN-IIE DEVELOPMENT BOARD

A TMS A
NE31 SHUNT-LO-CL P160 SOCKET & SAM & GPIO HEADERS

MemecBoard Last Modified

Sunday, January 26, 2003
Suite 540, 1212 31st Ave. NE Size Rev
Calgary, Alberta C 1
Canada Designer Sheet
T2E 7S8 Jim Elliott 6 of 8
10 9 8 7 6 5 4 3 2 1
 10 9 8 7 6 5 4 3 2 1

SEVEN SEGMENT DISPLAYs SERIAL PORT VGA PORT

3.3V

3.3V
3.3V
H U8 H
1 16
C13 2 EN FORCEOFF
15
.1u C1+ VCC C12
3 14
V+ GND .1u JD2
3 8 4 13
5 C1- DOUT 12
DD1 C2+ FORCEON R12
A B C D E F G DP 6 11
RED CA C14 7 C2- DIN 10 1
V- INVALID VGA.RED0 RED OUT
.1u 8 9
RIN ROUT 1k 1% 2
MAX3221 GREEN OUT
C15 R24 3
7 6 4 2 1 10 9 5 .1u R44 0 1% BLUE OUT
VGA.RED1
4
C16 510 1% MONID2
.1u 5
R41 GND

VGA.RED2 6
RED IN
G G
R22 220 1% 7
R20 GREEN IN
VGA.GREEN0
R18 R19 330 8
330 330 1% 1k 1% BLUE IN
FPGA SERIAL IN TXD
1% 1% JD1 9
FPGA SERIAL OUT RXD R26 R88 0 1% NC
R14 R15 R16 R17 10
VGA.GREEN1 SYNC IN
330 330 330 330 1
1% 1% 1% 1% DCD 510 1% 11
MONID0
6
JP5 JP3 DSR R42 R45 0 1% 12
MONID1
DISPLAY.1A 2 VGA.GREEN2
JP5 RD
DISPLAY.1B 1 VGA.HSYNC 13
1X3 220 1% R23 HSYNC
DISPLAY.1C 7
RTS

DCE
14
DISPLAY.1D VGA.BLUE0 VGA.VSYNC VSYNC
DISPLAY.1E 3
2 JP3 TD 1k 1%
DISPLAY.1F 15
3 MONID3
1X3 8
F DISPLAY.1G CTS R40 F
3
4 VGA.BLUE1
2 DTR
9 510 1% DB15HDF RA
RI
1

DTE
5 R43
GND
VGA.BLUE2
220 1%
DB9F RA
a

NE28 SHUNT-LO-CL
f b
NE29 SHUNT-LO-CL
g
USE STANDARD STRAIGHT-THRU
E CABLE WHEN CONNECTING TO A PC E
e c

LCD MODULE CONNECTOR

d
5V 5V

5V
3.3V R66 C45
LEDs 200k
1%
.1u

R67 R68 R69 R70 R71 R72 R73 R74 R75 R76
D 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k R77 D
1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 15.8k

24
3.3V 3.3V 3.3V 3.3V 1%
U14 DEPOPULATED = Y

GATE
WRITE ONLY
2 23
A1 B1
3 22
LCD.RS A2 B2
R21 R80 R81 R82 4 21
LCD.E A3 B3
330 330 330 330 LCD.DB0 5 20
1% 1% 1% 1% 6 A4 B4 19
LCD.DB1 A5 B5 5V R78 R79
LCD.DB2 7 18
A6 B6 3.3k 3.3k
LCD.DB3 8 17
A7 B7 1% 1%
LCD.DB4 9 16
A8 B8
10 15
DS5 DS6 DS7 DS8 LCD.DB5 A9 B9
LCD.DB6 11 14
GREEN GREEN GREEN GREEN A10 B10
LCD.DB7 12 13
A11 B11

GND
LABEL = LED1 LABEL = LED2 LABEL = LED3 LABEL = LED4
C 74TVC3010 C

14
13
12
11
10
9
8
7
6
5
4
3
2
1
1

RS

VDD
R/W

GND
VL
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
LED1

LED2
J6 LCD
LED3

LED4

PUSHBUTTONS DIP SWITCH

B B

PULL-UPS MUST BE IMPLEMENTED IN FPGA PULL-UPS MUST BE IMPLEMENTED IN FPGA

1 2
SW6
SW4 16 1
DIP1
TL1105SP 15 2
DIP2
DIP3 14 3
LABEL = PUSH1 13 4
DIP4
DIP5 12 5
4 3 11 6
DIP6
DIP7 10 7
DIP8 9 8
SPARTAN-IIE DEVELOPMENT BOARD
A SWDIP08 A
USER IO
PUSH1

MemecBoard Last Modified

Sunday, January 26, 2003
Suite 540, 1212 31st Ave. NE Size Rev
Calgary, Alberta C 1
Canada Designer Sheet
T2E 7S8 Jim Elliott 7 of 8
10 9 8 7 6 5 4 3 2 1
 10 9 8 7 6 5 4 3 2 1

FPGA BANK DECOUPLING FPGA CORE DECOUPLING (20 pins) MEMORY A DECOUPLING

2.5V 2.5V 2.5V 2.5V

H VBANK0 VBANK0 VBANK0 VBANK0 VBANK0 VBANK0 VBANK0 VBANK0 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V H
C67 C68 C69 C70
.1u .1u 1u 1u
C85 C86 C87 C88 C89 C90 C92 C17 C18 C19 C20 C21 C23 6.3 6.3 6 6
10n 10n 10n 10n .22u .22u 2.2u + C93 1n 1n 1n 1n 1n 1n 0402 0402 0402 0402
6.3 6.3 6.3 6.3 6 6 10 330u 10 10 10 10 10 10
0201 0201 0201 0201 0603 0603 1206 6.3 0201 0201 0201 0201 0201 0201

2.5V 2.5V 2.5V 2.5V

1.8V 1.8V 1.8V 1.8V 1.8V 1.8V

C63 C64 C65 C66
VBANK1 VBANK1 VBANK1 VBANK1 VBANK1 VBANK1 VBANK1 VBANK1 .01u .01u .01u .01u
G 6 6 6 6 G
C24 C25 C26 C27 C33 C157 0402 0402 0402 0402
1n 1n 1n 1n 1n 1n
C94 C95 C96 C97 C98 C99 C101 10 10 10 10 10 10
10n 10n 10n 10n .22u .22u 2.2u + C102 0201 0201 0201 0201 0201 0201
6.3 6.3 6.3 6.3 6 6 10 330u
0201 0201 0201 0201 0603 0603 1206 6.3

2.5V 2.5V 2.5V

C185 C186 C187

.1u .1u 1u
1.8V 1.8V 1.8V 1.8V 6.3 6.3 6
VBANK2 VBANK2 VBANK2 VBANK2 VBANK2 VBANK2 VBANK2 VBANK2 0402 0402 0402

F C29 C30 C31 C32 F

C103 C104 C105 C106 C107 C108 C110 10n 10n 10n 10n
10n 10n 10n 10n .22u .22u 2.2u + C111 6.3 6.3 6.3 6.3
6.3 6.3 6.3 6.3 6 6 10 330u 0201 0201 0201 0201
0201 0201 0201 0201 0603 0603 1206 6.3 2.5V 2.5V 2.5V 2.5V

C188 C189 C190

.01u .01u .01u + C191
6 6 6 330u
0402 0402 0402

3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V

1.8V 1.8V 1.8V 1.8V

E C113 C114 C115 C117 C116 C119 E

10n 10n 10n 10n .22u 2.2u + C120 C35 C36 C37 C38
6.3 6.3 6.3 6.3 6 10 330u .1u .1u .1u .1u
0201 0201 0201 0201 0603 1206 6.3 16 16 16 16
0402 0402 0402 0402 MEMORY B DECOUPLING

2.5V 2.5V 2.5V 2.5V

3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V C71 C72 C73 C74
.1u .1u 1u 1u
1.8V 1.8V 6.3 6.3 6 6
0402 0402 0402 0402
C121 C122 C123 C126 C125 C128
10n 10n 10n 10n .22u 2.2u + C129
D 6.3 6.3 6.3 6.3 6 10 330u C39 C40 D
0201 0201 0201 0201 0603 1206 6.3 1u 1u
6 6
0402 0402
2.5V 2.5V 2.5V 2.5V

C75 C76 C77 C78

.01u .01u .01u .01u
6 6 6 6
2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V
0402 0402 0402 0402
1.8V 1.8V

C130 C131 C124 C132 C134 C137

10n 10n 10n 10n .22u 2.2u + C138
6.3 6.3 6.3 6.3 6 10 330u
C 0201 0201 0201 0201 0603 1206 6.3 + C41 + C42 C
10u 10u 2.5V 2.5V 2.5V
6.3 6.3

C192 C193 C194

.1u .1u 1u
6.3 6.3 6
0402 0402 0402
2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V

1.8V 1.8V
C133 C139 C140 C141 C135 C146
10n 10n 10n 10n .22u 2.2u + C147 2.5V 2.5V 2.5V 2.5V
6.3 6.3 6.3 6.3 6 10 330u
0201 0201 0201 0201 0603 1206 6.3
+ C79 + C80
B 330u 330u C195 C196 C197 B
6.3 6.3 .01u .01u .01u + C198
6 6 6 330u
0402 0402 0402

VBANK7 VBANK7 VBANK7 VBANK7 VBANK7 VBANK7 VBANK7 VBANK7

C148 C149 C150 C151 C152 C153 C155

10n 10n 10n 10n .22u .22u 2.2u + C156
6.3 6.3 6.3 6.3 6 6 10 330u
0201 0201 0201 0201 0603 0603 1206 6.3

SPARTAN-IIE DEVELOPMENT BOARD

A A
DECOUPLING

MemecBoard Last Modified

Monday, January 27, 2003
<OrgAddr1> Size Rev
<OrgAddr2> C 1
<OrgAddr3> Designer Sheet
<OrgAddr4> Jim Elliott 8 of 8
10 9 8 7 6 5 4 3 2 1