Arrays may be declared in VHDL in the following way:

First - One needs to define a type that defines the base type for each element of the array and the size
(range | number of elements) of the array. Second - Signals are then declared with this type.
e.g.

type ta is array (0 to 63) of std_logic_vector (7 downto 0);

signal memory : ta;
type tb is array (0 to 1023) of integer range -255 to +255;
signal table : tb;

Initial values may be assigned as part of the declaration - a complete set of values for all elements of the
array must be provided - values are assigned in order first_element to last_element.
e.g.

type tc is array (0 to 7) of integer range 0 to 255;

signal look_up : tc := (27, 15, 4, 94, 187, 53, 99, 0);

If the array is read-only i.e. never written to then it could be declared as a constant.
e.g.

type td is array (0 to 3) of integer range 0 to 127;

constant rom : td := (19, 12, 108, 24);

Arrays are accessed using an integer value as an index. Targets must be of the same base type as the array
being read from, or written to.
e.g.

alpha <= memory (5);

bravo <= look_up ( ptr );
-- where signal ptr : integer range 0 to 7;

Two dimensional arrays may also be defined:

e.g.

type te is array (0 to 3) of integer range 0 to 127;

type tf is array (0 to 1) of te;
signal ram : tf := ( (3, 7, 19, 27) , ( 12, 42, 24, 10) );
charley <= ram ( sel ) ( loc );
-- where signal sel : integer range 0 to 1;
-- and signal loc : integer range 0 to 3;

Note the syntax for referencing a particular element of a two dimensional array
e.g.
ram ( sel ) ( loc );
[The VHDL language definition also shows an alternative method ram (sel, loc) but this is currently NOT
supported within Xilinx Tools]

Std_logic_vector is in reality an array of std_logic. Individual elements can therefore be accessed

using an integer as an index or using a range. Targets must have correct type and range (width)
e.g.

signal counter : std_logic_vector (7 downto 0);

signal nibble, nibble_A, nibble_B : std_logic_vector (3 downto 0);
signal flag
: std_logic;
.
flag <= counter (5);
nibble <= counter (7 downto 4);
counter <= nibble_A & nibble_B
-- Concatenate operator "&"