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PIC12F683
PIC12F683
Data Sheet
8-Pin Flash-Based, 8-Bit
CMOS Microcontrollers with
nanoWatt Technology
DS41211D
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,
PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and
SmartShunt are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
AmpLab, FilterLab, Linear Active Thermistor, Migratable
Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor
and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,
MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The
Companys quality system processes and procedures are for its PIC
MCUs and dsPIC DSCs, KEELOQ code hopping devices, Serial
EEPROMs, microperipherals, nonvolatile memory and analog
products. In addition, Microchips quality system for the design and
manufacture of development systems is ISO 9001:2000 certified.
DS41211D-page ii
PIC12F683
8-Pin Flash-Based, 8-Bit CMOS Microcontrollers with
nanoWatt Technology
High-Performance RISC CPU:
Low-Power Features:
Standby Current:
- 50 nA @ 2.0V, typical
Operating Current:
- 11 A @ 32 kHz, 2.0V, typical
- 220 A @ 4 MHz, 2.0V, typical
Watchdog Timer Current:
- 1 A @ 2.0V, typical
Peripheral Features:
Special Microcontroller Features:
Program Memory
Data Memory
Device
PIC12F683
I/O
Flash (words)
SRAM (bytes)
EEPROM (bytes)
2048
128
256
Timers
8/16-bit
2/1
DS41211D-page 1
PIC12F683
VDD
GP5/T1CKI/OSC1/CLKIN
GP4/AN3/T1G/OSC2/CLKOUT
GP3/MCLR/VPP
PIC12F683
VSS
GP0/AN0/CIN+/ICSPDAT/ULPWU
GP1/AN1/CIN-/VREF/ICSPCLK
GP2/AN2/T0CKI/INT/COUT/CCP1
VDD
GP5/TICKI/OSC1/CLKIN
2
PIC12F683
VSS
GP0/AN0/CIN+/ICSPDAT/ULPWU
GP4/AN3/TIG/OSC2/CLKOUT
GP1/AN1/CIN-/VREF/ICSPCLK
GP3/MCLR/VPP
GP2/AN2/T0CKI/INT/COUT/CCP1
VDD
VSS
GP5/TICKI/OSC1/CLKIN
GP0/AN0/CIN+/ICSPDAT/ULPWU
PIC12F683
GP4/AN3/TIG/OSC2/CLKOUT
GP1/AN1/CIN-/VREF/ICSPCLK
GP3/MCLR/VPP
GP2/AN2/T0CKI/INT/COUT/CCP1
TABLE 1:
I/O
8-PIN SUMMARY
Pin
Analog
Comparators
Timer
CCP
Interrupts
Pull-ups
Basic
GP0
AN0
CIN+
IOC
ICSPDAT/ULPWU
GP1
AN1/VREF
CIN-
IOC
ICSPCLK
GP2
AN2
COUT
T0CKI
CCP1
INT/IOC
MCLR/VPP
GP3(1)
IOC
Y(2)
GP4
AN3
T1G
IOC
OSC2/CLKOUT
GP5
T1CKI
IOC
OSC1/CLKIN
VDD
VSS
Note 1:
2:
Input only.
Only when pin is configured for external MCLR.
DS41211D-page 2
PIC12F683
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 5
2.0 Memory Organization ................................................................................................................................................................... 7
3.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 19
4.0 GPIO Port................................................................................................................................................................................... 31
5.0 Timer0 Module ........................................................................................................................................................................... 41
6.0 Timer1 Module with Gate Control............................................................................................................................................... 44
7.0 Timer2 Module ........................................................................................................................................................................... 49
8.0 Comparator Module.................................................................................................................................................................... 51
9.0 Analog-to-Digital Converter (ADC) Module ................................................................................................................................ 61
10.0 Data EEPROM Memory ............................................................................................................................................................. 71
11.0 Capture/Compare/PWM (CCP) Module ..................................................................................................................................... 75
12.0 Special Features of the CPU...................................................................................................................................................... 83
13.0 Instruction Set Summary .......................................................................................................................................................... 101
14.0 Development Support............................................................................................................................................................... 111
15.0 Electrical Specifications............................................................................................................................................................ 115
16.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 137
17.0 Packaging Information.............................................................................................................................................................. 159
Appendix A: Data Sheet Revision History.......................................................................................................................................... 165
Appendix B: Migrating From Other PIC Devices ............................................................................................................................. 165
The Microchip Web Site ..................................................................................................................................................................... 171
Customer Change Notification Service .............................................................................................................................................. 171
Customer Support .............................................................................................................................................................................. 171
Reader Response .............................................................................................................................................................................. 172
Product Identification System ............................................................................................................................................................ 173
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
Microchips Worldwide Web site; http://www.microchip.com
Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
DS41211D-page 3
PIC12F683
NOTES:
DS41211D-page 4
PIC12F683
1.0
DEVICE OVERVIEW
FIGURE 1-1:
Program
Bus
Data Bus
Program Counter
GP0
GP1
GP2
RAM
128 bytes
8-Level Stack
(13-bit)
GP3
GP4
File
Registers
14
RAM Addr
GP5
9
Addr MUX
Instruction Reg
7
Direct Addr
Indirect
Addr
FSR Reg
STATUS Reg
8
MUX
Power-up
Timer
Instruction
Decode &
Control
Oscillator
Start-up Timer
Timing
Generation
OSC1/CLKIN
ALU
Power-on
Reset
Watchdog
Timer
W Reg
Brown-out
Reset
OSC2/CLKOUT
Internal
Oscillator
Block
CCP1
T1G
MCLR
VDD
VSS
T1CKI
Timer0
Timer1
Timer2
CCP
T0CKI
Analog-to-Digital Converter
EEDATA
1 Analog Comparator
8
256 bytes
Data
EEPROM
EEADDR
VREF
CVREF
CIN-
CIN+
COUT
DS41211D-page 5
PIC12F683
TABLE 1-1:
VDD
GP5/T1CKI/OSC1/CLKIN
GP4/AN3/T1G/OSC2/CLKOUT
GP3/MCLR/VPP
GP2/AN2/T0CKI/INT/COUT/CCP1
GP1/AN1/CIN-/VREF/ICSPCLK
GP0/AN0/CIN+/ICSPDAT/ULPWU
VSS
Legend:
Function
Input
Type
Output
Type
VDD
Power
Positive supply
GP5
TTL
CMOS
T1CKI
ST
Timer1 clock
OSC1
XTAL
Crystal/Resonator
CLKIN
ST
GP4
TTL
CMOS
AN3
AN
T1G
ST
OSC2
XTAL
Crystal/Resonator
CLKOUT
CMOS
FOSC/4 output
Timer1 gate
GP3
TTL
MCLR
ST
VPP
HV
Programming voltage
GP2
ST
CMOS
AN2
AN
T0CKI
ST
INT
ST
External Interrupt
COUT
CMOS
Comparator 1 output
CCP1
ST
CMOS
GP1
TTL
CMOS
AN1
AN
CIN-
AN
VREF
AN
ICSPCLK
ST
GP0
TTL
CMOS
AN0
AN
CIN+
AN
Comparator 1 input
ICSPDAT
ST
CMOS
ULPWU
AN
VSS
Power
Ground reference
DS41211D-page 6
Description
PIC12F683
2.0
MEMORY ORGANIZATION
2.1
FIGURE 2-1:
CALL, RETURN
RETFIE, RETLW
2.2
Bank 0 is selected
Bank 1 is selected
13
Note:
Stack Level 1
Stack Level 2
Stack Level 8
Reset Vector
0000h
Interrupt Vector
0004h
0005h
On-chip Program
Memory
07FFh
0800h
Wraps to 0000h-07FFh
1FFFh
DS41211D-page 7
PIC12F683
2.2.1
2.2.2
FIGURE 2-2:
File
Address
Indirect addr.(1)
00h
Indirect addr.(1)
80h
TMR0
01h
OPTION_REG
81h
PCL
02h
PCL
82h
STATUS
03h
STATUS
83h
FSR
04h
FSR
84h
GPIO
05h
TRISIO
85h
06h
86h
07h
87h
08h
88h
09h
89h
PCLATH
0Ah
PCLATH
8Ah
INTCON
0Bh
INTCON
8Bh
PIR1
0Ch
PIE1
8Ch
0Dh
8Dh
TMR1L
0Eh
PCON
8Eh
TMR1H
0Fh
OSCCON
8Fh
T1CON
10h
OSCTUNE
90h
TMR2
11h
T2CON
12h
CCPR1L
13h
CCPR1H
14h
CCP1CON
15h
WPU
95h
16h
IOC
96h
91h
PR2
92h
93h
94h
17h
97h
WDTCON
18h
CMCON0
19h
VRCON
99h
CMCON1
1Ah
EEDAT
9Ah
1Bh
EEADR
9Bh
1Ch
EECON1
9Ch
1Dh
EECON2(1)
9Dh
ADRESH
1Eh
ADRESL
9Eh
ADCON0
1Fh
ANSEL
General
Purpose
Registers
32 Bytes
9Fh
A0h
20h
General
Purpose
Registers
98h
BFh
C0h
96 Bytes
Accesses 70h-7Fh
7Fh
BANK 0
EFh
F0h
FFh
BANK 1
DS41211D-page 8
PIC12F683
TABLE 2-1:
Addr
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Page
Bank 0
00h
INDF
01h
TMR0
02h
PCL
03h
STATUS
04h
FSR
05h
GPIO
Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 17, 90
(1)
IRP
RP1
(1)
RP0
TO
PD
DC
GP3
GP2
GP1
GP0
GP5
GP4
06h
Unimplemented
07h
Unimplemented
08h
Unimplemented
09h
Unimplemented
INTCON
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
PIR1
EEIF
ADIF
CCP1IF
CMIF
OSFIF
TMR2IF
0Ah
PCLATH
0Bh
0Ch
0Dh
Unimplemented
0Eh
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1
0Fh
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1
10h
T1CON
11h
TMR2
T1GINV
12h
T2CON
13h
CCPR1L
14h
CCPR1H
15h
CCP1CON
16h
Unimplemented
17h
Unimplemented
18h
WDTCON
WDTPS3
WDTPS2
WDTPS1
WDTPS0
19h
CMCON0
COUT
CINV
CIS
CM2
CM1
1Ah
CMCON1
T1GSS
1Bh
Unimplemented
1Ch
Unimplemented
1Dh
Unimplemented
1Eh
ADRESH
1Fh
ADCON0
Legend:
Note 1:
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 50, 90
DC1B1
DC1B0
CCP1M2
CCP1M1
Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result
ADFM
VCFG
CHS1
CHS0
GO/DONE
DS41211D-page 9
PIC12F683
TABLE 2-2:
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Page
Bank 1
80h
INDF
81h
OPTION_REG
Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 17, 90
82h
PCL
GPPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
RP1(1)
RP0
TO
PD
DC
83h
STATUS
84h
FSR
85h
TRISIO
86h
Unimplemented
87h
Unimplemented
88h
Unimplemented
89h
Unimplemented
TRISIO5
TRISIO4
TRISIO2
TRISIO1
8Ah
PCLATH
8Bh
INTCON
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
EEIE
ADIE
CCP1IE
CMIE
OSFIE
TMR2IE
8Ch PIE1
8Dh
GPIF
Unimplemented
8Eh
PCON
POR
BOR
8Fh
OSCCON
IRCF2
IRCF1
IRCF0
OSTS(2)
HTS
LTS
SCS
90h
OSCTUNE
TUN4
TUN3
TUN2
TUN1
TUN0
91h
92h
PR2
ULPWUE SBOREN
Unimplemented
93h
Unimplemented
94h
Unimplemented
(3)
95h
WPU
WPU5
WPU4
WPU2
WPU1
WPU0
96h
IOC
IOC5
IOC4
IOC3
IOC2
IOC1
IOC0
97h
Unimplemented
98h
Unimplemented
99h
VRCON
VREN
VRR
VR3
VR2
VR1
9Ah
EEDAT
EEDAT7
EEDAT6
EEDAT5
EEDAT4
EEDAT3
EEDAT2
EEDAT1
9Bh
EEADR
EEADR7
EEADR6
EEADR5
EEADR4
EEADR3
EEADR2
EEADR1
WRERR
WREN
WR
9Ch EECON1
VR0
RD
9Dh EECON2
9Eh
ADRESL
Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result
9Fh
ANSEL
Legend:
Note 1:
2:
3:
ADCS2
ADCS1
ADCS0
ANS3
ANS2
ANS1
DS41211D-page 10
PIC12F683
2.2.2.1
STATUS Register
REGISTER 2-1:
Reserved
Reserved
R/W-0
R-1
R-1
R/W-x
R/W-x
R/W-x
IRP
RP1
RP0
TO
PD
DC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions), For Borrow, the polarity is
reversed.
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0
Note 1:
For Borrow, the polarity is reversed. A subtraction is executed by adding the twos complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.
DS41211D-page 11
PIC12F683
2.2.2.2
OPTION Register
Note:
TMR0/WDT prescaler
External GP2/INT interrupt
TMR0
Weak pull-ups on GPIO
REGISTER 2-2:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
GPPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
Note 1:
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
A dedicated 16-bit WDT postscaler is available. See Section 12.6 Watchdog Timer (WDT) for more
information.
DS41211D-page 12
PIC12F683
2.2.2.3
INTCON Register
Note:
REGISTER 2-3:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
DS41211D-page 13
PIC12F683
2.2.2.4
PIE1 Register
REGISTER 2-4:
Note:
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
EEIE
ADIE
CCP1IE
CMIE
OSFIE
TMR2IE
TMR1IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
Unimplemented: Read as 0
bit 3
bit 2
bit 1
bit 0
DS41211D-page 14
x = Bit is unknown
PIC12F683
2.2.2.5
PIR1 Register
REGISTER 2-5:
Note:
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
EEIF
ADIF
CCP1IF
CMIF
OSFIF
TMR2IF
TMR1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
Unimplemented: Read as 0
bit 3
bit 2
bit 1
bit 0
DS41211D-page 15
PIC12F683
2.2.2.6
PCON Register
REGISTER 2-6:
U-0
U-0
R/W-0
R/W-1
U-0
U-0
R/W-0
R/W-x
ULPWUE
SBOREN
POR
BOR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as 0
bit 5
bit 4
bit 3-2
Unimplemented: Read as 0
bit 1
bit 0
Note 1:
Set BOREN<1:0> = 01 in the Configuration Word register for this bit to control the BOR.
DS41211D-page 16
PIC12F683
2.3
FIGURE 2-3:
12
Instruction with
0 PCL as
Destination
PCLATH<4:0>
ALU Result
PCLATH
PCH
11 10
PCL
8
PC
GOTO, CALL
2
PCLATH<4:3>
11
OPCODE<10:0>
PCLATH
2.3.1
COMPUTED GOTO
2.3.2
2.4
PCL
PC
12
LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
EXAMPLE 2-1:
MOVLW
MOVWF
NEXT
CLRF
INCF
BTFSS
GOTO
CONTINUE
INDIRECT ADDRESSING
0x20
FSR
INDF
FSR
FSR,4
NEXT
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
;all done?
;no clear next
;yes continue
STACK
DS41211D-page 17
PIC12F683
FIGURE 2-4:
Direct Addressing
RP1
(1)
RP0
Bank Select
Indirect Addressing
From Opcode
IRP(1)
Bank Select
Location Select
00
01
10
Location Select
11
00h
180h
Data
Memory
Not Used
7Fh
1FFh
Bank 0
Bank 1
Bank 2
Bank 3
The RP1 and IRP bits are reserved; always maintain these bits clear.
DS41211D-page 18
PIC12F683
3.0
3.1
Overview
1.
2.
3.
4.
5.
6.
7.
8.
FIGURE 3-1:
External Oscillator
OSC2
Sleep
MUX
OSC1
IRCF<2:0>
(OSCCON Register)
8 MHz
Internal Oscillator
4 MHz
System Clock
(CPU and Peripherals)
INTOSC
111
110
101
1 MHz
100
500 kHz
250 kHz
125 kHz
LFINTOSC
31 kHz
31 kHz
011
MUX
HFINTOSC
8 MHz
Postscaler
2 MHz
010
001
000
DS41211D-page 19
PIC12F683
3.2
Oscillator Control
REGISTER 3-1:
U-0
R/W-1
R/W-1
R/W-0
R-1
R-0
R-0
R/W-0
IRCF2
IRCF1
IRCF0
OSTS(1)
HTS
LTS
SCS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Read as 0
bit 6-4
bit 3
bit 2
bit 1
bit 0
Note 1:
Bit resets to 0 with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe
mode is enabled.
DS41211D-page 20
PIC12F683
3.3
3.4.1
TABLE 3-1:
3.4
Switch From
Switch To
Frequency
Oscillator Delay
Sleep/POR
LFINTOSC
HFINTOSC
31 kHz
125 kHz to 8 MHz
Sleep/POR
EC, RC
DC 20 MHz
2 instruction cycles
EC, RC
DC 20 MHz
1 cycle of each
Sleep/POR
LP, XT, HS
32 kHz to 20 MHz
HFINTOSC
1 s (approx.)
3.4.2
EC MODE
FIGURE 3-2:
Clock from
Ext. System
PIC MCU
I/O
Note 1:
OSC2/CLKOUT(1)
DS41211D-page 21
PIC12F683
3.4.3
FIGURE 3-3:
CERAMIC RESONATOR
OPERATION
(XT OR HS MODE)
QUARTZ CRYSTAL
OPERATION (LP, XT OR
HS MODE)
OSC1/CLKIN
C1
PIC MCU
OSC1/CLKIN
C1
PIC MCU
To Internal
Logic
RP(3)
RF(2)
Sleep
To Internal
Logic
Quartz
Crystal
C2
FIGURE 3-4:
RS(1)
RF(2)
Sleep
OSC2/CLKOUT
Note 1:
2:
DS41211D-page 22
C2 Ceramic
RS(1)
Resonator
OSC2/CLKOUT
PIC12F683
3.4.4
EXTERNAL RC MODES
3.5
FIGURE 3-5:
VDD
EXTERNAL RC MODES
PIC MCU
REXT
OSC1/CLKIN
Internal
Clock
CEXT
VSS
FOSC/4 or
I/O(2)
OSC2/CLKOUT(1)
2.
3.5.1
3.5.2
HFINTOSC
DS41211D-page 23
PIC12F683
3.5.2.1
OSCTUNE Register
REGISTER 3-2:
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TUN4
TUN3
TUN2
TUN1
TUN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-5
Unimplemented: Read as 0
bit 4-0
00001 =
00000 = Oscillator module is running at the calibrated frequency.
11111 =
DS41211D-page 24
x = Bit is unknown
PIC12F683
3.5.3
LFINTOSC
3.5.4
8 MHz
4 MHz (Default after Reset)
2 MHz
1 MHz
500 kHz
250 kHz
125 kHz
31 kHz (LFINTOSC)
Note:
3.5.5
6.
DS41211D-page 25
PIC12F683
FIGURE 3-6:
LF(1)
HF
HFINTOSC
HFINTOSC
Start-up Time
2-cycle Sync
Running
LFINTOSC
0
IRCF <2:0>
=0
System Clock
Note 1:
HFINTOSC
HFINTOSC
2-cycle Sync
Running
LFINTOSC
IRCF <2:0>
=0
System Clock
LFINTOSC
HFINTOSC
LFINTOSC turns off unless WDT or FSCM is enabled
LFINTOSC
Start-up Time 2-cycle Sync
Running
HFINTOSC
IRCF <2:0>
=0
System Clock
DS41211D-page 26
PIC12F683
3.6
Clock Switching
3.6.1
3.6.2
3.7
3.7.1
3.7.2
1.
2.
3.
4.
5.
6.
7.
TWO-SPEED START-UP
SEQUENCE
DS41211D-page 27
PIC12F683
3.7.3
FIGURE 3-7:
TWO-SPEED START-UP
HFINTOSC
TOST
OSC1
1022 1023
OSC2
Program Counter
PC - N
PC
PC + 1
System Clock
DS41211D-page 28
PIC12F683
3.8
3.8.3
FIGURE 3-8:
External
Clock
LFINTOSC
Oscillator
64
31 kHz
(~32 s)
488 Hz
(~2 ms)
3.8.4
3.8.1
Clock
Failure
Detected
FAIL-SAFE DETECTION
3.8.2
Sample Clock
FAIL-SAFE OPERATION
DS41211D-page 29
PIC12F683
FIGURE 3-9:
Sample Clock
Oscillator
Failure
System
Clock
Output
Clock Monitor Output
(Q)
Failure
Detected
OSCFIF
Test
Note:
Test
Test
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
TABLE 3-2:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets(1)
CONFIG(2)
CPD
CP
MCLRE
PWRTE
WDTE
FOSC2
FOSC1
FOSC0
INTCON
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
0000 0000
0000 000x
OSCCON
IRCF2
IRCF1
IRCF0
OSTS
HTS
LTS
SCS
-110 x000
-110 x000
Name
OSCTUNE
PIE1
PIR1
Legend:
Note 1:
2:
TUN4
TUN3
TUN2
TUN1
TUN0
---0 0000
---u uuuu
EEIE
ADIE
CCP1IE
CMIE
OSFIE
TMR2IE
TMR1IE
000- 0000
000- 0000
EEIF
ADIF
CCP1IF
CMIF
OSFIF
TMR2IF
TMR1IF
000- 0000
000- 0000
x = unknown, u = unchanged, = unimplemented locations read as 0. Shaded cells are not used by oscillators.
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
See Configuration Word register (Register 12-1) for operation of all register bits.
DS41211D-page 30
PIC12F683
4.0
GPIO PORT
4.1
REGISTER 4-1:
EXAMPLE 4-1:
BANKSEL
CLRF
MOVLW
MOVWF
BANKSEL
CLRF
MOVLW
MOVWF
GPIO
GPIO
07h
CMCON0
ANSEL
ANSEL
0Ch
TRISIO
INITIALIZING GPIO
;
;Init GPIO
;Set GP<2:0> to
;digital I/O
;
;digital I/O
;Set GP<3:2> as inputs
;and set GP<5:4,1:0>
;as outputs
U-0
U-0
R/W-x
R/W-0
R-x
R/W-0
R/W-0
R/W-0
GP5
GP4
GP3
GP2
GP1
GP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
x = Bit is unknown
DS41211D-page 31
PIC12F683
REGISTER 4-2:
U-0
U-0
R/W-1
R/W-1
R-1
R/W-1
R/W-1
R/W-1
TRISIO5(2,3)
TRISIO4(2)
TRISIO3(1)
TRISIO2
TRISIO1
TRISIO0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5:4
bit 3
bit 2:0
Note 1:
2:
3:
4.2
x = Bit is unknown
4.2.3
INTERRUPT-ON-CHANGE
4.2.1
ANSEL REGISTER
4.2.2
WEAK PULL-UPS
DS41211D-page 32
PIC12F683
REGISTER 4-3:
U-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-1
R/W-1
R/W-1
ADCS2
ADCS1
ADCS0
ANS3
ANS2
ANS1
ANS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 0
bit 6-4
bit 3-0
Note 1:
x = Bit is unknown
Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups and interrupt-on-change,
if available. The corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on
the pin.
DS41211D-page 33
PIC12F683
REGISTER 4-4:
U-0
U-0
R/W-1
R/W-1
U-0
R/W-1
R/W-1
R/W-1
WPU5
WPU4
WPU2
WPU1
WPU0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-4
bit 3
Unimplemented: Read as 0
bit 2-0
Note 1:
2:
3:
4:
x = Bit is unknown
REGISTER 4-5:
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IOC5
IOC4
IOC3
IOC2
IOC1
IOC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
Note 1:
2:
x = Bit is unknown
Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized.
IOC<5:4> always reads 0 in XT, HS and LP OSC modes.
DS41211D-page 34
PIC12F683
4.2.4
Note:
For more information, refer to the Application Note AN879, Using the Microchip
Ultra Low-Power Wake-up Module
(DS00879).
EXAMPLE 4-2:
BANKSEL
MOVLW
MOVWF
BANKSEL
BCF
BCF
BANKSEL
BSF
CALL
BANKSEL
BSF
BSF
BSF
MOVLW
MOVWF
SLEEP
NOP
ULTRA LOW-POWER
WAKE-UP INITIALIZATION
CMCON0
H7
CMCON0
ANSEL
ANSEL,0
TRISA,0
PORTA
PORTA,0
CapDelay
PCON
PCON,ULPWUE
IOCA,0
TRISA,0
B10001000
INTCON
;
;Turn off
;comparators
;
;RA0 to digital I/O
;Output high to
;
;charge capacitor
;
;
;Enable ULP Wake-up
;Select RA0 IOC
;RA0 to input
;Enable interrupt
; and clear flag
;Wait for IOC
;
DS41211D-page 35
PIC12F683
4.2.5
4.2.5.1
Figure 4-1 shows the diagram for this pin. The GP0 pin
is configurable to function as one of the following:
FIGURE 4-1:
GP0/AN0/CIN+/ICSPDAT/ULPWU
Weak
CK Q
GPPU
RD
WPU
VDD
D
WR
GPIO
Q
I/O pin
CK Q
VSS
+
D
WR
TRISIO
VT
CK Q
IULP
0
RD
TRISIO
Analog
Input Mode(1)
VSS
ULPWUE
RD
GPIO
D
WR
IOC
CK Q
D
EN
RD
IOC
Q3
D
EN
Interrupt-onChange
RD GPIO
To Comparator
To A/D Converter
Note
DS41211D-page 36
1:
PIC12F683
4.2.5.2
GP1/AN1/CIN-/VREF/ICSPCLK
4.2.5.3
GP2/AN2/T0CKI/INT/COUT/CCP1
Figure 4-2 shows the diagram for this pin. The GP1 pin
is configurable to function as one of the following:
Figure 4-3 shows the diagram for this pin. The GP2 pin
is configurable to function as one of the following:
FIGURE 4-2:
Data
Bus
WR
WPU
Analog
Input Mode(1)
Weak
Data
Bus
GPPU
RD
WPU
D
WR
GPIO
FIGURE 4-3:
VDD
CK Q
WR
WPU
CK
Analog
Input Mode
VDD
Weak
GPPU
RD
WPU
VDD
Analog
Input
Mode
COUT
Enable
CK Q
D
VDD
I/O pin
D
WR
TRISIO
WR
GPIO
CK Q
RD
GPIO
CK Q
D
EN
RD
IOC
1
I/O pin
CK
VSS
Analog
Input Mode
RD
TRISIO
COUT
0
D
WR
TRISIO
VSS
Analog
Input Mode(1)
RD
TRISIO
WR
IOC
CK
RD
GPIO
Q3
D
WR
IOC
CK
EN
EN
Interrupt-onchange
RD
IOC
RD GPIO
To Comparator
Q
Q3
D
EN
Interrupt-onchange
To A/D Converter
RD GPIO
Note 1: Comparator mode and ANSEL determines Analog
Input mode.
To Timer0
To INT
To A/D Converter
Note
1:
DS41211D-page 37
PIC12F683
4.2.5.4
GP3/MCLR/VPP
4.2.5.5
GP4/AN3/T1G/OSC2/CLKOUT
Figure 4-4 shows the diagram for this pin. The GP3 pin
is configurable to function as one of the following:
Figure 4-5 shows the diagram for this pin. The GP4 pin
is configurable to function as one of the following:
FIGURE 4-4:
Data
Bus
MCLRE
Reset
RD
TRISIO
MCLRE
D
CK
VSS
Q
Q
FIGURE 4-5:
Input
pin
VSS
RD
GPIO
WR
IOC
Weak
Data
Bus
WR
WPU
D
CK
VDD
Weak
GPPU
RD
WPU
Oscillator
Circuit
Q
EN
RD
IOC
Interrupt-onchange
CLK(1)
Modes
OSC1
Q3
VDD
CLKOUT
Enable
D
D
EN
WR
GPIO
FOSC/4
1
0
CK Q
I/O pin
CLKOUT
Enable
RD GPIO
VSS
D
WR
TRISIO
INTOSC/
RC/EC(2)
CK Q
CLKOUT
Enable
RD
TRISIO
Analog
Input Mode
RD
GPIO
D
WR
IOC
Q
Q
CK Q
D
EN
RD
IOC
Q3
D
EN
Interrupt-onchange
RD GPIO
To T1G
To A/D Converter
Note 1: CLK modes are XT, HS, LP, optional LP oscillator and
CLKOUT Enable.
2: With CLKOUT option.
DS41211D-page 38
PIC12F683
4.2.5.6
GP5/T1CKI/OSC1/CLKIN
FIGURE 4-6:
Figure 4-6 shows the diagram for this pin. The GP5 pin
is configurable to function as one of the following:
Data
Bus
VDD
WR
WPU
TMR1LPEN(1)
CK
Weak
Q
GPPU
RD
WPU
Oscillator
Circuit
OSC2
D
WR
GPIO
VDD
CK
I/O pin
Q
D
WR
TRISIO
CK
VSS
INTOSC
Mode
RD
TRISIO
(1)
RD
GPIO
D
CK
WR
IOC
Q
EN
Q3
RD
IOC
Q
D
EN
Interrupt-onchange
RD GPIO
To Timer1 or CLKGEN
Note
TABLE 4-1:
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
ANSEL
ADCS2
ADCS1
ADCS0
ANS3
ANS2
ANS1
ANS0
-000 1111
-000 1111
CCP1CON
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
--00 0000
--00 0000
CMCON0
COUT
CINV
CIS
CM2
CM1
CM0
-0-0 0000
-0-0 0000
PCON
ULPWUE
SBOREN
POR
BOR
--01 --qq
--0u --uu
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
0000 0000
0000 000x
IOC5
IOC4
IOC3
IOC2
IOC1
IOC0
--00 0000
--00 0000
GPPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
GP5
GP4
GP3
GP2
GP1
GP0
--xx xxxx
--x0 x000
0000 0000
INTCON
IOC
OPTION_REG
GPIO
T1CON
T1GINV
TMR1GE
T1SYNC
TMR1CS
TMR1ON
0000 0000
TRISIO
TRISIO5
TRISIO4
TRISIO3
TRISIO2
TRISIO1
TRISIO0
--11 1111
--11 1111
WPU
WPU5
WPU4
WPU2
WPU1
WPU0
--11 -111
--11 -111
Legend:
x = unknown, u = unchanged, = unimplemented locations read as 0. Shaded cells are not used by GPIO.
DS41211D-page 39
PIC12F683
NOTES:
DS41211D-page 40
PIC12F683
5.0
TIMER0 MODULE
5.1
Timer0 Operation
5.1.1
5.1.2
FIGURE 5-1:
FOSC/4
Data Bus
0
8
1
Sync
2 Tcy
1
T0CKI
pin
TMR0
0
0
T0SE
T0CS
8-bit
Prescaler
PSA
1
8
PSA
WDTE
SWDTEN
PS<2:0>
16-bit
Prescaler
31 kHz
INTOSC
1
WDT
Time-out
0
16
Watchdog
Timer
PSA
WDTPS<3:0>
Note
1:
2:
3:
DS41211D-page 41
PIC12F683
5.1.3
SOFTWARE PROGRAMMABLE
PRESCALER
5.1.3.1
EXAMPLE 5-1:
BANKSEL
CLRWDT
CLRF
CHANGING PRESCALER
(TIMER0 WDT)
TMR0
TMR0
BANKSEL
BSF
CLRWDT
OPTION_REG
OPTION_REG,PSA
MOVLW
ANDWF
IORLW
MOVWF
b11111000
OPTION_REG,W
b00000101
OPTION_REG
DS41211D-page 42
;
;Clear WDT
;Clear TMR0 and
;prescaler
;
;Select WDT
;
;
;Mask prescaler
;bits
;Set WDT prescaler
;to 1:32
EXAMPLE 5-2:
CHANGING PRESCALER
(WDT TIMER0)
CLRWDT
5.1.4
TIMER0 INTERRUPT
5.1.5
PIC12F683
REGISTER 5-1:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
GPPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
000
001
010
011
100
101
110
111
Note 1:
Name
TMR0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
INTCON
OPTION_REG
TRISIO
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
A dedicated 16-bit WDT postscaler is available. See Section 12.6 Watchdog Timer (WDT) for more
information.
TABLE 5-1:
Legend:
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
Value on
all other
Resets
xxxx xxxx
uuuu uuuu
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
0000 0000
0000 000x
GPPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
--11 1111
--11 1111
= Unimplemented locations, read as 0, u = unchanged, x = unknown. Shaded cells are not used by the Timer0
module.
DS41211D-page 43
PIC12F683
6.0
6.1
Timer1 Operation
6.2
TMR1CS
FOSC/4
T1CKI pin
FIGURE 6-1:
T1GINV
TMR1ON
Set flag bit
TMR1IF on
Overflow
To Comparator Module
Timer1 Clock
TMR1(2)
TMR1H
TMR1L
Synchronized
clock input
EN
1
Oscillator
(1)
T1SYNC
OSC1/T1CKI
OSC2/T1G
1
FOSC/4
Internal
Clock
Synchronize(3)
Prescaler
1, 2, 4, 8
det
0
2
T1CKPS<1:0>
TMR1CS
1
INTOSC
Without CLKOUT
T1OSCEN
COUT
0
T1GSS
Note 1:
2:
3:
DS41211D-page 44
ST Buffer is low power type when using LP oscillator, or high speed type when using T1CKI.
Timer1 register increments on rising edge.
Synchronize does not operate while in Sleep.
PIC12F683
6.2.1
6.2.2
6.5
6.3
6.4
Timer1 Oscillator
6.5.1
Timer1 Prescaler
Timer1 Operation in
Asynchronous Counter Mode
6.6
Timer1 Gate
DS41211D-page 45
PIC12F683
6.7
Timer1 Interrupt
6.9
In this mode of operation, the CCPR1H:CCPR1L register pair effectively becomes the period register for
Timer1.
Note:
6.8
FIGURE 6-2:
6.10
Comparator Synchronization
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1:
2:
DS41211D-page 46
PIC12F683
6.11
REGISTER 6-1:
R/W-0
R/W-0
(1)
T1GINV
TMR1GE
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5-4
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
x = Bit is unknown
DS41211D-page 47
PIC12F683
TABLE 6-1:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
CONFIG(1)
CPD
CP
MCLRE
PWRTE
WDTE
FOSC2
FOSC1
FOSC0
T1GSS
CMSYNC
---- --10
---- --10
0000 000x
CMCON1
Bit 0
Value on
POR, BOR
Name
INTCON
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
0000 0000
PIE1
EEIE
ADIE
CCP1IE
CMIE
OSFIE
TMR2IE
TMR1IE
000- 0000
000- 0000
PIR1
EEIF
ADIF
CCP1IF
CMIF
OSFIF
TMR2IF
TMR1IF
000- 0000
000- 0000
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
uuuu uuuu
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
uuuu uuuu
0000 0000
uuuu uuuu
T1CON
Legend:
Note 1:
T1GINV
TMR1GE
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
x = unknown, u = unchanged, = unimplemented, read as 0. Shaded cells are not used by the Timer1 module.
See Configuration Word register (Register 12-1) for operation of all register bits.
DS41211D-page 48
PIC12F683
7.0
TIMER2 MODULE
7.1
Timer2 Operation
FIGURE 7-1:
FOSC/4
Prescaler
1:1, 1:4, 1:16
2
TMR2
Sets Flag
bit TMR2IF
Reset
Comparator
EQ
Postscaler
1:1 to 1:16
T2CKPS<1:0>
PR2
4
TOUTPS<3:0>
DS41211D-page 49
PIC12F683
REGISTER 7-1:
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TOUTPS3
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 0
bit 6-3
bit 2
bit 1-0
TABLE 7-1:
Name
Bit 7
x = Bit is unknown
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
INTCON
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
0000 0000
0000 000x
PIE1
EEIE
ADIE
CCP1IE
CMIE
OSFIE
TMR2IE
TMR1IE
000- 0000
000- 0000
EEIF
ADIF
CCP1IF
CMIF
OSFIF
TMR2IF
TMR1IF
PIR1
000- 0000
000- 0000
PR2
1111 1111
1111 1111
TMR2
0000 0000
0000 0000
-000 0000
-000 0000
T2CON
Legend:
x = unknown, u = unchanged, - = unimplemented read as 0. Shaded cells are not used for Timer2 module.
DS41211D-page 50
TOUTPS3
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
PIC12F683
8.0
COMPARATOR MODULE
FIGURE 8-1:
VIN+
VIN-
Output
VINVIN+
8.1
SINGLE COMPARATOR
Output
Note:
Comparator Overview
FIGURE 8-2:
Port Pins
MULTIPLEX
To Timer1 Gate
CINV
0
To COUT pin
D
Timer1
clock source(1)
Q1
EN
To Data Bus
RD CMCON0
Set CMIF bit
D
Q3*RD CMCON0
EN
CL
Reset
Note 1:
2:
3:
DS41211D-page 51
PIC12F683
8.2
FIGURE 8-3:
Rs < 10K
RIC
To ADC Input
AIN
VA
CPIN
5 pF
VT 0.6V
ILEAKAGE
500 nA
Vss
Legend: CPIN
= Input Capacitance
ILEAKAGE = Leakage Current at the pin due to various junctions
RIC
= Interconnect Resistance
= Source Impedance
RS
= Analog Voltage
VA
VT
= Threshold Voltage
DS41211D-page 52
PIC12F683
8.3
Comparator Configuration
FIGURE 8-4:
CM<2:0> = 000
CM<2:0> = 100
CINCIN+
A
Off
(1)
CIN-
CIN+
I/O
COUT
CM<2:0> = 001
CM<2:0> = 101
CIN-
CIN+
COUT
COUT (pin) D
CIN-
CIN+
CIS = 0
CIS = 1
COUT
COUT (pin) D
From CVREF Module
CM<2:0> = 010
CM<2:0> = 110
CINCIN+
COUT (pin)
CINCOUT
CIN+
COUT (pin)
I/O
CIS = 0
CIS = 1
COUT
I/O
From CVREF Module
CM<2:0> = 011
CM<2:0> = 111
CIN-
CIN+
I/O
COUT
COUT (pin) D
From CVREF Module
CIN-
I/O
CIN+
I/O
Off(1)
DS41211D-page 53
PIC12F683
8.4
Comparator Control
8.5
Mode selection
Output state
Output polarity
Input switch
8.4.1
CM<2:0> = 001
CM<2:0> = 011
CM<2:0> = 101
When one of the above modes is selected, the associated TRIS bit of the COUT pin must be cleared.
8.4.2
TABLE 8-1:
Input Conditions
CINV
COUT
VIN-
> VIN+
Note:
8.4.3
DS41211D-page 54
PIC12F683
8.6
FIGURE 8-5:
COMPARATOR
INTERRUPT TIMING W/O
CMCON0 READ
Q1
Q3
CIN+
TRT
COUT
Set CMIF (level)
CMIF
reset by software
FIGURE 8-6:
COMPARATOR
INTERRUPT TIMING WITH
CMCON0 READ
Q1
Q3
CIN+
TRT
COUT
Set CMIF (level)
CMIF
cleared by CMCON0 read
reset by software
DS41211D-page 55
PIC12F683
8.7
8.8
Effects of a Reset
REGISTER 8-1:
U-0
R-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
COUT
CINV
CIS
CM2
CM1
CM0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Read as 0
bit 6
bit 5
Unimplemented: Read as 0
bit 4
bit 3
bit 2-0
DS41211D-page 56
PIC12F683
8.9
8.10
REGISTER 8-2:
U-0
U-0
U-0
U-0
U-0
U-0
R/W-1
R/W-0
T1GSS
CMSYNC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7-2
Unimplemented: Read as 0
bit 1
bit 0
Note 1:
2:
DS41211D-page 57
PIC12F683
8.11
EQUATION 8-1:
V RR = 1 (low range):
CVREF = (VR<3:0>/24) V DD
V RR = 0 (high range):
CV REF = (VDD/4) + (VR<3:0> VDD/32)
8.11.1
INDEPENDENT OPERATION
8.11.3
VREN = 0
VRR = 1
VR<3:0> = 0000
8.11.2
REGISTER 8-3:
8.11.4
R/W-0
U-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
VREN
VRR
VR3
VR2
VR1
VR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
Unimplemented: Read as 0
bit 5
bit 4
Unimplemented: Read as 0
bit 3-0
DS41211D-page 58
x = Bit is unknown
PIC12F683
FIGURE 8-7:
VDD
VRR
8R
16-1 Analog
MUX
VREN
15
14
CVREF to
Comparator
Input
2
1
0
VR<3:0>(1)
VREN
VR<3:0> = 0000
VRR
Note 1:
TABLE 8-2:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
ANSEL
ADCS2
ADCS1
ADCS0
ANS3
ANS2
ANS1
ANS0
-000 1111
-000 1111
CMCON0
COUT
CINV
CIS
CM2
CM1
CM0
-0-0 0000
-0-0 0000
CMCON1
T1GSS
CMSYNC
---- --10
---- --10
INTCON
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
0000 0000
0000 000x
PIE1
EEIE
ADIE
CCP1IE
CMIE
OSFIE
TMR2IE
TMR1IE
000- 0000
0000 0000
Name
PIR1
EEIF
ADIF
CCP1IF
CMIF
OSFIF
TMR2IF
TMR1IF
000- 0000
000- 0000
GPIO
GP5
GP4
GP3
GP2
GP1
GP0
--xx xxxx
--uu uuuu
TRISIO
TRISIO0
--11 1111
--11 1111
VRCON
VREN
VR0
0-0- 0000
-0-0 0000
Legend:
VR3
VR2
VR1
x = unknown, u = unchanged, - = unimplemented, read as 0. Shaded cells are not used for comparator.
DS41211D-page 59
PIC12F683
NOTES:
DS41211D-page 60
PIC12F683
9.0
ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
FIGURE 9-1:
VREF
VCFG = 1
GP0/AN0
GP1/AN1/VREF
A/D
GP2/AN2
10
GO/DONE
GP4/AN3
ADFM
CHS
0 = Left Justify
1 = Right Justify
ADON
10
ADRESH
9.1
ADC Configuration
9.1.2
ADRESL
CHANNEL SELECTION
GPIO configuration
Channel selection
ADC voltage reference selection
ADC conversion clock source
Interrupt control
Results formatting
9.1.1
GPIO CONFIGURATION
DS41211D-page 61
PIC12F683
ADC VOLTAGE REFERENCE
9.1.3
9.1.4
CONVERSION CLOCK
The source of the conversion clock is software selectable via the ADCS bits of the ANSEL register. There
are seven possible clock options:
Note:
FOSC/2
FOSC/4
FOSC/8
FOSC/16
FOSC/32
FOSC/64
FRC (dedicated internal oscillator)
TABLE 9-1:
ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES (VDD > 3.0V)
ADCS<2:0>
FOSC/2
20 MHz
000
100
ns(2)
ns(2)
8 MHz
250
ns(2)
500
ns(2)
4 MHz
500
ns(2)
1.0
s(2)
1 MHz
2.0 s
4.0 s
FOSC/4
100
200
FOSC/8
001
400 ns(2)
1.0 s(2)
2.0 s
8.0 s(3)
FOSC/16
101
800 ns(2)
2.0 s
4.0 s
16.0 s(3)
FOSC/32
010
1.6 s
4.0 s
FOSC/64
110
3.2 s
8.0 s(3)
FRC
Legend:
Note 1:
2:
3:
4:
2-6
x11
s(1,4)
2-6
s(3)
32.0 s(3)
16.0 s(3)
64.0 s(3)
s(1,4)
2-6 s(1,4)
8.0
s(1,4)
2-6
FIGURE 9-2:
TCY to TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Conversion Starts
Holding Capacitor is Disconnected from Analog Input (typically 100 ns)
Set GO/DONE bit
DS41211D-page 62
PIC12F683
9.1.5
INTERRUPTS
9.1.6
RESULT FORMATTING
FIGURE 9-3:
(ADFM = 0)
ADRESL
MSB
LSB
bit 7
bit 0
bit 7
Unimplemented: Read as 0
MSB
bit 7
LSB
bit 0
bit 7
Unimplemented: Read as 0
9.2
9.2.1
ADC Operation
STARTING A CONVERSION
COMPLETION OF A CONVERSION
bit 0
10-bit A/D Result
9.2.3
TERMINATING A CONVERSION
9.2.2
bit 0
DS41211D-page 63
PIC12F683
9.2.4
9.2.5
9.2.6
2.
3.
4.
5.
6.
7.
DS41211D-page 64
8.
EXAMPLE 9-1:
A/D
Acquisition
A/D CONVERSION
9.2.7
PIC12F683
REGISTER 9-1:
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
ADFM
VCFG
CHS1
CHS0
GO/DONE
ADON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5-4
Unimplemented: Read as 0
bit 3-2
bit 1
bit 0
DS41211D-page 65
PIC12F683
REGISTER 9-2:
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
ADRES9
ADRES8
ADRES7
ADRES6
ADRES5
ADRES4
ADRES3
ADRES2
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-0
x = Bit is unknown
REGISTER 9-3:
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
ADRES1
ADRES0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-6
bit 5-0
REGISTER 9-4:
x = Bit is unknown
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
ADRES9
ADRES8
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-2
bit 1-0
REGISTER 9-5:
x = Bit is unknown
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
ADRES7
ADRES6
ADRES5
ADRES4
ADRES3
ADRES2
ADRES1
ADRES0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-0
x = Bit is unknown
DS41211D-page 66
PIC12F683
9.3
EQUATION 9-1:
Assumptions:
T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= T AMP + T C + T COFF
= 2s + T C + [ ( Temperature - 25C ) ( 0.05s/C ) ]
The value for TC can be approximated with the following equations:
1
V AP PLIE D 1 ------------ = V CHOLD
2047
TC
----------
RC
V AP P LI ED 1 e = V CHOLD
Tc
---------
1
RC
V AP P LIED 1 e = V A P PLIE D 1 ------------
2047
T C = C HOLD ( R IC + R SS + R S ) ln(1/2047)
= 10pF ( 1k + 7k + 10k ) ln(0.0004885)
= 1.37 s
Therefore:
T ACQ = 2 S + 1.37 S + [ ( 50C- 25C ) ( 0.05 S /C ) ]
= 4.67 S
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
DS41211D-page 67
PIC12F683
FIGURE 9-4:
Rs
CPIN
5 pF
VA
VT = 0.6V
VT = 0.6V
RIC 1k
Sampling
Switch
SS Rss
I LEAKAGE
500 nA
CHOLD = 10 pF
VSS/VREF-
Legend: CPIN
= Input Capacitance
= Threshold Voltage
VT
I LEAKAGE = Leakage current at the pin due to
various junctions
RIC
= Interconnect Resistance
SS
= Sampling Switch
CHOLD
= Sample/Hold Capacitance
FIGURE 9-5:
6V
5V
VDD 4V
3V
2V
RSS
5 6 7 8 9 10 11
Sampling Switch
(k)
Full-Scale Range
3FFh
3FEh
ADC Output Code
3FDh
3FCh
1 LSB ideal
3FBh
Full-Scale
Transition
004h
003h
002h
001h
000h
VSS/VREF-
DS41211D-page 68
Zero-Scale
Transition
VDD/VREF+
PIC12F683
TABLE 9-2:
Name
Bit 7
ADCON0
ADFM
VCFG
ADCS2
ANSEL
Bit 6
Bit 5
Value on
all other
Resets
Value on
POR, BOR
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CHS1
CHS0
GO/DONE
ADON
00-- 0000
0000 0000
ADCS1
ADCS0
ANS3
ANS2
ANS1
ANS0
-000 1111
-000 1111
uuuu uuuu
ADRESH
xxxx xxxx
ADRESL
xxxx xxxx
uuuu uuuu
0000 0000
0000 000x
INTCON
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
PIE1
EEIE
ADIE
CCP1IE
CMIE
OSFIE
TMR2IE
TMR1IE
PIR1
EEIF
ADIF
CCP1IF
CMIF
OSFIF
TMR2IF
TMR1IF
GPIO
GP5
GP4
GP3
GP2
GP1
GP0
TRISIO5
TRISIO4
TRISIO3
TRISIO2
TRISIO1
TRISIO
Legend:
000- 0000
000- 0000
0000 0000
000- 0000
--xx xxxx
--uu uuuu
--11 1111
x = unknown, u = unchanged, = unimplemented read as 0. Shaded cells are not used for ADC module.
DS41211D-page 69
PIC12F683
NOTES:
DS41211D-page 70
PIC12F683
10.0
EECON1
EECON2 (not a physically implemented register)
EEDAT
EEADR
REGISTER 10-1:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EEDAT7
EEDAT6
EEDAT5
EEDAT4
EEDAT3
EEDAT2
EEDAT1
EEDAT0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-0
x = Bit is unknown
REGISTER 10-2:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EEADR7
EEADR6
EEADR5
EEADR4
EEADR3
EEADR2
EEADR1
EEADR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-0
x = Bit is unknown
EEADR: Specifies One of 256 Locations for EEPROM Read/Write Operation bits
DS41211D-page 71
PIC12F683
10.1
REGISTER 10-3:
U-0
U-0
U-0
U-0
R/W-x
R/W-0
R/S-0
R/S-0
WRERR
WREN
WR
RD
bit 7
bit 0
Legend:
S = Bit can only be set
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7-4
Unimplemented: Read as 0
bit 3
bit 2
bit 1
bit 0
DS41211D-page 72
PIC12F683
10.2
EXAMPLE 10-1:
BANKSEL
MOVLW
MOVWF
BSF
MOVF
EEADR
;
CONFIG_ADDR ;
EEADR
;Address to read
EECON1,RD ;EE Read
EEDAT,W
;Move data to W
10.3
Required
Sequence
EXAMPLE 10-2:
BANKSEL
BSF
BCF
BTFSC
GOTO
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
EECON1
EECON1,WREN
INTCON,GIE
INTCON,GIE
$-2
55h
EECON2
AAh
EECON2
EECON1,WR
INTCON,GIE
;
;Enable write
;Disable INTs
;See AN576
;
;Unlock write
;
;
;
;Start the write
;Enable INTS
10.4
Write Verify
EXAMPLE 10-3:
WRITE VERIFY
BANKSELEEDAT
MOVF
EEDAT,W
BSF
EECON1,RD
XORWF
BTFSS
GOTO
:
EEDAT,W
STATUS,Z
WRITE_ERR
10.4.1
;
;EEDAT not changed
;from previous write
;YES, Read the
;value written
;Is data the same
;No, handle error
;Yes, continue
DS41211D-page 73
PIC12F683
10.5
10.6
TABLE 10-1:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
INTCON
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
0000 0000
0000 0000
PIR1
EEIF
ADIF
CCP1IF
CMIF
OSFIF
TMR2IF
TMR1IF
000- 0000
000- 0000
EEIE
ADIE
CCP1IE
CMIE
OSFIE
TMR2IE
TMR1IE
000- 0000
000- 0000
EEDAT
EEDAT7
EEDAT6
EEDAT5
EEDAT4
EEDAT3
EEDAT2
EEDAT1
EEDAT0
0000 0000
0000 0000
EEADR
0000 0000
0000 0000
PIE1
EECON1
WRERR
WREN
WR
RD
---- x000
---- q000
---- ----
---- ----
x = unknown, u = unchanged, = unimplemented read as 0, q = value depends upon condition. Shaded cells are not
used by the Data EEPROM module.
EECON2 is not a physical register.
DS41211D-page 74
PIC12F683
11.0
CAPTURE/COMPARE/PWM
(CCP) MODULE
TABLE 11-1:
CCP Mode
REGISTER 11-1:
Capture
Timer1
Compare
Timer1
PWM
Timer2
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as 0
bit 5-4
bit 3-0
DS41211D-page 75
PIC12F683
11.1
11.1.2
Capture Mode
11.1.1
FIGURE 11-1:
Prescaler
1, 4, 16
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
CCPR1H
and
Edge Detect
11.1.3
SOFTWARE INTERRUPT
11.1.4
CCP PRESCALER
EXAMPLE 11-1:
CLRF
MOVLW
CCPR1L
Capture
Enable
TMR1H
CHANGING BETWEEN
CAPTURE PRESCALERS
BANKSEL CCP1CON
CCP1
pin
MOVWF
TMR1L
CCP1CON<3:0>
System Clock (FOSC)
DS41211D-page 76
PIC12F683
11.2
11.2.2
Compare Mode
FIGURE 11-2:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
CCP1CON<3:0>
Mode Select
S
R
Output
Logic
Match
TRIS
Output Enable
Comparator
TMR1H
TMR1L
11.2.1
11.2.4
CCP1
Pin
11.2.3
DS41211D-page 77
PIC12F683
11.3
PWM Mode
PR2
T2CON
CCPR1L
CCP1CON
FIGURE 11-4:
Period
Pulse Width
TMR2 = PR2
TMR2 = CCPR1L:CCP1CON<5:4>
TMR2 = 0
FIGURE 11-3:
CCPR1H(2) (Slave)
CCP1
Pin
R
Comparator
TMR2
(1)
S
TRIS
Comparator
PR2
Note 1:
2:
Clear Timer2,
toggle CCP1 pin and
latch duty cycle
DS41211D-page 78
PIC12F683
11.3.1
PWM PERIOD
EQUATION 11-2:
EQUATION 11-1:
EQUATION 11-3:
TMR2 is cleared
The CCP1 pin is set. (Exception: If the PWM duty
cycle = 0%, the pin will not be set.)
The PWM duty cycle is latched from CCPR1L into
CCPR1H.
When the 10-bit time base matches the CCPR1H and 2bit latch, then the CCP1 pin is cleared (see Figure 11-1).
11.3.3
EQUATION 11-4:
PWM RESOLUTION
[ 4 ( PR2 + 1 ) ]- bits
Resolution = log
----------------------------------------log ( 2 )
Note:
PWM Frequency
Timer Prescale (1, 4, 16)
PR2 Value
Maximum Resolution (bits)
TABLE 11-3:
PWM RESOLUTION
TABLE 11-2:
CCPR1L:CCP1CON<5:4> -)
Duty Cycle Ratio = (---------------------------------------------------------------------4 ( PR2 + 1 )
11.3.2
PWM PERIOD
Note:
PULSE WIDTH
1.22 kHz
4.88 kHz
19.53 kHz
78.12 kHz
156.3 kHz
208.3 kHz
16
0xFF
0xFF
0xFF
0x3F
0x1F
0x17
10
10
10
6.6
PWM Frequency
Timer Prescale (1, 4, 16)
PR2 Value
Maximum Resolution (bits)
1.22 kHz
4.90 kHz
19.61 kHz
76.92 kHz
153.85 kHz
200.0 kHz
16
0x65
0x65
0x65
0x19
0x0C
0x09
DS41211D-page 79
PIC12F683
11.3.4
11.3.5
11.3.6
11.3.7
4.
5.
EFFECTS OF RESET
Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
6.
DS41211D-page 80
PIC12F683
TABLE 11-4:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
CCP1CON
--00 0000
--00 0000
CCPR1L
xxxx xxxx
xxxx xxxx
CCPR1H
xxxx xxxx
xxxx xxxx
---- --10
---- --10
CMCON1
T1GSS
CMSYNC
INTCON
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
0000 0000
0000 000x
PIE1
EEIE
ADIE
CCP1IE
CMIE
OSFIE
TMR2IE
TMR1IE
000- 0000
000- 0000
PIR1
T1CON
EEIF
ADIF
CCP1IF
CMIF
OSFIF
TMR2IF
TMR1IF
000- 0000
000- 0000
T1GINV
TMR1GE
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
0000 0000
0000 0000
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
xxxx xxxx
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
xxxx xxxx
--11 1111
--11 1111
TRISIO
Legend:
CCP1CON
TRISIO5
TRISIO4
TRISIO3
TRISIO2
TRISIO1
TRISIO0
= Unimplemented locations, read as 0, u = unchanged, x = unknown. Shaded cells are not used by the Capture and Compare.
TABLE 11-5:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
--00 0000
--00 0000
CCPR1L
xxxx xxxx
xxxx xxxx
CCPR1H
xxxx xxxx
xxxx xxxx
0000 000x
INTCON
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
0000 0000
PIE1
EEIE
ADIE
CCP1IE
CMIE
OSFIE
TMR2IE
TMR1IE
000- 0000
-000 0000
PIR1
EEIF
ADIF
CCP1IF
CMIF
OSFIF
TMR2IF
TMR1IF
000- 0000
-000 0000
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
TRISIO5
TRISIO4
TRISIO3
TRISIO2
TRISIO1
TRISIO0
PR2
T2CON
TMR2
TRISIO
Legend:
TOUTPS3
1111 1111
1111 1111
-000 0000
-000 0000
0000 0000
0000 0000
--11 1111
--11 1111
= Unimplemented locations, read as 0, u = unchanged, x = unknown. Shaded cells are not used by the PWM.
DS41211D-page 81
PIC12F683
NOTES:
DS41211D-page 82
PIC12F683
12.0
Note:
12.1
Configuration Bits
DS41211D-page 83
PIC12F683
REGISTER 12-1:
FCMEN
IESO
BOREN1
BOREN0
bit 15
bit 8
CP
CPD
MCLRE
PWRTE
WDTE
FOSC2
FOSC1
FOSC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
P = Programmable
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 15-12
Unimplemented: Read as 1
bit 11
bit 10
bit 9-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
Note 1:
2:
3:
4:
DS41211D-page 84
PIC12F683
12.2
Calibration Bits
12.3
Reset
FIGURE 12-1:
Power-on Reset
MCLR Reset
MCLR Reset during Sleep
WDT Reset
Brown-out Reset (BOR)
MCLR/VPP pin
SLEEP
WDT
Module
WDT
Time-out
Reset
VDD Rise
Detect
Power-on Reset
VDD
Brown-out(1)
Reset
BOREN
SBOREN
OST/PWRT
OST
Chip_Reset
OSC1/
CLKI pin
PWRT
LFINTOSC
Enable PWRT
Enable OST
DS41211D-page 85
PIC12F683
12.3.1
POWER-ON RESET
MCLR
DS41211D-page 86
RECOMMENDED MCLR
CIRCUIT
VDD
R1
1 k (or greater)
PIC
MCU
R2
MCLR
SW1
(optional)
100
(needed with capacitor)
C1
0.1 F
(optional, not critical)
12.3.2
FIGURE 12-2:
12.3.3
Note:
(Section 15.0
PIC12F683
12.3.4
12.3.5
Note:
BOR CALIBRATION
Address 2008h is beyond the user program memory space. It belongs to the
special configuration memory space
(2000h-3FFFh), which can be accessed
only
during
programming.
See
PIC12F6XX/16F6XX Memory Programming Specification (DS41204) for more
information.
FIGURE 12-3:
BROWN-OUT SITUATIONS
VDD
Internal
Reset
VBOR
64 ms(1)
VDD
Internal
Reset
VBOR
< 64 ms
64 ms(1)
VDD
Internal
Reset
Note 1:
VBOR
64 ms(1)
DS41211D-page 87
PIC12F683
12.3.6
TIME-OUT SEQUENCE
12.3.7
TABLE 12-1:
Brown-out Reset
PWRTE = 0
PWRTE = 1
PWRTE = 0
PWRTE = 1
Wake-up from
Sleep
TPWRT + 1024
TOSC
1024 TOSC
TPWRT + 1024
TOSC
1024 TOSC
1024 TOSC
TPWRT
TPWRT
Oscillator Configuration
XT, HS, LP
RC, EC, INTOSC
TABLE 12-2:
POR
BOR
TO
PD
Condition
Power-on Reset
Brown-out Reset
WDT Reset
WDT Wake-up
TABLE 12-3:
Name
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets(1)
CONFIG(2)
BOREN1
BOREN0
CPD
CP
MCLRE
PWRTE
WDTE
FOSC2
FOSC1
FOSC0
POR
BOR
--01 --qq
--0u --uu
PD
DC
0001 1xxx
000q quuu
PCON
STATUS
Legend:
Note 1:
2:
IRP
RP1
ULPWUE SBOREN
RP0
TO
u = unchanged, x = unknown, = unimplemented bit, reads as 0, q = value depends on condition. Shaded cells are not used by BOR.
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
See Configuration Word register (Register 12-1) for operation of all register bits.
DS41211D-page 88
PIC12F683
FIGURE 12-4:
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
TOST
OST Time-out
Internal Reset
FIGURE 12-5:
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
TOST
OST Time-out
Internal Reset
FIGURE 12-6:
MCLR
Internal POR
TPWRT
PWRT Time-out
TOST
OST Time-out
Internal Reset
DS41211D-page 89
PIC12F683
TABLE 12-4:
Register
W
INDF
TMR0
Power-on Reset
MCLR Reset
WDT Reset
Brown-out Reset(1)
xxxx xxxx
uuuu uuuu
uuuu uuuu
00h/80h
xxxx xxxx
xxxx xxxx
uuuu uuuu
01h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCL
02h/82h
0000 0000
0000 0000
PC + 1(3)
STATUS
03h/83h
0001 1xxx
000q quuu(4)
uuuq quuu(4)
FSR
04h/84h
xxxx xxxx
uuuu uuuu
uuuu uuuu
GPIO
05h
--x0 x000
--x0 x000
--uu uuuu
PCLATH
0Ah/8Ah
---0 0000
---0 0000
---u uuuu
INTCON
0Bh/8Bh
0000 0000
0000 0000
uuuu uuuu(2)
PIR1
0Ch
0000 0000
0000 0000
uuuu uuuu(2)
TMR1L
0Eh
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR1H
0Fh
xxxx xxxx
uuuu uuuu
uuuu uuuu
T1CON
10h
0000 0000
uuuu uuuu
-uuu uuuu
TMR2
11h
0000 0000
0000 0000
uuuu uuuu
T2CON
12h
-000 0000
-000 0000
-uuu uuuu
CCPR1L
13h
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR1H
14h
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP1CON
15h
--00 0000
--00 0000
--uu uuuu
WDTCON
18h
---0 1000
---0 1000
---u uuuu
CMCON0
19h
0000 0000
0000 0000
uuuu uuuu
CMCON1
20h
---- --10
---- --10
---- --uu
ADRESH
1Eh
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON0
1Fh
00-- 0000
00-- 0000
uu-- uuuu
OPTION_REG
81h
1111 1111
1111 1111
uuuu uuuu
TRISIO
85h
--11 1111
--11 1111
--uu uuuu
PIE1
8Ch
0000 0000
0000 0000
uuuu uuuu
(1,5)
PCON
8Eh
--01 --0x
--0u --uu
--uu --uu
OSCCON
8Fh
-110 q000
-110 q000
-uuu uuuu
OSCTUNE
90h
---0 0000
---u uuuu
---u uuuu
PR2
92h
1111 1111
1111 1111
1111 1111
WPU
95h
--11 -111
--11 -111
uuuu uuuu
IOC
96h
--00 0000
--00 0000
--uu uuuu
VRCON
99h
0-0- 0000
0-0- 0000
u-u- uuuu
EEDAT
9Ah
0000 0000
0000 0000
uuuu uuuu
9Bh
0000 0000
0000 0000
uuuu uuuu
EEADR
Legend:
Note 1:
2:
3:
4:
5:
DS41211D-page 90
PIC12F683
TABLE 12-4:
Address
Power-on Reset
MCLR Reset
WDT Reset
Brown-out Reset(1)
EECON1
9Ch
---- x000
---- q000
---- uuuu
EECON2
9Dh
---- ----
---- ----
---- ----
ADRESL
9Eh
xxxx xxxx
uuuu uuuu
uuuu uuuu
9Fh
-000 1111
-000 1111
-uuu uuuu
Register
ANSEL
Legend:
Note 1:
2:
3:
4:
5:
TABLE 12-5:
Program
Counter
Status
Register
PCON
Register
Power-on Reset
000h
0001 1xxx
--01 --0x
000h
000u uuuu
--0u --uu
000h
0001 0uuu
--0u --uu
000h
0000 uuuu
--0u --uu
PC + 1
uuu0 0uuu
--uu --uu
WDT Reset
WDT Wake-up
Brown-out Reset
Interrupt Wake-up from Sleep
000h
0001 1uuu
--01 --10
PC + 1(1)
uuu1 0uuu
--uu --uu
DS41211D-page 91
PIC12F683
12.4
Interrupts
12.4.1
GP2/INT INTERRUPT
DS41211D-page 92
PIC12F683
12.4.2
TIMER0 INTERRUPT
12.4.3
FIGURE 12-7:
GPIO INTERRUPT
INTERRUPT LOGIC
IOC-GP0
IOC0
IOC-GP1
IOC1
IOC-GP2
IOC2
IOC-GP3
IOC3
IOC-GP4
IOC4
IOC-GP5
IOC5
TMR2IF
TMR2IE
TMR1IF
TMR1IE
CMIF
CMIE
ADIF
ADIE
T0IF
T0IE
INTF
INTE
GPIF
GPIE
Interrupt to CPU
PEIE
GIE
EEIF
EEIE
OSFIF
OSFIE
CCP1IF
CCP1IE
DS41211D-page 93
PIC12F683
FIGURE 12-8:
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKOUT (3)
(4)
INT pin
(1)
(1)
INTF flag
(INTCON reg.)
(5)
Interrupt Latency
(2)
GIE bit
(INTCON reg.)
INSTRUCTION FLOW
PC
Instruction
Fetched
Inst (PC + 1)
Inst (PC)
Instruction
Executed
Note 1:
PC + 1
PC
0004h
Dummy Cycle
Inst (PC)
Inst (PC 1)
PC + 1
0005h
Inst (0004h)
Inst (0005h)
Dummy Cycle
Inst (0004h)
2:
Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3:
4:
For minimum width of INT pulse, refer to AC specifications in Section 15.0 Electrical Specifications.
5:
TABLE 12-6:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
INTCON
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
IOC
IOC5
IOC4
IOC3
IOC2
IOC1
IOC0
PIR1
EEIF
ADIF
CCP1IF
CMIF
OSFIF
TMR2IF
TMR1IF
PIE1
EEIE
ADIE
CCP1IE
CMIE
OSFIE
TMR2IE
DS41211D-page 94
PIC12F683
12.5
EXAMPLE 12-1:
MOVWF
SWAPF
W_TEMP
STATUS,W
MOVWF
STATUS_TEMP
:
:(ISR)
:
SWAPF
STATUS_TEMP,W
MOVWF
SWAPF
SWAPF
STATUS
W_TEMP,F
W_TEMP,W
;Copy W to TEMP
;Swap status to
;Swaps are used
;Save status to
register
be saved into W
because they do not affect the status bits
bank zero STATUS_TEMP register
DS41211D-page 95
PIC12F683
12.6
12.6.2
12.6.1
WDT OSCILLATOR
WDT CONTROL
FIGURE 12-9:
0
Prescaler(1)
1
8
PSA
31 kHz
LFINTOSC Clock
PS<2:0>
WDTPS<3:0>
To Timer0
0
1
PSA
1:
This is the shared Timer0/WDT prescaler. See Section 5.0 Timer0 Module for more information.
TABLE 12-7:
WDT STATUS
Conditions
WDT
WDTE = 0
CLRWDT Command
Oscillator Fail Detected
Cleared
DS41211D-page 96
PIC12F683
REGISTER 12-2:
U-0
U-0
U-0
R/W-0
R/W-1
R/W-0
R/W-0
R/W-0
WDTPS3
WDTPS2
WDTPS1
WDTPS0
SWDTEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-5
Unimplemented: Read as 0
bit 4-1
bit 0
Note 1:
If WDTE Configuration bit = 1, then WDT is always enabled, irrespective of this control bit. If WDTE
Configuration bit = 0, then it is possible to turn WDT on/off with this control bit.
TABLE 12-8:
Name
WDTCON
Legend:
Note 1:
OPTION_REG
CONFIG
x = Bit is unknown
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
---0 1000
---0 1000
GPPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
CPD
CP
MCLRE
PWRTE
WDTE
FOSC2
FOSC1
FOSC0
DS41211D-page 97
PIC12F683
12.7
12.7.1
The first event will cause a device Reset. The two latter
events are considered a continuation of program
execution. The TO and PD bits in the STATUS register
can be used to determine the cause of a device Reset.
The PD bit, which is set on power-up, is cleared when
Sleep is invoked. TO bit is cleared if WDT wake-up
occurred.
The following peripheral interrupts can wake the device
from Sleep:
1.
2.
3.
4.
5.
6.
7.
12.7.2
DS41211D-page 98
PIC12F683
FIGURE 12-10:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
TOST(2)
CLKOUT(4)
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
Instruction Flow
PC
PC
Instruction
Fetched Inst(PC) = Sleep
Instruction
Inst(PC 1)
Executed
Note
12.8
1:
2:
3:
4:
Processor in
Sleep
PC + 1
PC + 2
PC + 2
Inst(PC + 1)
Inst(PC + 2)
Sleep
Inst(PC + 1)
PC + 2
Dummy Cycle
0004h
0005h
Inst(0004h)
Inst(0005h)
Dummy Cycle
Inst(0004h)
Code Protection
12.9
The entire data EEPROM and Flash program memory will be erased when the
code protection is turned off. See the
PIC12F6XX/16F6XX Memory
Programming Specification (DS41204)
for more information.
ID Locations
DS41211D-page 99
PIC12F683
12.10 In-Circuit Serial Programming
clock
data
power
ground
programming voltage
FIGURE 12-11:
TYPICAL IN-CIRCUIT
SERIAL PROGRAMMING
CONNECTION
To Normal
Connections
External
Connector
Signals
TABLE 12-9:
DEBUGGER RESOURCES
Resource
Description
Stack
1 level
Program Memory
FIGURE 12-12:
14-Pin PDIP
In-Circuit Debug Device
PIC12F683
+5V
VDD
0V
VSS
NC
ICDMCLR
VDD
VPP
MCLR/VPP/GP3
GP5
CLK
GP1
GP4
GP3
ICD
GP0
Data I/O
PIC12F683-ICD
14
ICDCLK
13
ICDDATA
12
GND
11
GP0
10
GP1
GP2
NC
To Normal
Connections
* Isolation devices (as required)
DS41211D-page 100
PIC12F683
13.0
TABLE 13-1:
Field
Description
Register file address (0x00 to 0x7F)
f
W
OPCODE FIELD
DESCRIPTIONS
PC
Program Counter
TO
Time-out bit
Carry bit
C
DC
Z
PD
Power-down bit
FIGURE 13-1:
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13
10 9
7 6
OPCODE
b (BIT #)
f (FILE #)
13.1
Read-Modify-Write Operations
13
OPCODE
0
k (literal)
11
OPCODE
10
0
k (literal)
DS41211D-page 101
PIC12F683
TABLE 13-2:
Mnemonic,
Operands
14-Bit Opcode
Description
Cycles
MSb
LSb
Status
Affected
Notes
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
C, DC, Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C, DC, Z
Z
1, 2
1, 2
2
1, 2
1, 2
1, 2, 3
1, 2
1, 2, 3
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
01
01
01
01
1, 2
1, 2
3
3
2:
3:
k
k
k
k
k
k
k
k
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
C, DC, Z
Z
TO, PD
Z
TO, PD
C, DC, Z
Z
When an I/O register is modified as a function of itself (e.g., MOVF GPIO, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is 1 for a pin configured as input and is driven low by an external
device, the data will be written back with a 0.
If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 module.
If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
DS41211D-page 102
PIC12F683
13.2
Instruction Descriptions
ADDLW
Syntax:
[ label ] ADDLW
Operands:
0 k 255
Operation:
(W) + k (W)
Status Affected:
C, DC, Z
Description:
BCF
Bit Clear f
Syntax:
[ label ] BCF
Operands:
0 f 127
0b7
Operation:
0 (f<b>)
Status Affected:
None
Description:
BSF
Bit Set f
Syntax:
[ label ] BSF
f,b
ADDWF
Add W and f
Syntax:
[ label ] ADDWF
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
0b7
Operation:
Operation:
1 (f<b>)
Status Affected:
C, DC, Z
Status Affected:
None
Description:
Description:
ANDLW
BTFSC
Syntax:
[ label ] ANDLW
Syntax:
Operands:
0 k 255
Operands:
Operation:
0 f 127
0b7
Status Affected:
Operation:
skip if (f<b>) = 0
Description:
Status Affected:
None
Description:
ANDWF
f,d
AND W with f
Syntax:
[ label ] ANDWF
Operands:
0 f 127
d [0,1]
Operation:
f,d
Status Affected:
Description:
f,b
DS41211D-page 103
PIC12F683
BTFSS
CLRWDT
Syntax:
Syntax:
[ label ] CLRWDT
Operands:
0 f 127
0b<7
Operands:
None
Operation:
00h WDT
0 WDT prescaler,
1 TO
1 PD
Status Affected:
TO, PD
Description:
Operation:
skip if (f<b>) = 1
Status Affected:
None
Description:
CALL
Call Subroutine
COMF
Complement f
Syntax:
[ label ] CALL k
Syntax:
[ label ] COMF
Operands:
0 k 2047
Operands:
Operation:
(PC)+ 1 TOS,
k PC<10:0>,
(PCLATH<4:3>) PC<12:11>
0 f 127
d [0,1]
Operation:
(f) (destination)
Status Affected:
Description:
DECF
Decrement f
Syntax:
f,d
Status Affected:
None
Description:
CLRF
Clear f
Syntax:
[ label ] CLRF
Operands:
0 f 127
Operands:
Operation:
00h (f)
1Z
0 f 127
d [0,1]
Operation:
(f) - 1 (destination)
Status Affected:
Status Affected:
Description:
Description:
Decrement register f. If d is 0,
the result is stored in the W
register. If d is 1, the result is
stored back in register f.
CLRW
Clear W
Syntax:
[ label ] CLRW
Operands:
None
Operation:
00h (W)
1Z
Status Affected:
Description:
DS41211D-page 104
PIC12F683
DECFSZ
Decrement f, Skip if 0
INCFSZ
Increment f, Skip if 0
Syntax:
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f) - 1 (destination);
skip if result = 0
Operation:
(f) + 1 (destination),
skip if result = 0
Status Affected:
None
Status Affected:
None
Description:
Description:
GOTO
Unconditional Branch
IORLW
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 k 2047
Operands:
0 k 255
Operation:
k PC<10:0>
PCLATH<4:3> PC<12:11>
Operation:
Status Affected:
Status Affected:
None
Description:
Description:
INCF
Increment f
IORWF
Inclusive OR W with f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f) + 1 (destination)
Operation:
Status Affected:
Status Affected:
Description:
Description:
GOTO k
INCF f,d
INCFSZ f,d
IORWF
f,d
DS41211D-page 105
PIC12F683
MOVF
Move f
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
MOVF f,d
MOVWF
Move W to f
Syntax:
[ label ]
MOVWF
Operands:
0 f 127
Operation:
(W) (f)
Operation:
(f) (dest)
Status Affected:
None
Status Affected:
Description:
Description:
Words:
Cycles:
Words:
Cycles:
Example:
MOVF
Example:
MOVW
F
OPTION
Before Instruction
OPTION =
W
=
After Instruction
OPTION =
W
=
FSR, 0
0xFF
0x4F
0x4F
0x4F
After Instruction
W =
value in FSR
register
Z = 1
MOVLW
Move literal to W
NOP
No Operation
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 k 255
Operands:
None
Operation:
k (W)
Operation:
No operation
Status Affected:
None
Status Affected:
None
Description:
Description:
No operation.
Words:
Cycles:
Words:
Cycles:
Example:
MOVLW k
Example:
MOVLW
NOP
0x5A
After Instruction
W =
DS41211D-page 106
NOP
0x5A
PIC12F683
RETFIE
RETLW
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
None
Operands:
0 k 255
Operation:
TOS PC,
1 GIE
Operation:
k (W);
TOS PC
Status Affected:
None
Status Affected:
None
Description:
Description:
Words:
Cycles:
Example:
RETFIE
Words:
Cycles:
Example:
RETFIE
After Interrupt
PC =
GIE =
TABLE
TOS
1
RETLW k
ADDWF PC ;W = offset
RETLW k1 ;Begin table
RETLW k2 ;
Before Instruction
W = 0x07
After Instruction
W = value of k8
RETURN
Syntax:
[ label ]
Operands:
None
Operation:
TOS PC
Status Affected:
None
Description:
RETURN
DS41211D-page 107
PIC12F683
RLF
SLEEP
Syntax:
[ label ]
Syntax:
[ label ] SLEEP
Operands:
0 f 127
d [0,1]
Operands:
None
Operation:
Operation:
Status Affected:
Description:
00h WDT,
0 WDT prescaler,
1 TO,
0 PD
RLF
f,d
Words:
Cycles:
Example:
Status Affected:
TO, PD
Description:
Register f
RLF
REG1,0
Before Instruction
REG1
C
=
=
1110 0110
0
=
=
=
1110 0110
1100 1100
1
After Instruction
REG1
W
C
RRF
SUBLW
Syntax:
[ label ]
Syntax:
[ label ] SUBLW k
Operands:
0 f 127
d [0,1]
Operands:
0 k 255
Operation:
k - (W) (W)
Operation:
Status Affected:
Description:
Description:
RRF f,d
DS41211D-page 108
Register f
W>k
C=1
Wk
DC = 0
DC = 1
W<3:0> k<3:0>
PIC12F683
SUBWF
Subtract W from f
XORLW
Syntax:
Syntax:
[ label ] XORLW k
Operands:
0 f 127
d [0,1]
Operands:
0 k 255
Operation:
Operation:
Status Affected:
Description:
SWAPF
W>f
C=1
Wf
DC = 0
DC = 1
W<3:0> f<3:0>
Swap Nibbles in f
XORWF
Exclusive OR W with f
Syntax:
Syntax:
[ label ] XORWF
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f<3:0>) (destination<7:4>),
(f<7:4>) (destination<3:0>)
Operation:
Status Affected:
Status Affected:
None
Description:
Description:
f,d
DS41211D-page 109
PIC12F683
NOTES:
DS41211D-page 110
PIC12F683
14.0
DEVELOPMENT SUPPORT
14.1
DS41211D-page 111
PIC12F683
14.2
MPASM Assembler
14.5
14.6
14.3
14.4
DS41211D-page 112
PIC12F683
14.7
14.8
14.9
DS41211D-page 113
PIC12F683
14.11 PICSTART Plus Development
Programmer
DS41211D-page 114
PIC12F683
15.0
ELECTRICAL SPECIFICATIONS
Power dissipation is calculated as follows: PDIS = VDD x {IDD IOH} + {(VDD VOH) x IOH} + (VOl x IOL).
NOTICE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for
extended periods may affect device reliability.
DS41211D-page 115
PIC12F683
FIGURE 15-1:
5.5
5.0
VDD (V)
4.5
4.0
3.5
3.0
2.5
2.0
0
10
20
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
FIGURE 15-2:
125
5%
Temperature (C)
85
2%
60
1%
25
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41211D-page 116
PIC12F683
15.1
DC CHARACTERISTICS
Param
No.
Sym
Characteristic
Conditions
VDD
Supply Voltage
2.0
2.0
3.0
4.5
5.5
5.5
5.5
5.5
V
V
V
V
D002*
VDR
1.5
D003
VPOR
VSS
D004*
SVDD
0.05
D001
D001C
D001D
DS41211D-page 117
PIC12F683
15.2
DC CHARACTERISTICS
Param
No.
D010
Conditions
Device Characteristics
Min
Typ
Max
Units
VDD
D011*
D012
D013*
D014
D015
D016*
D017
D018
D019
(1, 2)
11
16
2.0
18
28
3.0
35
54
5.0
140
240
2.0
220
380
3.0
380
550
5.0
260
360
2.0
420
650
3.0
0.8
1.1
mA
5.0
130
220
2.0
215
360
3.0
360
520
5.0
220
340
2.0
375
550
3.0
0.65
1.0
mA
5.0
20
2.0
16
40
3.0
31
65
5.0
340
450
2.0
500
700
3.0
0.8
1.2
mA
5.0
410
650
2.0
700
950
3.0
1.30
1.65
mA
5.0
230
400
2.0
400
680
3.0
0.63
1.1
mA
5.0
2.6
3.25
mA
4.5
2.8
3.35
mA
5.0
Note
FOSC = 32 kHz
LP Oscillator mode
FOSC = 1 MHz
XT Oscillator mode
FOSC = 4 MHz
XT Oscillator mode
FOSC = 1 MHz
EC Oscillator mode
FOSC = 4 MHz
EC Oscillator mode
FOSC = 31 kHz
LFINTOSC mode
FOSC = 4 MHz
HFINTOSC mode
FOSC = 8 MHz
HFINTOSC mode
FOSC = 4 MHz
EXTRC mode(3)
FOSC = 20 MHz
HS Oscillator mode
DS41211D-page 118
PIC12F683
15.3
DC CHARACTERISTICS
Param
No.
D020
Device Characteristics
Power-down Base
Current(IPD)(2)
D021
D022
D023
D024
D025*
D026
D027
Min
Typ
Max
Units
VDD
Note
WDT, BOR, Comparators, VREF and
T1OSC disabled
0.05
1.2
2.0
0.15
1.5
3.0
0.35
1.8
5.0
150
500
nA
3.0
-40C TA +25C
1.0
2.2
2.0
WDT Current(1)
2.0
4.0
3.0
3.0
7.0
5.0
42
60
3.0
85
122
5.0
32
45
2.0
60
78
3.0
120
160
5.0
30
36
2.0
45
55
3.0
75
95
5.0
39
47
2.0
59
72
3.0
98
124
5.0
4.5
7.0
2.0
5.0
8.0
3.0
6.0
12
5.0
0.30
1.6
3.0
0.36
1.9
5.0
BOR Current(1)
Comparator Current(1), both
comparators enabled
CVREF Current(1) (high range)
DS41211D-page 119
PIC12F683
15.4
DC CHARACTERISTICS
Param
No.
D020E
Device Characteristics
Power-down Base
Current (IPD)(2)
D021E
D022E
D023E
D024E
D025E*
D026E
D027E
Min
Typ
0.05
Max
9
Units
A
VDD
Note
2.0
0.15
11
3.0
0.35
15
5.0
17.5
2.0
19
3.0
22
5.0
42
65
3.0
85
127
5.0
32
45
2.0
60
78
3.0
120
160
5.0
30
70
2.0
45
90
3.0
75
120
5.0
39
91
2.0
59
117
3.0
98
156
5.0
4.5
25
2.0
30
3.0
40
5.0
0.30
12
3.0
0.36
16
5.0
WDT Current(1)
BOR Current(1)
Comparator Current(1), both
comparators enabled
CVREF Current(1) (high range)
DS41211D-page 120
PIC12F683
15.5
DC Characteristics:
PIC12F683-I (Industrial)
PIC12F683-E (Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40C TA +85C for industrial
-40C TA +125C for extended
DC CHARACTERISTICS
Param
No.
Sym
VIL
Characteristic
Min
Typ
Max
Units
Vss
Vss
Conditions
0.8
0.15 VDD
Vss
0.2 VDD
D030
D030A
D031
D032
VSS
0.2 VDD
D033
VSS
0.3
VSS
0.3 VDD
D033A
VIH
D040
D040A
D041
2.0
VDD
VDD
0.8 VDD
VDD
0.8 VDD
VDD
1.6
VDD
D042
MCLR
D043
D043A
0.7 VDD
VDD
D043B
0.9 VDD
VDD
(Note 1)
(2)
IIL
D060
I/O ports
0.1
D061
MCLR(3)
0.1
D063
OSC1
0.1
IPUR
50
250
400
VOL
0.6
VDD 0.7
D070*
D080
I/O ports
VOH
D090
Note 1:
2:
3:
4:
5:
DS41211D-page 121
PIC12F683
15.5
DC Characteristics:
PIC12F683-I (Industrial)
PIC12F683-E (Extended) (Continued)
DC CHARACTERISTICS
Param
No.
Sym
D100
IULP
Characteristic
Typ
Max
Units
200
nA
OSC2 pin
15
pF
50
pF
Conditions
COSC2
D101A* CIO
D120
ED
Byte Endurance
100K
1M
E/W
D120A
ED
Byte Endurance
10K
100K
E/W
D121
VDRW
VMIN
5.5
D122
TDEW
D123
TRETD
Characteristic Retention
40
D124
TREF
1M
10M
E/W
-40C TA +85C
-40C TA +85C
+85C TA +125C
Using EECON1 to read/write
VMIN = Minimum operating
voltage
ms
EP
Cell Endurance
10K
100K
E/W
D130A
ED
Cell Endurance
1K
10K
E/W
D131
VPR
VMIN
5.5
D132
VPEW
4.5
5.5
D133
TPEW
2.5
ms
D134
TRETD
Characteristic Retention
40
Note 1:
2:
3:
4:
5:
+85C TA +125C
VMIN = Minimum operating
voltage
DS41211D-page 122
PIC12F683
15.6
Thermal Considerations
TH02
TH03
TH04
TH05
TH06
TH07
Note 1:
2:
3:
Sym
JA
Characteristic
Thermal Resistance
Junction to Ambient
Typ
Units
84.6
163.0
52.4
46.3
41.2
38.8
3.0
2.6
150
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C
W
W
Conditions
W
PI/O = (IOL * VOL) + (IOH * (VDD - VOH))
PDER
Derated Power
W
PDER = (TJ - TA)/JA
(NOTE 2, 3)
IDD is current to run the chip alone without driving any load on the output pins.
TA = Ambient Temperature.
Maximum allowable power dissipation is the lower value of either the absolute maximum total power
dissipation or derated power (PDER).
DS41211D-page 123
PIC12F683
15.7
FIGURE 15-3:
Time
osc
rd
rw
sc
ss
t0
t1
wr
OSC1
RD
RD or WR
SCK
SS
T0CKI
T1CKI
WR
P
R
V
Z
Period
Rise
Valid
High-impedance
LOAD CONDITIONS
Load Condition
Pin
CL
VSS
Legend: CL =
DS41211D-page 124
50 pF
15 pF
PIC12F683
15.8
FIGURE 15-4:
CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
OSC1/CLKIN
OS02
OS04
OS04
OS03
OSC2/CLKOUT
(LP,XT,HS Modes)
OSC2/CLKOUT
(CLKOUT Mode)
TABLE 15-1:
Sym
FOSC
Characteristic
External CLKIN Frequency(1)
Oscillator Frequency(1)
OS02
TOSC
Oscillator Period(1)
OS03
OS04*
TCY
TosH,
TosL
Min
Typ
Max
Units
DC
DC
DC
DC
0.1
1
DC
27
250
50
50
250
50
250
32.768
30.5
37
4
20
20
4
20
4
10,000
1,000
kHz
MHz
MHz
MHz
kHz
MHz
MHz
MHz
s
ns
ns
ns
s
ns
ns
ns
Conditions
LP Oscillator mode
XT Oscillator mode
HS Oscillator mode
EC Oscillator mode
LP Oscillator mode
XT Oscillator mode
HS Oscillator mode
RC Oscillator mode
LP Oscillator mode
XT Oscillator mode
HS Oscillator mode
EC Oscillator mode
LP Oscillator mode
XT Oscillator mode
HS Oscillator mode
RC Oscillator mode
200
TCY
DC
ns
TCY = 4/FOSC
2
s
LP oscillator
100
ns
XT oscillator
20
ns
HS oscillator
OS05* TosR, External CLKIN Rise,
0
ns
LP oscillator
TosF
External CLKIN Fall
0
ns
XT oscillator
0
ns
HS oscillator
* These parameters are characterized but not tested.
Data in Typ column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and
are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at min values with an external
clock applied to OSC1 pin. When an external clock input is used, the max cycle time limit is DC (no clock) for
all devices.
DS41211D-page 125
PIC12F683
TABLE 15-2:
OSCILLATOR PARAMETERS
Sym
Characteristic
Freq.
Tolerance
Min
Typ
Max
Units
Conditions
OS06
TWARM
TOSC
Slowest clock
OS07
TSC
21
ms
LFINTOSC/64
OS08
HFOSC
Internal Calibrated
HFINTOSC Frequency(2)
OS09*
OS10*
LFOSC
Internal Uncalibrated
LFINTOSC Frequency
TIOSC
HFINTOSC Oscillator
Wake-up from Sleep
Start-up Time
ST
1%
7.92
8.0
8.08
MHz
2%
7.84
8.0
8.16
MHz
5%
7.60
8.0
8.40
MHz
15
31
45
kHz
5.5
12
24
3.5
14
11
DS41211D-page 126
PIC12F683
FIGURE 15-5:
Cycle
Write
Fetch
Read
Execute
Q4
Q1
Q2
Q3
Fosc
OS12
OS11
OS20
OS21
CLKOUT
OS19
OS18
OS16
OS13
OS17
I/O pin
(Input)
OS14
OS15
I/O pin
(Output)
New Value
Old Value
OS18, OS19
TABLE 15-3:
Sym
Characteristic
TOSH2CKL
OS12
TOSH2CKH
FOSC to CLKOUT
(1)
OS13
TCKL2IOV
OS14
TIOV2CKH
OS15*
TOSH2IOV
OS16
OS11
Min
Typ
Max
Units
Conditions
70
ns
VDD = 5.0V
VDD = 5.0V
72
ns
20
ns
TOSC + 200 ns
ns
50
70
ns
VDD = 5.0V
TOSH2IOI
50
ns
VDD = 5.0V
OS17
TIOV2OSH
20
ns
OS18
TIOR
15
40
72
32
ns
VDD = 2.0V
VDD = 5.0V
OS19
TIOF
28
15
55
30
ns
VDD = 2.0V
VDD = 5.0V
OS20*
TINP
25
ns
OS21*
TGPP
TCY
ns
Note 1:
2:
DS41211D-page 127
PIC12F683
FIGURE 15-6:
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Start-Up Time
Internal Reset(1)
Watchdog Timer
Reset(1)
31
34
34
I/O pins
Note 1:
Asserted low.
FIGURE 15-7:
VDD
VBOR + VHYST
VBOR
37
Reset
(due to BOR)
*
33*
DS41211D-page 128
PIC12F683
TABLE 15-4:
Sym
Characteristic
Min
Typ
Max
Units
Conditions
30
TMCL
2
5
s
s
31
TWDT
10
10
16
16
29
31
ms
ms
32
TOST
1024
33*
TPWRT
40
65
140
ms
34*
TIOZ
2.0
35
VBOR
2.0
2.2
36*
VHYST
50
mV
37*
TBOR
100
TOSC (NOTE 3)
(NOTE 4)
VDD VBOR
DS41211D-page 129
PIC12F683
FIGURE 15-8:
T0CKI
40
41
42
T1CKI
45
46
49
47
TMR0 or
TMR1
TABLE 15-5:
Sym
TT0H
Characteristic
T0CKI High Pulse Width
No Prescaler
With Prescaler
41*
TT0L
No Prescaler
42*
TT0P
T0CKI Period
45*
TT1H
With Prescaler
Asynchronous
46*
TT1L
T1CKI Low
Time
Synchronous, No Prescaler
Synchronous,
with Prescaler
Asynchronous
47*
TT1P
48
FT1
49*
Asynchronous
Min
Typ
Max
Units
0.5 TCY + 20
ns
10
ns
0.5 TCY + 20
ns
10
ns
Greater of:
20 or TCY + 40
N
ns
0.5 TCY + 20
ns
15
ns
30
ns
0.5 TCY + 20
ns
15
ns
30
ns
Greater of:
30 or TCY + 40
N
ns
60
ns
32.768
kHz
2 TOSC
7 TOSC
Conditions
N = prescale value
(2, 4, ..., 256)
N = prescale value
(1, 2, 4, 8)
Timers in Sync
mode
DS41211D-page 130
PIC12F683
FIGURE 15-9:
CCP1
(Capture mode)
CC01
CC02
CC03
Note:
TABLE 15-6:
Sym
TccL
TccH
TccP
Characteristic
CCP1 Input Low Time
CCP1 Input High Time
CCP1 Input Period
Min
Typ
Max
Units
No Prescaler
0.5TCY + 20
ns
With Prescaler
20
ns
No Prescaler
0.5TCY + 20
ns
With Prescaler
20
ns
3TCY + 40
N
ns
Conditions
N = prescale
value (1, 4 or
16)
DS41211D-page 131
PIC12F683
TABLE 15-7:
COMPARATOR SPECIFICATIONS
Sym
Characteristics
CM01
VOS
CM02
VCM
CM03* CMRR
CM04* TRT
Response Time
Min
Typ
Max
Units
5.0
10
mV
VDD 1.5
+55
dB
Falling
150
600
ns
Rising
200
1000
ns
10
Comments
(VDD - 1.5)/2
(NOTE 1)
TABLE 15-8:
Sym
Characteristics
Min
Typ
Max
Units
Comments
CV01*
CLSB
Step Size(2)
VDD/24
VDD/32
V
V
CV02*
CACC
Absolute Accuracy
1/2
1/2
LSb
LSb
CV03*
CR
2k
CV04*
CST
Settling Time(1)
10
DS41211D-page 132
PIC12F683
TABLE 15-9:
Characteristic
Min
Typ
Max
Units
Conditions
AD01
NR
Resolution
10 bits
AD02
EIL
Integral Error
AD03
EDL
Differential Error
AD04
EOFF
Offset Error
AD07
EGN
bit
Gain Error
AD06 VREF
AD06A
Reference Voltage(3)
2.2
2.7
VDD
AD07
VAIN
Full-Scale Range
VSS
VREF
AD08
ZAIN
Recommended
Impedance of Analog
Voltage Source
10
AD09* IREF
10
1000
50
DS41211D-page 133
PIC12F683
TABLE 15-10: PIC12F683 A/D CONVERSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40C TA +125C
Param
No.
Sym
AD130* TAD
Characteristic
A/D Clock Period
A/D Internal RC
Oscillator Period
AD131 TCNV
Conversion Time
(not including
Acquisition Time)(1)
Min
Typ
1.6
9.0
3.0
9.0
3.0
6.0
9.0
1.6
4.0
6.0
At VDD = 5.0V
11
TAD
11.5
TOSC/2
TOSC/2 + TCY
TAMP
AD134 TGO
Max Units
Conditions
DS41211D-page 134
PIC12F683
FIGURE 15-10:
BSF ADCON0, GO
AD134
1 TCY
(TOSC/2(1))
AD131
Q4
AD130
A/D CLK
9
A/D Data
0
NEW_DATA
OLD_DATA
ADRES
1 TCY
ADIF
GO
DONE
Note 1:
Sampling Stopped
AD132
Sample
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
FIGURE 15-11:
BSF ADCON0, GO
AD134
(TOSC/2 + TCY(1))
1 TCY
AD131
Q4
AD130
A/D CLK
9
A/D Data
OLD_DATA
ADRES
0
NEW_DATA
ADIF
1 TCY
GO
DONE
Sample
Note 1:
AD132
Sampling Stopped
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
DS41211D-page 135
PIC12F683
NOTES:
DS41211D-page 136
PIC12F683
16.0
The graphs and tables provided in this section are for design guidance and are not tested.
In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD
range). This is for information only and devices are ensured to operate properly only within the specified range.
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein are
not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
Typical represents the mean of the distribution at 25C. Maximum or minimum represents
(mean + 3) or (mean - 3) respectively, where is a standard deviation, over each temperature range.
FIGURE 16-1:
3.5
3.0
5.5V
5.0V
IDD (mA)
2.5
2.0
4.0V
1.5
3.0V
1.0
2.0V
0.5
0.0
1 MHz
2 MHz
4 MHz
6 MHz
8 MHz
10 MHz
12 MHz
14 MHz
16 MHz
18 MHz
20 MHz
FOSC
DS41211D-page 137
PIC12F683
FIGURE 16-2:
4.0
3.5
5.5V
5.0V
3.0
IDD (mA)
2.5
4.0V
2.0
3.0V
1.5
2.0V
1.0
0.5
0.0
1 MHz
2 MHz
4 MHz
6 MHz
8 MHz
10 MHz
12 MHz
14 MHz
16 MHz
18 MHz
20 MHz
FOSC
FIGURE 16-3:
4.0
3.5
5.5V
3.0
5.0V
IDD (mA)
2.5
4.5V
2.0
1.5
4.0V
3.5V
3.0V
1.0
0.5
0.0
4 MHz
10 MHz
16 MHz
20 MHz
FOSC
DS41211D-page 138
PIC12F683
FIGURE 16-4:
5.0
4.5
4.0
IDD (mA)
3.5
5.0V
3.0
4.5V
2.5
2.0
1.5
4.0V
3.5V
3.0V
1.0
0.5
0.0
4 MHz
10 MHz
16 MHz
20 MHz
FOSC
FIGURE 16-5:
900
800
700
IDD (A)
600
500
4 MHz
400
300
1 MHz
200
100
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41211D-page 139
PIC12F683
FIGURE 16-6:
1,400
Typical: Statistical Mean @25C
Maximum: Mean (Worst-case Temp) + 3
(-40C to 125C)
1,200
IDD (A)
1,000
800
4 MHz
600
400
1 MHz
200
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
5.0
5.5
VDD (V)
FIGURE 16-7:
800
700
600
IDD (A)
500
4 MHz
400
300
1 MHz
200
100
0
2.0
2.5
3.0
3.5
4.0
4.5
VDD (V)
DS41211D-page 140
PIC12F683
FIGURE 16-8:
1,400
Typical: Statistical Mean @25C
Maximum: Mean (Worst-case Temp) + 3
(-40C to 125C)
1,200
IDD (A)
1,000
4 MHz
800
600
1 MHz
400
200
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
5.0
5.5
VDD (V)
FIGURE 16-9:
80
70
60
IDD (A)
50
Maximum
40
30
Typical
20
10
0
2.0
2.5
3.0
3.5
4.0
4.5
VDD (V)
DS41211D-page 141
PIC12F683
FIGURE 16-10:
LP Mode
70
Typical: Statistical Mean @25C
Maximum: Mean (Worst-case Temp) + 3
(-40C to 125C)
60
50
IDD (A)
32 kHz Maximum
40
30
32 kHz Typical
20
10
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 16-11:
1,600
1,400
5.5V
5.0V
1,200
IDD (A)
1,000
4.0V
800
3.0V
600
2.0V
400
200
0
125 kHz
250 kHz
500 kHz
1 MHz
2 MHz
4 MHz
8 MHz
FOSC
DS41211D-page 142
PIC12F683
FIGURE 16-12:
2,000
1,800
5.5V
5.0V
1,600
1,400
4.0V
IDD (A)
1,200
1,000
3.0V
800
600
2.0V
400
200
0
125 kHz
250 kHz
500 kHz
1 MHz
2 MHz
4 MHz
8 MHz
FOSC
FIGURE 16-13:
0.45
0.40
0.35
IPD (A)
0.30
0.25
0.20
0.15
0.10
0.05
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41211D-page 143
PIC12F683
FIGURE 16-14:
18.0
16.0
14.0
Max. 125C
IPD (A)
12.0
10.0
8.0
6.0
4.0
Max. 85C
2.0
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 16-15:
180
160
140
IPD (A)
120
Maximum
100
Typical
80
60
40
20
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41211D-page 144
PIC12F683
FIGURE 16-16:
160
140
120
IPD (A)
100
Maximum
80
Typical
60
40
20
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 16-17:
3.0
2.5
Typical: Statistical
StatisticalMean
Mean @25C
@25C
Typical:
Maximum: Mean (Worst-case Temp) + 3
(-40C to 125C)
IPD (A)
2.0
1.5
1.0
0.5
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41211D-page 145
PIC12F683
FIGURE 16-18:
25.0
20.0
IPD (A)
Max. 125C
15.0
10.0
Max. 85C
5.0
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 16-19:
30
28
26
Max. (85C)
24
Time (ms)
22
20
Typical
18
16
14
Minimum
12
10
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41211D-page 146
PIC12F683
FIGURE 16-20:
30
28
26
Maximum
24
Time (ms)
22
20
Typical
18
16
Minimum
14
12
10
-40C
25C
85C
125C
Temperature (C)
FIGURE 16-21:
140
120
100
IPD (A)
Max. 125C
80
Max. 85C
60
Typical
40
20
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41211D-page 147
PIC12F683
FIGURE 16-22:
180
Typical: Statistical Mean @25C
Maximum: Mean (Worst-case Temp) + 3
(-40C to 125C)
160
140
120
IPD (A)
Max. 125C
100
Max. 85C
80
Typical
60
40
20
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 16-23:
0.8
0.7
Max. 125C
0.6
VOL (V)
0.5
Max. 85C
0.4
Typical 25C
0.3
0.2
Min. -40C
0.1
0.0
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
IOL (mA)
DS41211D-page 148
PIC12F683
FIGURE 16-24:
0.45
Typical: Statistical Mean @25C
Typical:
Statistical
Mean Temp)
@25C+ 3
Maximum:
Mean
(Worst-case
Maximum: Means
(-40C
+ 3 to 125C)
(-40C to 125C)
0.40
Max. 125C
0.35
Max. 85C
VOL (V)
0.30
0.25
Typ. 25C
0.20
0.15
Min. -40C
0.10
0.05
0.00
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
IOL (mA)
FIGURE 16-25:
3.5
3.0
Max. -40C
Typ. 25C
2.5
Min. 125C
VOH (V)
2.0
1.5
1.0
0.5
0.0
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
-4.0
IOH (mA)
DS41211D-page 149
PIC12F683
FIGURE 16-26:
5.5
5.0
Max. -40C
Typ. 25C
VOH (V)
4.5
Min. 125C
4.0
3.5
3.0
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
-4.0
-4.5
-5.0
IOH (mA)
FIGURE 16-27:
1.7
1.5
VIN (V)
1.3
Typ. 25C
1.1
Min. 125C
0.9
0.7
0.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41211D-page 150
PIC12F683
FIGURE 16-28:
4.0
VIH Max. 125C
3.5
VIN (V)
3.0
2.5
2.0
VIL Max. -40C
1.5
1.0
0.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 16-29:
45.0
40.0
35.0
Max. 125C
IPD (mA)
30.0
25.0
20.0
15.0
Max. 85C
10.0
5.0
Typ. 25C
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41211D-page 151
PIC12F683
FIGURE 16-30:
806
1000
900
Max. 125C
800
700
600
Note:
500
Max. 85C
400
300
Typ. 25C
200
Min. -40C
100
0
2.0
2.5
4.0
5.5
VDD (V)
FIGURE 16-31:
1000
900
Max. 125C
800
700
600
Note:
500
Max. 85C
400
300
Typ. 25C
200
Min. -40C
100
0
2.0
2.5
4.0
5.5
VDD (V)
DS41211D-page 152
PIC12F683
FIGURE 16-32:
45,000
40,000
Max. -40C
35,000
Typ. 25C
Frequency (Hz)
30,000
25,000
20,000
Min. 85C
Min. 125C
15,000
10,000
5,000
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 16-33:
8
Typical: Statistical Mean @25C
Maximum: Mean (Worst-case Temp) + 3
(-40C to 125C)
125C
6
Time (s)
85C
25C
-40C
2
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41211D-page 153
PIC12F683
FIGURE 16-34:
16
Typical: Statistical Mean @25C
Maximum: Mean (Worst-case Temp) + 3
(-40C to 125C)
14
85C
12
25C
Time (s)
10
-40C
8
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 16-35:
25
Time (s)
20
15
85C
25C
10
-40C
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41211D-page 154
PIC12F683
FIGURE 16-36:
10
9
Typical: Statistical Mean @25C
Maximum: Mean (Worst-case Temp) + 3
(-40C to 125C)
8
7
Time (s)
85C
6
25C
5
-40C
4
3
2
1
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 16-37:
5
4
3
2
1
0
-1
-2
-3
-4
-5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41211D-page 155
PIC12F683
FIGURE 16-38:
5
4
Change from Calibration (%)
3
2
1
0
-1
-2
-3
-4
-5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 16-39:
5
4
3
2
1
0
-1
-2
-3
-4
-5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41211D-page 156
PIC12F683
FIGURE 16-40:
5
4
3
2
1
0
-1
-2
-3
-4
-5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41211D-page 157
PIC12F683
NOTES:
DS41211D-page 158
PIC12F683
17.0
PACKAGING INFORMATION
17.1
Example
12F683
I/P e3 017
0415
XXXXXXXX
XXXXXNNN
YYWW
8-Lead SOIC (3.90 mm)
12F683 e3
I/SN0415
017
XXXXXXXX
XXXXYYWW
NNN
8-Lead DFN (4x4x0.9 mm)
XXXXXX
XXXXXX
YYWW
NNN
Legend: XX...X
Y
YY
WW
NNN
e3
Note:
Example
12F683
I/MD e3
0415
017
XXXXXXX
XXXXXXX
XXYYWW
NNN
Example
Example
12F683
I/MF e3
0415
017
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week 01)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
Standard PIC device marking consists of Microchip part number, year code, week code and traceability
code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip
Sales Office. For QTP devices, any special marking adders are included in QTP price.
DS41211D-page 159
PIC12F683
17.2
Package Details
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
NOTE 1
E1
2
D
E
A2
A1
e
eB
b1
b
Units
Dimension Limits
Number of Pins
INCHES
MIN
NOM
MAX
Pitch
.210
A2
.115
.130
.195
A1
.015
.290
.310
.325
E1
.240
.250
.280
Overall Length
.348
.365
.400
.115
.130
.150
Lead Thickness
.008
.010
.015
b1
.040
.060
.070
.014
.018
.022
eB
.100 BSC
.430
Notes:
1. Pin 1 visual index feature may vary, but must be located with the hatched area.
2. Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-018B
DS41211D-page 160
PIC12F683
8-Lead Plastic Small Outline (SN or OA) Narrow, 3.90 mm Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
e
N
E
E1
NOTE 1
1
b
h
A2
A1
L1
Units
Dimension Limits
Number of Pins
MILLIMETERS
MIN
NOM
MAX
Pitch
Overall Height
1.27 BSC
A2
1.25
Standoff
A1
0.10
0.25
Overall Width
E1
3.90 BSC
Overall Length
4.90 BSC
1.75
6.00 BSC
Chamfer (optional)
0.25
0.50
Foot Length
0.40
1.27
Footprint
L1
1.04 REF
Foot Angle
Lead Thickness
0.17
0.25
Lead Width
0.31
0.51
15
15
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-057B
DS41211D-page 161
PIC12F683
8-Lead Plastic Dual Flat, No Lead Package (MD) 4x4x0.9 mm Body [DFN]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
N
L
E2
K
EXPOSED
PAD
1
1
NOTE 1
NOTE 1
D2
TOP VIEW
BOTTOM VIEW
A3
A
A1
NOTE 2
Units
Dimension Limits
Number of Pins
MILLIMETERS
MIN
NOM
MAX
Pitch
Overall Height
0.80
0.90
1.00
Standoff
A1
0.00
0.02
0.05
Contact Thickness
A3
Overall Length
E2
Overall Width
0.80 BSC
0.20 REF
4.00 BSC
0.00
2.20
2.80
4.00 BSC
D2
0.00
3.00
Contact Width
0.25
0.30
0.35
Contact Length
0.30
0.55
0.65
Contact-to-Exposed Pad
K
0.20
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package may have one or more exposed tie bars at ends.
3. Package is saw singulated.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
3.60
DS41211D-page 162
PIC12F683
8-Lead Plastic Dual Flat, No Lead Package (MF) 6x5 mm Body [DFN-S]
PUNCH SINGULATED
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D1
L
N
K
E2
E1
EXPOSED
PAD
NOTE 1
NOTE 1
D2
TOP VIEW
BOTTOM VIEW
A2
A
A1
A3
NOTE 2
Units
Dimension Limits
Number of Pins
MILLIMETERS
MIN
NOM
MAX
Pitch
Overall Height
1.27 BSC
0.85
A2
0.65
0.80
Standoff
A1
0.00
0.01
0.05
Base Thickness
A3
0.20 REF
Overall Length
4.92 BSC
D1
D2
Overall Width
E1
E2
2.16
2.31
Contact Width
0.35
0.40
0.47
Contact Length
0.50
0.60
0.75
Contact-to-Exposed Pad
0.20
12
1.00
4.67 BSC
3.85
4.00
4.15
5.99 BSC
5.74 BSC
2.46
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package may have one or more exposed tie bars at ends.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-113B
DS41211D-page 163
PIC12F683
NOTES:
DS41211D-page 164
PIC12F683
APPENDIX A:
DATA SHEET
REVISION HISTORY
Revision A
APPENDIX B:
MIGRATING FROM
OTHER PIC
DEVICES
Revision B
B.1
TABLE B-1:
Revision C
Revisions throughout document. Incorporated Golden
Chapters.
Revision D
Replaced Package Drawings; Revised Product ID
Section (SN package to 3.90 mm); Replaced PICmicro
with PIC; Replaced Dev Tool Section.
PIC16F676 to PIC12F683
FEATURE COMPARISON
Feature
Max Operating
Speed
Max Program
Memory (Words)
PIC12F683
20 MHz
20 MHz
1024
2048
SRAM (bytes)
64
128
A/D Resolution
10-bit
10-bit
Data EEPROM
(Bytes)
128
256
Timers (8/16-bit)
1/1
2/1
Oscillator Modes
Brown-out Reset
Internal Pull-ups
RA0/1/2/4/5
GP0/1/2/4/5,
MCLR
Interrupt-on-change
RA0/1/2/3/4/5 GP0/1/2/3/4/5
Comparator
ECCP
Ultra Low-Power
Wake-Up
Extended WDT
Software Control
Option of WDT/BOR
4 MHz
32 kHz8 MHz
INTOSC
Frequencies
Clock Switching
Note:
PIC16F676
DS41211D-page 165
PIC12F683
NOTES:
DS41211D-page 166
PIC12F683
INDEX
A
A/D
Specifications.................................................... 133, 134
Absolute Maximum Ratings .............................................. 115
AC Characteristics
Industrial and Extended ............................................ 125
Load Conditions ........................................................ 124
ADC .................................................................................... 61
Acquisition Requirements ........................................... 67
Associated registers.................................................... 69
Block Diagram............................................................. 61
Calculating Acquisition Time....................................... 67
Channel Selection....................................................... 61
Configuration............................................................... 61
Configuring Interrupt ................................................... 64
Conversion Clock........................................................ 62
Conversion Procedure ................................................ 64
GPIO Configuration..................................................... 61
Internal Sampling Switch (RSS) IMPEDANCE ................ 67
Interrupts..................................................................... 63
Operation .................................................................... 63
Operation During Sleep .............................................. 64
Reference Voltage (VREF)........................................... 62
Result Formatting........................................................ 63
Source Impedance...................................................... 67
Special Event Trigger.................................................. 64
Starting an A/D Conversion ........................................ 63
ADCON0 Register............................................................... 65
ADRESH Register (ADFM = 0) ........................................... 66
ADRESH Register (ADFM = 1) ........................................... 66
ADRESL Register (ADFM = 0)............................................ 66
ADRESL Register (ADFM = 1)............................................ 66
Analog Input Connection Considerations............................ 52
Analog-to-Digital Converter. See ADC
ANSEL Register .................................................................. 33
Assembler
MPASM Assembler................................................... 112
B
Block Diagrams
(CCP) Capture Mode Operation ................................. 76
ADC ............................................................................ 61
ADC Transfer Function ............................................... 68
Analog Input Model ............................................... 52, 68
CCP PWM................................................................... 78
Clock Source............................................................... 19
Comparator ................................................................. 51
Compare ..................................................................... 77
Crystal Operation ........................................................ 22
External RC Mode....................................................... 23
Fail-Safe Clock Monitor (FSCM) ................................. 29
GP1 Pin....................................................................... 37
GP2 Pin....................................................................... 37
GP3 Pin....................................................................... 38
GP4 Pin....................................................................... 38
GP5 Pin....................................................................... 39
In-Circuit Serial Programming Connections.............. 100
Interrupt Logic ............................................................. 93
MCLR Circuit............................................................... 86
On-Chip Reset Circuit ................................................. 85
PIC12F683.................................................................... 5
Resonator Operation................................................... 22
Timer1......................................................................... 44
Timer2 ........................................................................ 49
TMR0/WDT Prescaler ................................................ 41
Watchdog Timer (WDT).............................................. 96
Brown-out Reset (BOR)...................................................... 87
Associated .................................................................. 88
Calibration .................................................................. 87
Specifications ........................................................... 129
Timing and Characteristics ....................................... 128
C
C Compilers
MPLAB C18.............................................................. 112
MPLAB C30.............................................................. 112
Calibration Bits.................................................................... 85
Capture Module. See Capture/Compare/PWM (CCP)
Capture/Compare/PWM (CCP) .......................................... 75
Associated registers w/ Capture, Compare
and Timer1 ......................................................... 81
Associated registers w/ PWM and Timer2.................. 81
Capture Mode............................................................. 76
CCPx Pin Configuration.............................................. 76
Compare Mode........................................................... 77
CCPx Pin Configuration...................................... 77
Software Interrupt Mode ............................... 76, 77
Special Event Trigger ......................................... 77
Timer1 Mode Selection................................. 76, 77
Prescaler .................................................................... 76
PWM Mode................................................................. 78
Duty Cycle .......................................................... 79
Effects of Reset .................................................. 80
Example PWM Frequencies and
Resolutions, 20 MHZ .................................. 79
Example PWM Frequencies and
Resolutions, 8 MHz .................................... 79
Operation in Sleep Mode.................................... 80
Setup for Operation ............................................ 80
System Clock Frequency Changes .................... 80
PWM Period ............................................................... 79
Setup for PWM Operation .......................................... 80
Timer Resources ........................................................ 75
CCP. See Capture/Compare/PWM (CCP)
CCP1CON Register............................................................ 75
Clock Sources
External Modes........................................................... 21
EC ...................................................................... 21
HS ...................................................................... 22
LP ....................................................................... 22
OST .................................................................... 21
RC ...................................................................... 23
XT ....................................................................... 22
Internal Modes............................................................ 23
Frequency Selection........................................... 25
HFINTOSC ......................................................... 23
INTOSC .............................................................. 23
INTOSCIO .......................................................... 23
LFINTOSC.......................................................... 25
Clock Switching .................................................................. 27
Code Examples
A/D Conversion .......................................................... 64
Assigning Prescaler to Timer0.................................... 42
Assigning Prescaler to WDT....................................... 42
Changing Between Capture Prescalers ..................... 76
Data EEPROM Read.................................................. 73
Data EEPROM Write .................................................. 73
DS41211D-page 167
PIC12F683
Indirect Addressing ..................................................... 18
Initializing GPIO .......................................................... 31
Saving STATUS and W Registers in RAM ................. 95
Ultra Low-Power Wake-up Initialization ...................... 35
Write Verify ................................................................. 73
Code Protection .................................................................. 99
Comparator ......................................................................... 51
C2OUT as T1 Gate ..................................................... 57
Configurations ............................................................. 53
I/O Operating Modes................................................... 53
Interrupts ..................................................................... 55
Operation .............................................................. 51, 54
Operation During Sleep .............................................. 56
Response Time ........................................................... 54
Synchronizing COUT w/Timer1 .................................. 57
Comparator Module
Associated registers.................................................... 59
Comparator Voltage Reference (CVREF)
Response Time ........................................................... 54
Comparator Voltage Reference (CVREF) ............................ 58
Effects of a Reset........................................................ 56
Specifications ............................................................ 132
Comparators
C2OUT as T1 Gate ..................................................... 45
Effects of a Reset........................................................ 56
Specifications ............................................................ 132
Compare Module. See Capture/Compare/PWM (CCP)
CONFIG Register................................................................ 84
Configuration Bits................................................................ 83
CPU Features ..................................................................... 83
Customer Change Notification Service ............................. 171
Customer Notification Service........................................... 171
Customer Support ............................................................. 171
D
Data EEPROM Memory
Associated Registers .................................................. 74
Code Protection .................................................... 71, 74
Data Memory Organization ................................................... 7
Map of the PIC12F683 .................................................. 8
DC and AC Characteristics
Graphs and Tables ................................................... 137
DC Characteristics
Extended and Industrial ............................................ 121
Industrial and Extended ............................................ 117
Development Support ....................................................... 111
Device Overview ................................................................... 5
E
EEADR Register ................................................................. 71
EECON1 Register ............................................................... 72
EECON2 Register ............................................................... 72
EEDAT Register.................................................................. 71
EEPROM Data Memory
Avoiding Spurious Write.............................................. 74
Reading....................................................................... 73
Write Verify ................................................................. 73
Writing ......................................................................... 73
Effects of Reset
PWM mode ................................................................. 80
Electrical Specifications .................................................... 115
Enhanced Capture/Compare/PWM (ECCP)
Specifications ............................................................ 131
Errata .................................................................................... 3
DS41211D-page 168
F
Fail-Safe Clock Monitor ...................................................... 29
Fail-Safe Condition Clearing....................................... 29
Fail-Safe Detection ..................................................... 29
Fail-Safe Operation..................................................... 29
Reset or Wake-up from Sleep .................................... 29
Firmware Instructions ....................................................... 101
Fuses. See Configuration Bits
G
General Purpose Register File ............................................. 8
GPIO................................................................................... 31
Additional Pin Functions ............................................. 32
ANSEL Register ................................................. 32
Interrupt-on-Change ........................................... 32
Ultra Low-Power Wake-up............................ 32, 35
Weak Pull-up ...................................................... 32
Associated Registers .................................................. 39
GP0 ............................................................................ 36
GP1 ............................................................................ 37
GP2 ............................................................................ 37
GP3 ............................................................................ 38
GP4 ............................................................................ 38
GP5 ............................................................................ 39
Pin Descriptions and Diagrams .................................. 36
Specifications ........................................................... 127
GPIO Register .................................................................... 31
I
ID Locations........................................................................ 99
In-Circuit Debugger........................................................... 100
In-Circuit Serial Programming (ICSP)............................... 100
Indirect Addressing, INDF and FSR Registers ................... 18
Instruction Format............................................................. 101
Instruction Set................................................................... 101
ADDLW..................................................................... 103
ADDWF..................................................................... 103
ANDLW..................................................................... 103
ANDWF..................................................................... 103
BCF .......................................................................... 103
BSF........................................................................... 103
BTFSC ...................................................................... 103
BTFSS ...................................................................... 104
CALL......................................................................... 104
CLRF ........................................................................ 104
CLRW ....................................................................... 104
CLRWDT .................................................................. 104
COMF ....................................................................... 104
DECF ........................................................................ 104
DECFSZ ................................................................... 105
GOTO ....................................................................... 105
INCF ......................................................................... 105
INCFSZ..................................................................... 105
IORLW ...................................................................... 105
IORWF...................................................................... 105
MOVF ....................................................................... 106
MOVLW .................................................................... 106
MOVWF .................................................................... 106
NOP .......................................................................... 106
RETFIE ..................................................................... 107
RETLW ..................................................................... 107
RETURN................................................................... 107
RLF ........................................................................... 108
RRF .......................................................................... 108
SLEEP ...................................................................... 108
PIC12F683
SUBLW ..................................................................... 108
SUBWF ..................................................................... 109
SWAPF ..................................................................... 109
XORLW..................................................................... 109
XORWF..................................................................... 109
INTCON Register ................................................................ 14
Internal Oscillator Block
INTOSC
Specifications............................................ 126, 127
Internal Sampling Switch (RSS) IMPEDANCE ........................ 67
Internet Address................................................................ 171
Interrupts ............................................................................. 92
ADC ............................................................................ 64
Associated Registers .................................................. 94
Comparator ................................................................. 55
Context Saving............................................................ 95
Data EEPROM Memory Write .................................... 72
GP2/INT ...................................................................... 92
GPIO Interrupt-on-change .......................................... 93
Interrupt-on-Change.................................................... 32
Timer0......................................................................... 93
TMR1 .......................................................................... 46
INTOSC Specifications ............................................. 126, 127
IOC Register ....................................................................... 34
L
Load Conditions ................................................................ 124
M
MCLR .................................................................................. 86
Internal ........................................................................ 86
Memory Organization
Data EEPROM Memory.............................................. 71
Microchip Internet Web Site .............................................. 171
Migrating from other PIC Devices ..................................... 165
MPLAB ASM30 Assembler, Linker, Librarian ................... 112
MPLAB ICD 2 In-Circuit Debugger ................................... 113
MPLAB ICE 2000 High-Performance Universal
In-Circuit Emulator .................................................... 113
MPLAB ICE 4000 High-Performance Universal
In-Circuit Emulator .................................................... 113
MPLAB Integrated Development Environment Software .. 111
MPLAB PM3 Device Programmer .................................... 113
MPLINK Object Linker/MPLIB Object Librarian ................ 112
O
OPCODE Field Descriptions ............................................. 101
OPTION Register .......................................................... 13, 43
OSCCON Register .............................................................. 20
Oscillator
Associated registers.............................................. 30, 48
Oscillator Module ................................................................ 19
EC ............................................................................... 19
HFINTOSC.................................................................. 19
HS ............................................................................... 19
INTOSC ...................................................................... 19
INTOSCIO................................................................... 19
LFINTOSC .................................................................. 19
LP................................................................................ 19
RC............................................................................... 19
RCIO ........................................................................... 19
XT ............................................................................... 19
Oscillator Parameters ....................................................... 126
Oscillator Specifications .................................................... 125
Oscillator Start-up Timer (OST)
Specifications............................................................ 129
Oscillator Switching
Fail-Safe Clock Monitor .............................................. 29
Two-Speed Clock Start-up ......................................... 27
OSCTUNE Register............................................................ 24
P
Packaging ......................................................................... 159
Details....................................................................... 160
Marking..................................................................... 159
PCL and PCLATH............................................................... 18
Computed GOTO ....................................................... 18
Stack........................................................................... 18
PCON Register ............................................................. 17, 88
PICSTART Plus Development Programmer..................... 114
PIE1 Register ..................................................................... 15
Pin Diagram .......................................................................... 2
Pinout Descriptions
PIC12F683 ................................................................... 6
PIR1 Register ..................................................................... 16
Power-Down Mode (Sleep)................................................. 98
Power-On Reset (POR) ...................................................... 86
Power-up Timer (PWRT) .................................................... 86
Specifications ........................................................... 129
Precision Internal Oscillator Parameters .......................... 127
Prescaler
Shared WDT/Timer0................................................... 42
Switching Prescaler Assignment ................................ 42
Program Memory Organization............................................. 7
Map and Stack for the PIC12F683 ............................... 7
Programming, Device Instructions.................................... 101
R
Reader Response............................................................. 172
Read-Modify-Write Operations ......................................... 101
Registers
ADCON0 (ADC Control 0) .......................................... 65
ADRESH (ADC Result High) with ADFM = 0) ............ 66
ADRESH (ADC Result High) with ADFM = 1) ............ 66
ADRESL (ADC Result Low) with ADFM = 0).............. 66
ADRESL (ADC Result Low) with ADFM = 1).............. 66
ANSEL (Analog Select) .............................................. 33
CCP1CON (CCP1 Control) ........................................ 75
CMCON0 (Comparator Control) Register................... 56
CMCON1 (Comparator Control) Register................... 57
CONFIG (Configuration Word) ................................... 84
EEADR (EEPROM Address) ...................................... 71
EECON1 (EEPROM Control 1) .................................. 72
EECON2 (EEPROM Control 2) .................................. 72
EEDAT (EEPROM Data) ............................................ 71
GPIO........................................................................... 31
INTCON (Interrupt Control) ........................................ 14
IOC (Interrupt-on-Change GPIO) ............................... 34
OPTION_REG (OPTION)..................................... 13, 43
OSCCON (Oscillator Control)..................................... 20
OSCTUNE (Oscillator Tuning).................................... 24
PCON (Power Control Register)................................. 17
PCON (Power Control) ............................................... 88
PIE1 (Peripheral Interrupt Enable 1) .......................... 15
PIR1 (Peripheral Interrupt Register 1) ........................ 16
Reset Values .............................................................. 90
Reset Values (Special Registers)............................... 91
STATUS ..................................................................... 12
T1CON ....................................................................... 47
T2CON ....................................................................... 50
TRISIO (Tri-State GPIO) ............................................ 32
VRCON (Voltage Reference Control) ......................... 58
DS41211D-page 169
PIC12F683
WDTCON (Watchdog Timer Control).......................... 97
WPU (Weak Pull-Up GPIO) ........................................ 34
Resets ................................................................................. 85
Brown-out Reset (BOR) .............................................. 85
MCLR Reset, Normal Operation ................................. 85
MCLR Reset, Sleep .................................................... 85
Power-on Reset (POR) ............................................... 85
WDT Reset, Normal Operation ................................... 85
WDT Reset, Sleep ...................................................... 85
Revision History ................................................................ 165
S
Sleep
Power-Down Mode ..................................................... 98
Wake-up...................................................................... 98
Wake-up Using Interrupts ........................................... 98
Software Simulator (MPLAB SIM)..................................... 112
Special Event Trigger.......................................................... 64
Special Function Registers ................................................... 8
STATUS Register................................................................ 12
T
T1CON Register.................................................................. 47
T2CON Register.................................................................. 50
Thermal Considerations .................................................... 123
Time-out Sequence............................................................. 88
Timer0 ................................................................................. 41
Associated Registers .................................................. 43
External Clock ............................................................. 42
Interrupt................................................................. 13, 43
Operation .............................................................. 41, 44
Specifications ............................................................ 130
T0CKI .......................................................................... 42
Timer1 ................................................................................. 44
Associated registers.................................................... 48
Asynchronous Counter Mode ..................................... 45
Reading and Writing ........................................... 45
Interrupt....................................................................... 46
Modes of Operation .................................................... 44
Operation During Sleep .............................................. 46
Oscillator ..................................................................... 45
Prescaler ..................................................................... 45
Specifications ............................................................ 130
Timer1 Gate
Inverting Gate ..................................................... 45
Selecting Source........................................... 45, 57
Synchronizing COUT w/Timer1 .......................... 57
TMR1H Register ......................................................... 44
TMR1L Register .......................................................... 44
Timer2
Associated registers.................................................... 50
Timers
Timer1
T1CON................................................................ 47
Timer2
T2CON................................................................ 50
Timing Diagrams
A/D Conversion ......................................................... 135
A/D Conversion (Sleep Mode) .................................. 135
Brown-out Reset (BOR) ............................................ 128
Brown-out Reset Situations ........................................ 87
CLKOUT and I/O....................................................... 127
Clock Timing ............................................................. 125
Comparator Output ..................................................... 51
Enhanced Capture/Compare/PWM (ECCP) ............. 131
Fail-Safe Clock Monitor (FSCM) ................................. 30
DS41211D-page 170
U
Ultra Low-Power Wake-up............................................ 32, 35
V
Voltage Reference. See Comparator Voltage
Reference (CVREF)
Voltage References
Associated registers ................................................... 59
VREF. SEE ADC Reference Voltage
W
Wake-up Using Interrupts ................................................... 98
Watchdog Timer (WDT)...................................................... 96
Associated Registers .................................................. 97
Clock Source .............................................................. 96
Modes ......................................................................... 96
Period ......................................................................... 96
Specifications ........................................................... 129
WDTCON Register ............................................................. 97
WPU Register ..................................................................... 34
WWW Address ................................................................. 171
WWW, On-Line Support ....................................................... 3
PIC12F683
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Product Support Data sheets and errata, application notes and sample programs, design
resources, users guides and hardware support
documents, latest software releases and archived
software
General Technical Support Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
Business of Microchip Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Development Systems Information Line
Customers should contact their distributor, representative or field application engineer (FAE) for support.
Local sales offices are also available to help customers. A listing of sales offices and locations is included in
the back of this document.
Technical support is available through the web site
at: http://support.microchip.com
DS41211D-page 171
PIC12F683
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
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Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
Application (optional):
Would you like a reply?
Device: PIC12F683
N
Literature Number: DS41211D
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
DS41211D-page 172
PIC12F683
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
/XX
XXX
Device
Temperature
Range
Package
Pattern
Examples:
a)
b)
Device:
PIC12F683(1), PIC12F683T(2)
VDD range 2.0V to 5.5V
Temperature
Range:
I
E
= -40C to +85C(Industrial)
= -40C to +125C (Extended)
Package:
P
MD
MF
SN
=
=
=
=
Pattern:
Plastic DIP
Dual-Flat, No Leads (DFN-S, 4x4x0.9 mm)
Dual-Flat, No Leads (DFN-S, 6x5 mm)
8-lead Small Outline (3.90 mm)
Note 1:
2:
DS41211D-page 173
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Fax: 49-89-627-144-44
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Korea - Gumi
Tel: 82-54-473-4301
Fax: 82-54-473-4302
China - Fuzhou
Tel: 86-591-8750-3506
Fax: 86-591-8750-3521
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Malaysia - Penang
Tel: 60-4-646-8870
Fax: 60-4-646-5086
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
China - Shunde
Tel: 86-757-2839-5507
Fax: 86-757-2839-5571
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Xian
Tel: 86-29-8833-7250
Fax: 86-29-8833-7256
12/08/06
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