Brief Profile

Date: 23rd Nov, 2015

Personal Details
Name

: CHOKKARAPU PRASHANTH

Qualification

: MS in VLSI

Title

: PHYSICAL DESIGN ENGINEER

Total work Experience

: 2 year & 3months (1 year as Internee)

Professional Summary
Physical Design Engineer acting as a Tile Owner in the last and the current projects , successfully
made three tiles ready for Tapeout. Apart from the responsibilities as a Tile Owner (Timing, IR
analysis, Physical Verification ), handled several other tasks useful for the entire team. Used
several industry standard tools like ICC, ICC2, Encounter, Primetime, Finale, Red Hawk, Calibre
and Conformal, scripting languages like Tcl/TK, Perl, python, AWK and c -shell to accomplish the
tasks in a smart way. Apart from the Tools stated above, possess hands -on experience on other
tools like: Spice Design Architect, Virtuoso Layout Editor, NC-Verilog, VHDL and DC Shell tools.

Set
Appreciable content on various DIGITAL STANDARD CELL LIBRARY design concepts.
Skill

Hands-on Experience with EDA tools like SYNOPSYS ICC, ICC2 & PT Shell, MENTOR GRAPHICS
SPICE DESIGN ARCHITECT, ENCOUNTERs CADENCE, VIRTUOSO, NC VERILOG, RED HAWK,
FINALE.

Good Working Knowledge of DESIGN SYNTHESIS and STA (SYNOPSYS -DC, PT-SHELL).

Built inflow in VERILOG HDL and TCL/PERL/PYTHON/AWK/ UNIX SCRIPTING LANGUAGE.

Strong ability to handle the blocks with large gate count.

Good fundamental understanding of CMOS/BICMOS basics.

Possess expertise in DIGITAL and ANALOG CIRCUIT and LAYOUT DESIGN.

Knowledge of complete ASIC FLOW (RTL TO GDSII).

Strong Hold regarding entire NUANCES IN SUBMICRON REGIME (STI): STRESS effects, LOD and
DEVICE ISOLATION TECHNIQUES (TRIPLE NWELL), ELECTROMIGRATION, FDSOI

Projects Worked

Project
Title : Raven
Role: Tile Owner
Team Size: ~100
Period: July 2015 to till
date

Title : Stoney
Role: Tile Owner
Team Size: ~70
Period: Sept. 2015 to
June 2015.

Description

Tile Owner for two tiles with 900k and 360k of instance count, one
tile has 19 clocks among them 8 clocks are major with maximum
frequency of 1.12Ghz. Responsible for cleaning Timing, IR issues,
Physical Verification Issues and Routing. Part of the Flow Czar
team, helped in regression to build-up the flow. This project is at
intermediate stage.
Tile Owner for two tiles till PNR with, handled three tiles and
helped to clean timing in other tiles at ECO stage. Responsible for
cleaning Timing, IR issues, Physical Verification Issues and
Routing.