Lab1.

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Page 1

Lab 1 instructions:
Produce layout for the Four bit ripple carry adder that you have created in Spice. C
reate a DRC and LVS/NCC clean layout view of the circuit described in you working sp
ice simulation. Youll have three labs to complete this. Anticipate that the design
will change as you create better designs.
For those whod rather, you can use CADENCE. I do not have access to CADENCE and the
grad students have not done layout in CADENCE. However there is a deep knowledge of
CADENCE at OSU.
Sizing:
Note that all sizes in Electric are specified with unitless dimensions. While the S
pice transistors are sized in units of micrometers.
The gate length for the transistors in the spice deck I gave you is 80nm.
Electric is defaulted to use lambda rules, the minimum gate length in lambda rules i
s 2 lambda.
Therefore lambda is 40nm.
If your transistor in spice is 10um wide, then this transistor is 250 lambda wide in
Electric.
If this is the size of your transistors, then you should scale back by an order of m
agnitude.
You are using way more power than necessary to implement a simple operation! Also yo
ur layout will be less manageable.
DRC:
While working at the gate level, turn on incremental DRC ( Preferences > Tools >
DRC > checkbox for incremental DRC). This will give you live feedback.
Each DRC error will be give with a reference. The reference is to the DRC rule numbe
r. The dropbox contains a document that provides descriptions and drawings of these
rules.
Id suggest printing out this document and studying the rules when you suffer an inf
raction. I also attached this document to this email.
NCC:
Electric relies upon connectivity. Just because the artwork touches, it does not mea
n that Electric sees this as a connection. Electric uses the term network to descr
ibe connected nodes. Highlighting a node and pressing controlk highlights the whole
network.
General Editing:
If you press controli then a dialogue appears that governs all highlighted nodes.
I would drag all components onto the canvas: contacts, vias, transistors,
then size them
highlight all transistors and contacts and vias that are in the pull up block, pres
s controli give them all the same y location value.
This will align them quickly so that you do not have half lambda offsets.
If you are using gates that are sized and integer multiple of each other, then they
can be quickly constructed by wiring multiple gate in parallel!
This is a huge time saver.
Happy polygon pushing!