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Embedded Systems
with
ARM 7 Controller (LPC 2148 )

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Syllabus
Programming Concepts
GPIO

Introduction to ARM

Embedded Systems
Difference between uC & uP
Difference between RISC & CISC
Instruction Queue
Instruction Pipeline

ARM Architecture

ARM Core Data Flow

ARM processor family 3 Hrs
Exceptions & Interrupt Handling
Application of ARM Processor

Serial Protocol
UART - 12 Hrs

Assembly Language
Working with QEMU
Sample Assembly Programs

Interrupt Programming

LPC2148 Microcontroller

SPI and IIC

Features of LPC2148
Block diagram of LPC2148
Pin diagram of LPC2148
Architectural overview
On-chip flash program memory
On-chip static RAM 6 Hrs

Timers
Real Time Clock

Introduction to Coding Environment

uKEIL
WINARM

Pin Connect Block

General Purpose I/O:
LED and switches interfacing
Buzzer
LCD
DC Motor
44 Matrix Keypad

ADC and DAC

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Session 1

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Embedded Daemons
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Embedded Systems
Combination of hardware and software
that performs a specific task.
Is a system built to perform its duty,
completely or partially independent of
human intervention.
Is specially designed to perform a few
tasks in the most efficient way.
Interacts with physical elements in our
environment, e.g. controlling and driving a
motor, sensing temperature
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Embedded Systems
Characteristics
Specific Purpose
Very strict memory
limitations
Processor
limitations
Speed limitations
Cost Limitations
Accuracy & Timing
constraints
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Micro Processors Vs Micro

Controllers

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uC & uP
Micro Controllers
Specific Purpose
CPU with some
fixed RAM, ROM &
other peripherals
embedded in a
single chip
Clock speed is low
Cost is less

Micro Processors
General Purpose
Just the CPU with no
additional
peripherals within
the IC
Clock speed is
generally high
Cost is also high

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Existing Embedded CPU

Architectures
ARM's
ARM architecture(32-bit)
ARM64(64/32-bit)

Atmel'sAVRarchitecture
Microchip'sPICarchitectur
e
Texas Instruments
MSP430architecture
Intel's8051architecture
Zilog'sZ80architecture
Western Design
Center's65816architectur
e

Hitachi'sSuperHarchitectu
re
Axis
Communications'ETRAX
CRISarchitecture
Power
Architecture(formerlyPow
erPC)
EnSilica'seSiRISCarchitecture
Milkymistarchitecture
Inmos'Transputerarchitec
tures

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CISC & RISC

Complex Instruction
Set Computing
More number of
Instructions
Variable width
Instructions
Macro Instructions
More CPU Cycles
Instruction Queue
Concept
Simplified Compiler

Reduced Instruction
Set Computing
Less number of
Instructions
Fixed Width
Instructions
Micro Instructions
Less CPU Cycles
Instruction Pipeline
Concept
Simplified Instructions

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Instruction Queue
Stores one or more instructions

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Instruction Queue
Stores one or more instructions

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Instruction Pipeline
Parallel execution of multiple instructions
Reads consecutive instruction from memory while previous
instruction are executed in various stages of pipeline
Pipeline Strategy
Instruction pipelining is similar to the use of an assembly line in a
manufacturing plant. An assembly line takes advantage of the
fact that a product goes through various staged of production.
By laying the production process out in an assembly line,
products at various stages can be worked on simultaneously. This
process is also referred to as pipelining, because, as in a pipeline,
new inputs are accepted at one end before previously accepted
inputs appear as outputs at the other end.
To apply this concept to instruction execution, we must recognize
that , in fact , an instruction has a number of stages.

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Instruction Pipeline

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Session 2

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ARM Architecture
ARM Processor Core is a key
component of many successful 32-bit
embedded systems.
ARM 1 Prototype in 1985
Over 1 billion ARM Processors being
shipped- by the end of 2001
ARM Core- Not a single core, but
whole family of design shares similar
design & common instruction set.
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ARM Core Data Flow Model

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Registers

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CPSR
Current Program Status Register

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Seven Operating Modes

USER
Unprivileged mode under which most task run

FIQ
High Priority interrupt is raised

IRQ
Low priority interrupt is raised

Supervisor
Most Privileged

Abort
Invalid memory access

Undef
Handles Undef Instructions

System
Most Priviledged
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Processor Modes

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Exceptions & Interrupts

Exception handling
Specific details of how the ARM
Processor handles exceptions

Interrupts
ARM defines interrupt as special type of
Exception
Interrupt Requests
Interrupts are at Heart of Embedded
Systems

Interrupt handlers

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Exception handling
A software routine that executes when an
exception occurs
Data Abort exception will have a Data Abort
Handler
Handler first determines the cause of
exception and then services the exception
Servicing takes place either within the handler
or by branching to a specific service routine
Reset Exception is a special exception
because it initializes the embedded system
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ARM Processor Exception

Modes

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Vector Table

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Exception Priority Levels

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3 level Nested Interrupt

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Procedure of Handling
Interrupt
An IRQ or FIQ exception causes the processor hardware to
go through a standard procedure (provided the interrupts
are not masked):
1. The processor changes to a specific interrupt request mode,
which reflects the interrupt
being raised.
2. The previous modes cpsr is saved into the spsr of the new
interrupt request mode.
3. The pc is saved in the lr of the new interrupt request mode.
4. Interrupt/s are disabledeither the IRQ or both IRQ and FIQ
exceptions are disabled
in the cpsr. This immediately stops another interrupt request of the
same type being
raised.
5. The processor branches to a specific entry in the vector table.
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Interrupt Handling scheme

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ARM Applications

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ARM 7 applications

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M9 applications

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ARM11 applications

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ARM CortexM applications

Dell E4300
Latitude Laptop
instant boot-up
for users and
access to select
applications,
with multi-day
battery lifetimes
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ARM CortexA applications

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ARM CortexR

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Session 3

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Assembly Language
Instructions in text form
Flow of Assembly language program
.s .o .out [ Linux ]

C Program Flow
.c (Preprocessor) .i (Compiler) .s
(Assembler ) .o (Linker ).out

Advantage is we can observe all

instructions in machine level and
helps in understanding.
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QEMU Installation 5 Mins

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QEMU
QEMU is a FAST! processor emulator using dynamic
translation to achieve good emulation speed.
QEMU has two operating modes:
Full system emulation. In this mode, QEMU emulates a full
system (for example a PC), including one or several
processors and various peripherals. It can be used to
launch different Operating Systems without rebooting the
PC or to debug system code.
User mode emulation. In this mode, QEMU can launch
processes compiled for one CPU on another CPU. It can be
used to launch the Wine Windows API emulator (
http://www.winehq.org) or to ease cross-compilation and
cross-debugging.

QEMU can run without an host kernel driver and yet

gives acceptable performance.
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QEMU Limitations

Current QEMU limitations:

Limited x86-64 support.
IPC syscalls are missing.
The x86 segment limits and access
rights are not tested at every
memory access (yet). Hopefully, very
few OSes seem to rely on that for
normal use.
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Assembly Introduction
Commonly Used Instructions
Moving
MOV , MVN

Arithmetic
ADD, SUB, MUL

Branch
B, BX, BL

Logical
AND, ORR, EOR

Compare
CMP
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Sample Programs
Demo using QEMU
Using Linux Terminal
Some basic Linux commands
VI Editor Working
Sample Programs

Addition, subtraction, multiplication

Odd or Even
Arithmetic Progression
Using Thumb Instructions
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Session 4

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LPC 2148

32 / 16 ARM7TDMI-s CPU
Embedded High Speed Flash Memory
Tiny size & low Power Consumption
LQFP64 package
128 bit wide Interface/ Accelerator enables High Speed 60 MHz
Operation
Blend of Serial Communication Interface
USB 2.0 Full Speed Device
Multiple UARTS
SPI, SSP
IIC
32 bit Timers
10 bit ADC, DAC
PWM Channels
45 Fast GPIO Lines
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LPC2148 development board

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Applications in General

Industrial control
Medical systems
Access control
Point-of-sale
Communication gateway
Embedded soft modem
General purpose applications

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Development board
schematic

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Understanding User Manual of LPC

2148

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Session 5
Programming in ARM

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uKEIL Installation & Introduction to

Programming

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