LIST OF FIGURES

FIGURE NO

DESCRIPTION

PAGE NO

4.1

4-bit Binary to Excess-1 Converter (BEC

21

4.0

4-bit BEC with 8:4 mux

23

4.2

Delay and Area evaluation of an XOR gate

23

4.3

Delay and Area evaluation of a 2:1 Mux gate

23

4.4

Delay and Area evaluation of an Full Adder

23

4.5

Binary Adder Example

24

4.6

1-bit Half Adder

26

4.7

1-bit Full Adder

27

4.8

4-b Ripple Carry Adder

28

4.9

4-bit Carry Look Ahead Adder

29

4.10

4-bit Carry Save Adder

31

The N-bit Ripple Carry Adder constructed by N

4.11

set single bit Full-adder

33

4.12

Carry skip adder structure basic concept

35

4.13

Carry Skip Adder

35

4.14

32-bit Carry skip adder

37

4.15

Block Schematics for First Three Blocks of 32-bit Adder

38

4.16

32-bit Regular CSLA Architecture

42

4.17

Delay and area evaluation of regular SQRT CSLA: (a)

group2,(b)group3, (c) group4, and (d) group5.
F is a Full Adder

LIST OF TABLES
ii

47

TABLE NO

DESCRIPTION

PAGE NO

4.0

Functional Table of 4-Bit BEC

21

iii