CISC

Complex Instruction Set Computer

Large number of complex instructions
Low level
Facilitate the extensive manipulation of lowlevel computational elements and events such
as memory, binary arithmetic, and
addressing.

CISC Examples
Examples of CISC processors are the
System/360(excluding the 'scientific' Model
44),
VAX,
PDP-11,
Motorola 68000 family
Intel x86 architecture based processors.

Pros
Emphasis on hardware
Includes multi-clock complex
instructions
Memory-to-memory:
"LOAD" and "STORE"
incorporated in instructions
Small code sizes,
high cycles per second
Transistors used for storing
complex instructions

Cons
Many specialized CISC instructions were not used
frequently enough to justify their existence.
Because each CISC command must be translated
by the processor into tens or even hundreds of
lines of microcode, it tends to run slower than an
equivalent series of simpler commands that do
not require so much translation.

The CISC Approach

MULT 2:3, 5:2

RISC
Reduced Instruction Set Computer

Small number of instructions

instruction size constant
bans the indirect addressing mode
retains only those instructions that can be
overlapped and made to execute in one machine
cycle or less.

RISC Examples
Apple iPods (custom ARM7TDMI SoC)
Apple iPhone (Samsung ARM1176JZF)
Palm and PocketPC PDAs and smartphones (Intel
XScale family, Samsung SC32442 - ARM9)
Nintendo Game Boy Advance (ARM7)
Nintendo DS (ARM7, ARM9)
Sony Network Walkman (Sony in-house ARM
based chip)
Some Nokia and Sony Ericsson mobile phones

Pros
Emphasis on software
Single-clock,
reduced instruction only
Register to register:
"LOAD" and "STORE"
are independent instructions
Low cycles per second,
large code sizes
Spends more transistors
on memory registers

Pipelining
- fetch instructions from memory
- read registers and decode the instruction
- execute the instruction or calculate an address
- access an operand in data memory
- write the result into a register

The RISC Approach

LOAD A, 2:3
LOAD B, 5:2
PROD A, B
STORE 2:3, A

Performance

Performance
The CISC approach attempts to
minimize the number of instructions
per program, sacrificing the number
of cycles per instruction.
RISC does the opposite, reducing
the cycles per instruction at the
cost of the number of instructions
per program.

RISC vs. CISC

Complex instruction set computer (CISC):
many addressing modes;
many operations.

Reduced instruction set computer (RISC):

load/store;
pipelinable instructions.

ARM assembly language example

label1 ADRr4,c
LDRr0,[r4];acomment
ADRr4,d
LDRr1,[r4]
SUBr0,r0,r1;comment

2008 Wayne Wolf

von Neumann architecture

Memory holds data, instructions.
Central processing unit (CPU) fetches
instructions from memory.
Separate CPU and memory distinguishes
programmable computer.

CPU registers help out: program counter

(PC), instruction register (IR), generalpurpose registers, etc.

CPU + memory
address
memory

data

200
PC
CPU

200

ADD r5,r1,r3

ADD IR
r5,r1,r3

The von Neumann model

Buses

CPU

So where is the
Input/Output?

here

Input

Outpu
t

The Harvard Architecture (1)

Harvard architecture is a computer architecture with
physically separate storage and signal pathways for
instructions and data.
The term originated from the Harvard Mark I relay-based
computer, which stored instructions on punched tape (24
bits wide) and data in electro-mechanical counters (23
digits wide). These early machines had limited data
storage, entirely contained within the data processing unit,
and provided no access to the instruction storage as data,
making loading and modifying programs an entirely offline
process.
2008 Wayne Wolf

The Harvard Architecture (2)

In a computer with a von Neumann architecture (and no
cache), the CPU can be either reading an instruction or
reading/writing data from/to the memory.
Both cannot occur at the same time since the instructions
and data use the same bus system.
In a computer using the Harvard architecture, the CPU can
read both an instruction and perform a data memory access
at the same time, even without a cache.
A Harvard architecture computer can thus be faster for a
given circuit complexity because instruction fetches and
data access do not contend for a single memory pathway.

The Harvard Architecture (3)

In a Harvard architecture, there is no need to
make the two memories share characteristics.
In particular, the word width, timing,
implementation technology, and memory
address structure can differ.
In some systems, instructions can be stored in
read-only memory while data memory
generally requires read-write memory.
Instruction memory is often wider than data
memory.

Harvard architecture
address
data memory

data
address

program memory

data

PC
CPU

Harvard Architecture Example

Block Diagram of the

PIC16C8X

Modified Harvard Architecture

The Modified Harvard architecture is very like the Harvard
architecture but provides a pathway between the instruction memory
and the CPU that allows words from the instruction memory to be
treated as read-only data.
This allows constant data, particularly text strings, to be accessed
without first having to be copied into data memory, thus preserving
more data memory for read/write variables.
Special machine language instructions are provided to read data from
the instruction memory.
Standards-based high-level languages, such as the C language, do not
support the Modified Harvard Architecture, so that in-line assembly or
non-standard extensions are needed to take advantage of it.
Most modern computers that are documented as Harvard Architecture
are, in fact, Modified Harvard Architecture.

von Neumann vs. Harvard

Harvard cant use self-modifying code.
Harvard allows two simultaneous memory
fetches.
Most DSPs use Harvard architecture for
streaming data:
greater memory bandwidth;
more predictable bandwidth.
2008 Wayne Wolf