Professional Documents
Culture Documents
PIC18F2420/2520/4420/4520 Data Sheet
PIC18F2420/2520/4420/4520 Data Sheet
Data Sheet
28/40/44-Pin
Enhanced Flash Microcontrollers
with 10-Bit A/D and nanoWatt Technology
Preliminary
DS39631A
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL,
SmartSensor and The Embedded Control Solutions Company
are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Migratable Memory, MPASM,
MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net,
PICLAB, PICtail, PowerCal, PowerInfo, PowerMate,
PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial,
SmartTel and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
2004, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
DS39631A-page ii
Preliminary
PIC18F2420/2520/4420/4520
28/40/44-Pin Enhanced Flash Microcontrollers with
10-Bit A/D and nanoWatt Technology
Power Managed Modes:
Peripheral Highlights:
Preliminary
DS39631A-page 1
PIC18F2420/2520/4420/4520
Program Memory
Device
Data Memory
I/O
10-bit
A/D (ch)
CCP/
ECCP
(PWM)
MSSP
SPI
Master
I2C
EUSART
Comp.
Timers
8/16-bit
PIC18F2420
16K
8192
768
256
25
10
2/0
1/3
PIC18F2520
32K
16384
1536
256
25
10
2/0
1/3
PIC18F4420
16K
8192
768
256
36
13
1/1
1/3
PIC18F4520
32K
16384
1536
256
36
13
1/1
1/3
DS39631A-page 2
Preliminary
PIC18F2420/2520/4420/4520
Pin Diagrams
28-pin PDIP, SOIC
40-pin PDIP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PIC18F4420
PIC18F4520
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS/HLVDIN/C2OUT
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
OSC1/CLKI/RA7
OSC2/CLKO/RA6
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1/P1A
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PIC18F2420
PIC18F2520
1
2
3
4
5
6
7
8
9
10
11
12
13
14
RA1/AN1
RA0/AN0
28-pin QFN
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RB7/KBI3/PGD
RB6//KBI2/PGC
RB5/KBI1/PGM
RB4/KBI0/AN11
RB3/AN9/CCP2(1)
RB2/INT2/AN8
RB1/INT1/AN10
RB0/INT0/FLT0/AN12
VDD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/KBI0/AN11
RB3/AN9/CCP2(1)
RB2/INT2/AN8
RB1/INT1/AN10
RB0/INT0/FLT0/AN12
VDD
VSS
RD7/PSP7/P1D
RD6/PSP6/P1C
RD5/PSP5/P1B
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
MCLR/VPP/RE3
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4KBI0/AN11
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS/HLVDIN/C2OUT
VSS
OSC1/CLKI/RA7
OSC2/CLKO/RA6
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1
RC3/SCK/SCL
28 27 26 25 24 23 22
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS/HLVDIN/C2OUT
VSS
OSC1/CLKI/RA7
OSC2/CLKO/RA6
1
2
3
4
5
6
7
PIC18F2420
PIC18F2520
21
20
19
18
17
16
15
RB3/AN9/CCP2(1)
RB2/INT2/AN8
RB1/INT1/AN10
RB0/INT0/FLT0/AN12
VDD
VSS
RC7/RX/DT
Note
1:
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
8 9 10 11 12 13 14
Preliminary
DS39631A-page 3
PIC18F2420/2520/4420/4520
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1/P1A
RC1/T1OSI/CCP2(1)
NC
44
43
42
41
40
39
38
37
36
35
34
44-pin TQFP
33
32
31
30
29
28
27
26
25
24
23
PIC18F4420
PIC18F4520
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
NC
RC0/T1OSO/T13CKI
OSC2/CLKO/RA6
OSC1/CLKI/RA7
VSS
VDD
RE2/CS/AN7
RE1/WR/AN6
RE0/RD/AN5
RA5/AN4/SS/HLVDIN/C2OUT
RA4/T0CKI/C1OUT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1/P1A
RC1/T1OSI/CCP2(1)
RC0/T1OSO/T13CKI
NC
NC
RB4/KBI0/AN11
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RC7/RX/DT
RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
VSS
VDD
RB0/INT0/FLT0/AN12
RB1/INT1/AN10
RB2/INT2/AN8
RB3/AN9/CCP2(1)
44
43
42
41
40
39
38
37
36
35
34
44-pin QFN
PIC18F4420
PIC18F4520
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
OSC2/CLKO/RA6
OSC1/CLKI/RA7
VSS
VSS
VDD
VDD
RE2/CS/AN7
RE1/WR/AN6
RE0/RD/AN5
RA5/AN4/SS/HLVDIN/C2OUT
RA4/T0CKI/C1OUT
RB3/AN9/CCP2(1)
NC
RB4/KBI0/AN11
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RC7/RX/DT
RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
VSS
VDD
VDD
RB0/INT0/FLT0/AN12
RB1/INT1/AN10
RB2/INT2/AN8
Note
1:
DS39631A-page 4
Preliminary
PIC18F2420/2520/4420/4520
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 Oscillator Configurations ............................................................................................................................................................ 23
3.0 Power Managed Modes ............................................................................................................................................................. 33
4.0 Reset .......................................................................................................................................................................................... 41
5.0 Memory Organization ................................................................................................................................................................. 53
6.0 Flash Program Memory.............................................................................................................................................................. 73
7.0 Data EEPROM Memory ............................................................................................................................................................. 83
8.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 89
9.0 Interrupts .................................................................................................................................................................................... 91
10.0 I/O Ports ................................................................................................................................................................................... 105
11.0 Timer0 Module ......................................................................................................................................................................... 123
12.0 Timer1 Module ......................................................................................................................................................................... 127
13.0 Timer2 Module ......................................................................................................................................................................... 133
14.0 Timer3 Module ......................................................................................................................................................................... 135
15.0 Capture/Compare/Pwm (CCP) Modules .................................................................................................................................. 139
16.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 147
17.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 161
18.0 Enhanced Universal Synchronous Receiver Transmitter (EUSART)....................................................................................... 201
19.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 223
20.0 Comparator Module.................................................................................................................................................................. 233
21.0 Comparator Voltage Reference Module................................................................................................................................... 239
22.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 243
23.0 Special Features of the CPU.................................................................................................................................................... 249
24.0 Instruction Set Summary .......................................................................................................................................................... 267
25.0 Development Support............................................................................................................................................................... 317
26.0 Electrical Characteristics .......................................................................................................................................................... 323
27.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 361
28.0 Packaging Information.............................................................................................................................................................. 363
Appendix A: Revision History............................................................................................................................................................. 371
Appendix B: Device Differences ........................................................................................................................................................ 371
Appendix C: Conversion Considerations ........................................................................................................................................... 372
Appendix D: Migration from Baseline to Enhanced Devices.............................................................................................................. 372
Appendix E: Migration from Mid-Range to Enhanced Devices .......................................................................................................... 373
Appendix F: Migration from High-End to Enhanced Devices ............................................................................................................. 373
Index .................................................................................................................................................................................................. 375
On-Line Support................................................................................................................................................................................. 385
Systems Information and Upgrade Hot Line ...................................................................................................................................... 385
Reader Response .............................................................................................................................................................................. 386
PIC18F2420/2520/4420/4520 Product Identification System ............................................................................................................ 387
Preliminary
DS39631A-page 5
PIC18F2420/2520/4420/4520
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
Microchips Worldwide Web site; http://www.microchip.com
Your local Microchip sales office (see last page)
The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277
When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include
literature number) you are using.
DS39631A-page 6
Preliminary
PIC18F2420/2520/4420/4520
1.0
DEVICE OVERVIEW
1.1.2
PIC18LF2420
PIC18F2520
PIC18LF2520
PIC18F4420
PIC18LF4420
PIC18F4520
PIC18LF4520
This family offers the advantages of all PIC18 microcontrollers namely, high computational performance
at an economical price with the addition of highendurance, Enhanced Flash program memory. On top
of these features, the PIC18F2420/2520/4420/4520
family introduces design enhancements that make
these microcontrollers a logical choice for many highperformance, power sensitive applications.
1.1
1.1.1
Preliminary
DS39631A-page 7
PIC18F2420/2520/4420/4520
1.2
1.3
DS39631A-page 8
2.
3.
4.
5.
Preliminary
PIC18F2420/2520/4420/4520
TABLE 1-1:
DEVICE FEATURES
Features
Operating Frequency
PIC18F2420
PIC18F2520
PIC18F4420
PIC18F4520
DC 40 MHz
DC 40 MHz
DC 40 MHz
DC 40 MHz
16384
32768
16384
32768
Program Memory
(Instructions)
8192
16384
8192
16384
768
1536
768
1536
256
256
256
256
Interrupt Sources
19
19
20
20
Ports A, B, C, (E)
Ports A, B, C, (E)
Ports A, B, C, D, E
Ports A, B, C, D, E
I/O Ports
Timers
Capture/Compare/PWM Modules
Enhanced
Capture/Compare/PWM Modules
MSSP,
Enhanced USART
MSSP,
Enhanced USART
MSSP,
Enhanced USART
MSSP,
Enhanced USART
Serial Communications
Parallel Communications (PSP)
No
No
Yes
Yes
10 Input Channels
10 Input Channels
13 Input Channels
13 Input Channels
Programmable
High/Low-Voltage Detect
Programmable Brown-out Reset
Instruction Set
Packages
POR, BOR,
POR, BOR,
POR, BOR,
POR, BOR,
RESET Instruction,
RESET Instruction,
RESET Instruction,
RESET Instruction,
Stack Full, Stack
Stack Full, Stack
Stack Full, Stack
Stack Full, Stack
Underflow (PWRT, OST), Underflow (PWRT, OST), Underflow (PWRT, OST), Underflow (PWRT, OST),
MCLR (optional), WDT
MCLR (optional), WDT
MCLR (optional), WDT
MCLR (optional), WDT
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
75 Instructions;
83 with Extended
Instruction Set enabled
75 Instructions;
83 with Extended
Instruction Set enabled
75 Instructions;
83 with Extended
Instruction Set enabled
75 Instructions;
83 with Extended
Instruction Set enabled
28-pin PDIP
28-pin SOIC
28-pin QFN
28-pin PDIP
28-pin SOIC
28-pin QFN
40-pin PDIP
44-pin QFN
44-pin TQFP
40-pin PDIP
44-pin QFN
44-pin TQFP
Preliminary
DS39631A-page 9
PIC18F2420/2520/4420/4520
FIGURE 1-1:
Table Pointer<21>
Data Latch
inc/dec logic
PCLATU PCLATH
21
PORTA
Data Memory
( 3.9 Kbytes )
Address Latch
20
PCU PCH PCL
Program Counter
12
Data Address<12>
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS/HLVDIN/C2OUT
OSC2/CLKO(3)/RA6
OSC1/CLKI(3)/RA7
31 Level Stack
4
BSR
Address Latch
Program Memory
(16/32 Kbytes)
STKPTR
4
Access
Bank
12
FSR0
FSR1
FSR2
Data Latch
12
PORTB
inc/dec
logic
8
Table Latch
Address
Decode
ROM Latch
RB0/INT0/FLT0/AN12
RB1/INT1/AN10
RB2/INT2/AN8
RB3/AN9/CCP2(1)
RB4/KBI0/AN11
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
IR
8
Instruction
Decode and
Control
State machine
control signals
PRODH PRODL
PORTC
3
8
W
BITOP
8
Internal
Oscillator
Block
Power-up
Timer
T1OSI
INTRC
Oscillator
T1OSO
8 MHz
Oscillator
Oscillator
Start-up Timer
Power-on
Reset
OSC1(3)
OSC2
(3)
VDD, VSS
8
ALU<8>
8
Brown-out
Reset
Fail-Safe
Clock Monitor
Precision
Band Gap
Reference
PORTE
MCLR/VPP/RE3(2)
BOR
HLVD
Data
EEPROM
Timer0
Timer1
Timer2
Timer3
Comparator
CCP1
CCP2
MSSP
EUSART
ADC
10-bit
Note
Watchdog
Timer
Single-Supply
Programming
In-Circuit
Debugger
MCLR(2)
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
8 x 8 Multiply
1:
CCP2 is multiplexed with RC1 when configuration bit CCP2MX is set, or RB3 when CCP2MX is not set.
2:
3:
OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.
Refer to Section 2.0 Oscillator Configurations for additional information.
DS39631A-page 10
Preliminary
PIC18F2420/2520/4420/4520
FIGURE 1-2:
PORTA
Table Pointer<21>
Data Memory
( 3.9 Kbytes )
PCLATU PCLATH
21
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS/HLVDIN/C2OUT
OSC2/CLKO(3)/RA6
OSC1/CLKI(3)/RA7
Data Latch
inc/dec logic
Address Latch
20
PCU PCH PCL
Program Counter
12
Data Address<12>
PORTB
31 Level Stack
4
BSR
Address Latch
Program Memory
(16/32 Kbytes)
STKPTR
Data Latch
12
FSR0
FSR1
FSR2
RB0/INT0/FLT0/AN12
RB1/INT1/AN10
RB2/INT2/AN8
RB3/AN9/CCP2(1)
RB4/KBI0/AN11
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
4
Access
Bank
12
inc/dec
logic
8
Table Latch
PORTC
Address
Decode
ROM Latch
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1/P1A
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
IR
8
State machine
control signals
Instruction
Decode and
Control
PRODH PRODL
3
8 x 8 Multiply
8
W
BITOP
8
Internal
Oscillator
Block
Power-up
Timer
T1OSI
INTRC
Oscillator
T1OSO
8 MHz
Oscillator
Oscillator
Start-up Timer
Power-on
Reset
OSC1(3)
OSC2
(3)
Single-Supply
Programming
In-Circuit
Debugger
MCLR(2)
VDD, VSS
ALU<8>
8
PORTE
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
MCLR/VPP/RE3(2)
Precision
Band Gap
Reference
BOR
HLVD
Data
EEPROM
Timer0
Timer1
Timer2
Timer3
Comparator
ECCP1
CCP2
MSSP
EUSART
ADC
10-bit
Note
RD0/PSP0 :RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
Watchdog
Timer
Brown-out
Reset
Fail-Safe
Clock Monitor
PORTD
1:
CCP2 is multiplexed with RC1 when configuration bit CCP2MX is set, or RB3 when CCP2MX is not set.
2:
3:
OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.
Refer to Section 2.0 Oscillator Configurations for additional information.
Preliminary
DS39631A-page 11
PIC18F2420/2520/4420/4520
TABLE 1-2:
Pin Name
MCLR/VPP/RE3
MCLR
Pin Buffer
PDIP,
QFN Type Type
SOIC
1
26
VPP
RE3
OSC1/CLKI/RA7
OSC1
ST
P
I
ST
ST
CLKO
RA6
I/O
TTL
RA7
OSC2/CLKO/RA6
OSC2
10
CLKI
Description
Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.
DS39631A-page 12
Preliminary
PIC18F2420/2520/4420/4520
TABLE 1-2:
Pin Name
Pin Number
Pin Buffer
PDIP,
QFN Type Type
SOIC
Description
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
RA1/AN1
RA1
AN1
RA2/AN2/VREF-/CVREF
RA2
AN2
VREFCVREF
RA3/AN3/VREF+
RA3
AN3
VREF+
RA4/T0CKI/C1OUT
RA4
T0CKI
C1OUT
RA5/AN4/SS/HLVDIN/
C2OUT
RA5
AN4
SS
HLVDIN
C2OUT
27
I/O
TTL
I Analog
Digital I/O.
Analog input 0.
I/O
TTL
I Analog
Digital I/O.
Analog input 1.
I/O
TTL
I Analog
I Analog
O Analog
Digital I/O.
Analog input 2.
A/D reference voltage (low) input.
Comparator reference voltage output.
I/O
TTL
I Analog
I Analog
Digital I/O.
Analog input 3.
A/D reference voltage (high) input.
I/O
I
O
Digital I/O.
Timer0 external clock input.
Comparator 1 output.
28
3
ST
ST
4
I/O
TTL
I Analog
I
TTL
I Analog
O
Digital I/O.
Analog input 4.
SPI slave select input.
High/Low-Voltage Detect input.
Comparator 2 output.
RA6
RA7
Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.
Preliminary
DS39631A-page 13
PIC18F2420/2520/4420/4520
TABLE 1-2:
Pin Name
Pin Number
Pin Buffer
PDIP,
QFN Type Type
SOIC
Description
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT0/FLT0/AN12
RB0
INT0
FLT0
AN12
21
RB1/INT1/AN10
RB1
INT1
AN10
22
RB2/INT2/AN8
RB2
INT2
AN8
23
RB3/AN9/CCP2
RB3
AN9
CCP2(1)
24
RB4/KBI0/AN11
RB4
KBI0
AN11
25
RB5/KBI1/PGM
RB5
KBI1
PGM
26
RB6/KBI2/PGC
RB6
KBI2
PGC
27
RB7/KBI3/PGD
RB7
KBI3
PGD
28
18
I/O
TTL
I
ST
I
ST
I Analog
Digital I/O.
External interrupt 0.
PWM Fault input for CCP1.
Analog input 12.
I/O
TTL
I
ST
I Analog
Digital I/O.
External interrupt 1.
Analog input 10.
I/O
TTL
I
ST
I Analog
Digital I/O.
External interrupt 2.
Analog input 8.
I/O
TTL
I Analog
I/O
ST
Digital I/O.
Analog input 9.
Capture 2 input/Compare 2 output/PWM 2 output.
I/O
TTL
I
TTL
I Analog
Digital I/O.
Interrupt-on-change pin.
Analog input 11.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
Low-Voltage ICSP Programming enable pin.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
19
20
21
22
23
24
25
Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.
DS39631A-page 14
Preliminary
PIC18F2420/2520/4420/4520
TABLE 1-2:
Pin Name
Pin Number
Pin Buffer
PDIP,
QFN Type Type
SOIC
Description
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI
11
RC1/T1OSI/CCP2
RC1
T1OSI
CCP2(2)
12
RC2/CCP1
RC2
CCP1
13
RC3/SCK/SCL
RC3
SCK
SCL
14
RC4/SDI/SDA
RC4
SDI
SDA
15
RC5/SDO
RC5
SDO
16
RC6/TX/CK
RC6
TX
CK
17
RC7/RX/DT
RC7
RX
DT
18
RE3
VSS
VDD
8
I/O
O
I
ST
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
9
I/O
ST
I Analog
I/O
ST
10
I/O
I/O
ST
ST
Digital I/O.
Capture 1 input/Compare 1 output/PWM 1 output.
I/O
I/O
I/O
ST
ST
ST
Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C mode.
I/O
I
I/O
ST
ST
ST
Digital I/O.
SPI data in.
I2C data I/O.
I/O
O
ST
Digital I/O.
SPI data out.
I/O
O
I/O
ST
ST
Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see related RX/DT).
I/O
I
I/O
ST
ST
ST
Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see related TX/CK).
11
12
13
14
15
8, 19 5, 16
20
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM 2 output.
17
Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.
Preliminary
DS39631A-page 15
PIC18F2420/2520/4420/4520
TABLE 1-3:
Pin Name
MCLR/VPP/RE3
MCLR
Pin Number
PDIP
1
Pin Buffer
QFN TQFP Type Type
18
18
VPP
RE3
OSC1/CLKI/RA7
OSC1
13
32
ST
P
I
ST
30
I
CLKI
RA7
OSC2/CLKO/RA6
OSC2
I/O
14
33
Description
Master Clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
Programming voltage input.
Digital input.
31
O
CLKO
RA6
I/O
TTL
Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.
DS39631A-page 16
Preliminary
PIC18F2420/2520/4420/4520
TABLE 1-3:
Pin Name
Pin Number
PDIP
Pin Buffer
QFN TQFP Type Type
Description
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
RA1/AN1
RA1
AN1
RA2/AN2/VREF-/CVREF
RA2
AN2
VREFCVREF
RA3/AN3/VREF+
RA3
AN3
VREF+
RA4/T0CKI/C1OUT
RA4
T0CKI
C1OUT
RA5/AN4/SS/HLVDIN/
C2OUT
RA5
AN4
SS
HLVDIN
C2OUT
19
20
21
22
23
24
19
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
I/O
I
I
O
TTL
Analog
Analog
Analog
Digital I/O.
Analog input 2.
A/D reference voltage (low) input.
Comparator reference voltage output.
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (high) input.
I/O
I
O
ST
ST
I/O
I
I
I
O
TTL
Analog
TTL
Analog
20
21
22
23
Digital I/O.
Timer0 external clock input.
Comparator 1 output.
24
Digital I/O.
Analog input 4.
SPI slave select input.
High/Low-Voltage Detect input.
Comparator 2 output.
RA6
RA7
Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.
Preliminary
DS39631A-page 17
PIC18F2420/2520/4420/4520
TABLE 1-3:
Pin Name
Pin Number
PDIP
Pin Buffer
QFN TQFP Type Type
Description
PORTB is a bidirectional I/O port. PORTB can be
software programmed for internal weak pull-ups on all
inputs.
RB0/INT0/FLT0/AN12
RB0
INT0
FLT0
AN12
33
RB1/INT1/AN10
RB1
INT1
AN10
34
RB2/INT2/AN8
RB2
INT2
AN8
35
RB3/AN9/CCP2
RB3
AN9
CCP2(1)
36
RB4/KBI0/AN11
RB4
KBI0
AN11
37
RB5/KBI1/PGM
RB5
KBI1
PGM
38
RB6/KBI2/PGC
RB6
KBI2
PGC
39
RB7/KBI3/PGD
RB7
KBI3
PGD
40
10
11
12
14
15
16
17
8
I/O
I
I
I
TTL
ST
ST
Analog
Digital I/O.
External interrupt 0.
PWM Fault input for Enhanced CCP1.
Analog input 12.
I/O
I
I
TTL
ST
Analog
Digital I/O.
External interrupt 1.
Analog input 10.
I/O
I
I
TTL
ST
Analog
Digital I/O.
External interrupt 2.
Analog input 8.
I/O
I
I/O
TTL
Analog
ST
Digital I/O.
Analog input 9.
Capture 2 input/Compare 2 output/PWM 2 output.
I/O
I
I
TTL
TTL
Analog
Digital I/O.
Interrupt-on-change pin.
Analog input 11.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
Low-Voltage ICSP Programming enable pin.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming
clock pin.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming
data pin.
10
11
14
15
16
17
Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.
DS39631A-page 18
Preliminary
PIC18F2420/2520/4420/4520
TABLE 1-3:
Pin Name
Pin Number
PDIP
Pin Buffer
QFN TQFP Type Type
Description
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI
15
RC1/T1OSI/CCP2
RC1
T1OSI
CCP2(2)
16
RC2/CCP1/P1A
RC2
CCP1
P1A
17
RC3/SCK/SCL
RC3
SCK
18
34
35
36
37
32
23
RC5/SDO
RC5
SDO
24
RC6/TX/CK
RC6
TX
CK
25
RC7/RX/DT
RC7
RX
DT
26
42
43
44
ST
ST
I/O
I
I/O
ST
CMOS
ST
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM 2 output.
I/O
I/O
O
ST
ST
Digital I/O.
Capture 1 input/Compare 1 output/PWM 1 output.
Enhanced CCP1 output.
I/O
I/O
ST
ST
I/O
ST
Digital I/O.
Synchronous serial clock input/output for
SPI mode.
Synchronous serial clock input/output for I2C mode.
I/O
I
I/O
ST
ST
ST
Digital I/O.
SPI data in.
I2C data I/O.
I/O
O
ST
Digital I/O.
SPI data out.
I/O
O
I/O
ST
ST
Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see related RX/DT).
I/O
I
I/O
ST
ST
ST
Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see related TX/CK).
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
35
36
37
SCL
RC4/SDI/SDA
RC4
SDI
SDA
I/O
O
I
42
43
44
Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.
Preliminary
DS39631A-page 19
PIC18F2420/2520/4420/4520
TABLE 1-3:
Pin Name
Pin Buffer
QFN TQFP Type Type
Description
PORTD is a bidirectional I/O port or a Parallel Slave
Port (PSP) for interfacing to a microprocessor port.
These pins have TTL input buffers when PSP module
is enabled.
RD0/PSP0
RD0
PSP0
19
RD1/PSP1
RD1
PSP1
20
RD2/PSP2
RD2
PSP2
21
RD3/PSP3
RD3
PSP3
22
RD4/PSP4
RD4
PSP4
27
RD5/PSP5/P1B
RD5
PSP5
P1B
28
RD6/PSP6/P1C
RD6
PSP6
P1C
29
RD7/PSP7/P1D
RD7
PSP7
P1D
30
38
39
40
41
38
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
I/O
I/O
O
ST
TTL
Digital I/O.
Parallel Slave Port data.
Enhanced CCP1 output.
I/O
I/O
O
ST
TTL
Digital I/O.
Parallel Slave Port data.
Enhanced CCP1 output.
I/O
I/O
O
ST
TTL
Digital I/O.
Parallel Slave Port data.
Enhanced CCP1 output.
39
40
41
Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.
DS39631A-page 20
Preliminary
PIC18F2420/2520/4420/4520
TABLE 1-3:
Pin Name
Pin Buffer
QFN TQFP Type Type
Description
PORTE is a bidirectional I/O port.
RE0/RD/AN5
RE0
RD
25
25
AN5
RE1/WR/AN6
RE1
WR
26
10
27
Analog
I/O
I
ST
TTL
Analog
I/O
I
ST
TTL
Digital I/O.
Read control for Parallel Slave Port
(see also WR and CS pins).
Analog input 5.
Digital I/O.
Write control for Parallel Slave Port
(see CS and RD pins).
Analog input 6.
27
AN7
RE3
ST
TTL
26
AN6
RE2/CS/AN7
RE2
CS
I/O
I
Digital I/O.
Chip Select control for Parallel Slave Port
(see related RD and WR).
Analog input 7.
Analog
6, 29
7, 8, 7, 28
28, 29
No connect.
VSS
12, 31 6, 30,
31
VDD
11, 32
NC
13
12, 13,
33, 34
Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.
Preliminary
DS39631A-page 21
PIC18F2420/2520/4420/4520
NOTES:
DS39631A-page 22
Preliminary
PIC18F2420/2520/4420/4520
2.0
OSCILLATOR
CONFIGURATIONS
2.1
Oscillator Types
FIGURE 2-1:
C1(1)
Low-Power Crystal
Crystal/Resonator
High-Speed Crystal/Resonator
High-Speed Crystal/Resonator
with PLL enabled
5. RC
External Resistor/Capacitor with
FOSC/4 output on RA6
6. RCIO
External Resistor/Capacitor with I/O
on RA6
7. INTIO1 Internal Oscillator with FOSC/4 output
on RA6 and I/O on RA7
8. INTIO2 Internal Oscillator with I/O on RA6
and RA7
9. EC
External Clock with FOSC/4 output
10. ECIO
External Clock with I/O on RA6
C2(1)
Sleep
PIC18FXXXX
OSC2
Note 1:
2:
3:
TABLE 2-1:
Freq
OSC1
OSC2
XT
3.58 MHz
4.19 MHz
4 MHz
4 MHz
15 pF
15 pF
30 pF
50 pF
15 pF
15 pF
30 pF
50 pF
Crystal Oscillator/Ceramic
Resonators
To
Internal
Logic
RF(3)
RS(2)
Note:
OSC1
XTAL
LP
XT
HS
HSPLL
2.2
CRYSTAL/CERAMIC
RESONATOR OPERATION
(XT, LP, HS OR HSPLL
CONFIGURATION)
Preliminary
DS39631A-page 23
PIC18F2420/2520/4420/4520
TABLE 2-2:
Osc Type
C2
LP
32 kHz
30 pF
30 pF
XT
1 MHz
4 MHz
15 pF
15 pF
15 pF
15 pF
HS
4 MHz
10 MHz
20 MHz
25 MHz
25 MHz
15 pF
15 pF
15 pF
0 pF
15 pF
15 pF
15 pF
15 pF
5 pF
15 pF
FIGURE 2-2:
OSC1
Clock from
Ext. System
PIC18FXXXX
Open
2.3
4 MHz
25 MHz
10 MHz
1 MHz
20 MHz
EXTERNAL CLOCK
INPUT OPERATION
(EC CONFIGURATION)
OSC1/CLKI
Clock from
Ext. System
(HS Mode)
OSC2
FIGURE 2-3:
Crystals Used:
PIC18FXXXX
FOSC/4
OSC2/CLKO
FIGURE 2-4:
Preliminary
EXTERNAL CLOCK
INPUT OPERATION
(ECIO CONFIGURATION)
OSC1/CLKI
Clock from
Ext. System
DS39631A-page 24
PIC18FXXXX
RA6
I/O (OSC2)
PIC18F2420/2520/4420/4520
2.4
RC Oscillator
2.5
2.5.1
Given the same device, operating voltage and temperature and component values, there will also be unit-to-unit
frequency variations. These are due to factors such as:
normal manufacturing variation
difference in lead frame capacitance between
package types (especially for low CEXT values)
variations within the tolerance of limits of REXT
and CEXT
FIGURE 2-5:
FIGURE 2-7:
HS Oscillator Enable
PLL Enable
(from Configuration Register 1H)
RC OSCILLATOR MODE
VDD
OSC2
HS Mode
OSC1 Crystal
Osc
REXT
OSC1
Internal
Clock
FIN
FOUT
Loop
Filter
CEXT
PIC18FXXXX
VSS
FOSC/4
OSC2/CLKO
4
VDD
REXT
OSC1
VCO
MUX
FIGURE 2-6:
Phase
Comparator
Internal
Clock
2.5.2
SYSCLK
CEXT
PIC18FXXXX
VSS
RA6
I/O (OSC2)
Preliminary
DS39631A-page 25
PIC18F2420/2520/4420/4520
2.6
Power-up Timer
Fail-Safe Clock Monitor
Watchdog Timer
Two-Speed Start-up
2.6.1
INTIO MODES
Using the internal oscillator as the clock source eliminates the need for up to two external oscillator pins,
which can then be used for digital I/O. Two distinct
configurations are available:
In INTIO1 mode, the OSC2 pin outputs FOSC/4,
while OSC1 functions as RA7 for digital input and
output.
In INTIO2 mode, OSC1 functions as RA7 and
OSC2 functions as RA6, both for digital input and
output.
2.6.2
2.6.3
OSCTUNE REGISTER
DS39631A-page 26
2.6.4
The 4x frequency multiplier can be used with the internal oscillator block to produce faster device clock
speeds than are normally possible with an internal
oscillator. When enabled, the PLL produces a clock
speed of up to 32 MHz.
Unlike HSPLL mode, the PLL is controlled through
software. The control bit, PLLEN (OSCTUNE<6>), is
used to enable or disable its operation.
The PLL is available when the device is configured to
use the internal oscillator block as its primary clock
source (FOSC3:FOSC0 = 1001 or 1000). Additionally,
the PLL will only function when the selected output frequency is either 4 MHz or 8 MHz (OSCCON<6:4> = 111
or 110). If both of these conditions are not met, the PLL
is disabled.
The PLLEN control bit is only functional in those internal oscillator modes where the PLL is available. In all
other modes, it is forced to 0 and is effectively
unavailable.
2.6.5
Preliminary
PIC18F2420/2520/4420/4520
REGISTER 2-1:
R/W-0(1)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INTSRC
PLLEN(1)
TUN4
TUN3
TUN2
TUN1
TUN0
bit 7
bit 0
bit 7
bit 6
bit 5
Unimplemented: Read as 0
bit 4-0
00001
00000 = Center frequency. Oscillator module is running at the calibrated frequency.
11111
2.6.5.1
W = Writable bit
1 = Bit is set
2.6.5.3
2.6.5.2
Preliminary
DS39631A-page 27
PIC18F2420/2520/4420/4520
2.7
Primary oscillators
Secondary oscillators
Internal oscillator block
The primary oscillators include the External Crystal
and Resonator modes, the External RC modes, the
External Clock modes and the internal oscillator block.
The particular mode is defined by the FOSC3:FOSC0
configuration bits. The details of these modes are
covered earlier in this chapter.
FIGURE 2-8:
PIC18F2420/2520/4420/4520
Primary Oscillator
OSC2
Sleep
4 x PLL
OSC1
Secondary Oscillator
T1OSCEN
Enable
Oscillator
OSCCON<6:4>
8 MHz
OSCCON<6:4>
4 MHz
INTRC
Source
Internal Oscillator
CPU
111
110
2 MHz
31 kHz (INTRC)
1 MHz
500 kHz
250 kHz
125 kHz
IDLEN
101
100
011
MUX
8 MHz
(INTOSC)
Postscaler
Internal
Oscillator
Block
8 MHz
Source
Peripherals
MUX
T1OSC
T1OSO
T1OSI
HSPLL, INTOSC/PLL
OSCTUNE<6>
010
001
1 31 kHz
000
0
Clock
Control
FOSC3:FOSC0
OSCCON<1:0>
OSCTUNE<7>
WDT, PWRT, FSCM
and Two-Speed Start-up
DS39631A-page 28
Preliminary
PIC18F2420/2520/4420/4520
2.7.1
2.7.2
OSCILLATOR TRANSITIONS
Preliminary
DS39631A-page 29
PIC18F2420/2520/4420/4520
REGISTER 2-2:
OSCCON REGISTER
R/W-0
R/W-1
R/W-0
R/W-0
R(1)
R-0
R/W-0
R/W-0
IDLEN
IRCF2
IRCF1
IRCF0
OSTS
IOFS
SCS1
SCS0
bit 7
bit 0
bit 7
bit 6-4
bit 3
bit 2
bit 1-0
DS39631A-page 30
W = Writable bit
1 = Bit is set
Preliminary
PIC18F2420/2520/4420/4520
2.8
When PRI_IDLE mode is selected, the designated primary oscillator continues to run without interruption.
For all other power managed modes, the oscillator
using the OSC1 pin is disabled. The OSC1 pin (and
OSC2 pin, if used by the oscillator) will stop oscillating.
In secondary clock modes (SEC_RUN and
SEC_IDLE), the Timer1 oscillator is operating and providing the device clock. The Timer1 oscillator may also
run in all power managed modes if required to clock
Timer1 or Timer3.
In internal oscillator modes (RC_RUN and RC_IDLE),
the internal oscillator block provides the device clock
source. The 31 kHz INTRC output can be used directly
to provide the clock and may be enabled to support
various special features, regardless of the power
managed mode (see Section 23.2 Watchdog Timer
(WDT), Section 23.3 Two-Speed Start-up and
Section 23.4 Fail-Safe Clock Monitor for more
information on WDT, Fail-Safe Clock Monitor and TwoSpeed Start-up). The INTOSC output at 8 MHz may be
used directly to clock the device or may be divided
down by the postscaler. The INTOSC output is disabled
if the clock is provided directly from the INTRC output.
If the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).
Enabling any on-chip feature that will operate during
Sleep will increase the current consumed during Sleep.
The INTRC is required to support WDT operation. The
Timer1 oscillator may be operating to support a realtime clock. Other features may be operating that do not
TABLE 2-3:
2.9
Power-up Delays
OSC Mode
OSC1 Pin
OSC2 Pin
RC, INTIO1
RCIO
INTIO2
ECIO
EC
LP, XT and HS
Note:
See Table 4-2 in Section 4.0 Reset for time-outs due to Sleep and MCLR Reset.
Preliminary
DS39631A-page 31
PIC18F2420/2520/4420/4520
NOTES:
DS39631A-page 32
Preliminary
PIC18F2420/2520/4420/4520
3.0
3.1.1
CLOCK SOURCES
3.1.2
Run modes
Idle modes
Sleep mode
3.1
TABLE 3-1:
Mode
IDLEN(1) SCS1:SCS0
<7>
<1:0>
Sleep
Module Clocking
Available Clock and Oscillator Source
CPU
Peripherals
N/A
Off
Off
PRI_RUN
N/A
00
Clocked
Clocked
SEC_RUN
N/A
01
Clocked
Clocked
RC_RUN
N/A
1x
Clocked
Clocked
PRI_IDLE
00
Off
Clocked
SEC_IDLE
01
Off
Clocked
RC_IDLE
1x
Off
Clocked
Note 1:
2:
DS39631A-page 33
PIC18F2420/2520/4420/4520
3.1.3
3.1.4
DS39631A-page 34
3.2
Run Modes
3.2.1
PRI_RUN MODE
3.2.2
SEC_RUN MODE
PIC18F2420/2520/4420/4520
FIGURE 3-1:
Q2
1
T1OSI
n-1
Q3
Q4
Q1
Q2
Q3
Clock Transition(1)
OSC1
CPU
Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
PC + 4
FIGURE 3-2:
Q2
Q3
Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3
T1OSI
OSC1
TOST(1)
TPLL(1)
1
PLL Clock
Output
n-1 n
Clock
Transition(2)
CPU Clock
Peripheral
Clock
Program
Counter
SCS1:SCS0 bits changed
PC + 2
PC
PC + 4
Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
2: Clock transition typically occurs within 2-4 TOSC.
3.2.3
RC_RUN MODE
DS39631A-page 35
PIC18F2420/2520/4420/4520
If the IRCF bits and the INTSRC bit are all clear, the
INTOSC output is not enabled and the IOFS bit will
remain clear; there will be no indication of the current
clock source. The INTRC source is providing the
device clocks.
FIGURE 3-3:
Q2
1
INTRC
n-1
Q3
Q4
Q1
Q2
Q3
Clock Transition(1)
OSC1
CPU
Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
PC + 4
FIGURE 3-4:
Q2
Q3
Q4
Q2 Q3 Q4 Q1 Q2 Q3
Q1
INTOSC
Multiplexer
OSC1
TOST(1)
TPLL(1)
1
PLL Clock
Output
n-1 n
Clock
Transition(2)
CPU Clock
Peripheral
Clock
Program
Counter
SCS1:SCS0 bits changed
PC + 2
PC
PC + 4
Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
2: Clock transition typically occurs within 2-4 TOSC.
DS39631A-page 36
PIC18F2420/2520/4420/4520
3.3
Sleep Mode
3.4
Idle Modes
Entering the Sleep mode from any other mode does not
require a clock switch. This is because no clocks are
needed once the controller has entered Sleep. If the
WDT is selected, the INTRC source will continue to
operate. If the Timer1 oscillator is enabled, it will also
continue to run.
FIGURE 3-5:
Q1 Q2 Q3 Q4 Q1
OSC1
CPU
Clock
Peripheral
Clock
Sleep
Program
Counter
PC
FIGURE 3-6:
PC + 2
Q1
OSC1
TOST(1)
PLL Clock
Output
TPLL(1)
CPU Clock
Peripheral
Clock
Program
Counter
PC
Wake Event
PC + 2
PC + 4
PC + 6
Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
DS39631A-page 37
PIC18F2420/2520/4420/4520
3.4.1
PRI_IDLE MODE
3.4.2
SEC_IDLE MODE
FIGURE 3-7:
Q3
Q2
Q4
Q1
OSC1
CPU Clock
Peripheral
Clock
Program
Counter
PC
FIGURE 3-8:
PC + 2
Q2
Q3
Q4
OSC1
TCSD
CPU Clock
Peripheral
Clock
Program
Counter
PC
Wake Event
DS39631A-page 38
PIC18F2420/2520/4420/4520
3.4.3
RC_IDLE MODE
In RC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the internal oscillator
block using the INTOSC multiplexer. This mode allows
for controllable power conservation during Idle periods.
From RC_RUN, this mode is entered by setting the
IDLEN bit and executing a SLEEP instruction. If the
device is in another Run mode, first set IDLEN, then set
the SCS1 bit and execute SLEEP. Although its value is
ignored, it is recommended that SCS0 also be cleared;
this is to maintain software compatibility with future
devices. The INTOSC multiplexer may be used to
select a higher clock frequency by modifying the IRCF
bits before executing the SLEEP instruction. When the
clock source is switched to the INTOSC multiplexer, the
primary oscillator is shut down and the OSTS bit is
cleared.
If the IRCF bits are set to any non-zero value, or the
INTSRC bit is set, the INTOSC output is enabled. The
IOFS bit becomes set, after the INTOSC output
becomes stable, after an interval of TIOBST
(parameter 39, Table 26-10). Clocks to the peripherals
continue while the INTOSC source stabilizes. If the
IRCF bits were previously at a non-zero value, or
INTSRC was set before the SLEEP instruction was executed and the INTOSC source was already stable, the
IOFS bit will remain set. If the IRCF bits and INTSRC
are all clear, the INTOSC output will not be enabled, the
IOFS bit will remain clear and there will be no indication
of the current clock source.
When a wake event occurs, the peripherals continue to
be clocked from the INTOSC multiplexer. After a delay
of TCSD following the wake event, the CPU begins executing code being clocked by the INTOSC multiplexer.
The IDLEN and SCS bits are not affected by the wakeup. The INTRC source will continue to run if either the
WDT or the Fail-Safe Clock Monitor is enabled.
3.5
3.5.1
EXIT BY INTERRUPT
3.5.2
3.5.3
EXIT BY RESET
DS39631A-page 39
PIC18F2420/2520/4420/4520
3.5.4
TABLE 3-2:
EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
Clock Source
before Wake-up
Clock Source
after Wake-up
Exit Delay
LP, XT, HS
Primary Device Clock
(PRI_IDLE mode)
HSPLL
EC, RC
TCSD(1)
INTOSC(2)
T1OSC or INTRC(1)
INTOSC(2)
None
(Sleep mode)
2:
3:
4:
IOFS
LP, XT, HS
TOST(3)
HSPLL
TOST + trc(3)
OSTS
EC, RC
INTOSC(1)
TCSD(1)
TIOBST(4)
IOFS
LP, XT, HS
TOST(4)
HSPLL
TOST + trc(3)
EC, RC
TCSD(1)
INTOSC(1)
None
LP, XT, HS
TOST(3)
HSPLL
TOST + trc(3)
OSTS
EC, RC
TCSD(1)
TIOBST(4)
IOFS
INTOSC(1)
Note 1:
OSTS
OSTS
IOFS
TCSD (parameter
38) is a required delay when waking from Sleep and all Idle modes and runs concurrently
with any other required delays (see Section 3.4 Idle Modes). On Reset, INTOSC defaults to 1 MHz.
Includes both the INTOSC 8 MHz source and postscaler derived frequencies.
TOST is the Oscillator Start-up Timer (parameter 32). trc is the PLL Lock-out Timer (parameter F12); it is
also designated as TPLL.
Execution continues during TIOBST (parameter 39), the INTOSC stabilization period.
DS39631A-page 40
PIC18F2420/2520/4420/4520
4.0
RESET
RCON Register
FIGURE 4-1:
4.1
RESET
Instruction
Stack Full/Underflow Reset
Stack
Pointer
External Reset
MCLRE
MCLR
( )_IDLE
Sleep
WDT
Time-out
VDD Rise
Detect
POR Pulse
VDD
Brown-out
Reset
BOREN
OST/PWRT
OST
1024 Cycles
Chip_Reset
OSC1
32 s
INTRC(1)
PWRT
65.5 ms
Enable PWRT
Enable OST(2)
Note 1:
2:
This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin.
See Table 4-2 for time-out situations.
Preliminary
DS39631A-page 41
PIC18F2420/2520/4420/4520
REGISTER 4-1:
RCON REGISTER
R/W-0
R/W-1(1)
U-0
R/W-1
R-1
R-1
R/W-0(2)
R/W-0
IPEN
SBOREN
RI
TO
PD
POR
BOR
bit 7
bit 0
bit 7
bit 6
bit 5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
bit 1
bit 0
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
Note 1: It is recommended that the POR bit be set after a Power-on Reset has been
detected so that subsequent Power-on Resets may be detected.
2: Brown-out Reset is said to have occurred when BOR is 0 and POR is 1 (assuming
that POR was set to 1 by software immediately after POR).
DS39631A-page 42
Preliminary
PIC18F2420/2520/4420/4520
4.2
FIGURE 4-2:
4.3
VDD
VDD
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
R
R1
MCLR
C
PIC18FXXXX
Note 1:
2:
3:
Preliminary
DS39631A-page 43
PIC18F2420/2520/4420/4520
4.4
4.4.1
TABLE 4-1:
4.4.2
DETECTING BOR
4.4.3
BOR CONFIGURATIONS
BOR Configuration
BOREN1
BOREN0
Status of
SBOREN
(RCON<6>)
Unavailable
Available
Unavailable
Unavailable
DS39631A-page 44
BOR Operation
BOR disabled; must be enabled by reprogramming the configuration bits.
BOR enabled in software; operation controlled by SBOREN.
Preliminary
PIC18F2420/2520/4420/4520
4.5
4.5.3
4.5.1
4.5.4
TIME-OUT SEQUENCE
4.5.2
1.
2.
The total time-out will vary based on oscillator configuration and the status of the PWRT. Figure 4-3,
Figure 4-4, Figure 4-5, Figure 4-6 and Figure 4-7 all
depict time-out sequences on power-up, with the
Power-up Timer enabled and the device operating in
HS Oscillator mode. Figures 4-3 through 4-6 also
apply to devices operating in XT or LP modes. For
devices in RC mode and with the PWRT disabled, on
the other hand, there will be no time-out at all.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, all time-outs will expire. Bringing MCLR high will begin execution immediately
(Figure 4-5). This is useful for testing purposes or to
synchronize more than one PIC18FXXXX device
operating in parallel.
TABLE 4-2:
Oscillator
Configuration
HSPLL
PWRTEN = 1
Exit from
Power Managed Mode
PWRTEN = 0
66 ms
(1)
+ 1024 TOSC + 2
ms(2)
HS, XT, LP
1024 TOSC
1024 TOSC
EC, ECIO
66 ms(1)
RC, RCIO
66
ms(1)
66
ms(1)
INTIO1, INTIO2
Preliminary
DS39631A-page 45
PIC18F2420/2520/4420/4520
FIGURE 4-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 4-4:
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 4-5:
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
DS39631A-page 46
Preliminary
PIC18F2420/2520/4420/4520
FIGURE 4-6:
SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)
5V
VDD
0V
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 4-7:
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
TPLL
OST TIME-OUT
PLL TIME-OUT
INTERNAL RESET
Note:
Preliminary
DS39631A-page 47
PIC18F2420/2520/4420/4520
4.6
TABLE 4-3:
Condition
Program
Counter
RCON Register
SBOREN
RI
TO
PD
STKPTR Register
POR BOR STKFUL
STKUNF
Power-on Reset
0000h
RESET Instruction
0000h
u(2)
Brown-out Reset
0000h
(2)
0000h
u(2)
0000h
u(2)
0000h
u(2)
0000h
u(2)
0000h
u(2)
0000h
u(2)
0000h
u(2)
PC + 2
u(2)
PC + 2(1)
u(2)
Legend: u = unchanged
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (008h or 0018h).
2: Reset state is 1 for POR and unchanged for all other Resets when software BOR is enabled
(BOREN1:BOREN0 configuration bits = 01 and SBOREN = 1). Otherwise, the Reset state is 0.
DS39631A-page 48
Preliminary
PIC18F2420/2520/4420/4520
TABLE 4-4:
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
TOSU
2420
2520
4420
4520
---0 0000
---0 0000
---0 uuuu(3)
TOSH
2420
2520
4420
4520
0000 0000
0000 0000
uuuu uuuu(3)
TOSL
2420
2520
4420
4520
0000 0000
0000 0000
uuuu uuuu(3)
STKPTR
2420
2520
4420
4520
00-0 0000
uu-0 0000
uu-u uuuu(3)
PCLATU
2420
2520
4420
4520
---0 0000
---0 0000
---u uuuu
PCLATH
2420
2520
4420
4520
0000 0000
0000 0000
uuuu uuuu
PCL
2420
2520
4420
4520
0000 0000
0000 0000
PC + 2(2)
TBLPTRU
2420
2520
4420
4520
--00 0000
--00 0000
--uu uuuu
TBLPTRH
2420
2520
4420
4520
0000 0000
0000 0000
uuuu uuuu
TBLPTRL
2420
2520
4420
4520
0000 0000
0000 0000
uuuu uuuu
TABLAT
2420
2520
4420
4520
0000 0000
0000 0000
uuuu uuuu
PRODH
2420
2520
4420
4520
xxxx xxxx
uuuu uuuu
uuuu uuuu
PRODL
2420
2520
4420
4520
xxxx xxxx
uuuu uuuu
uuuu uuuu
INTCON
2420
2520
4420
4520
0000 000x
0000 000u
uuuu uuuu(1)
INTCON2
2420
2520
4420
4520
1111 -1-1
1111 -1-1
uuuu -u-u(1)
INTCON3
2420
2520
4420
4520
11-0 0-00
11-0 0-00
uu-u u-uu(1)
INDF0
2420
2520
4420
4520
N/A
N/A
N/A
POSTINC0
2420
2520
4420
4520
N/A
N/A
N/A
POSTDEC0
2420
2520
4420
4520
N/A
N/A
N/A
PREINC0
2420
2520
4420
4520
N/A
N/A
N/A
PLUSW0
2420
2520
4420
4520
N/A
N/A
N/A
FSR0H
2420
2520
4420
4520
---- 0000
---- 0000
---- uuuu
FSR0L
2420
2520
4420
4520
xxxx xxxx
uuuu uuuu
uuuu uuuu
WREG
2420
2520
4420
4520
xxxx xxxx
uuuu uuuu
uuuu uuuu
INDF1
2420
2520
4420
4520
N/A
N/A
N/A
POSTINC1
2420
2520
4420
4520
N/A
N/A
N/A
POSTDEC1
2420
2520
4420
4520
N/A
N/A
N/A
PREINC1
2420
2520
4420
4520
N/A
N/A
N/A
PLUSW1
2420
2520
4420
4520
N/A
N/A
N/A
Legend:
Note 1:
2:
3:
4:
5:
Preliminary
DS39631A-page 49
PIC18F2420/2520/4420/4520
TABLE 4-4:
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
FSR1H
2420
2520
4420
4520
---- 0000
---- 0000
---- uuuu
FSR1L
2420
2520
4420
4520
xxxx xxxx
uuuu uuuu
uuuu uuuu
---- uuuu
BSR
2420
2520
4420
4520
---- 0000
---- 0000
INDF2
2420
2520
4420
4520
N/A
N/A
N/A
POSTINC2
2420
2520
4420
4520
N/A
N/A
N/A
POSTDEC2
2420
2520
4420
4520
N/A
N/A
N/A
PREINC2
2420
2520
4420
4520
N/A
N/A
N/A
PLUSW2
2420
2520
4420
4520
N/A
N/A
N/A
FSR2H
2420
2520
4420
4520
---- 0000
---- 0000
---- uuuu
FSR2L
2420
2520
4420
4520
xxxx xxxx
uuuu uuuu
uuuu uuuu
STATUS
2420
2520
4420
4520
---x xxxx
---u uuuu
---u uuuu
TMR0H
2420
2520
4420
4520
0000 0000
0000 0000
uuuu uuuu
TMR0L
2420
2520
4420
4520
xxxx xxxx
uuuu uuuu
uuuu uuuu
T0CON
2420
2520
4420
4520
1111 1111
1111 1111
uuuu uuuu
OSCCON
2420
2520
4420
4520
0100 q000
0100 q000
uuuu uuqu
HLVDCON
2420
2520
4420
4520
0-00 0101
0-00 0101
u-uu uuuu
WDTCON
2420
2520
4420
4520
---- ---0
---- ---0
---- ---u
RCON(4)
2420
2520
4420
4520
0q-1 11q0
0q-q qquu
uq-u qquu
TMR1H
2420
2520
4420
4520
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR1L
2420
2520
4420
4520
xxxx xxxx
uuuu uuuu
uuuu uuuu
T1CON
2420
2520
4420
4520
0000 0000
u0uu uuuu
uuuu uuuu
TMR2
2420
2520
4420
4520
0000 0000
0000 0000
uuuu uuuu
PR2
2420
2520
4420
4520
1111 1111
1111 1111
1111 1111
T2CON
2420
2520
4420
4520
-000 0000
-000 0000
-uuu uuuu
SSPBUF
2420
2520
4420
4520
xxxx xxxx
uuuu uuuu
uuuu uuuu
SSPADD
2420
2520
4420
4520
0000 0000
0000 0000
uuuu uuuu
SSPSTAT
2420
2520
4420
4520
0000 0000
0000 0000
uuuu uuuu
SSPCON1
2420
2520
4420
4520
0000 0000
0000 0000
uuuu uuuu
SSPCON2
2420
2520
4420
4520
0000 0000
0000 0000
uuuu uuuu
Legend:
Note 1:
2:
3:
4:
5:
DS39631A-page 50
Preliminary
PIC18F2420/2520/4420/4520
TABLE 4-4:
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
ADRESH
2420
2520
4420
4520
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADRESL
2420
2520
4420
4520
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON0
2420
2520
4420
4520
--00 0000
--00 0000
--uu uuuu
ADCON1
2420
2520
4420
4520
--00 0qqq
--00 0qqq
--uu uuuu
ADCON2
2420
2520
4420
4520
0-00 0000
0-00 0000
u-uu uuuu
CCPR1H
2420
2520
4420
4520
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR1L
CCP1CON
CCPR2H
2420
2520
4420
4520
xxxx xxxx
uuuu uuuu
uuuu uuuu
2420
2520
4420
4520
0000 0000
0000 0000
uuuu uuuu
2420
2520
4420
4520
--00 0000
--00 0000
--uu uuuu
2420
2520
4420
4520
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR2L
2420
2520
4420
4520
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP2CON
2420
2520
4420
4520
--00 0000
--00 0000
--uu uuuu
BAUDCON
2420
2520
4420
4520
01-0 0-00
01-0 0-00
--uu uuuu
PWM1CON
2420
2520
4420
4520
0000 0000
0000 0000
uuuu uuuu
2420
2520
4420
4520
0000 0000
0000 0000
uuuu uuuu
2420
2520
4420
4520
0000 00--
0000 00--
uuuu uu--
CVRCON
2420
2520
4420
4520
0000 0000
0000 0000
uuuu uuuu
CMCON
2420
2520
4420
4520
0000 0111
0000 0111
uuuu uuuu
TMR3H
2420
2520
4420
4520
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR3L
2420
2520
4420
4520
xxxx xxxx
uuuu uuuu
uuuu uuuu
T3CON
2420
2520
4420
4520
0000 0000
uuuu uuuu
uuuu uuuu
SPBRGH
2420
2520
4420
4520
0000 0000
0000 0000
uuuu uuuu
ECCP1AS
SPBRG
2420
2520
4420
4520
0000 0000
0000 0000
uuuu uuuu
RCREG
2420
2520
4420
4520
0000 0000
0000 0000
uuuu uuuu
TXREG
2420
2520
4420
4520
0000 0000
0000 0000
uuuu uuuu
TXSTA
2420
2520
4420
4520
0000 0010
0000 0010
uuuu uuuu
RCSTA
2420
2520
4420
4520
0000 000x
0000 000x
uuuu uuuu
EEADR
2420
2520
4420
4520
0000 0000
0000 0000
uuuu uuuu
EEDATA
2420
2520
4420
4520
0000 0000
0000 0000
uuuu uuuu
EECON2
2420
2520
4420
4520
0000 0000
0000 0000
0000 0000
2420
2520
4420
4520
xx-0 x000
uu-0 u000
uu-0 u000
EECON1
Legend:
Note 1:
2:
3:
4:
5:
Preliminary
DS39631A-page 51
PIC18F2420/2520/4420/4520
TABLE 4-4:
Register
Power-on Reset,
Brown-out Reset
Applicable Devices
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
IPR2
2420
2520
4420
4520
11-1 1111
11-1 1111
uu-u uuuu
PIR2
2420
2520
4420
4520
00-0 0000
00-0 0000
uu-u uuuu(1)
PIE2
IPR1
PIR1
2420
2520
4420
4520
00-0 0000
00-0 0000
uu-u uuuu
2420
2520
4420
4520
1111 1111
1111 1111
uuuu uuuu
2420
2520
4420
4520
-111 1111
-111 1111
-uuu uuuu
2420
2520
4420
4520
0000 0000
0000 0000
uuuu uuuu(1)
2420
2520
4420
4520
-000 0000
-000 0000
-uuu uuuu(1)
2420
2520
4420
4520
0000 0000
0000 0000
uuuu uuuu
2420
2520
4420
4520
-000 0000
-000 0000
-uuu uuuu
OSCTUNE
2420
2520
4420
4520
00-0 0000
00-0 0000
uu-u uuuu
PIE1
TRISE
2420
2520
4420
4520
0000 -111
0000 -111
uuuu -uuu
TRISD
2420
2520
4420
4520
1111 1111
1111 1111
uuuu uuuu
TRISC
2420
2520
4420
4520
1111 1111
1111 1111
uuuu uuuu
TRISB
2420
2520
4420
4520
1111 1111
1111 1111
uuuu uuuu
TRISA(5)
2420
2520
4420
4520
1111
1111(5)
1111
1111(5)
uuuu uuuu(5)
LATE
2420
2520
4420
4520
---- -xxx
---- -uuu
---- -uuu
LATD
2420
2520
4420
4520
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATC
2420
2520
4420
4520
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATB
2420
2520
4420
4520
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATA(5)
2420
2520
4420
4520
xxxx xxxx(5)
uuuu uuuu(5)
uuuu uuuu(5)
PORTE
2420
2520
4420
4520
---- xxxx
---- uuuu
---- uuuu
PORTD
2420
2520
4420
4520
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTC
2420
2520
4420
4520
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTB
2420
2520
4420
4520
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTA(5)
2420
2520
4420
4520
xx0x 0000(5)
uu0u 0000(5)
uuuu uuuu(5)
Legend:
Note 1:
2:
3:
4:
5:
DS39631A-page 52
Preliminary
PIC18F2420/2520/4420/4520
5.0
MEMORY ORGANIZATION
5.1
FIGURE 5-1:
21
Stack Level 31
Reset Vector
0000h
0008h
0018h
On-Chip
Program Memory
On-Chip
Program Memory
3FFFh
4000h
PIC18FX4X0
7FFFh
8000h
PIC18FX5X0
Read 0
Read 0
1FFFFFh
200000h
Preliminary
DS39631A-page 53
PIC18F2420/2520/4420/4520
5.1.1
PROGRAM COUNTER
5.1.2
FIGURE 5-2:
5.1.2.1
Top-of-Stack Access
Top-of-Stack Registers
TOSU
00h
TOSH
1Ah
STKPTR<4:0>
00010
TOSL
34h
Top-of-Stack
DS39631A-page 54
Stack Pointer
001A34h
000D58h
Preliminary
00011
00010
00001
00000
PIC18F2420/2520/4420/4520
5.1.2.2
Note:
5.1.2.3
REGISTER 5-1:
The POP instruction discards the current TOS by decrementing the stack pointer. The previous value pushed
onto the stack then becomes the TOS value.
STKPTR REGISTER
R/C-0
R/C-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
STKFUL(1)
STKUNF(1)
SP4
SP3
SP2
SP1
SP0
bit 7
bit 0
bit 7
bit 6
bit 5
Unimplemented: Read as 0
bit 4-0
W = Writable bit
U = Unimplemented
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
Preliminary
DS39631A-page 55
PIC18F2420/2520/4420/4520
5.1.2.4
5.1.4
5.1.3
5.1.4.1
Computed GOTO
EXAMPLE 5-2:
EXAMPLE 5-1:
CALL SUB1, FAST
RETURN, FAST
SUB1
DS39631A-page 56
ORG
TABLE
5.1.4.2
MOVF
CALL
nn00h
ADDWF
RETLW
RETLW
RETLW
.
.
.
Preliminary
PIC18F2420/2520/4420/4520
5.2
5.2.2
5.2.1
CLOCKING SCHEME
The microcontroller clock input, whether from an internal or external source, is internally divided by four to
generate four non-overlapping quadrature clocks (Q1,
Q2, Q3 and Q4). Internally, the program counter is
incremented on every Q1; the instruction is fetched
from the program memory and latched into the instruction register during Q4. The instruction is decoded and
executed during the following Q1 through Q4. The
clocks and instruction execution flow are shown in
Figure 5-3.
FIGURE 5-3:
INSTRUCTION FLOW/PIPELINING
CLOCK/INSTRUCTION CYCLE
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Internal
Phase
Clock
Q3
Q4
PC
PC
PC + 2
PC + 4
OSC2/CLKO
(RC mode)
Execute INST (PC 2)
Fetch INST (PC)
EXAMPLE 5-3:
TCY0
TCY1
Fetch 1
Execute 1
2. MOVWF PORTB
4. BSF
1. MOVLW 55h
3. BRA
SUB_1
Fetch 2
TCY2
TCY3
TCY4
TCY5
Execute 2
Fetch 3
Execute 3
Fetch 4
Flush (NOP)
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is flushed from the pipeline while the new instruction is being fetched and then executed.
Preliminary
DS39631A-page 57
PIC18F2420/2520/4420/4520
5.2.3
INSTRUCTIONS IN PROGRAM
MEMORY
The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program
memory. The Least Significant Byte of an instruction
word is always stored in a program memory location
with an even address (LSb = 0). To maintain alignment
with instruction boundaries, the PC increments in steps
of 2 and the LSb will always read 0 (see Section 5.1.1
Program Counter).
Figure 5-4 shows an example of how instruction words
are stored in the program memory.
FIGURE 5-4:
The CALL and GOTO instructions have the absolute program memory address embedded into the instruction.
Since instructions are always stored on word boundaries, the data contained in the instruction is a word
address. The word address is written to PC<20:1>,
which accesses the desired byte address in program
memory. Instruction #2 in Figure 5-4 shows how the
instruction GOTO 0006h is encoded in the program
memory. Program branch instructions, which encode a
relative address offset, operate in the same manner. The
offset value stored in a branch instruction represents the
number of single-word instructions that the PC will be
offset by. Section 24.0 Instruction Set Summary
provides further details of the instruction set.
LSB = 0
0Fh
EFh
F0h
C1h
F4h
55h
03h
00h
23h
56h
Program Memory
Byte Locations
5.2.4
Instruction 1:
Instruction 2:
MOVLW
GOTO
055h
0006h
Instruction 3:
MOVFF
123h, 456h
TWO-WORD INSTRUCTIONS
EXAMPLE 5-4:
Word Address
000000h
000002h
000004h
000006h
000008h
00000Ah
00000Ch
00000Eh
000010h
000012h
000014h
TWO-WORD INSTRUCTIONS
CASE 1:
Object Code
0110 0110 0000
1100 0001 0010
1111 0100 0101
0010 0100 0000
0000
0011
0110
0000
Source Code
TSTFSZ
REG1
; is RAM location 0?
MOVFF
REG1, REG2 ; No, skip this word
; Execute this word as a NOP
ADDWF
REG3
; continue code
0000
0011
0110
0000
Source Code
TSTFSZ
REG1
; is RAM location 0?
MOVFF
REG1, REG2 ; Yes, execute this word
; 2nd word of instruction
ADDWF
REG3
; continue code
CASE 2:
Object Code
0110 0110 0000
1100 0001 0010
1111 0100 0101
0010 0100 0000
DS39631A-page 58
Preliminary
PIC18F2420/2520/4420/4520
5.3
Note:
5.3.1
Preliminary
DS39631A-page 59
PIC18F2420/2520/4420/4520
FIGURE 5-5:
BSR<3:0>
= 0000
00h
Access RAM
FFh
00h
GPR
Bank 0
= 0001
= 0011
= 0100
= 0101
= 0110
= 0111
= 1000
= 1001
= 1010
= 1011
= 1100
= 1101
= 1110
= 1111
DS39631A-page 60
1FFh
200h
FFh
00h
Bank 2
Bank 3
Bank 4
Bank 5
000h
07Fh
080h
0FFh
100h
GPR
Bank 1
= 0010
When a = 0:
GPR
FFh
00h
2FFh
300h
FFh
00h
3FFh
400h
FFh
00h
4FFh
500h
FFh
00h
5FFh
600h
FFh
00h
6FFh
700h
When a = 1:
The BSR specifies the Bank
used by the instruction.
Bank 6
Bank 7
Bank 8
Bank 9
7FFh
800h
FFh
00h
FFh
00h
Unused
Read 00h
9FFh
A00h
FFh
00h
AFFh
B00h
FFh
00h
BFFh
C00h
FFh
Bank 13 00h
CFFh
D00h
FFh
00h
DFFh
E00h
Bank 11
Bank 12
00h
7Fh
Access RAM High 80h
(SFRs)
FFh
8FFh
900h
FFh
00h
Bank 10
Access Bank
Bank 14
FFh
00h
Unused
FFh
SFR
Bank 15
EFFh
F00h
F7Fh
F80h
FFFh
Preliminary
PIC18F2420/2520/4420/4520
FIGURE 5-6:
BSR<3:0>
= 0000
00h
Access RAM
FFh
00h
GPR
Bank 0
= 0001
= 0011
= 0100
= 0101
= 0110
= 0111
= 1000
= 1001
= 1010
= 1011
= 1100
= 1101
= 1110
= 1111
1FFh
200h
FFh
00h
Bank 2
Bank 3
Bank 4
Bank 5
000h
07Fh
080h
0FFh
100h
GPR
Bank 1
= 0010
When a = 0:
GPR
FFh
00h
2FFh
300h
GPR
3FFh
400h
FFh
00h
When a = 1:
The BSR specifies the Bank
used by the instruction.
GPR
4FFh
500h
FFh
00h
GPR
FFh
00h
5FFh
600h
FFh
00h
6FFh
700h
Bank 6
Bank 7
Bank 8
Bank 9
Bank 10
FFh
00h
7FFh
800h
FFh
00h
8FFh
900h
FFh
00h
Unused
Read 00h
AFFh
B00h
FFh
00h
BFFh
C00h
FFh
Bank 13 00h
CFFh
D00h
FFh
00h
DFFh
E00h
Bank 12
00h
7Fh
Access RAM High 80h
(SFRs)
FFh
9FFh
A00h
FFh
00h
Bank 11
Access Bank
Bank 14
FFh
00h
Unused
FFh
SFR
Bank 15
EFFh
F00h
F7Fh
F80h
FFFh
Preliminary
DS39631A-page 61
PIC18F2420/2520/4420/4520
FIGURE 5-7:
Data Memory
BSR(1)
000h
00h
Bank 0
FFh
00h
100h
Bank 1
Bank Select(2)
From Opcode(2)
FFh
00h
200h
Bank 2
FFh
00h
300h
Bank 3
through
Bank 13
FFh
00h
E00h
Bank 14
FFh
00h
F00h
Bank 15
FFFh
Note 1:
2:
5.3.2
FFh
The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to
the registers of the Access Bank.
The MOVFF instruction embeds the entire 12-bit address in the instruction.
ACCESS BANK
DS39631A-page 62
5.3.3
Preliminary
PIC18F2420/2520/4420/4520
5.3.4
The SFRs can be classified into two sets: those associated with the core device functionality (ALU, Resets
and interrupts) and those related to the peripheral functions. The reset and interrupt registers are described in
their respective chapters, while the ALUs Status register is described later in this section. Registers related to
the operation of a peripheral feature are described in
the chapter for that peripheral.
TABLE 5-1:
Address
FFFh
Address
TOSU
FDFh
Name
INDF2
Address
(1)
FBFh
PIR1
PIE1
CCPR2H
F9Ch
(2)
FBBh
CCPR2L
F9Bh
OSCTUNE
FBAh
CCP2CON
F9Ah
(2)
F99h
(2)
FDCh
FBCh
FDDh POSTDEC2(1)
STKPTR
F9Eh
F9Dh
PREINC2(1)
FDEh POSTINC2
TOSL
FFCh
CCPR1L
CCP1CON
FBEh
TOSH
FFBh
PCLATU
FDBh
PLUSW2(1)
FFAh
PCLATH
FDAh
FSR2H
Name
IPR1
FBDh
FFEh
CCPR1H
Address
F9Fh
(1)
FFDh
Name
FF9h
PCL
FD9h
FSR2L
FB9h
(2)
FF8h
TBLPTRU
FD8h
STATUS
FB8h
BAUDCON
F98h
(2)
F97h
(2)
FF7h
TBLPTRH
FD7h
TMR0H
FB7h
PWM1CON(3)
FF6h
TBLPTRL
FD6h
TMR0L
FB6h
ECCP1AS(3)
F96h
TRISE(3)
FF5h
TABLAT
FD5h
T0CON
FB5h
CVRCON
F95h
TRISD(3)
FF4h
PRODH
FD4h
(2)
FB4h
CMCON
F94h
TRISC
FF3h
PRODL
FD3h
OSCCON
FB3h
TMR3H
F93h
TRISB
FF2h
INTCON
FD2h
HLVDCON
FB2h
TMR3L
F92h
TRISA
FF1h
INTCON2
FD1h
WDTCON
FB1h
T3CON
F91h
(2)
FF0h
INTCON3
FD0h
RCON
FB0h
SPBRGH
F90h
(2)
FEFh
INDF0(1)
FCFh
TMR1H
FAFh
SPBRG
F8Fh
(2)
FEEh POSTINC0(1)
FCEh
TMR1L
FAEh
RCREG
F8Eh
(2)
FEDh
POSTDEC0(1)
FCDh
T1CON
FADh
TXREG
F8Dh
LATE(3)
FECh
PREINC0(1)
FCCh
TMR2
FACh
TXSTA
F8Ch
LATD(3)
FEBh
(1)
FCBh
PR2
FABh
RCSTA
F8Bh
LATC
PLUSW0
FEAh
FSR0H
FCAh
T2CON
FAAh
(2)
F8Ah
LATB
FE9h
FSR0L
FC9h
SSPBUF
FA9h
EEADR
F89h
LATA
FE8h
WREG
FC8h
SSPADD
FA8h
EEDATA
F88h
(2)
FE7h
INDF1(1)
F87h
(2)
FE6h POSTINC1(1)
FC7h
SSPSTAT
FA7h
EECON2(1)
FC6h
SSPCON1
FA6h
EECON1
F86h
(2)
F85h
(2)
FE5h
POSTDEC1(1)
FC5h
SSPCON2
FA5h
(2)
FE4h
PREINC1(1)
FC4h
ADRESH
FA4h
(2)
F84h
PORTE(3)
FE3h
PLUSW1(1)
FC3h
ADRESL
FA3h
(2)
F83h
PORTD(3)
FE2h
FSR1H
FC2h
ADCON0
FA2h
IPR2
F82h
PORTC
FE1h
FSR1L
FC1h
ADCON1
FA1h
PIR2
F81h
PORTB
FE0h
BSR
FC0h
ADCON2
FA0h
PIE2
F80h
PORTA
Note 1:
2:
3:
Preliminary
DS39631A-page 63
PIC18F2420/2520/4420/4520
TABLE 5-2:
File Name
TOSU
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Details
on page:
---0 0000
49, 54
TOSH
0000 0000
49, 54
TOSL
0000 0000
49, 54
00-0 0000
49, 55
STKPTR
PCLATU
STKFUL
STKUNF
Value on
POR, BOR
SP4
SP3
SP2
SP1
SP0
---0 0000
49, 54
PCLATH
0000 0000
49, 54
PCL
0000 0000
49, 54
--00 0000
49, 76
TBLPTRU
bit 21
TBLPTRH
0000 0000
49, 76
TBLPTRL
0000 0000
49, 76
TABLAT
0000 0000
49, 76
PRODH
xxxx xxxx
49, 89
PRODL
xxxx xxxx
49, 89
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x
49, 93
INTCON2
RBPU
INTEDG0
INTEDG1
INTEDG2
TMR0IP
RBIP
1111 -1-1
49, 94
INT2IP
INT1IP
INT2IE
INT1IE
INT2IF
INT1IF
11-0 0-00
49, 95
INTCON3
INDF0
Uses contents of FSR0 to address data memory value of FSR0 not changed (not a physical register)
N/A
49, 69
POSTINC0
Uses contents of FSR0 to address data memory value of FSR0 post-incremented (not a physical register)
N/A
49, 69
POSTDEC0
Uses contents of FSR0 to address data memory value of FSR0 post-decremented (not a physical register)
N/A
49, 69
PREINC0
Uses contents of FSR0 to address data memory value of FSR0 pre-incremented (not a physical register)
N/A
49, 69
PLUSW0
Uses contents of FSR0 to address data memory value of FSR0 pre-incremented (not a physical register)
value of FSR0 offset by W
N/A
49, 69
FSR0H
---- 0000
49, 69
FSR0L
xxxx xxxx
49, 69
WREG
Working Register
xxxx xxxx
49
INDF1
Uses contents of FSR1 to address data memory value of FSR1 not changed (not a physical register)
N/A
49, 69
POSTINC1
Uses contents of FSR1 to address data memory value of FSR1 post-incremented (not a physical register)
N/A
49, 69
POSTDEC1
Uses contents of FSR1 to address data memory value of FSR1 post-decremented (not a physical register)
N/A
49, 69
PREINC1
Uses contents of FSR1 to address data memory value of FSR1 pre-incremented (not a physical register)
N/A
49, 69
PLUSW1
Uses contents of FSR1 to address data memory value of FSR1 pre-incremented (not a physical register)
value of FSR1 offset by W
N/A
49, 69
---- 0000
50, 69
FSR1H
FSR1L
BSR
xxxx xxxx
50, 69
---- 0000
50, 59
INDF2
Uses contents of FSR2 to address data memory value of FSR2 not changed (not a physical register)
N/A
50, 69
POSTINC2
Uses contents of FSR2 to address data memory value of FSR2 post-incremented (not a physical register)
N/A
50, 69
POSTDEC2
Uses contents of FSR2 to address data memory value of FSR2 post-decremented (not a physical register)
N/A
50, 69
PREINC2
Uses contents of FSR2 to address data memory value of FSR2 pre-incremented (not a physical register)
N/A
50, 69
PLUSW2
Uses contents of FSR2 to address data memory value of FSR2 pre-incremented (not a physical register)
value of FSR2 offset by W
N/A
50, 69
---- 0000
50, 69
FSR2H
FSR2L
STATUS
Legend:
Note 1:
2:
3:
4:
5:
OV
DC
xxxx xxxx
50, 69
---x xxxx
50, 67
DS39631A-page 64
Preliminary
PIC18F2420/2520/4420/4520
TABLE 5-2:
File Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details
on page:
TMR0H
0000 0000
50, 125
TMR0L
xxxx xxxx
50, 125
50, 123
T0CON
TMR0ON
T08BIT
T0CS
T0SE
PSA
T0PS2
T0PS1
T0PS0
1111 1111
OSCCON
IDLEN
IRCF2
IRCF1
IRCF0
OSTS
IOFS
SCS1
SCS0
0100 q000
30, 50
HLVDCON
VDIRMAG
IRVST
HLVDEN
HLVDL3
HLVDL2
HLVDL1
HLVDL0
0-00 0101
50, 245
SWDTEN
--- ---0
50, 259
IPEN
SBOREN(1)
RI
TO
PD
POR
BOR
0q-1 11q0
42, 48,
102
WDTCON
RCON
TMR1H
xxxx xxxx
50, 131
TMR1L
xxxx xxxx
50, 131
T1CON
RD16
T1RUN
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
0000 0000
50, 127
TMR2
Timer2 Register
0000 0000
50, 134
PR2
1111 1111
50, 134
-000 0000
50, 133
xxxx xxxx
50, 169,
170
T2CON
T2OUTPS3
T2OUTPS2
T2OUTPS1
T2OUTPS0
TMR2ON
TMR1CS
T2CKPS1
SSPBUF
SSPADD
SSP Address Register in I2C Slave Mode. SSP Baud Rate Reload Register in I2C Master Mode.
TMR1ON
T2CKPS0
0000 0000
50, 170
SSPSTAT
SMP
CKE
D/A
R/W
UA
BF
0000 0000
50, 162,
171
SSPCON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000
50, 163,
172
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
SSPCON2
0000 0000
50, 173
ADRESH
xxxx xxxx
51, 232
ADRESL
xxxx xxxx
51, 232
ADON
--00 0000
51, 223
ADCON0
ADCON1
ADCON2
ADFM
CHS3
CHS2
CHS1
CHS0
GO/DONE
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
--00 0qqq
51, 224
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
0-00 0000
51, 225
51, 140
CCPR1H
xxxx xxxx
CCPR1L
xxxx xxxx
51, 140
0000 0000
51, 139,
147
51, 140
CCP1CON
P1M1(2)
P1M0(2)
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
CCPR2H
xxxx xxxx
CCPR2L
xxxx xxxx
51, 140
--00 0000
51, 139
CCP2CON
BAUDCON
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
01-0 0-00
51, 204
PWM1CON
PRSEN
PDC6(2)
PDC5(2)
PDC4(2)
PDC3(2)
PDC2(2)
PDC1(2)
PDC0(2)
0000 0000
51, 156
ECCP1AS
ECCPASE
ECCPAS2
ECCPAS1
ECCPAS0
PSSAC1
PSSAC0
PSSBD1(2)
51, 157
CVRCON
CVREN
CVROE
CVRR
CVRSS
CVR3
CVR2
CVR1
CVR0
0000 0000
51, 239
CMCON
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
0000 0111
51, 233
DC2B1
DC2B0
CCP2M3
CCP2M2
CCP2M1
CCP2M0
TMR3H
xxxx xxxx
51, 137
TMR3L
xxxx xxxx
51, 137
0000 0000
51, 135
T3CON
RD16
Legend:
Note 1:
2:
3:
4:
5:
T3CCP2
T3CKPS1
T3CKPS0
T3CCP1
T3SYNC
TMR3CS
TMR3ON
Preliminary
DS39631A-page 65
PIC18F2420/2520/4420/4520
TABLE 5-2:
File Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details
on page:
SPBRGH
0000 0000
51, 206
SPBRG
0000 0000
51, 206
RCREG
0000 0000
51, 213
TXREG
0000 0000
51, 211
TXSTA
RCSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
0000 0010
51, 202
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
51, 203
EEADR
EEDATA
EECON2
EECON1
EEPGD
CFGS
FREE
WRERR
WREN
WR
RD
IPR2
OSCFIP
CMIP
EEIP
BCLIP
HLVDIP
TMR3IP
CCP2IP
11-1 1111
52, 101
PIR2
OSCFIF
CMIF
EEIF
BCLIF
HLVDIF
TMR3IF
CCP2IF
00-0 0000
52, 97
PIE2
OSCFIE
CMIE
EEIE
BCLIE
HLVDIE
TMR3IE
CCP2IE
00-0 0000
52, 99
IPR1
PSPIP(2)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
1111 1111
52, 100
PIR1
PSPIF(2)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
52, 96
PIE1
PSPIE(2)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
52, 98
OSCTUNE
INTSRC
PLLEN(3)
TUN4
TUN3
TUN2
TUN1
TUN0
0q-0 0000
27, 52
IBF
OBF
IBOV
PSPMODE
TRISE2
TRISE1
TRISE0
TRISE(2)
0000 -111
52, 118
1111 1111
52, 114
TRISC
1111 1111
52, 111
TRISB
1111 1111
52, 108
1111 1111
52, 105
---- -xxx
52, 117
52, 114
TRISD(2)
TRISA
(2)
LATE
TRISA7(5)
TRISA6(5)
LATD(2)
xxxx xxxx
LATC
xxxx xxxx
52, 111
LATB
xxxx xxxx
52, 108
xxxx xxxx
52, 105
LATA7(5)
LATA6(5)
RE3(4)
RE2(2)
RE1(2)
RE0(2)
---- xxxx
52, 117
PORTD(2)
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx xxxx
52, 114
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx
52, 111
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
52, 108
PORTA
RA7(5)
RA6(5)
RA5
RA4
RA3
RA2
RA1
RA0
xx0x 0000
52, 105
LATA
PORTE
Legend:
Note 1:
2:
3:
4:
5:
DS39631A-page 66
Preliminary
PIC18F2420/2520/4420/4520
5.3.5
STATUS REGISTER
REGISTER 5-2:
STATUS REGISTER
U-0
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
OV
DC
bit 7
bit 0
bit 7-5
Unimplemented: Read as 0
bit 4
N: Negative bit
This bit is used for signed arithmetic (2s complement). It indicates whether the result was
negative (ALU MSB = 1).
1 = Result was negative
0 = Result was positive
bit 3
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
bit 0
C: Carry/borrow bit
For ADDWF, ADDLW, SUBLW and SUBWF instructions:
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note:
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
Preliminary
x = Bit is unknown
DS39631A-page 67
PIC18F2420/2520/4420/4520
5.4
Note:
Inherent
Literal
Direct
Indirect
5.4.3
5.4.1
Many PIC18 control instructions do not need any argument at all; they either perform an operation that globally affects the device or they operate implicitly on one
register. This addressing mode is known as Inherent
Addressing. Examples include SLEEP, RESET and DAW.
Other instructions work in a similar way but require an
additional explicit argument in the opcode. This is
known as Literal Addressing mode because they
require some literal value as an argument. Examples
include ADDLW and MOVLW, which respectively, add or
move a literal value to the W register. Other examples
include CALL and GOTO, which include a 20-bit
program memory address.
EXAMPLE 5-5:
NEXT
5.4.2
INDIRECT ADDRESSING
LFSR
CLRF
DIRECT ADDRESSING
BTFSS
BRA
CONTINUE
In the core PIC18 instruction set, bit-oriented and byteoriented instructions use some version of direct
addressing by default. All of these instructions include
some 8-bit literal address as their Least Significant
Byte. This address specifies either a register address in
one of the banks of data RAM (Section 5.3.3 General
Purpose Register File) or a location in the Access
Bank (Section 5.3.2 Access Bank) as the data
source for the instruction.
DS39631A-page 68
Preliminary
PIC18F2420/2520/4420/4520
5.4.3.1
5.4.3.2
At the core of indirect addressing are three sets of registers: FSR0, FSR1 and FSR2. Each represents a pair
of 8-bit registers, FSRnH and FSRnL. The four upper
bits of the FSRnH register are not used so each FSR
pair holds a 12-bit value. This represents a value that
can address the entire range of the data memory in a
linear fashion. The FSR register pairs, then, serve as
pointers to data memory locations.
FIGURE 5-8:
INDIRECT ADDRESSING
000h
Bank 0
ADDWF, INDF1, 1
100h
Bank 1
200h
Bank 2
300h
FSR1H:FSR1L
7
x x x x 1 1 1 0
Bank 3
through
Bank 13
1 1 0 0 1 1 0 0
Bank 14
F00h
Bank 15
FFFh
Data Memory
Preliminary
DS39631A-page 69
PIC18F2420/2520/4420/4520
The PLUSW register can be used to implement a form
of indexed addressing in the data memory space. By
manipulating the value in the W register, users can
reach addresses that are fixed offsets from pointer
addresses. In some applications, this can be used to
implement some powerful program control structure,
such as software stacks, inside of data memory.
5.4.3.3
5.5
DS39631A-page 70
5.5.1
5.5.2
INSTRUCTIONS AFFECTED BY
INDEXED LITERAL OFFSET MODE
Preliminary
PIC18F2420/2520/4420/4520
FIGURE 5-9:
000h
F00h
060h
080h
Bank 0
100h
00h
Bank 1
through
Bank 14
60h
80h
Access RAM
Valid range
for f
FFh
Bank 15
F80h
SFRs
FFFh
Data Memory
000h
Bank 0
080h
100h
001001da ffffffff
Bank 1
through
Bank 14
FSR2H
FSR2L
F00h
Bank 15
F80h
SFRs
FFFh
Data Memory
BSR
00000000
000h
Bank 0
080h
100h
Bank 1
through
Bank 14
001001da ffffffff
F00h
Bank 15
F80h
SFRs
FFFh
Data Memory
Preliminary
DS39631A-page 71
PIC18F2420/2520/4420/4520
5.5.3
FIGURE 5-10:
Remapping of the Access Bank applies only to operations using the Indexed Literal Offset mode. Operations
that use the BSR (Access RAM bit is 1) will continue
to use direct addressing as before.
5.6
Example Situation:
ADDWF f, d, a
FSR2H:FSR2L = 120h
Locations in the region
from the FSR2 pointer
(120h) to the pointer plus
05Fh (17Fh) are mapped
to the bottom of the
Access RAM (000h-05Fh).
000h
05Fh
07Fh
Bank 0
100h
120h
17Fh
200h
Bank 1
Window
00h
Bank 1
Bank 1 Window
5Fh
Bank 0
Bank 0
Bank 2
through
Bank 14
7Fh
80h
SFRs
FFh
Access Bank
F00h
Bank 15
F80h
SFRs
FFFh
Data Memory
DS39631A-page 72
Preliminary
PIC18F2420/2520/4420/4520
6.0
6.1
FIGURE 6-1:
Program Memory
Table Pointer(1)
TBLPTRU
TBLPTRH
Program Memory
(TBLPTR)
Preliminary
DS39631A-page 73
PIC18F2420/2520/4420/4520
FIGURE 6-2:
Program Memory
Holding Registers
Table Pointer(1)
TBLPTRU
TBLPTRH
TABLAT
Program Memory
(TBLPTR)
Note 1: Table Pointer actually points to one of 64 holding registers, the address of which is determined by
TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in
Section 6.5 Writing to Flash Program Memory.
6.2
Control Registers
EECON1 register
EECON2 register
TABLAT register
TBLPTR registers
6.2.1
Note:
DS39631A-page 74
Preliminary
PIC18F2420/2520/4420/4520
REGISTER 6-1:
EECON1 REGISTER
R/W-x
R/W-x
U-0
R/W-0
R/W-x
R/W-0
R/S-0
R/S-0
EEPGD
CFGS
FREE
WRERR
WREN
WR
RD
bit 7
bit 0
bit 7
bit 6
bit 5
Unimplemented: Read as 0
bit 4
bit 3
When a WRERR occurs, the EEPGD and CFGS bits are not cleared.
This allows tracing of the error condition.
bit 2
bit 1
bit 0
W = Writable bit
-n = Value at POR
0 = Bit is cleared
1 = Bit is set
Preliminary
x = Bit is unknown
DS39631A-page 75
PIC18F2420/2520/4420/4520
6.2.2
6.2.4
6.2.3
TABLE 6-1:
Example
TBLRD*
TBLWT*
TBLRD*+
TBLWT*+
TBLRD*TBLWT*-
TBLRD+*
TBLWT+*
FIGURE 6-3:
21
16
15
TBLPTRH
TABLE ERASE/WRITE
TBLPTR<21:6>
TBLPTRL
TABLE WRITE
TBLPTR<5:0>
DS39631A-page 76
Preliminary
PIC18F2420/2520/4420/4520
6.3
FIGURE 6-4:
Program Memory
TBLPTR = xxxxx1
Instruction Register
(IR)
EXAMPLE 6-1:
FETCH
TBLRD
TBLPTR = xxxxx0
TABLAT
Read Register
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
READ_WORD
TBLRD*+
MOVF
MOVWF
TBLRD*+
MOVFW
MOVF
TABLAT, W
WORD_EVEN
TABLAT, W
WORD_ODD
Preliminary
DS39631A-page 77
PIC18F2420/2520/4420/4520
6.4
6.4.1
3.
4.
5.
6.
7.
EXAMPLE 6-2:
2.
8.
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
BSF
BCF
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
EECON1,
EECON1,
EECON1,
EECON1,
INTCON,
55h
EECON2
0AAh
EECON2
EECON1,
INTCON,
;
;
;
;
;
ERASE_ROW
Required
Sequence
DS39631A-page 78
EEPGD
CFGS
WREN
FREE
GIE
; write 55h
WR
GIE
; write 0AAh
; start erase (CPU stall)
; re-enable interrupts
Preliminary
PIC18F2420/2520/4420/4520
6.5
The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long
write cycle. The long write will be terminated by the
internal programming timer.
FIGURE 6-5:
Note:
8
TBLPTR = xxxxx0
TBLPTR = xxxxx1
Holding Register
8
TBLPTR = xxxx3F
TBLPTR = xxxxx2
Holding Register
Holding Register
Holding Register
Program Memory
6.5.1
8.
9.
10.
11.
12.
Disable interrupts.
Write 55h to EECON2.
Write 0AAh to EECON2.
Set the WR bit. This will begin the write cycle.
The CPU will stall for duration of the write (about
2 ms using internal timer).
13. Re-enable interrupts.
14. Verify the memory (table read).
This procedure will require about 6 ms to update one
row of 64 bytes of memory. An example of the required
code is given in Example 6-3.
Note:
Preliminary
DS39631A-page 79
PIC18F2420/2520/4420/4520
EXAMPLE 6-3:
D'64
COUNTER
BUFFER_ADDR_HIGH
FSR0H
BUFFER_ADDR_LOW
FSR0L
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
TBLRD*+
MOVF
MOVWF
DECFSZ
BRA
TABLAT, W
POSTINC0
COUNTER
READ_BLOCK
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
DATA_ADDR_HIGH
FSR0H
DATA_ADDR_LOW
FSR0L
NEW_DATA_LOW
POSTINC0
NEW_DATA_HIGH
INDF0
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BCF
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
TBLRD*MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
EECON1, FREE
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
INTCON, GIE
MOVLW
MOVWF
D64
COUNTER
MOVFF
MOVWF
TBLWT+*
POSTINC0, WREG
TABLAT
DECFSZ
BRA
COUNTER
WRITE_WORD_TO_HREGS
;
;
;
;
;
; point to buffer
READ_BLOCK
;
;
;
;
;
MODIFY_WORD
; point to buffer
ERASE_BLOCK
Required
Sequence
BUFFER_ADDR_HIGH
FSR0H
BUFFER_ADDR_LOW
FSR0L
;
;
;
;
;
; write 55h
;
;
;
;
;
write 0AAh
start erase (CPU stall)
re-enable interrupts
dummy read decrement
point to buffer
WRITE_BUFFER_BACK
WRITE_BYTE_TO_HREGS
DS39631A-page 80
Preliminary
PIC18F2420/2520/4420/4520
EXAMPLE 6-3:
PROGRAM_MEMORY
BSF
BCF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
BCF
Required
Sequence
6.5.2
EECON1,
EECON1,
EECON1,
INTCON,
55h
EECON2
0AAh
EECON2
EECON1,
INTCON,
EECON1,
EEPGD
CFGS
WREN
GIE
;
;
;
;
; write 55h
;
;
;
;
WR
GIE
WREN
UNEXPECTED TERMINATION OF
WRITE OPERATION
TABLE 6-2:
write 0AAh
start program (CPU stall)
re-enable interrupts
disable write to memory
6.5.4
WRITE VERIFY
6.5.3
PROTECTION AGAINST
SPURIOUS WRITES
6.6
Name
Bit 7
Bit 6
Bit 5
TBLPTRU
bit 21
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values on
page
49
49
49
TABLAT
49
INTCON
EECON2
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
49
51
EECON1
EEPGD
CFGS
FREE
WRERR
WREN
WR
RD
51
IPR2
OSCFIP
CMIP
EEIP
BCLIP
HLVDIP
TMR3IP
CCP2IP
52
PIR2
OSCFIF
CMIF
EEIF
BCLIF
HLVDIF
TMR3IF
CCP2IF
52
PIE2
OSCFIE
CMIE
EEIE
BCLIE
HLVDIE
TMR3IE
CCP2IE
52
Legend: = unimplemented, read as 0. Shaded cells are not used during Flash/EEPROM access.
Preliminary
DS39631A-page 81
PIC18F2420/2520/4420/4520
NOTES:
DS39631A-page 82
Preliminary
PIC18F2420/2520/4420/4520
7.0
The data EEPROM is a nonvolatile memory array, separate from the data RAM and program memory, that is
used for long-term storage of program data. It is not
directly mapped in either the register file or program
memory space but is indirectly addressed through the
Special Function Registers (SFRs). The EEPROM is
readable and writable during normal operation over the
entire VDD range.
Five SFRs are used to read and write to the data
EEPROM as well as the program memory. They are:
EECON1
EECON2
EEDATA
EEADR
7.1
EEADR Register
7.2
The EECON1 register (Register 7-1) is the control register for data and program memory access. Control bit
EEPGD determines if the access will be to program or
data EEPROM memory. When clear, operations will
access the data EEPROM memory. When set, program
memory is accessed.
Control bit, CFGS, determines if the access will be to
the configuration registers or to program memory/data
EEPROM memory. When set, subsequent operations
access configuration registers. When CFGS is clear,
the EEPGD bit selects either program Flash or data
EEPROM memory.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set in hardware when the WR bit is set and cleared
when the internal programming timer expires and the
write operation is complete.
Note:
Preliminary
DS39631A-page 83
PIC18F2420/2520/4420/4520
REGISTER 7-1:
EECON1 REGISTER
R/W-x
R/W-x
U-0
R/W-0
R/W-x
R/W-0
R/S-0
R/S-0
EEPGD
CFGS
FREE
WRERR
WREN
WR
RD
bit 7
bit 0
bit 7
bit 6
bit 5
Unimplemented: Read as 0
bit 4
bit 3
When a WRERR occurs, the EEPGD and CFGS bits are not cleared.
This allows tracing of the error condition.
bit 2
bit 1
bit 0
DS39631A-page 84
W = Writable bit
-n = Value at POR
0 = Bit is cleared
1 = Bit is set
Preliminary
x = Bit is unknown
PIC18F2420/2520/4420/4520
7.3
7.4
EXAMPLE 7-1:
MOVLW
MOVWF
BCF
BCF
BSF
MOVF
7.5
Write Verify
EXAMPLE 7-2:
Required
Sequence
;
;
;
;
;
;
DATA_EE_ADDR
EEADR
DATA_EE_DATA
EEDATA
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
;
;
;
;
;
;
;
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
INTCON, GIE
;
;
;
;
;
;
;
BCF
EECON1, WREN
Preliminary
DS39631A-page 85
PIC18F2420/2520/4420/4520
7.6
7.8
7.7
EXAMPLE 7-3:
CLRF
BCF
BCF
BCF
BSF
EEADR
EECON1,
EECON1,
INTCON,
EECON1,
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BTFSC
BRA
INCFSZ
BRA
EECON1, RD
55h
EECON2
0AAh
EECON2
EECON1, WR
EECON1, WR
$-2
EEADR, F
LOOP
BCF
BSF
EECON1, WREN
INTCON, GIE
CFGS
EEPGD
GIE
WREN
Loop
DS39631A-page 86
;
;
;
;
;
;
;
;
;
;
;
;
;
Start at address 0
Set for memory
Set for Data EEPROM
Disable interrupts
Enable writes
Loop to refresh array
Read current address
Write 55h
Write 0AAh
Set WR bit to begin write
Wait for write to complete
; Increment address
; Not zero, do it again
; Disable writes
; Enable interrupts
Preliminary
PIC18F2420/2520/4420/4520
TABLE 7-1:
Name
INTCON
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
49
EEADR
51
EEDATA
51
EECON2
51
EECON1
EEPGD
CFGS
FREE
WRERR
WREN
WR
RD
51
IPR2
OSCFIP
CMIP
EEIP
BCLIP
HLVDIP
TMR3IP
CCP2IP
52
PIR2
OSCFIF
CMIF
EEIF
BCLIF
HLVDIF
TMR3IF
CCP2IF
52
PIE2
OSCFIE
CMIE
EEIE
BCLIE
HLVDIE
TMR3IE
CCP2IE
52
Legend: = unimplemented, read as 0. Shaded cells are not used during Flash/EEPROM access.
Preliminary
DS39631A-page 87
PIC18F2420/2520/4420/4520
NOTES:
DS39631A-page 88
Preliminary
PIC18F2420/2520/4420/4520
8.0
8 x 8 HARDWARE MULTIPLIER
8.1
Introduction
EXAMPLE 8-1:
MOVF
MULWF
ARG1, W
ARG2
;
; ARG1 * ARG2 ->
; PRODH:PRODL
EXAMPLE 8-2:
8.2
8 x 8 UNSIGNED
MULTIPLY ROUTINE
8 x 8 SIGNED MULTIPLY
ROUTINE
MOVF
MULWF
ARG1, W
ARG2
BTFSC
SUBWF
ARG2, SB
PRODH, F
MOVF
BTFSC
SUBWF
ARG2, W
ARG1, SB
PRODH, F
;
;
;
;
;
Operation
TABLE 8-1:
Routine
8 x 8 unsigned
8 x 8 signed
16 x 16 unsigned
16 x 16 signed
Program
Memory
(Words)
Cycles
(Max)
13
Hardware multiply
33
Hardware multiply
Multiply Method
Time
@ 40 MHz
@ 10 MHz
@ 4 MHz
69
6.9 s
27.6 s
69 s
100 ns
400 ns
1 s
91
9.1 s
36.4 s
91 s
600 ns
2.4 s
6 s
21
242
24.2 s
96.8 s
242 s
28
28
2.8 s
11.2 s
28 s
52
254
25.4 s
102.6 s
254 s
Hardware multiply
35
40
4.0 s
16.0 s
40 s
Preliminary
DS39631A-page 89
PIC18F2420/2520/4420/4520
Example 8-3 shows the sequence to do a 16 x 16
unsigned multiplication. Equation 8-1 shows the
algorithm that is used. The 32-bit result is stored in four
registers (RES3:RES0).
EQUATION 8-1:
RES3:RES0
=
=
EXAMPLE 8-3:
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
ARG1H:ARG1L ARG2H:ARG2L
(ARG1H ARG2H 216) +
(ARG1H ARG2L 28) +
(ARG1L ARG2H 28) +
(ARG1L ARG2L)
EQUATION 8-2:
EXAMPLE 8-4:
16 x 16 UNSIGNED
MULTIPLY ROUTINE
MOVF
MULWF
ARG1L, W
ARG2L
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
MOVF
MULWF
ARG1H, W
ARG2H
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
MOVF
MULWF
ARG1L, W
ARG2H
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
MOVF
MULWF
ARG1H, W
ARG2L
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
; ARG1L * ARG2L->
; PRODH:PRODL
;
;
ARG1L * ARG2H->
PRODH:PRODL
Add cross
products
ARG1H * ARG2L->
PRODH:PRODL
Add cross
products
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
MOVF
MULWF
ARG1H, W
ARG2H
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
MOVF
MULWF
ARG1L, W
ARG2H
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
MOVF
MULWF
ARG1H, W
ARG2L
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
BTFSS
BRA
MOVF
SUBWF
MOVF
SUBWFB
ARG2H, 7
SIGN_ARG1
ARG1L, W
RES2
ARG1H, W
RES3
; ARG2H:ARG2L neg?
; no, check ARG1
;
;
;
ARG1H, 7
CONT_CODE
ARG2L, W
RES2
ARG2H, W
RES3
; ARG1H:ARG1L neg?
; no, done
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
DS39631A-page 90
ARG1L, W
ARG2L
;
;
;
;
;
;
;
;
;
;
MOVF
MULWF
;
;
;
;
;
;
;
;
;
16 x 16 SIGNED
MULTIPLY ROUTINE
;
; ARG1H * ARG2H->
; PRODH:PRODL
;
;
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
;
SIGN_ARG1
BTFSS
BRA
MOVF
SUBWF
MOVF
SUBWFB
;
CONT_CODE
:
Preliminary
PIC18F2420/2520/4420/4520
9.0
INTERRUPTS
The PIC18F2420/2520/4420/4520 devices have multiple interrupt sources and an interrupt priority feature
that allows most interrupt sources to be assigned a
high priority level or a low priority level. The high priority
interrupt vector is at 0008h and the low priority interrupt
vector is at 0018h. High priority interrupt events will
interrupt any low priority interrupts that may be in
progress.
There are ten registers which are used to control
interrupt operation. These registers are:
RCON
INTCON
INTCON2
INTCON3
PIR1, PIR2
PIE1, PIE2
IPR1, IPR2
It is recommended that the Microchip header files supplied with MPLAB IDE be used for the symbolic bit
names in these registers. This allows the assembler/
compiler to automatically take care of the placement of
these bits within the specified register.
In general, interrupt sources have three bits to control
their operation. They are:
Flag bit to indicate that an interrupt event
occurred
Enable bit that allows program execution to
branch to the interrupt vector address when the
flag bit is set
Priority bit to select high priority or low priority
Preliminary
DS39631A-page 91
PIC18F2420/2520/4420/4520
FIGURE 9-1:
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
SSPIF
SSPIE
SSPIP
GIEH/GIE
ADIF
ADIE
ADIP
IPEN
IPEN
RCIF
RCIE
RCIP
GIEL/PEIE
IPEN
Additional Peripheral Interrupts
SSPIF
SSPIE
SSPIP
Interrupt to CPU
Vector to Location
0018h
TMR0IF
TMR0IE
TMR0IP
ADIF
ADIE
ADIP
RBIF
RBIE
RBIP
RCIF
RCIE
RCIP
GIEH/GIE
GIEL/PEIE
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
DS39631A-page 92
Preliminary
PIC18F2420/2520/4420/4520
9.1
INTCON Registers
Note:
REGISTER 9-1:
INTCON REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-x
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
A mismatch condition will continue to set this bit. Reading PORTB will end the
mismatch condition and allow the bit to be cleared.
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
Preliminary
x = Bit is unknown
DS39631A-page 93
PIC18F2420/2520/4420/4520
REGISTER 9-2:
INTCON2 REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
U-0
R/W-1
U-0
R/W-1
RBPU
INTEDG0
INTEDG1
INTEDG2
TMR0IP
RBIP
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
Unimplemented: Read as 0
bit 2
bit 1
Unimplemented: Read as 0
bit 0
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
Note:
DS39631A-page 94
x = Bit is unknown
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows for software polling.
Preliminary
PIC18F2420/2520/4420/4520
REGISTER 9-3:
INTCON3 REGISTER
R/W-1
R/W-1
U-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
INT2IP
INT1IP
INT2IE
INT1IE
INT2IF
INT1IF
bit 7
bit 0
bit 7
bit 6
bit 5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
Unimplemented: Read as 0
bit 1
bit 0
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
Note:
x = Bit is unknown
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows for software polling.
Preliminary
DS39631A-page 95
PIC18F2420/2520/4420/4520
9.2
PIR Registers
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are two Peripheral Interrupt
Request Flag registers (PIR1 and PIR2).
REGISTER 9-4:
2: User software should ensure the appropriate interrupt flag bits are cleared prior to
enabling an interrupt and after servicing
that interrupt.
R/W-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
bit 7
bit 7
bit 0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS39631A-page 96
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
Preliminary
x = Bit is unknown
PIC18F2420/2520/4420/4520
REGISTER 9-5:
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
OSCFIF
CMIF
EEIF
BCLIF
HLVDIF
TMR3IF
CCP2IF
bit 7
bit 0
bit 7
bit 6
bit 5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
bit 1
bit 0
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
Preliminary
x = Bit is unknown
DS39631A-page 97
PIC18F2420/2520/4420/4520
9.3
PIE Registers
REGISTER 9-6:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
bit 7
bit 7
bit 0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS39631A-page 98
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
Preliminary
x = Bit is unknown
PIC18F2420/2520/4420/4520
REGISTER 9-7:
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
OSCFIE
CMIE
EEIE
BCLIE
HLVDIE
TMR3IE
CCP2IE
bit 7
bit 0
bit 7
bit 6
bit 5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
bit 1
bit 0
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
Preliminary
x = Bit is unknown
DS39631A-page 99
PIC18F2420/2520/4420/4520
9.4
IPR Registers
REGISTER 9-8:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
bit 7
bit 7
bit 0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS39631A-page 100
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
Preliminary
x = Bit is unknown
PIC18F2420/2520/4420/4520
REGISTER 9-9:
R/W-1
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
OSCFIP
CMIP
EEIP
BCLIP
HLVDIP
TMR3IP
CCP2IP
bit 7
bit 0
bit 7
bit 6
bit 5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
bit 1
bit 0
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
Preliminary
x = Bit is unknown
DS39631A-page 101
PIC18F2420/2520/4420/4520
9.5
RCON Register
REGISTER 9-10:
RCON REGISTER
R/W-0
R/W-1(1)
U-0
R/W-1
R-1
R-1
R/W-0(1)
R/W-0
IPEN
SBOREN
RI
TO
PD
POR
BOR
bit 7
bit 0
bit 7
bit 6
bit 5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
bit 1
bit 0
DS39631A-page 102
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
Preliminary
x = Bit is unknown
PIC18F2420/2520/4420/4520
9.6
9.7
TMR0 Interrupt
9.8
PORTB Interrupt-on-Change
9.9
EXAMPLE 9-1:
MOVWF
W_TEMP
MOVFF
STATUS, STATUS_TEMP
MOVFF
BSR, BSR_TEMP
;
; USER ISR CODE
;
MOVFF
BSR_TEMP, BSR
MOVF
W_TEMP, W
MOVFF
STATUS_TEMP, STATUS
; Restore BSR
; Restore WREG
; Restore STATUS
Preliminary
DS39631A-page 103
PIC18F2420/2520/4420/4520
NOTES:
DS39631A-page 104
Preliminary
PIC18F2420/2520/4420/4520
10.0
I/O PORTS
FIGURE 10-1:
RD LAT
Note:
Data
Bus
WR LAT
or Port
Q
I/O pin(1)
CK
Data Latch
D
WR TRIS
CK
TRIS Latch
Input
Buffer
EXAMPLE 10-1:
RD TRIS
CLRF
Q
CLRF
ENEN
RD Port
Note 1:
10.1
MOVLW
MOVWF
MOVWF
MOVWF
MOVLW
PORTA is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
high-impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
MOVWF
Preliminary
PORTA
;
;
;
LATA
;
;
;
07h
;
ADCON1 ;
07h
;
CMCON
;
0CFh
;
;
;
TRISA
;
;
INITIALIZING PORTA
Initialize PORTA by
clearing output
data latches
Alternate method
to clear output
data latches
Configure A/D
for digital inputs
Configure comparators
for digital input
Value used to
initialize data
direction
Set RA<3:0> as inputs
RA<5:4> as outputs
DS39631A-page 105
PIC18F2420/2520/4420/4520
TABLE 10-1:
Pin
RA0/AN0
RA1/AN1
RA2/AN2/
VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS/
HLVDIN/C2OUT
OSC2/CLKO/RA6
OSC1/CLKI/RA7
Legend:
Function
TRIS
Setting
I/O
I/O
Type
RA0
DIG
Description
LATA<0> data output; not affected by analog input.
TTL
AN0
ANA
RA1
DIG
TTL
AN1
ANA
RA2
DIG
TTL
AN2
ANA
VREF-
ANA
CVREF
ANA
RA3
DIG
TTL
AN3
ANA
VREF+
ANA
RA4
DIG
ST
T0CKI
ST
C1OUT
DIG
RA5
DIG
TTL
AN4
ANA
SS
TTL
HLVDIN
ANA
C2OUT
DIG
RA6
DIG
LATA<6> data output. Enabled in RCIO, INTIO2 and ECIO modes only.
TTL
OSC2
ANA
CLKO
DIG
RA7
DIG
TTL
OSC1
ANA
CLKI
ANA
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x = Dont care (TRIS bit does not affect port direction or is overridden for this option).
DS39631A-page 106
Preliminary
PIC18F2420/2520/4420/4520
TABLE 10-2:
Name
PORTA
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RA7(1)
RA6(1)
RA5
RA4
RA3
RA2
RA1
RA0
(1)
LATA6(1) PORTA Data Latch Register (Read and Write to Data Latch)
LATA
LATA7
TRISA
Reset
Values
on page
52
52
52
ADCON1
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
51
CMCON
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
51
CVRCON
CVREN
CVROE
CVRR
CVRSS
CVR3
CVR2
CVR1
CVR0
51
Preliminary
DS39631A-page 107
PIC18F2420/2520/4420/4520
10.2
PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISB bit (= 0)
will make the corresponding PORTB pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATB) is also memory
mapped. Read-modify-write operations on the LATB
register read and write the latched output value for
PORTB.
EXAMPLE 10-2:
CLRF
CLRF
MOVLW
MOVWF
MOVLW
MOVWF
PORTB
;
;
;
LATB
;
;
;
0Fh
;
ADCON1 ;
;
;
0CFh
;
;
;
TRISB
;
;
;
INITIALIZING PORTB
Four of the PORTB pins (RB7:RB4) have an interrupton-change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupton-change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The mismatch outputs of RB7:RB4
are ORed together to generate the RB Port Change
Interrupt with Flag bit, RBIF (INTCON<0>).
This interrupt can wake the device from the Sleep
mode, or any of the Idle modes. The user, in the
Interrupt Service Routine, can clear the interrupt in the
following manner:
a)
b)
Initialize PORTB by
clearing output
data latches
Alternate method
to clear output
data latches
Set RB<4:0> as
digital I/O pins
(required if config bit
PBADEN is set)
Value used to
initialize data
direction
Set RB<3:0> as inputs
RB<5:4> as outputs
RB<7:6> as inputs
DS39631A-page 108
Preliminary
PIC18F2420/2520/4420/4520
TABLE 10-3:
Pin
RB0/INT0/FLT0/
AN12
RB1/INT1/AN10
RB2/INT2/AN8
RB3/AN9/CCP2
RB4/KBI0/AN11
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
Legend:
Note 1:
2:
3:
TRIS
Setting
I/O
I/O
Type
RB0
DIG
TTL
Description
INT0
ST
FLT0
ST
AN12
ANA
RB1
DIG
TTL
INT1
ST
AN10
ANA
RB2
DIG
TTL
INT2
ST
AN8
ANA
RB3
DIG
TTL
AN9
ANA
CCP2(2)
DIG
RB4
ST
DIG
TTL
KBI0
TTL
AN11
ANA
RB5
DIG
TTL
KBI1
TTL
PGM
ST
RB6
DIG
TTL
KBI2
TTL
PGC
ST
Serial execution (ICSP) clock input for ICSP and ICD operation.(3)
RB7
DIG
TTL
KBI3
TTL
PGD
DIG
ST
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x = Dont care (TRIS bit does not affect port direction or is overridden for this option).
Configuration on POR is determined by the PBADEN configuration bit. Pins are configured as analog inputs by default
when PBADEN is set and digital inputs when PBADEN is cleared.
Alternate assignment for CCP2 when the CCP2MX configuration bit is 0. Default assignment is RC1.
All other pin functions are disabled when ICSP or ICD are enabled.
Preliminary
DS39631A-page 109
PIC18F2420/2520/4420/4520
TABLE 10-4:
Name
PORTB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
LATB
TRISB
INTCON
GIE/GIEH PEIE/GIEL
TMR0IE
INT0IE
Reset
Values
on page
52
52
52
RBIE
TMR0IF
INT0IF
RBIF
49
TMR0IP
RBIP
49
INTCON2
RBPU
INTCON3
INT2IP
INT1IP
INT2IE
INT1IE
INT2IF
INT1IF
49
ADCON1
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
51
DS39631A-page 110
Preliminary
PIC18F2420/2520/4420/4520
10.3
Note:
PORTC is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISC bit (= 0)
will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATC) is also memory
mapped. Read-modify-write operations on the LATC
register read and write the latched output value for
PORTC.
PORTC is multiplexed with several peripheral functions
(Table 10-5). The pins have Schmitt Trigger input buffers. RC1 is normally configured by configuration bit,
CCP2MX, as the default peripheral pin of the CCP2
module (default/erased state, CCP2MX = 1).
EXAMPLE 10-3:
CLRF
PORTC
CLRF
LATC
MOVLW
0CFh
MOVWF
TRISC
Preliminary
INITIALIZING PORTC
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTC by
clearing output
data latches
Alternate method
to clear output
data latches
Value used to
initialize data
direction
Set RC<3:0> as inputs
RC<5:4> as outputs
RC<7:6> as inputs
DS39631A-page 111
PIC18F2420/2520/4420/4520
TABLE 10-5:
Pin
TRIS
Setting
I/O
I/O
Type
RC0
DIG
ST
T1OSO
ANA
T13CKI
ST
RC1
DIG
ST
T1OSI
ANA
CCP2(1)
DIG
CCP2 compare and PWM output; takes priority over port data.
ST
DIG
RC0/T1OSO/
T13CKI
RC1/T1OSI/CCP2
RC2/CCP1/P1A
RC3/SCK/SCL
RC2
RC6/TX/CK
RC7/RX/DT
Legend:
Note 1:
2:
ST
DIG
ST
P1A(2)
DIG
RC3
DIG
ST
DIG
SPI clock output (MSSP module); takes priority over port data.
ST
DIG
I2C clock output (MSSP module); takes priority over port data.
SCL
RC5/SDO
CCP1
SCK
RC4/SDI/SDA
Description
RC4
I C/SMB I2C clock input (MSSP module); input type depends on module setting.
DIG
ST
SDI
ST
SDA
DIG
I2C data output (MSSP module); takes priority over port data.
RC5
ST
SDO
DIG
SPI data output (MSSP module); takes priority over port data.
RC6
DIG
ST
TX
DIG
CK
DIG
RC7
I2C/SMB I2C data input (MSSP module); input type depends on module setting.
DIG
ST
DIG
ST
RX
ST
DT
DIG
ST
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
I2C/SMB = I2C/SMBus input buffer; x = Dont care (TRIS bit does not affect port direction or is overridden for this option).
Default assignment for CCP2 when the CCP2MX configuration bit is set. Alternate assignment is RB3.
Enhanced PWM output is available only on PIC18F4520 devices.
DS39631A-page 112
Preliminary
PIC18F2420/2520/4420/4520
TABLE 10-6:
Name
PORTC
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
Reset
Values
on page
52
LATC
52
TRISC
52
Preliminary
DS39631A-page 113
PIC18F2420/2520/4420/4520
10.4
Note:
PORTD is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISD. Setting a
TRISD bit (= 1) will make the corresponding PORTD
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISD bit (= 0)
will make the corresponding PORTD pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATD) is also memory
mapped. Read-modify-write operations on the LATD
register read and write the latched output value for
PORTD.
All pins on PORTD are implemented with Schmitt Trigger input buffers. Each pin is individually configurable
as an input or output.
Three of the PORTD pins are multiplexed with outputs
P1B, P1C and P1D of the enhanced CCP module. The
operation of these additional PWM output pins is
covered in greater detail in Section 16.0 Enhanced
Capture/Compare/PWM (ECCP) Module.
Note:
PORTD can also be configured as an 8-bit wide microprocessor port (Parallel Slave Port) by setting control
bit, PSPMODE (TRISE<4>). In this mode, the input
buffers are TTL. See Section 10.6 Parallel Slave
Port for additional information on the Parallel Slave
Port (PSP).
Note:
EXAMPLE 10-4:
CLRF
PORTD
CLRF
LATD
MOVLW
0CFh
MOVWF
TRISD
INITIALIZING PORTD
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTD by
clearing output
data latches
Alternate method
to clear output
data latches
Value used to
initialize data
direction
Set RD<3:0> as inputs
RD<5:4> as outputs
RD<7:6> as inputs
DS39631A-page 114
Preliminary
PIC18F2420/2520/4420/4520
TABLE 10-7:
Pin
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
TRIS
Setting
I/O
I/O
Type
RD0
DIG
ST
PSP0
DIG
PSP read data output (LATD<0>); takes priority over port data.
Legend:
TTL
RD1
DIG
ST
PSP1
DIG
PSP read data output (LATD<1>); takes priority over port data.
TTL
RD2
DIG
ST
PSP2
DIG
PSP read data output (LATD<2>); takes priority over port data.
TTL
RD3
DIG
ST
PSP3
DIG
PSP read data output (LATD<3>); takes priority over port data.
TTL
RD4
DIG
ST
PSP4
DIG
PSP read data output (LATD<4>); takes priority over port data.
TTL
RD5
DIG
ST
PSP5
DIG
PSP read data output (LATD<5>); takes priority over port data.
TTL
P1B
DIG
ECCP1 Enhanced PWM output, channel B; takes priority over port and
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RD6
DIG
ST
PSP6
RD7/PSP7/P1D
Description
DIG
PSP read data output (LATD<6>); takes priority over port data.
TTL
P1C
DIG
ECCP1 Enhanced PWM output, channel C; takes priority over port and
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RD7
DIG
ST
PSP7
DIG
PSP read data output (LATD<7>); takes priority over port data.
TTL
P1D
DIG
ECCP1 Enhanced PWM output, channel D; takes priority over port and
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; x = Dont care
(TRIS bit does not affect port direction or is overridden for this option).
Preliminary
DS39631A-page 115
PIC18F2420/2520/4420/4520
TABLE 10-8:
Name
PORTD
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
LATD
TRISD
TRISE
CCP1CON
Reset
Values
on page
52
52
52
IBF
OBF
IBOV
PSPMODE
TRISE2
TRISE1
TRISE0
52
P1M1
P1M0
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
51
DS39631A-page 116
Preliminary
PIC18F2420/2520/4420/4520
10.5
EXAMPLE 10-5:
CLRF
CLRF
MOVLW
MOVWF
MOVLW
MOVWF
10.5.1
PORTE
;
;
;
LATE
;
;
;
0Ah
;
ADCON1 ;
03h
;
;
;
TRISE
;
;
;
INITIALIZING PORTE
Initialize PORTE by
clearing output
data latches
Alternate method
to clear output
data latches
Configure A/D
for digital inputs
Value used to
initialize data
direction
Set RE<0> as inputs
RE<1> as outputs
RE<2> as inputs
Preliminary
DS39631A-page 117
PIC18F2420/2520/4420/4520
REGISTER 10-1:
R-0
R/W-0
R/W-0
U-0
R/W-1
R/W-1
R/W-1
IBF
OBF
IBOV
PSPMODE
TRISE2
TRISE1
TRISE0
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
Unimplemented: Read as 0
bit 2
bit 1
bit 0
DS39631A-page 118
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
Preliminary
x = Bit is unknown
PIC18F2420/2520/4420/4520
TABLE 10-9:
Pin
Function
TRIS
Setting
I/O
I/O
Type
RE0
DIG
ST
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
MCLR/VPP/RE3(1)
Legend:
Note 1:
2:
Description
RD
TTL
AN5
ANA
RE1
DIG
ST
WR
TTL
AN6
ANA
RE2
DIG
ST
CS
TTL
AN7
ANA
MCLR
ST
VPP
ANA
RE3
(2)
ST
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x = Dont care (TRIS bit does not affect port direction or is overridden for this option).
RE3 is available on both 28-pin and 40/44-pin devices. All other PORTE pins are only implemented on 40/44-pin
devices.
RE3 does not have a corresponding TRIS bit to control data direction.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
RE3(1,2)
RE2
RE1
RE0
52
LATE
TRISE
IBF
OBF
IBOV
PSPMODE
TRISE1
TRISE0
52
52
ADCON1
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
51
Preliminary
DS39631A-page 119
PIC18F2420/2520/4420/4520
10.6
Note:
FIGURE 10-2:
The PSP can directly interface to an 8-bit microprocessor data bus. The external microprocessor can
read or write the PORTD latch as an 8-bit latch. Setting
the control bit, PSPMODE, enables the PORTE I/O
pins to become control inputs for the microprocessor
port. When set, port pin RE0 is the RD input, RE1 is the
WR input and RE2 is the CS (Chip Select) input. For
this functionality, the corresponding data direction bits
of the TRISE register (TRISE<2:0>) must be configured as inputs (set). The A/D port configuration bits,
PFCG3:PFCG0 (ADCON1<3:0>), must also be set to a
value in the range of 1010 through 1111.
Preliminary
RDx pin
Data Latch
RD PORTD
TTL
D
ENEN
RD LATD
PORTE Pins
Read
DS39631A-page 120
CK
TTL
RD
Chip Select
TTL
CS
Write
TTL
Note:
WR
PIC18F2420/2520/4420/4520
FIGURE 10-3:
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
FIGURE 10-4:
Q2
Q3
Q4
Q1
Q2
Q3
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
LATD
TRISD
PORTE
52
RE3
RE2
LATE
IBF
OBF
IBOV
PSPMODE
TRISE2
RE1
RE0
52
TRISE0
52
52
TMR0IF
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
49
PIR1
PSPIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
52
PIE1
PSPIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
52
IPR1
PSPIP
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
52
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
51
ADCON1
GIE/GIEH PEIE/GIEL
52
52
TRISE
INTCON
Reset
Values
on page
Legend: = unimplemented, read as 0. Shaded cells are not used by the Parallel Slave Port.
Preliminary
DS39631A-page 121
PIC18F2420/2520/4420/4520
NOTES:
DS39631A-page 122
Preliminary
PIC18F2420/2520/4420/4520
11.0
TIMER0 MODULE
REGISTER 11-1:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
TMR0ON
T08BIT
T0CS
T0SE
PSA
T0PS2
T0PS1
T0PS0
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
Preliminary
x = Bit is unknown
DS39631A-page 123
PIC18F2420/2520/4420/4520
11.1
Timer0 Operation
FIGURE 11-1:
11.2
0
0
1
Programmable
Prescaler
T0CKI pin
T0SE
T0CS
Sync with
Internal
Clocks
Set
TMR0IF
on Overflow
TMR0L
(2 TCY Delay)
8
T0PS2:T0PS0
PSA
Note:
Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
FIGURE 11-2:
FOSC/4
0
0
1
T0CKI pin
T0SE
T0CS
Programmable
Prescaler
Sync with
Internal
Clocks
TMR0
High Byte
TMR0L
Set
TMR0IF
on Overflow
(2 TCY Delay)
Read TMR0L
T0PS2:T0PS0
Write TMR0L
PSA
TMR0H
8
8
Internal Data Bus
Note:
Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
DS39631A-page 124
Preliminary
PIC18F2420/2520/4420/4520
11.3
11.3.1
Prescaler
TABLE 11-1:
Name
SWITCHING PRESCALER
ASSIGNMENT
11.4
Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h in 8-bit mode, or from
FFFFh to 0000h in 16-bit mode. This overflow sets the
TMR0IF flag bit. The interrupt can be masked by clearing the TMR0IE bit (INTCON<5>). Before re-enabling
the interrupt, the TMR0IF bit must be cleared in
software by the Interrupt Service Routine.
Since Timer0 is shut down in Sleep mode, the TMR0
interrupt cannot awaken the processor from Sleep.
Bit 6
Bit 5
TMR0L
TMR0H
INTCON
T0CON
TMR0ON
T08BIT
TRISA
RA7(1)
RA6(1)
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
50
50
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
49
T0CS
T0SE
PSA
T0PS2
T0PS1
T0PS0
50
RA5
RA4
RA3
RA2
RA1
RA0
52
Preliminary
DS39631A-page 125
PIC18F2420/2520/4420/4520
NOTES:
DS39631A-page 126
Preliminary
PIC18F2420/2520/4420/4520
12.0
TIMER1 MODULE
REGISTER 12-1:
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RD16
T1RUN
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
bit 7
bit 0
bit 7
bit 6
bit 5-4
bit 3
bit 2
bit 1
bit 0
W = Writable bit
1 = Bit is set
Preliminary
DS39631A-page 127
PIC18F2420/2520/4420/4520
12.1
Timer1 Operation
FIGURE 12-1:
On/Off
T1OSO/T13CKI
T1OSI
Synchronize
Prescaler
1, 2, 4, 8
FOSC/4
Internal
Clock
Detect
0
2
T1OSCEN(1)
Sleep Input
Timer1
On/Off
TMR1CS
T1CKPS1:T1CKPS0
T1SYNC
TMR1ON
Clear TMR1
(CCP Special Event Trigger)
Set
TMR1IF
on Overflow
TMR1
High Byte
TMR1L
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
FIGURE 12-2:
T1OSO/T13CKI
T1OSI
1
FOSC/4
Internal
Clock
Synchronize
Prescaler
1, 2, 4, 8
Detect
0
2
Sleep Input
TMR1CS
T1OSCEN(1)
T1CKPS1:T1CKPS0
T1SYNC
TMR1ON
Clear TMR1
(CCP Special Event Trigger)
Timer1
On/Off
TMR1
High Byte
TMR1L
Set
TMR1IF
on Overflow
Read TMR1L
Write TMR1L
8
TMR1H
8
8
Internal Data Bus
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
DS39631A-page 128
Preliminary
PIC18F2420/2520/4420/4520
12.2
TABLE 12-1:
Osc Type
LP
C1
27 pF
C2
(1)
27 pF(1)
12.3
Timer1 Oscillator
FIGURE 12-3:
EXTERNAL
COMPONENTS FOR THE
TIMER1 LP OSCILLATOR
C1
27 pF
PIC18FXXXX
XTAL
32.768 kHz
T1OSO
C2
27 pF
See the Notes with Table 12-1 for additional
information about capacitor selection.
USING TIMER1 AS A
CLOCK SOURCE
12.3.2
T1OSI
Note:
12.3.1
Preliminary
DS39631A-page 129
PIC18F2420/2520/4420/4520
12.3.3
12.5
FIGURE 12-4:
OSCILLATOR CIRCUIT
WITH GROUNDED
GUARD RING
VDD
VSS
12.6
OSC1
OSC2
RC0
RC1
RC2
Note: Not drawn to scale.
12.4
Timer1 Interrupt
DS39631A-page 130
Preliminary
PIC18F2420/2520/4420/4520
EXAMPLE 12-1:
RTCinit
MOVLW
MOVWF
CLRF
MOVLW
MOVWF
CLRF
CLRF
MOVLW
MOVWF
BSF
RETURN
80h
TMR1H
TMR1L
b00001111
T1CON
secs
mins
.12
hours
PIE1, TMR1IE
BSF
BCF
INCF
MOVLW
CPFSGT
RETURN
CLRF
INCF
MOVLW
CPFSGT
RETURN
CLRF
INCF
MOVLW
CPFSGT
RETURN
CLRF
RETURN
TMR1H, 7
PIR1, TMR1IF
secs, F
.59
secs
;
;
;
;
;
;
;
;
No, done
Clear seconds
Increment minutes
60 minutes elapsed?
;
;
;
;
No, done
clear minutes
Increment hours
24 hours elapsed?
RTCisr
TABLE 12-2:
Name
secs
mins, F
.59
mins
mins
hours, F
.23
hours
; No, done
; Reset hours
; Done
hours
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
49
Bit 6
INTCON
GIE/GIEH PEIE/GIEL
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
52
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
52
IPR1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
52
TMR1L
50
TMR1H
50
T1CON
RD16
T1RUN
TMR1CS
TMR1ON
50
Preliminary
DS39631A-page 131
PIC18F2420/2520/4420/4520
NOTES:
DS39631A-page 132
Preliminary
PIC18F2420/2520/4420/4520
13.0
TIMER2 MODULE
13.1
Timer2 Operation
REGISTER 13-1:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T2CKPS0
bit 7
bit 0
bit 7
Unimplemented: Read as 0
bit 6-3
bit 2
bit 1-0
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
Preliminary
x = Bit is unknown
DS39631A-page 133
PIC18F2420/2520/4420/4520
13.2
Timer2 Interrupt
13.3
Timer2 Output
FIGURE 13-1:
1:1 to 1:16
Postscaler
T2OUTPS3:T2OUTPS0
Set TMR2IF
TMR2 Output
(to PWM or MSSP)
T2CKPS1:T2CKPS0
FOSC/4
TMR2/PR2
Match
Reset
TMR2
Comparator
PR2
8
TABLE 13-1:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
49
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
52
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
52
IPR1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
TMR2
T2CON
PR2
Timer2 Register
52
50
T2CKPS1 T2CKPS0
50
50
Legend: = unimplemented, read as 0. Shaded cells are not used by the Timer2 module.
Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear.
DS39631A-page 134
Preliminary
PIC18F2420/2520/4420/4520
14.0
TIMER3 MODULE
REGISTER 14-1:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RD16
T3CCP2
T3CKPS1
T3CKPS0
T3CCP1
T3SYNC
TMR3CS
TMR3ON
bit 7
bit 0
bit 7
bit 6,3
bit 5-4
bit 2
bit 1
bit 0
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
Preliminary
x = Bit is unknown
DS39631A-page 135
PIC18F2420/2520/4420/4520
14.1
Timer3 Operation
FIGURE 14-1:
T1OSO/T13CKI
1
FOSC/4
Internal
Clock
T1OSI
Synchronize
Prescaler
1, 2, 4, 8
Detect
0
2
T1OSCEN
(1)
Sleep Input
Timer3
On/Off
TMR3CS
T3CKPS1:T3CKPS0
T3SYNC
TMR3ON
Clear TMR3
Set
TMR3IF
on Overflow
TMR3
High Byte
TMR3L
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
FIGURE 14-2:
T13CKI/T1OSO
1
FOSC/4
Internal
Clock
T1OSI
Synchronize
Prescaler
1, 2, 4, 8
Detect
0
2
Sleep Input
TMR3CS
T1OSCEN(1)
T3CKPS1:T3CKPS0
Timer3
On/Off
T3SYNC
TMR3ON
CCP1/CCP2 Special Event Trigger
CCP1/CCP2 Select from T3CON<6,3>
Clear TMR3
Set
TMR3IF
on Overflow
TMR3
High Byte
TMR3L
Read TMR1L
Write TMR1L
8
TMR3H
8
8
Internal Data Bus
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
DS39631A-page 136
Preliminary
PIC18F2420/2520/4420/4520
14.2
14.4
Timer3 Interrupt
14.5
14.3
TABLE 14-1:
Name
INTCON
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
49
Bit 6
GIE/GIEH PEIE/GIEL
PIR2
OSCFIF
CMIF
EEIF
BCLIF
HLVDIF
TMR3IF
CCP2IF
52
PIE2
OSCFIE
CMIE
EEIE
BCLIE
HLVDIE
TMR3IE
CCP2IE
52
IPR2
OSCFIP
CMIP
EEIP
BCLIP
HLVDIP
TMR3IP
CCP2IP
52
TMR3L
51
TMR3H
51
T1CON
RD16
T1RUN
TMR1CS
TMR1ON
50
T3CON
RD16
T3CCP2
T3CKPS1 T3CKPS0
TMR3CS
TMR3ON
51
T3CCP1
T3SYNC
Legend: = unimplemented, read as 0. Shaded cells are not used by the Timer3 module.
Preliminary
DS39631A-page 137
PIC18F2420/2520/4420/4520
NOTES:
DS39631A-page 138
Preliminary
PIC18F2420/2520/4420/4520
15.0
CAPTURE/COMPARE/PWM
(CCP) MODULES
REGISTER 15-1:
U-0
R/W-0
R/W-0
R/W-0
R/W-0
DCxB1
DCxB0
CCPxM3
CCPxM2
R/W-0
R/W-0
CCPxM1 CCPxM0
bit 7
bit 0
bit 7-6
Unimplemented: Read as 0
bit 5-4
DCxB1:DCxB0: PWM Duty Cycle bit 1 and bit 0 for CCP Module x
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight MSbs
(DCx9:DCx2) of the duty cycle are found in CCPRxL.
bit 3-0
W = Writable bit
1 = Bit is set
Preliminary
DS39631A-page 139
PIC18F2420/2520/4420/4520
15.1
15.1.1
15.1.2
TABLE 15-1:
CCP/ECCP Mode
Timer Resource
Capture
Compare
PWM
Timer1 or Timer3
Timer1 or Timer3
Timer2
TABLE 15-2:
Interaction
Capture
Capture
Each module can use TMR1 or TMR3 as the time base. The time base can be different
for each CCP.
Capture
Compare
CCP2 can be configured for the Special Event Trigger to reset TMR1 or TMR3
(depending upon which time base is used). Automatic A/D conversions on trigger event
can also be done. Operation of CCP1 could be affected if it is using the same timer as a
time base.
Compare
Capture
CCP1 can be configured for the Special Event Trigger to reset TMR1 or TMR3
(depending upon which time base is used). Operation of CCP2 could be affected if it is
using the same timer as a time base.
Compare
Compare
Either module can be configured for the Special Event Trigger to reset the time base.
Automatic A/D conversions on CCP2 trigger event can be done. Conflicts may occur if
both modules are using the same time base.
Capture
PWM(1)
None
Compare
PWM(1)
None
PWM(1)
Capture
None
PWM(1)
Compare
None
PWM(1)
PWM
Note 1:
Both PWMs will have the same frequency and update rate (TMR2 interrupt).
DS39631A-page 140
Preliminary
PIC18F2420/2520/4420/4520
15.2
15.2.3
Capture Mode
15.2.4
15.2.2
EXAMPLE 15-1:
CLRF
MOVLW
FIGURE 15-1:
CCP PRESCALER
15.2.1
SOFTWARE INTERRUPT
MOVWF
CHANGING BETWEEN
CAPTURE PRESCALERS
(CCP2 SHOWN)
CCP2CON
; Turn CCP module off
NEW_CAPT_PS ; Load WREG with the
; new prescaler mode
; value and CCP ON
CCP2CON
; Load CCP2CON with
; this value
TMR3L
Set CCP1IF
T3CCP2
CCP1 pin
Prescaler
1, 4, 16
and
Edge Detect
CCPR1H
T3CCP2
4
CCP1CON<3:0>
Q1:Q4
CCP2CON<3:0>
TMR3
Enable
CCPR1L
TMR1
Enable
TMR1H
TMR1L
TMR3H
TMR3L
Set CCP2IF
4
T3CCP1
T3CCP2
TMR3
Enable
CCP2 pin
Prescaler
1, 4, 16
and
Edge Detect
CCPR2H
CCPR2L
TMR1
Enable
T3CCP2
T3CCP1
Preliminary
TMR1H
TMR1L
DS39631A-page 141
PIC18F2420/2520/4420/4520
15.3
15.3.2
Compare Mode
15.3.3
driven high
driven low
toggled (high-to-low or low-to-high)
remain unchanged (that is, reflects the state of the
I/O latch)
15.3.1
15.3.4
FIGURE 15-2:
CCPR1H
Set CCP1IF
CCPR1L
Comparator
Output
Logic
Compare
Match
R
TRIS
Output Enable
4
CCP1CON<3:0>
0
TMR1H
TMR1L
TMR3H
TMR3L
T3CCP1
T3CCP2
Set CCP2IF
Comparator
CCPR2H
CCP2 pin
Compare
Match
Output
Logic
4
CCPR2L
R
TRIS
Output Enable
CCP2CON<3:0>
DS39631A-page 142
Preliminary
PIC18F2420/2520/4420/4520
TABLE 15-3:
Name
INTCON
Bit 6
Bit 5
Reset
Values
on page
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
49
RI
TO
PD
POR
BOR
48
IPEN
SBOREN
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
52
PIE1
(1)
PSPIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
52
IPR1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
52
RCON
PIR2
OSCFIF
CMIF
EEIF
BCLIF
HLVDIF
TMR3IF
CCP2IF
52
PIE2
OSCFIE
CMIE
EEIE
BCLIE
HLVDIE
TMR3IE
CCP2IE
52
IPR2
OSCFIP
CMIP
EEIP
BCLIP
HLVDIP
TMR3IP
CCP2IP
52
TRISB
52
TRISC
52
TMR1L
50
TMR1H
T1CON
RD16
T1RUN
50
TMR1CS TMR1ON
50
TMR3H
51
TMR3L
51
T3CON
RD16
T3CCP2
T3CKPS1 T3CKPS0
T3CCP1
T3SYNC
TMR3CS TMR3ON
51
CCPR1L
51
CCPR1H
51
CCP1CON
P1M1(1)
P1M0(1)
DC1B1
DC1B0
CCPR2L
CCPR2H
CCP2CON
DC2B1
DC2B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
51
51
51
CCP2M3
CCP2M2
CCP2M1
CCP2M0
51
Legend: = unimplemented, read as 0. Shaded cells are not used by Capture/Compare, Timer1 or Timer3.
Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear.
Preliminary
DS39631A-page 143
PIC18F2420/2520/4420/4520
15.4
15.4.1
PWM Mode
FIGURE 15-3:
EQUATION 15-1:
PWM Period = [(PR2) + 1] 4 TOSC
(TMR2 Prescale Value)
PWM frequency is defined as 1/[PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
TMR2 is cleared
The CCPx pin is set (exception: if PWM duty
cycle = 0%, the CCPx pin will not be set)
The PWM duty cycle is latched from CCPRxL into
CCPRxH
Note:
CCPxCON<5:4>
15.4.2
CCPRxH (Slave)
CCPx Output
R
Comparator
TMR2
(Note 1)
S
Comparator
Clear Timer,
CCP1 pin and
latch D.C.
PR2
Corresponding
TRIS bit
EQUATION 15-2:
FIGURE 15-4:
PWM PERIOD
PWM OUTPUT
Period
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2
DS39631A-page 144
Preliminary
PIC18F2420/2520/4420/4520
The CCPRxH register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM
operation.
EQUATION 15-3:
F OSC
log ---------------
F PWM
PWM Resolution (max) = -----------------------------bits
log ( 2 )
Note:
TABLE 15-4:
PWM Frequency
Timer Prescaler (1, 4, 16)
PR2 Value
Maximum Resolution (bits)
15.4.3
2.44 kHz
9.77 kHz
39.06 kHz
312.50 kHz
416.67 kHz
16
FFh
FFh
FFh
3Fh
1Fh
17h
10
10
10
6.58
15.4.4
PWM AUTO-SHUTDOWN
(CCP1 ONLY)
156.25 kHz
Preliminary
DS39631A-page 145
PIC18F2420/2520/4420/4520
TABLE 15-5:
Name
INTCON
Bit 6
GIE/GIEH PEIE/GIEL
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
49
RI
TO
PD
POR
BOR
48
IPEN
SBOREN
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
52
PIE1
PSPIE
(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
52
IPR1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
52
RCON
TRISB
52
TRISC
52
TMR2
Timer2 Register
50
PR2
50
T2CON
CCPR1L
CCPR1H
CCP1CON
P1M1(1)
P1M0(1)
DC1B1
DC1B0
50
51
51
CCP1M3
CCP1M2
CCP1M1
CCP1M0
51
CCPR2L
51
CCPR2H
51
CCP2CON
ECCP1AS
PWM1CON
ECCPASE ECCPAS2
PRSEN
PDC6(1)
DC2B1
DC2B0
CCP2M3
CCP2M2
ECCPAS1
ECCPAS0
PSSAC1
CCP2M1
51
PDC5(1)
PDC4(1)
PDC3(1)
PDC2(1)
51
PDC1(1)
CCP2M0
PDC0(1)
51
Legend: = unimplemented, read as 0. Shaded cells are not used by PWM or Timer2.
Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear.
DS39631A-page 146
Preliminary
PIC18F2420/2520/4420/4520
16.0
Note:
ENHANCED CAPTURE/
COMPARE/PWM (ECCP)
MODULE
REGISTER 16-1:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
P1M1
P1M0
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
bit 7
bit 0
bit 7-6
bit 5-4
bit 3-0
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
Preliminary
x = Bit is unknown
DS39631A-page 147
PIC18F2420/2520/4420/4520
In addition to the expanded range of modes available
through the CCP1CON register and ECCP1AS
register, the ECCP module has an additional register
associated with Enhanced PWM operation and
auto-shutdown features. It is:
PWM1CON (Dead-band delay)
16.1
16.1.1
TABLE 16-1:
16.2
16.2.1
16.3
When setting up single output PWM operations, users are free to use either of the processes described in Section 15.4.4 Setup
for PWM Operation or Section 16.4.9
Setup for PWM Operation. The latter is
more generic and will work for either single
or multi-output PWM.
ECCP Mode
CCP1CON
Configuration
RC2
RD5
RD6
RD7
00xx 11xx
CCP1
RD5/PSP5
RD6/PSP6
RD7/PSP7
Dual PWM
10xx 11xx
P1A
P1B
RD6/PSP6
RD7/PSP7
Quad PWM
x1xx 11xx
P1A
P1B
P1C
P1D
Legend: x = Dont care. Shaded cells indicate pin assignments not used by ECCP1 in a given mode.
DS39631A-page 148
Preliminary
PIC18F2420/2520/4420/4520
16.4
16.4.1
PWM PERIOD
EQUATION 16-1:
PWM Period =
FIGURE 16-1:
[(PR2) + 1] 4 TOSC
(TMR2 Prescale Value)
CCP1M<3:0>
4
P1M1<1:0>
2
CCPR1L
CCP1/P1A
CCP1/P1A
TRISx<x>
CCPR1H (Slave)
P1B
R
Comparator
Output
Controller
P1B
TRISx<x>
P1C
TMR2
(Note 1)
P1D
Comparator
PR2
P1C
TRISx<x>
Clear Timer,
set CCP1 pin and
latch D.C.
P1D
TRISx<x>
PWM1CON
Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit
time base.
Preliminary
DS39631A-page 149
PIC18F2420/2520/4420/4520
16.4.2
EQUATION 16-3:
log FOSC
FPWM
PWM Resolution (max) =
log(2)
Note:
EQUATION 16-2:
PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>)
TOSC (TMR2 Prescale Value)
16.4.3
TABLE 16-2:
) bits
Single Output
Half-Bridge Output
Full-Bridge Output, Forward mode
Full-Bridge Output, Reverse mode
PWM Frequency
Timer Prescaler (1, 4, 16)
PR2 Value
Maximum Resolution (bits)
DS39631A-page 150
2.44 kHz
9.77 kHz
39.06 kHz
156.25 kHz
312.50 kHz
416.67 kHz
16
FFh
FFh
FFh
3Fh
1Fh
17h
10
10
10
6.58
Preliminary
PIC18F2420/2520/4420/4520
FIGURE 16-2:
CCP1CON
<7:6>
00
(Single Output)
PR2 + 1
Duty
Cycle
SIGNAL
Period
P1A Modulated
Delay(1)
Delay(1)
P1A Modulated
10
(Half-Bridge)
P1B Modulated
P1A Active
01
(Full-Bridge,
Forward)
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
11
(Full-Bridge,
Reverse)
P1B Modulated
P1C Active
P1D Inactive
FIGURE 16-3:
CCP1CON
<7:6>
00
(Single Output)
SIGNAL
0
Duty
Cycle
PR2 + 1
Period
P1A Modulated
P1A Modulated
10
(Half-Bridge)
Delay(1)
Delay(1)
P1B Modulated
P1A Active
01
(Full-Bridge,
Forward)
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
11
(Full-Bridge,
Reverse)
P1B Modulated
P1C Active
P1D Inactive
Relationships:
Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)
Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)
Delay = 4 * TOSC * (PWM1CON<6:0>)
Note 1: Dead-band delay is programmed using the PWM1CON register (see Section 16.4.6 Programmable
Dead-Band Delay).
Preliminary
DS39631A-page 151
PIC18F2420/2520/4420/4520
16.4.4
HALF-BRIDGE MODE
FIGURE 16-4:
HALF-BRIDGE PWM
OUTPUT
Period
Period
Duty Cycle
P1A(2)
td
td
P1B(2)
(1)
(1)
(1)
td = Dead-Band Delay
Note 1: At this time, the TMR2 register is equal to the
PR2 register.
2: Output signals are shown as active-high.
FIGURE 16-5:
PIC18F4X2X
FET
Driver
+
V
-
P1A
Load
FET
Driver
+
V
-
P1B
FET
Driver
P1A
FET
Driver
Load
FET
Driver
P1B
V-
DS39631A-page 152
Preliminary
PIC18F2420/2520/4420/4520
16.4.5
FULL-BRIDGE MODE
FIGURE 16-6:
Forward Mode
Period
P1A
(2)
Duty Cycle
P1B(2)
P1C(2)
P1D(2)
(1)
(1)
Reverse Mode
Period
Duty Cycle
P1A(2)
P1B(2)
P1C(2)
P1D(2)
(1)
(1)
Note 1: At this time, the TMR2 register is equal to the PR2 register.
Note 2: Output signal is shown as active-high.
Preliminary
DS39631A-page 153
PIC18F2420/2520/4420/4520
FIGURE 16-7:
PIC18F4X2X
FET
Driver
QC
QA
FET
Driver
P1A
Load
P1B
FET
Driver
P1C
FET
Driver
QD
QB
VP1D
16.4.5.1
DS39631A-page 154
Preliminary
PIC18F2420/2520/4420/4520
FIGURE 16-8:
SIGNAL
Period
P1A (Active-High)
P1B (Active-High)
DC
P1C (Active-High)
(Note 2)
P1D (Active-High)
DC
Note 1: The direction bit in the CCP1 Control register (CCP1CON<7>) is written any time during the PWM cycle.
2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervals
of 4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value. The modulated P1B and P1D signals
are inactive at this time.
FIGURE 16-9:
t1
Reverse Period
P1A(1)
P1B(1)
DC
P1C(1)
P1D(1)
DC
tON(2)
Potential
Shoot-Through
Current(1)
Note 1: All signals are shown as active-high.
2: tON is the turn-on delay of power switch QC and its driver.
3: tOFF is the turn-off delay of power switch QD and its driver.
Preliminary
DS39631A-page 155
PIC18F2420/2520/4420/4520
16.4.6
Note:
PROGRAMMABLE DEAD-BAND
DELAY
Programmable dead-band delay is not
implemented in 28-pin devices with
standard CCP modules.
16.4.7
REGISTER 16-2:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PRSEN
PDC6(1)
PDC5(1)
PDC4(1)
PDC3(1)
PDC2(1)
PDC1(1)
PDC0(1)
bit 7
bit 0
bit 7
bit 6-0
DS39631A-page 156
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
Preliminary
x = Bit is unknown
PIC18F2420/2520/4420/4520
REGISTER 16-3:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
bit 7
bit 6-4
bit 3-2
bit 1-0
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
Preliminary
x = Bit is unknown
DS39631A-page 157
PIC18F2420/2520/4420/4520
16.4.7.1
16.4.8
Independent of the PRSEN bit setting, if the autoshutdown source is one of the comparators, the
shutdown condition is a level. The ECCPASE bit
cannot be cleared as long as the cause of the shutdown
persists.
The Auto-Shutdown mode can be forced by writing a 1
to the ECCPASE bit.
FIGURE 16-10:
START-UP CONSIDERATIONS
Shutdown Event
ECCPASE bit
PWM Activity
Normal PWM
Start of
PWM Period
FIGURE 16-11:
Shutdown
Shutdown
Event Occurs Event Clears
PWM
Resumes
Shutdown Event
ECCPASE bit
PWM Activity
Normal PWM
Start of
PWM Period
DS39631A-page 158
ECCPASE
Cleared by
Shutdown
Shutdown Firmware PWM
Event Occurs Event Clears
Resumes
Preliminary
PIC18F2420/2520/4420/4520
16.4.9
16.4.10
16.4.10.1
16.4.11
EFFECTS OF A RESET
Preliminary
DS39631A-page 159
PIC18F2420/2520/4420/4520
TABLE 16-3:
Name
INTCON
Bit 6
GIE/GIEH PEIE/GIEL
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
49
RCON
IPEN
SBOREN
RI
TO
PD
POR
BOR
48
PIR1
PSPIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
52
PIE1
PSPIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
52
IPR1
PSPIP
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
52
PIR2
OSCFIF
CMIF
EEIF
BCLIF
HLVDIF
TMR3IF
CCP2IF
52
PIE2
OSCFIE
CMIE
EEIE
BCLIE
HLVDIE
TMR3IE
CCP2IE
52
IPR2
OSCFIP
CMIP
EEIP
BCLIP
HLVDIP
TMR3IP
CCP2IP
52
TRISB
52
TRISC
52
TRISD
52
TMR1L
50
TMR1H
50
T1CON
TMR2
T2CON
RD16
T1RUN
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
Timer2 Register
50
50
50
PR2
50
TMR3L
51
TMR3H
T3CON
RD16
T3CCP2
51
T3CKPS1
T3CKPS0
CCPR1L
CCPR1H
CCP1CON
ECCP1AS
PWM1CON
Legend:
Note 1:
P1M1(1)
P1M0(1)
ECCPASE ECCPAS2
PRSEN
PDC6(1)
DC1B1
DC1B0
T3CCP1
T3SYNC
TMR3CS
TMR3ON
51
51
51
CCP1M3
CCP1M2
CCP1M1
(1)
CCP1M0
(1)
51
ECCPAS1
ECCPAS0
PSSAC1
PSSAC0
PSSBD1
PSSBD0
51
PDC5(1)
PDC4(1)
PDC3(1)
PDC2(1)
PDC1(1)
PDC0(1)
51
= unimplemented, read as 0. Shaded cells are not used during ECCP operation.
These bits are unimplemented on 28-pin devices; always maintain these bits clear.
DS39631A-page 160
Preliminary
PIC18F2420/2520/4420/4520
17.0
17.1
MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
17.3
SPI Mode
FIGURE 17-1:
Internal
Data Bus
Read
Master mode
Multi-Master mode
Slave mode
17.2
Write
SSPBUF reg
Control Registers
RC4/SDI/SDA
SSPSR reg
RC5/SDO
RA5/AN4/SS/
HLVDIN/C2OUT
Shift
Clock
bit 0
SS Control
Enable
Edge
Select
2
Clock Select
RC3/SCK/
SCL
SSPM3:SSPM0
SMP:CKE 4
TMR2 Output
2
2
Edge
Select
Prescaler TOSC
4, 16, 64
Preliminary
DS39631A-page 161
PIC18F2420/2520/4420/4520
17.3.1
REGISTERS
During transmission, the SSPBUF is not doublebuffered. A write to SSPBUF will write to both SSPBUF
and SSPSR.
REGISTER 17-1:
R/W-0
R-0
R-0
R-0
R-0
R-0
R-0
SMP
CKE
D/A
R/W
UA
BF
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
P: Stop bit
Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is
cleared.
bit 3
S: Start bit
Used in I2C mode only.
bit 2
bit 1
bit 0
DS39631A-page 162
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
Preliminary
x = Bit is unknown
PIC18F2420/2520/4420/4520
REGISTER 17-2:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
bit 7
bit 6
bit 5
In Master mode, the overflow bit is not set since each new reception (and
transmission) is initiated by writing to the SSPBUF register.
bit 4
bit 3-0
Bit combinations not specifically listed here are either reserved or implemented in
I2C mode only.
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
Preliminary
x = Bit is unknown
DS39631A-page 163
PIC18F2420/2520/4420/4520
17.3.2
OPERATION
EXAMPLE 17-1:
LOOP
reading the data that was just received. Any write to the
SSPBUF register during transmission/reception of data
will be ignored and the write collision detect bit, WCOL
(SSPCON1<7>), will be set. User software must clear
the WCOL bit so that it can be determined if the following write(s) to the SSPBUF register completed
successfully.
When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data to transfer is written to the SSPBUF. The
Buffer Full bit, BF (SSPSTAT<0>), indicates when
SSPBUF has been loaded with the received data
(transmission is complete). When the SSPBUF is read,
the BF bit is cleared. This data may be irrelevant if the
SPI is only a transmitter. Generally, the MSSP interrupt
is used to determine when the transmission/reception
has completed. The SSPBUF must be read and/or
written. If the interrupt method is not going to be used,
then software polling can be done to ensure that a write
collision does not occur. Example 17-1 shows the
loading of the SSPBUF (SSPSR) for data transmission.
The SSPSR is not directly readable or writable and can
only be accessed by addressing the SSPBUF register.
Additionally, the MSSP status register (SSPSTAT)
indicates the various status conditions.
BTFSS
BRA
MOVF
SSPSTAT, BF
LOOP
SSPBUF, W
MOVWF
RXDATA
MOVF
MOVWF
TXDATA, W
SSPBUF
DS39631A-page 164
Preliminary
PIC18F2420/2520/4420/4520
17.3.3
17.3.4
TYPICAL CONNECTION
FIGURE 17-2:
SDI
SDI
Shift Register
(SSPSR)
MSb
SDO
LSb
MSb
SCK
Serial Clock
PROCESSOR 1
Shift Register
(SSPSR)
LSb
SCK
PROCESSOR 2
Preliminary
DS39631A-page 165
PIC18F2420/2520/4420/4520
17.3.5
MASTER MODE
FIGURE 17-3:
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
Modes
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
SDO
(CKE = 0)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDO
(CKE = 1)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
bit 0
bit 7
Input
Sample
(SMP = 1)
SSPIF
Next Q4 Cycle
after Q2
SSPSR to
SSPBUF
DS39631A-page 166
Preliminary
PIC18F2420/2520/4420/4520
17.3.6
SLAVE MODE
17.3.7
SLAVE SELECT
SYNCHRONIZATION
FIGURE 17-4:
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDO
SDI
(SMP = 0)
bit 7
bit 6
bit 7
bit 0
bit 0
bit 7
bit 7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 Cycle
after Q2
SSPSR to
SSPBUF
Preliminary
DS39631A-page 167
PIC18F2420/2520/4420/4520
FIGURE 17-5:
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDO
SDI
(SMP = 0)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 0
bit 7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 Cycle
after Q2
SSPSR to
SSPBUF
FIGURE 17-6:
SS
Not Optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
SDO
bit 7
SDI
(SMP = 0)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 0
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 Cycle
after Q2
SSPSR to
SSPBUF
DS39631A-page 168
Preliminary
PIC18F2420/2520/4420/4520
17.3.8
17.3.9
EFFECTS OF A RESET
17.3.10
TABLE 17-1:
CKP
CKE
0, 0
0, 1
1, 0
1, 1
TABLE 17-2:
Name
INTCON
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
49
PIR1
PSPIF
(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
52
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
52
IPR1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
52
TRISA
TRISA7(2)
TRISA6(2)
TRISC
SSPBUF
52
52
50
SSPCON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
50
SSPSTAT
SMP
CKE
D/A
R/W
UA
BF
50
Legend: Shaded cells are not used by the MSSP in SPI mode.
Note 1: These bits are unimplemented in 28-pin devices; always maintain these bits clear.
2: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary
oscillator modes. When disabled, these bits read as 0.
Preliminary
DS39631A-page 169
PIC18F2420/2520/4420/4520
17.4
I2C Mode
17.4.1
FIGURE 17-7:
Write
Shift
Clock
MSb
LSb
Match Detect
Addr Match
DS39631A-page 170
During transmission, the SSPBUF is not doublebuffered. A write to SSPBUF will write to both SSPBUF
and SSPSR.
SSPADD reg
Start and
Stop bit Detect
SSPSR reg
RC4/SDI/
SDA
SSPBUF reg
RC3/SCK/SCL
Internal
Data Bus
Read
REGISTERS
Set, Reset
S, P bits
(SSPSTAT reg)
Preliminary
PIC18F2420/2520/4420/4520
REGISTER 17-3:
R/W-0
R-0
R-0
R-0
R-0
R-0
R-0
SMP
CKE
D/A
R/W
UA
BF
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
P: Stop bit
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
Note:
bit 3
S: Start bit
1 = Indicates that a Start bit has been detected last
0 = Start bit was not detected last
Note:
bit 2
This bit holds the R/W bit information following the last address match. This bit is
only valid from the address match to the next Start bit, Stop bit or not ACK bit.
In Master mode:
1 = Transmit is in progress
0 = Transmit is not in progress
Note:
ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is
in Active mode.
bit 1
bit 0
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
Preliminary
x = Bit is unknown
DS39631A-page 171
PIC18F2420/2520/4420/4520
REGISTER 17-4:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
bit 7
bit 6
bit 5
When enabled, the SDA and SCL pins must be properly configured as input or
output.
bit 4
bit 3-0
DS39631A-page 172
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
Preliminary
x = Bit is unknown
PIC18F2420/2520/4420/4520
REGISTER 17-5:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
GCEN
ACKSTAT
ACKDT
ACKEN(1)
RCEN(1)
PEN(1)
RSEN(1)
SEN(1)
bit 7
bit 0
bit 7
bit 6
bit 5
Value that will be transmitted when the user initiates an Acknowledge sequence at
the end of a receive.
bit 4
bit 3
bit 2
bit 1
bit 0
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
Preliminary
x = Bit is unknown
DS39631A-page 173
PIC18F2420/2520/4420/4520
17.4.2
OPERATION
17.4.3.1
17.4.3
SLAVE MODE
In Slave mode, the SCL and SDA pins must be configured as inputs (TRISC<4:3> set). The MSSP module
will override the input state with the output data when
required (slave-transmitter).
The I 2C Slave mode hardware will always generate an
interrupt on an address match. Through the mode
select bits, the user can also choose to interrupt on
Start and Stop bits
When an address is matched, or the data transfer after
an address match is received, the hardware automatically will generate the Acknowledge (ACK) pulse and
load the SSPBUF register with the received value
currently in the SSPSR register.
Any combination of the following conditions will cause
the MSSP module not to give this ACK pulse:
The Buffer Full bit, BF (SSPSTAT<0>), was set
before the transfer was received.
The overflow bit, SSPOV (SSPCON<6>), was set
before the transfer was received.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set. The
BF bit is cleared by reading the SSPBUF register, while
bit SSPOV is cleared through software.
Addressing
3.
4.
5.
6.
7.
8.
9.
DS39631A-page 174
Preliminary
PIC18F2420/2520/4420/4520
17.4.3.2
Reception
17.4.3.3
Transmission
Preliminary
DS39631A-page 175
DS39631A-page 176
Preliminary
CKP
A6
A4
A3
Receiving Address
A5
A2
SSPOV (SSPCON1<6>)
BF (SSPSTAT<0>)
(PIR1<3>)
SSPIF
SCL
A7
A1
ACK
R/W = 0
D7
D4
D3
Receiving Data
D5
Cleared in software
SSPBUF is read
D6
D2
D1
D0
ACK
D7
D6
D4
D3
Receiving Data
D5
D2
D1
D0
Bus master
terminates
transfer
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
ACK
FIGURE 17-8:
SDA
PIC18F2420/2520/4420/4520
I2C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS)
Preliminary
CKP
A6
Data in
sampled
BF (SSPSTAT<0>)
SSPIF (PIR1<3>)
A7
A5
A4
A3
A2
Receiving Address
A1
R/W = 0
ACK
D7
D5
D4
D3
D2
Cleared in software
D6
Transmitting Data
D0
ACK
D1
D7
D4
D3
D2
D0
ACK
D1
Transmitting Data
Cleared in software
D5
D6
FIGURE 17-9:
SCL
SDA
PIC18F2420/2520/4420/4520
DS39631A-page 177
DS39631A-page 178
Preliminary
A8
A9
UA (SSPSTAT<1>)
SSPOV (SSPCON1<6>)
CKP
Cleared in software
BF (SSPSTAT<0>)
(PIR1<3>)
SSPIF
SCL
ACK
R/W = 0
A7
A4
A3
A2
A0 ACK
Cleared by hardware
when SSPADD is updated
with low byte of address
A1
Cleared in software
A5
A6
D7
Cleared in software
9
1
Cleared in software
D3 D2
D3 D2
D1 D0
P
Bus master
terminates
transfer
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
ACK
FIGURE 17-10:
SDA
PIC18F2420/2520/4420/4520
I2C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS)
Preliminary
CKP (SSPCON1<4>)
UA (SSPSTAT<1>)
BF (SSPSTAT<0>)
(PIR1<3>)
SSPIF
SCL
A9 A8
ACK
Cleared in software
A6 A5 A4 A3 A2 A1
A0
A7
ACK
Cleared in software
ACK
R/W=1
Completion of
data transmission
clears BF flag
ACK
Bus master
terminates
transfer
D4 D3 D2 D1 D0
Cleared in software
D7 D6 D5
Write of SSPBUF
BF flag is clear
initiates transmit
at the end of the
third address sequence
A9 A8
Sr
FIGURE 17-11:
SDA
R/W = 0
PIC18F2420/2520/4420/4520
DS39631A-page 179
PIC18F2420/2520/4420/4520
17.4.4
CLOCK STRETCHING
17.4.4.3
17.4.4.1
17.4.4.2
17.4.4.4
In 10-bit Slave Transmit mode, clock stretching is controlled during the first two address sequences by the
state of the UA bit, just as it is in 10-bit Slave Receive
mode. The first two addresses are followed by a third
address sequence which contains the high-order bits
of the 10-bit address and the R/W bit set to 1. After
the third address sequence is performed, the UA bit is
not set, the module is now configured in Transmit
mode and clock stretching is controlled by the BF flag
as in 7-bit Slave Transmit mode (see Figure 17-11).
DS39631A-page 180
Preliminary
PIC18F2420/2520/4420/4520
17.4.4.5
FIGURE 17-12:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA
DX
DX 1
SCL
CKP
Master device
asserts clock
Master device
deasserts clock
WR
SSPCON
Preliminary
DS39631A-page 181
DS39631A-page 182
Preliminary
CKP
SSPOV (SSPCON1<6>)
BF (SSPSTAT<0>)
(PIR1<3>)
SSPIF
SCL
A7
A6
A4
A3
A2
Receiving Address
A5
A1
ACK
R/W = 0
D4
D3
Receiving Data
D5
Cleared in software
D6
If BF is cleared
prior to the falling
edge of the 9th clock,
CKP will not be reset
to 0 and no clock
stretching will occur
SSPBUF is read
D7
D2
D1
ACK
D7
D0
D4
D3
Receiving Data
D5
CKP
written
to 1 in
software
D6
D2
D1
D0
Bus master
terminates
transfer
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
ACK
FIGURE 17-13:
SDA
PIC18F2420/2520/4420/4520
I2C SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)
Preliminary
UA (SSPSTAT<1>)
SSPOV (SSPCON1<6>)
CKP
A9 A8
Cleared in software
BF (SSPSTAT<0>)
(PIR1<3>)
SSPIF
SCL
ACK
R/W = 0
A7
A4
A3
A2
Cleared in software
A5
A1
A0
A6
ACK
Cleared in software
D3 D2
ACK
Cleared in software
CKP written to 1
in software
D3 D2
D1 D0
D7 D6 D5 D4
Bus master
terminates
transfer
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
D1 D0
ACK
FIGURE 17-14:
SDA
PIC18F2420/2520/4420/4520
DS39631A-page 183
PIC18F2420/2520/4420/4520
17.4.5
FIGURE 17-15:
SDA
Receiving Data
ACK
D6
D5
D4
D3
D2
D1
D0
SCL
S
SSPIF
BF (SSPSTAT<0>)
Cleared in software
SSPBUF is read
SSPOV (SSPCON1<6>)
GCEN (SSPCON2<7>)
1
DS39631A-page 184
Preliminary
PIC18F2420/2520/4420/4520
MASTER MODE
Note:
FIGURE 17-16:
Start condition
Stop condition
Data transfer byte transmitted/received
Acknowledge transmit
Repeated Start
SSPM3:SSPM0
SSPADD<6:0>
Write
SSPBUF
Baud
Rate
Generator
Shift
Clock
SDA
SDA In
SCL In
Bus Collision
LSb
Preliminary
Clock Cntl
SCL
Receive Enable
SSPSR
MSb
17.4.6
DS39631A-page 185
PIC18F2420/2520/4420/4520
17.4.6.1
DS39631A-page 186
1.
Preliminary
PIC18F2420/2520/4420/4520
17.4.7
BAUD RATE
FIGURE 17-17:
Once the given operation is complete (i.e., transmission of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCL pin
will remain in its last state.
Table 17-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
SSPM3:SSPM0
Reload
SCL
Control
CLKO
TABLE 17-3:
Note 1:
SSPADD<6:0>
Reload
FOSC/4
FCY
FCY*2
BRG Value
FSCL
(2 Rollovers of BRG)
10 MHz
20 MHz
18h
400 kHz(1)
10 MHz
20 MHz
1Fh
312.5 kHz
10 MHz
20 MHz
63h
100 kHz
4 MHz
8 MHz
09h
400 kHz(1)
4 MHz
8 MHz
0Ch
308 kHz
4 MHz
8 MHz
27h
100 kHz
1 MHz
2 MHz
02h
333 kHz(1)
1 MHz
2 MHz
09h
100 kHz
1 MHz
2 MHz
00h
1 MHz(1)
The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
Preliminary
DS39631A-page 187
PIC18F2420/2520/4420/4520
17.4.7.1
Clock Arbitration
FIGURE 17-18:
SDA
DX
DX 1
SCL
BRG decrements on
Q2 and Q4 cycles
BRG
Value
03h
02h
01h
03h
02h
DS39631A-page 188
Preliminary
PIC18F2420/2520/4420/4520
17.4.8
Note:
FIGURE 17-19:
17.4.8.1
TBRG
SDA
2nd bit
TBRG
SCL
TBRG
S
Preliminary
DS39631A-page 189
PIC18F2420/2520/4420/4520
17.4.9
17.4.9.1
FIGURE 17-20:
SDA = 1,
SCL = 1
TBRG
TBRG
TBRG
1st bit
SDA
RSEN bit set by hardware
on falling edge of ninth clock,
end of Xmit
SCL
TBRG
Sr = Repeated Start
DS39631A-page 190
Preliminary
PIC18F2420/2520/4420/4520
17.4.10
17.4.10.3
17.4.10.1
BF Status Flag
17.4.11
17.4.11.1
BF Status Flag
17.4.11.2
17.4.11.3
17.4.10.2
Preliminary
DS39631A-page 191
DS39631A-page 192
S
Preliminary
R/W
PEN
SEN
BF (SSPSTAT<0>)
SSPIF
SCL
SDA
A6
A5
A4
A3
A2
A1
Cleared in software
SSPBUF written
D7
1
SCL held low
while CPU
responds to SSPIF
ACK = 0
R/W = 0
A7
D5
D4
D3
D2
D1
D0
D6
Cleared in software
ACK
ACKSTAT in
SSPCON2 = 1
FIGURE 17-21:
SEN = 0
PIC18F2420/2520/4420/4520
I 2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
Preliminary
ACKEN
SSPOV
BF
(SSPSTAT<0>)
SDA = 0, SCL = 1
while CPU
responds to SSPIF
SSPIF
SCL
SDA
A7
4
5
Cleared in software
A6 A5 A4 A3 A2
A1
R/W = 0
ACK
D0
ACK
Cleared in software
D7 D6 D5 D4 D3 D2 D1
Cleared in
software
ACK
P
Set SSPIF interrupt
at end of Acknowledge sequence
Bus master
terminates
transfer
Set P bit
(SSPSTAT<4>)
and SSPIF
PEN bit = 1
written here
D0
RCEN cleared
automatically
RCEN = 1, start
next receive
Cleared in software
Cleared in software
D7 D6 D5 D4 D3 D2 D1
RCEN cleared
automatically
FIGURE 17-22:
SEN = 0
Write to SSPBUF occurs here,
start XMIT
Write to SSPCON2<4>
to start Acknowledge sequence
SDA = ACKDT (SSPCON2<5>) = 0
PIC18F2420/2520/4420/4520
DS39631A-page 193
PIC18F2420/2520/4420/4520
17.4.12
ACKNOWLEDGE SEQUENCE
TIMING
17.4.13
17.4.12.1
17.4.13.1
FIGURE 17-23:
TBRG
SDA
ACK
D0
SCL
SSPIF
SSPIF set at
the end of receive
Cleared in
software
SSPIF set at the end
of Acknowledge sequence
Cleared in
software
FIGURE 17-24:
Write to SSPCON2,
set PEN
Falling edge of
9th clock
TBRG
SCL
SDA
ACK
P
TBRG
TBRG
TBRG
DS39631A-page 194
Preliminary
PIC18F2420/2520/4420/4520
17.4.14
SLEEP OPERATION
17.4.17
17.4.15
EFFECTS OF A RESET
17.4.16
MULTI-MASTER MODE
Address Transfer
Data Transfer
A Start Condition
A Repeated Start Condition
An Acknowledge Condition
Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a 1 on SDA, by letting SDA float high and
another master asserts a 0. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a 1 and the data sampled on the SDA pin = 0,
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag, BCLIF and reset the
I2C port to its Idle state (Figure 17-25).
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are deasserted and the
SSPBUF can be written to. When the user services the
bus collision Interrupt Service Routine and if the I2C
bus is free, the user can resume communication by
asserting a Start condition.
If a Start, Repeated Start, Stop or Acknowledge condition was in progress when the bus collision occurred, the
condition is aborted, the SDA and SCL lines are deasserted and the respective control bits in the SSPCON2
register are cleared. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free,
the user can resume communication by asserting a Start
condition.
The master will continue to monitor the SDA and SCL
pins. If a Stop condition occurs, the SSPIF bit will be set.
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus
can be taken when the P bit is set in the SSPSTAT
register, or the bus is Idle and the S and P bits are
cleared.
FIGURE 17-25:
SDA
SCL
BCLIF
Preliminary
DS39631A-page 195
PIC18F2420/2520/4420/4520
17.4.17.1
FIGURE 17-26:
SDA
SCL
Set SEN, enable Start
condition if SDA = 1, SCL = 1
SEN
BCLIF
SSPIF
DS39631A-page 196
Preliminary
PIC18F2420/2520/4420/4520
FIGURE 17-27:
TBRG
SDA
SCL
SEN
SCL = 0 before BRG time-out,
bus collision occurs. Set BCLIF.
BCLIF
Interrupt cleared
in software
S
SSPIF
FIGURE 17-28:
SDA
Set SSPIF
TBRG
SCL
S
SCL pulled low after BRG
time-out
SEN
BCLIF
SSPIF
SDA = 0, SCL = 1,
set SSPIF
Preliminary
Interrupts cleared
in software
DS39631A-page 197
PIC18F2420/2520/4420/4520
17.4.17.2
FIGURE 17-29:
If, at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is
complete.
SDA
SCL
BCLIF
Cleared in software
0
SSPIF
FIGURE 17-30:
TBRG
SDA
SCL
BCLIF
RSEN
0
S
SSPIF
DS39631A-page 198
Preliminary
PIC18F2420/2520/4420/4520
17.4.17.3
b)
FIGURE 17-31:
TBRG
TBRG
SDA sampled
low after TBRG,
set BCLIF
SDA
SDA asserted low
SCL
PEN
BCLIF
P
SSPIF
FIGURE 17-32:
TBRG
TBRG
SDA
SCL goes low before SDA goes high,
set BCLIF
Assert SDA
SCL
PEN
BCLIF
P
SSPIF
Preliminary
DS39631A-page 199
PIC18F2420/2520/4420/4520
NOTES:
DS39631A-page 200
Preliminary
PIC18F2420/2520/4420/4520
18.0
ENHANCED UNIVERSAL
SYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
Preliminary
DS39631A-page 201
PIC18F2420/2520/4420/4520
REGISTER 18-1:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-1
R/W-0
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS39631A-page 202
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
Preliminary
x = Bit is unknown
PIC18F2420/2520/4420/4520
REGISTER 18-2:
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R-0
R-x
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
Preliminary
x = Bit is unknown
DS39631A-page 203
PIC18F2420/2520/4420/4520
REGISTER 18-3:
R-1
U-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
bit 7
bit 0
bit 7
bit 6
bit 5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
Unimplemented: Read as 0
bit 1
bit 0
DS39631A-page 204
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
Preliminary
x = Bit is unknown
PIC18F2420/2520/4420/4520
18.1
TABLE 18-1:
18.1.1
18.1.2
SAMPLING
Configuration Bits
BRG/EUSART Mode
8-bit/Asynchronous
FOSC/[64 (n + 1)]
SYNC
BRG16
BRGH
8-bit/Asynchronous
16-bit/Asynchronous
16-bit/Asynchronous
8-bit/Synchronous
16-bit/Synchronous
FOSC/[16 (n + 1)]
FOSC/[4 (n + 1)]
Preliminary
DS39631A-page 205
PIC18F2420/2520/4420/4520
EXAMPLE 18-1:
For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG:
Desired Baud Rate
= FOSC/(64 ([SPBRGH:SPBRG] + 1))
Solving for SPBRGH:SPBRG:
X
= ((FOSC/Desired Baud Rate)/64) 1
= ((16000000/9600)/64) 1
= [25.042] = 25
Calculated Baud Rate = 16000000/(64 (25 + 1))
= 9615
Error
= (Calculated Baud Rate Desired Baud Rate)/Desired Baud Rate
= (9615 9600)/9600 = 0.16%
TABLE 18-2:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset Values
on page
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
51
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
51
RCIDL
SCKP
BRG16
WUE
ABDEN
51
Name
BAUDCON ABDOVF
SPBRGH
51
SPBRG
51
Legend: = unimplemented, read as 0. Shaded cells are not used by the BRG.
DS39631A-page 206
Preliminary
PIC18F2420/2520/4420/4520
TABLE 18-3:
BAUD
RATE
(K)
Actual
Rate
(K)
%
Error
0.3
1.2
1.221
1.73
255
1.202
0.16
129
1201
-0.16
103
2.4
2.441
1.73
255
2.404
0.16
129
2.404
0.16
64
2403
-0.16
51
9.6
9.615
0.16
64
9.766
1.73
31
9.766
1.73
15
9615
-0.16
12
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
19.2
19.531
1.73
31
19.531
1.73
15
19.531
1.73
57.6
56.818
-1.36
10
62.500
8.51
52.083
-9.58
115.2
125.000
8.51
104.167
-9.58
78.125
-32.18
%
Error
207
300
-0.16
51
1201
-0.16
0.16
25
2403
Actual
Rate
(K)
%
Error
0.3
0.300
0.16
1.2
1.202
0.16
2.4
2.404
SPBRG
value
(decimal)
%
Error
103
300
-0.16
51
25
1201
-0.16
12
-0.16
12
SPBRG
value
(decimal)
SPBRG
value
(decimal)
9.6
8.929
-6.99
19.2
20.833
8.51
57.6
62.500
8.51
115.2
62.500
-45.75
(decimal)
Actual
Rate
(K)
%
Error
9.6
9.766
1.73
19.2
19.231
0.16
Actual
Rate
(K)
%
Error
0.3
1.2
2.4
(decimal)
Actual
Rate
(K)
%
Error
255
9.615
0.16
129
19.231
0.16
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
2.441
1.73
255
2403
-0.16
207
129
9.615
0.16
64
9615
-0.16
51
64
19.531
1.73
31
19230
-0.16
25
SPBRG
value
SPBRG
value
SPBRG
value
(decimal)
57.6
58.140
0.94
42
56.818
-1.36
21
56.818
-1.36
10
55555
3.55
115.2
113.636
-1.36
21
113.636
-1.36
10
125.000
8.51
(decimal)
Actual
Rate
(K)
%
Error
0.16
207
1201
0.16
103
Actual
Rate
(K)
%
Error
0.3
1.2
1.202
2.4
2.404
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
-0.16
103
300
1201
-0.16
-0.16
207
51
2403
-0.16
51
2403
-0.16
25
SPBRG
value
SPBRG
value
(decimal)
9.6
9.615
0.16
25
9615
-0.16
12
19.2
19.231
0.16
12
57.6
62.500
8.51
115.2
125.000
8.51
Preliminary
DS39631A-page 207
PIC18F2420/2520/4420/4520
TABLE 18-3:
BAUD
RATE
(K)
(decimal)
Actual
Rate
(K)
%
Error
0.00
0.02
8332
2082
0.300
1.200
2.402
0.06
1040
Actual
Rate
(K)
%
Error
0.3
1.2
0.300
1.200
2.4
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
0.02
-0.03
4165
1041
0.300
1.200
2.399
-0.03
520
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
0.02
-0.03
2082
520
300
1201
-0.04
-0.16
1665
415
2.404
0.16
259
2403
-0.16
207
SPBRG
value
SPBRG
value
(decimal)
9.6
9.615
0.16
259
9.615
0.16
129
9.615
0.16
64
9615
-0.16
51
19.2
19.231
0.16
129
19.231
0.16
64
19.531
1.73
31
19230
-0.16
25
57.6
58.140
0.94
42
56.818
-1.36
21
56.818
-1.36
10
55555
3.55
115.2
113.636
-1.36
21
113.636
-1.36
10
125.000
8.51
FOSC
= 4.000 MHz
(decimal)
Actual
Rate
(K)
%
Error
832
300
-0.16
0.16
207
1201
0.16
103
2403
Actual
Rate
(K)
%
Error
0.300
0.04
1.2
1.202
2.4
2.404
0.3
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
415
300
-0.16
-0.16
103
1201
-0.16
51
-0.16
51
2403
-0.16
25
SPBRG
value
SPBRG
value
(decimal)
207
9.6
9.615
0.16
25
9615
-0.16
12
19.2
19.231
0.16
12
57.6
62.500
8.51
115.2
125.000
8.51
(decimal)
Actual
Rate
(K)
%
Error
0.00
33332
0.300
0.00
8332
1.200
2.400
0.02
4165
9.606
0.06
1040
19.2
19.193
-0.03
520
57.6
57.803
0.35
172
115.2
114.943
-0.22
86
116.279
Actual
Rate
(K)
%
Error
0.3
0.300
1.2
1.200
2.4
9.6
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
0.00
16665
0.300
0.00
0.02
4165
1.200
0.02
2.400
0.02
2082
2.402
9.596
-0.03
520
19.231
0.16
57.471
-0.22
0.94
%
Error
8332
300
-0.01
6665
2082
1200
-0.04
1665
0.06
1040
2400
-0.04
832
9.615
0.16
259
9615
-0.16
207
259
19.231
0.16
129
19230
-0.16
103
86
58.140
0.94
42
57142
0.79
34
42
113.636
-1.36
21
117647
-2.12
16
SPBRG
value
SPBRG
value
(decimal)
SPBRG
value
(decimal)
%
Error
0.3
0.300
0.01
1.2
1.200
0.04
(decimal)
Actual
Rate
(K)
%
Error
3332
300
-0.04
832
1201
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
1665
300
-0.04
832
-0.16
415
1201
-0.16
207
SPBRG
value
SPBRG
value
(decimal)
2.4
2.404
0.16
415
2403
-0.16
207
2403
-0.16
103
9.6
9.615
0.16
103
9615
-0.16
51
9615
-0.16
25
19.2
19.231
0.16
51
19230
-0.16
25
19230
-0.16
12
57.6
58.824
2.12
16
55555
3.55
115.2
111.111
-3.55
DS39631A-page 208
Preliminary
PIC18F2420/2520/4420/4520
18.1.3
TABLE 18-4:
BRG COUNTER
CLOCK RATES
BRG16
BRGH
FOSC/512
FOSC/128
FOSC/128
FOSC/32
Note:
18.1.3.1
Since the BRG clock is reversed during ABD acquisition, the EUSART transmitter cannot be used during
ABD. This means that whenever the ABDEN bit is set,
TXREG cannot be written to. Users should also ensure
that ABDEN does not become set during a transmit
sequence. Failing to do this may result in unpredictable
EUSART operation.
While calibrating the baud rate period, the BRG registers are clocked at 1/8th the preconfigured clock rate.
Note that the BRG clock will be configured by the
BRG16 and BRGH bits. Independent of the BRG16 bit
setting, both the SPBRG and SPBRGH will be used as
a 16-bit counter. This allows the user to verify that no
carry occurred for 8-bit modes by checking for 00h in
the SPBRGH register. Refer to Table 18-4 for counter
clock rates to the BRG.
While the ABD sequence takes place, the EUSART
state machine is held in Idle. The RCIF interrupt is set
once the fifth rising edge on RX is detected. The value
in the RCREG needs to be read to clear the RCIF
interrupt. The contents of RCREG should be discarded.
Preliminary
DS39631A-page 209
PIC18F2420/2520/4420/4520
FIGURE 18-1:
BRG Value
RX pin
0000h
001Ch
Start
Edge #1
Bit 1
Bit 0
Edge #2
Bit 3
Bit 2
Edge #3
Bit 5
Bit 4
Edge #4
Bit 7
Bit 6
Edge #5
Stop Bit
BRG Clock
Auto-Cleared
Set by User
ABDEN bit
RCIF bit
(Interrupt)
Read
RCREG
SPBRG
XXXXh
1Ch
SPBRGH
XXXXh
00h
Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.
FIGURE 18-2:
BRG Clock
ABDEN bit
RX pin
Start
Bit 0
ABDOVF bit
FFFFh
BRG Value
DS39631A-page 210
XXXXh
0000h
0000h
Preliminary
PIC18F2420/2520/4420/4520
18.2
18.2.1
2.
EUSART ASYNCHRONOUS
TRANSMITTER
3.
4.
FIGURE 18-3:
5.
6.
7.
8.
TXREG Register
TXIE
8
MSb
(8)
LSb
Pin Buffer
and Control
TSR Register
TX pin
Interrupt
TXEN
BRG16
SPBRGH
SPBRG
SPEN
TX9
TX9D
Preliminary
DS39631A-page 211
PIC18F2420/2520/4420/4520
FIGURE 18-4:
ASYNCHRONOUS TRANSMISSION
Write to TXREG
Word 1
BRG Output
(Shift Clock)
TX (pin)
Start bit
bit 0
bit 1
bit 7/8
Stop bit
Word 1
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
1 TCY
Word 1
Transmit Shift Reg
TRMT bit
(Transmit Shift
Reg. Empty Flag)
FIGURE 18-5:
Write to TXREG
Word 2
Word 1
BRG Output
(Shift Clock)
TX (pin)
Start bit
bit 0
bit 1
1 TCY
TXIF bit
(Interrupt Reg. Flag)
bit 7/8
Stop bit
Start bit
bit 0
Word 2
Word 1
1 TCY
Word 1
Transmit Shift Reg.
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 2
Transmit Shift Reg.
TABLE 18-5:
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
49
INTCON
GIE/GIEH PEIE/GIEL
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
52
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
52
IPR1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
52
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
51
RCSTA
TXREG
TXSTA
51
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
51
BAUDCON
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
51
SPBRGH
51
SPBRG
51
Legend: = unimplemented locations read as 0. Shaded cells are not used for asynchronous transmission.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.
DS39631A-page 212
Preliminary
PIC18F2420/2520/4420/4520
18.2.2
EUSART ASYNCHRONOUS
RECEIVER
18.2.3
FIGURE 18-6:
OERR
FERR
SPBRGH
SPBRG
64
or
16
or
4
RSR Register
MSb
Stop
(8)
LSb
0
Start
RX9
Pin Buffer
and Control
Data
Recovery
RX
RX9D
RCREG Register
FIFO
SPEN
8
Interrupt
RCIF
Data Bus
RCIE
Preliminary
DS39631A-page 213
PIC18F2420/2520/4420/4520
FIGURE 18-7:
ASYNCHRONOUS RECEPTION
Start
bit
RX (pin)
bit 0
bit 1
Start
bit
bit 0
bit 7/8
Start
bit
bit 7/8
Stop
bit
Word 2
RCREG
Word 1
RCREG
Read Rcv
Buffer Reg
RCREG
Stop
bit
RCIF
(Interrupt Flag)
OERR bit
CREN
Note:
TABLE 18-6:
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
INTCON
GIE/GIEH PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
49
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
52
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
52
IPR1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
52
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
RCSTA
RCREG
TXSTA
BAUDCON
51
51
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
51
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
51
SPBRGH
51
SPBRG
51
Legend: = unimplemented locations read as 0. Shaded cells are not used for asynchronous reception.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.
18.2.4
DS39631A-page 214
Preliminary
PIC18F2420/2520/4420/4520
18.2.4.1
18.2.4.2
The fact that the WUE bit has been cleared (or is still
set) and the RCIF flag is set should not be used as an
indicator of the integrity of the data in RCREG. Users
should consider implementing a parallel method in
firmware to verify received data integrity.
To assure that no actual data is lost, check the RCIDL
bit to verify that a receive operation is not in process. If
a receive operation is not occurring, the WUE bit may
then be set just prior to entering the Sleep mode.
FIGURE 18-8:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Bit set by user
Auto-Cleared
WUE bit(1)
RX/DT Line
RCIF
Note 1:
FIGURE 18-9:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Bit set by user
Auto-Cleared
WUE bit(2)
RX/DT Line
Note 1
RCIF
Sleep Ends
If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur before the oscillator is ready. This
sequence should not depend on the presence of Q clocks.
The EUSART remains in Idle while the WUE bit is set.
Preliminary
DS39631A-page 215
PIC18F2420/2520/4420/4520
18.2.5
18.2.5.1
FIGURE 18-10:
Write to TXREG
1.
2.
3.
4.
5.
18.2.6
BRG Output
(Shift Clock)
TX (pin)
Start Bit
Bit 0
Bit 1
Bit 11
Stop Bit
Break
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
SENDB sampled here
Auto-Cleared
SENDB
(Transmit Shift
Reg. Empty Flag)
DS39631A-page 216
Preliminary
PIC18F2420/2520/4420/4520
18.3
EUSART Synchronous
Master Mode
The Master mode indicates that the processor transmits the master clock on the CK line. Clock polarity is
selected with the SCKP bit (BAUDCON<4>); setting
SCKP sets the Idle state on CK as high, while clearing
the bit sets the Idle state as low. This option is provided
to support Microwire devices with this module.
18.3.1
2.
FIGURE 18-11:
3.
4.
5.
6.
7.
8.
SYNCHRONOUS TRANSMISSION
Q1 Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT
bit 0
bit 1
bit 2
bit 7
bit 0
bit 1
bit 7
Word 2
Word 1
RC6/TX/CK pin
(SCKP = 0)
RC6/TX/CK pin
(SCKP = 1)
Write to
TXREG Reg
Write Word 1
Write Word 2
TXIF bit
(Interrupt Flag)
TRMT bit
TXEN bit
Note:
Preliminary
DS39631A-page 217
PIC18F2420/2520/4420/4520
FIGURE 18-12:
RC7/RX/DT pin
bit 0
bit 1
bit 2
bit 6
bit 7
RC6/TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
TABLE 18-7:
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
INTCON
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
49
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
52
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
52
IPR1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
52
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
51
RCSTA
TXREG
51
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
51
BAUDCON
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
51
SPBRGH
51
SPBRG
51
TXSTA
Legend: = unimplemented, read as 0. Shaded cells are not used for synchronous master transmission.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.
DS39631A-page 218
Preliminary
PIC18F2420/2520/4420/4520
18.3.2
EUSART SYNCHRONOUS
MASTER RECEPTION
3.
4.
5.
6.
2.
FIGURE 18-13:
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT
pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
RC6/TX/CK pin
(SCKP = 0)
RC6/TX/CK pin
(SCKP = 1)
Write to
bit SREN
SREN bit
CREN bit 0
RCIF bit
(Interrupt)
Read
RXREG
Note:
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TABLE 18-8:
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
INTCON
GIE/GIEH PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
49
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
52
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
52
IPR1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
52
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
RCSTA
RCREG
TXSTA
BAUDCON ABDOVF
51
51
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
51
RCIDL
SCKP
BRG16
WUE
ABDEN
51
SPBRGH
51
SPBRG
51
Legend: = unimplemented, read as 0. Shaded cells are not used for synchronous master reception.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.
Preliminary
DS39631A-page 219
PIC18F2420/2520/4420/4520
18.4
EUSART Synchronous
Slave Mode
18.4.1
EUSART SYNCHRONOUS
SLAVE TRANSMISSION
2.
3.
4.
5.
6.
7.
8.
e)
TABLE 18-9:
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
INTCON
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
49
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
52
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
52
IPR1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
52
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
51
RCSTA
TXREG
51
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
51
BAUDCON
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
51
SPBRGH
51
SPBRG
51
TXSTA
Legend: = unimplemented, read as 0. Shaded cells are not used for synchronous slave transmission.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.
DS39631A-page 220
Preliminary
PIC18F2420/2520/4420/4520
18.4.2
2.
3.
4.
5.
6.
7.
8.
9.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
49
INTCON
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
52
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
52
IPR1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
52
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
51
RCSTA
RCREG
TXSTA
BAUDCON
51
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
51
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
51
SPBRGH
51
SPBRG
51
Legend: = unimplemented, read as 0. Shaded cells are not used for synchronous slave reception.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.
Preliminary
DS39631A-page 221
PIC18F2420/2520/4420/4520
NOTES:
DS39631A-page 222
Preliminary
PIC18F2420/2520/4420/4520
19.0
10-BIT ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
REGISTER 19-1:
ADCON0 REGISTER
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
bit 7
bit 0
bit 7-6
Unimplemented: Read as 0
bit 5-2
bit 1
bit 0
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
Preliminary
x = Bit is unknown
DS39631A-page 223
PIC18F2420/2520/4420/4520
REGISTER 19-2:
ADCON1 REGISTER
U-0
U-0
R/W-0
R/W-0
R/W-0(1)
R/W(1)
R/W(1)
R/W(1)
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
PCFG3:
PCFG0
AN7(2)
AN6(2)
AN5(2)
AN4
AN3
AN2
AN1
AN0
bit 3-0
AN9
AN10
bit 4
AN11
Unimplemented: Read as 0
VCFG1: Voltage Reference Configuration bit (VREF- source)
1 = VREF- (AN2)
0 = VSS
AN12
bit 7-6
bit 5
0000(1)
0001
0010
0011
0100
0101
0110
A
A
A
D
D
D
D
D
A
A
A
A
D
D
D
D
A
A
A
A
A
D
D
D
A
A
A
A
A
A
D
D
A
A
A
A
A
A
A
D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
A
D
D
D
D
D
D
D
A
A
D
D
D
D
D
D
A
A
A
D
D
D
D
D
A
A
A
A
D
D
D
D
A
A
A
A
A
D
D
D
A
A
A
A
A
A
D
D
A
A
A
A
A
A
A
D
0111(1)
1000
1001
1010
1011
1100
1101
1110
1111
A = Analog input
D = Digital I/O
Note 1: The POR value of the PCFG bits depends on the value of the PBADEN configuration bit. When PBADEN = 1, PCFG<3:0> = 0000; when PBADEN = 0,
PCFG<3:0> = 0111.
2: AN5 through AN7 are available only on 40/44-pin devices.
Legend:
DS39631A-page 224
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
Preliminary
x = Bit is unknown
PIC18F2420/2520/4420/4520
REGISTER 19-3:
ADCON2 REGISTER
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADFM
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
bit 7
bit 0
bit 7
bit 6
Unimplemented: Read as 0
bit 5-3
bit 2-0
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
Preliminary
x = Bit is unknown
DS39631A-page 225
PIC18F2420/2520/4420/4520
The analog reference voltage is software selectable to
either the devices positive and negative supply voltage
(VDD and VSS), or the voltage level on the RA3/AN3/
VREF+ and RA2/AN2/VREF-/CVREF pins.
FIGURE 19-1:
Reference
Voltage
VREF+
X0
X1
1X
VREF-
0X
AN8
AN6(1)
0101
AN5(1)
0010
0001
0000
VDD
AN9
0110
0011
VCFG1:VCFG0
AN10
AN7(1)
0100
(Input Voltage)
AN11
0111
VAIN
10-Bit
Converter
A/D
AN12
AN4
AN3
AN2
AN1
AN0
VSS
Note 1:
2:
DS39631A-page 226
Preliminary
PIC18F2420/2520/4420/4520
Wait for A/D conversion to complete, by either:
Polling for the GO/DONE bit to be cleared
OR
Waiting for the A/D interrupt
Read A/D Result registers (ADRESH:ADRESL);
clear bit ADIF, if required.
For next conversion, go to step 1 or step 2, as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2 TAD is
required before the next acquisition starts.
6.
7.
FIGURE 19-2:
3FFh
1.
3FEh
FIGURE 19-3:
002h
001h
1023 LSB
1023.5 LSB
1022 LSB
1022.5 LSB
3 LSB
Sampling
Switch
VT = 0.6V
Rs
VAIN
2 LSB
000h
2.5 LSB
3.
4.
003h
0.5 LSB
2.
1 LSB
5.
1.5 LSB
ANx
RIC 1k
CPIN
5 pF
VT = 0.6V
SS
RSS
ILEAKAGE
100 nA
CHOLD = 25 pF
VSS
Legend: CPIN
= input capacitance
VT
= threshold voltage
ILEAKAGE = leakage current at the pin due to
various junctions
= interconnect resistance
RIC
= sampling switch
SS
= sample/hold capacitance (from DAC)
CHOLD
RSS
= sampling switch resistance
Preliminary
VDD
6V
5V
4V
3V
2V
1
DS39631A-page 227
PIC18F2420/2520/4420/4520
19.1
CHOLD
Rs
Conversion Error
VDD
Temperature
=
=
=
=
25 pF
2.5 k
1/2 LSb
5V Rss = 2 k
85C (system max.)
ACQUISITION TIME
TAMP + TC + TCOFF
EQUATION 19-2:
VHOLD
or
TC
EQUATION 19-1:
TACQ
EQUATION 19-3:
TACQ
TAMP + TC + TCOFF
TAMP
0.2 s
TCOFF
Temperature coefficient is only required for temperatures > 25C. Below 25C, TCOFF = 0 ms.
TC
TACQ
0.2 s + 1 s + 1.2 s
2.4 s
DS39631A-page 228
Preliminary
PIC18F2420/2520/4420/4520
19.2
19.3
Manual
acquisition
is
selected
when
ACQT2:ACQT0 = 000. When the GO/DONE bit is set,
sampling is stopped and a conversion begins. The user
is responsible for ensuring the required acquisition time
has passed between selecting the desired input
channel and setting the GO/DONE bit. This option is
also the default Reset state of the ACQT2:ACQT0 bits
and is compatible with devices that do not offer
programmable acquisition times.
2 TOSC
4 TOSC
8 TOSC
16 TOSC
32 TOSC
64 TOSC
Internal RC Oscillator
TABLE 19-1:
Operation
ADCS2:ADCS0
PIC18F2X20/4X20
4:
PIC18LF2X20/4X20(4)
2 TOSC
000
2.86 MHz
1.43 kHz
4 TOSC
100
5.71 MHz
2.86 MHz
8 TOSC
001
11.43 MHz
5.72 MHz
16 TOSC
101
22.86 MHz
11.43 MHz
32 TOSC
010
40.0 MHz
22.86 MHz
64 TOSC
110
40.0 MHz
22.86 MHz
RC(3)
Note 1:
2:
3:
1.00
x11
MHz(1)
1.00 MHz(2)
Preliminary
DS39631A-page 229
PIC18F2420/2520/4420/4520
19.4
19.5
DS39631A-page 230
Preliminary
2: Analog levels on any pin defined as a digital input may cause the digital input buffer
to consume current out of the devices
specification limits.
3: The PBADEN bit in Configuration
Register 3H configures PORTB pins to
reset as analog or digital pins by controlling how the PCFG0 bits in ADCON1 are
reset.
PIC18F2420/2520/4420/4520
19.6
A/D Conversions
Note:
19.7
Discharge
FIGURE 19-4:
TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 TAD1
b4
b1
b0
b6
b7
b2
b9
b8
b3
b5
Conversion starts
Discharge
FIGURE 19-5:
TAD Cycles
TACQT Cycles
1
Automatic
Acquisition
Time
10
11
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Conversion starts
(Holding capacitor is disconnected)
Set GO bit
(Holding capacitor continues
acquiring input)
TAD1
Discharge
Preliminary
DS39631A-page 231
PIC18F2420/2520/4420/4520
19.8
TABLE 19-2:
Name
desired location). The appropriate analog input channel must be selected and the minimum acquisition
period is either timed by the user, or an appropriate
TACQ time selected before the Special Event Trigger
sets the GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared), the
Special Event Trigger will be ignored by the A/D
module, but will still reset the Timer1 (or Timer3)
counter.
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
49
INTCON
GIE/GIEH PEIE/GIEL
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
52
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
52
IPR1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
52
PIR2
OSCFIF
CMIF
EEIF
BCLIF
HLVDIF
TMR3IF
CCP2IF
52
PIE2
OSCFIE
CMIE
EEIE
BCLIE
HLVDIE
TMR3IE
CCP2IE
52
IPR2
OSCFIP
CMIP
EEIP
BCLIP
HLVDIP
TMR3IP
CCP2IP
52
ADRESH
ADRESL
ADCON0
51
51
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
51
ADCON1
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
51
ADCON2
ADFM
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
51
PORTA
RA7(1)
RA6(1)
RA5
RA4
RA3
RA2
RA1
RA0
52
TRISA
PORTB
RB6
RB5
RB4
RB3
TRISB
LATB
RB2
52
RB1
RB0
52
52
PORTE(4)
RE3(3)
TRISE(4)
IBF
OBF
IBOV
PSPMODE
LATE(4)
52
RE2
RE1
RE0
TRISE2
TRISE1
TRISE0
52
52
52
Legend: = unimplemented, read as 0. Shaded cells are not used for A/D conversion.
Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear.
2: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary
oscillator modes. When disabled, these bits read as 0.
3: RE3 port bit is available only as an input pin when the MCLRE configuration bit is 0.
4: These registers are not implemented on 28-pin devices.
DS39631A-page 232
Preliminary
PIC18F2420/2520/4420/4520
20.0
COMPARATOR MODULE
REGISTER 20-1:
CMCON REGISTER
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-1
R/W-1
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
Preliminary
x = Bit is unknown
DS39631A-page 233
PIC18F2420/2520/4420/4520
20.1
Comparator Configuration
There are eight modes of operation for the comparators, shown in Figure 20-1. Bits CM2:CM0 of the
CMCON register are used to select these modes. The
TRISA register controls the data direction of the comparator pins for each mode. If the Comparator mode is
FIGURE 20-1:
VIN-
RA3/AN3/ A
VREF+
VIN+
VIN-
RA2/AN2/ A
VREF-/CVREF
VIN+
C1
Off (Read as 0)
C2
Off (Read as 0)
VIN-
RA3/AN3/ A
VREF+
VIN+
VIN-
RA2/AN2/ A
VREF-/CVREF
VIN+
RA0/AN0
RA1/AN1
Note:
Comparators Reset
CM2:CM0 = 000
RA0/AN0
C1
RA0/AN0
VIN-
RA3/AN3/
VREF+
VIN+
RA1/AN1
VIN-
D
RA2/AN2/
VREF-/CVREF
VIN+
C1
Off (Read as 0)
C2
Off (Read as 0)
C1OUT
VIN-
VIN+
C1
C1OUT
C2
C2OUT
RA4/T0CKI/C1OUT*
RA1/AN1
C2
VIN-
RA2/AN2/ A
VREF-/CVREF
VIN+
RA1/AN1
C2OUT
RA5/AN4/SS/HLVDIN/C2OUT*
Two Common Reference Comparators
CM2:CM0 = 100
A
VIN-
RA3/AN3/ A
VREF+
VIN+
VIN-
RA2/AN2/ D
VREF-/CVREF
VIN+
RA0/AN0
C1
C1OUT
VIN-
VIN+
C1
C1OUT
C2
C2OUT
RA4/T0CKI/C1OUT*
RA1/AN1
C2
VIN-
RA2/AN2/
D
VREF-/CVREF
VIN+
RA1/AN1
C2OUT
RA5/AN4/SS/HLVDIN/C2OUT*
Four Inputs Multiplexed to Two Comparators
CM2:CM0 = 110
VIN-
RA3/AN3/ A
VREF+
VIN+
RA0/AN0
C1
C1OUT
RA4/T0CKI/C1OUT*
D
VIN-
RA2/AN2/ D
VREF-/CVREF
VIN+
RA1/AN1
RA0/AN0
RA3/AN3/
VREF+
RA1/AN1
VINVIN+
A
RA2/AN2/
VREF-/CVREF
C2
CIS = 0
CIS = 1
CIS = 0
CIS = 1
C1
C1OUT
C2
C2OUT
VINVIN+
Off (Read as 0)
CVREF
DS39631A-page 234
Preliminary
PIC18F2420/2520/4420/4520
20.2
20.3.2
Comparator Operation
20.3
Comparator Reference
FIGURE 20-2:
SINGLE COMPARATOR
VIN+
VIN-
20.4
Comparator Outputs
VINVIN+
Output
20.3.1
20.5
Output
Preliminary
DS39631A-page 235
PIC18F2420/2520/4420/4520
To RA4 or
RA5 pin
Port pins
MULTIPLEX
FIGURE 20-3:
Bus
Data
CxINV
EN
Read CMCON
EN
CL
From
other
Comparator
Reset
20.6
Comparator Interrupts
20.7
Set
CMIF
bit
Comparator Operation
During Sleep
20.8
Effects of a Reset
DS39631A-page 236
Preliminary
PIC18F2420/2520/4420/4520
20.9
FIGURE 20-4:
RS < 10k
RIC
Comparator
Input
AIN
CPIN
5 pF
VA
VT = 0.6V
ILEAKAGE
500 nA
VSS
Legend:
TABLE 20-1:
Name
CMCON
CVRCON
INTCON
CPIN
VT
ILEAKAGE
RIC
RS
VA
=
=
=
=
=
=
Input Capacitance
Threshold Voltage
Leakage Current at the pin due to various junctions
Interconnect Resistance
Source Impedance
Analog Voltage
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
51
CVREN
CVROE
CVRR
CVRSS
CVR3
CVR2
CVR1
CVR0
51
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
52
GIE/GIEH PEIE/GIEL
PIR2
OSCFIF
CMIF
EEIF
BCLIF
HLVDIF
TMR3IF
CCP2IF
52
PIE2
OSCFIE
CMIE
EEIE
BCLIE
HLVDIE
TMR3IE
CCP2IE
52
IPR2
OSCFIP
CMIP
EEIP
BCLIP
HLVDIP
TMR3IP
CCP2IP
52
RA7(1)
RA6(1)
RA5
RA4
RA3
RA2
RA1
RA0
52
PORTA
(1)
LATA
LATA7
TRISA
TRISA7(1)
LATA6(1)
52
52
Legend: = unimplemented, read as 0. Shaded cells are unused by the comparator module.
Note 1: PORTA<7:6> and their direction and latch bits are individually configured as port pins based on various
primary oscillator modes. When disabled, these bits read as 0.
Preliminary
DS39631A-page 237
PIC18F2420/2520/4420/4520
NOTES:
DS39631A-page 238
Preliminary
PIC18F2420/2520/4420/4520
21.0
COMPARATOR VOLTAGE
REFERENCE MODULE
21.1
REGISTER 21-1:
is selected by the CVRR bit (CVRCON<5>). The primary difference between the ranges is the size of the
steps selected by the CVREF Selection bits
(CVR3:CVR0), with one range offering finer resolution.
The equations used to calculate the output of the
comparator voltage reference are as follows:
If CVRR = 1:
CVREF = ((CVR3:CVR0)/24) x CVRSRC
If CVRR = 0:
CVREF = (CVRSRC x 1/4) + (((CVR3:CVR0)/32) x
CVRSRC)
The comparator reference supply voltage can come
from either VDD and VSS, or the external VREF+ and
VREF- that are multiplexed with RA2 and RA3. The
voltage source is selected by the CVRSS bit
(CVRCON<4>).
The settling time of the comparator voltage reference
must be considered when changing the CVREF output (see Table 26-3 in Section 26.0 Electrical
Characteristics).
CVRCON REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CVREN
CVROE(1)
CVRR
CVRSS
CVR3
CVR2
CVR1
CVR0
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3-0
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
Preliminary
x = Bit is unknown
DS39631A-page 239
PIC18F2420/2520/4420/4520
FIGURE 21-1:
CVRSS = 1
8R
CVRSS = 0
CVR3:CVR0
CVREN
16-to-1 MUX
R
R
16 Steps
CVREF
R
R
R
CVRR
VREF-
8R
CVRSS = 1
CVRSS = 0
21.2
21.3
21.4
Effects of a Reset
21.5
Connection Considerations
DS39631A-page 240
Preliminary
PIC18F2420/2520/4420/4520
FIGURE 21-2:
R(1)
Voltage
Reference
Output
Impedance
Note 1:
TABLE 21-1:
Name
CVRCON
CMCON
TRISA
RA2
CVREF Output
R is dependent upon the voltage reference configuration bits, CVRCON<3:0> and CVRCON<5>.
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
CVREN
CVROE
CVRR
CVRSS
CVR3
CVR2
CVR1
CVR0
51
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
51
52
Legend: Shaded cells are not used with the comparator voltage reference.
Note 1: PORTA pins are enabled based on oscillator configuration.
Preliminary
DS39631A-page 241
PIC18F2420/2520/4420/4520
NOTES:
DS39631A-page 242
Preliminary
PIC18F2420/2520/4420/4520
22.0
HIGH/LOW-VOLTAGE
DETECT (HLVD)
PIC18F2420/2520/4420/4520
devices
have
a
High/Low-Voltage Detect module (HLVD). This is a programmable circuit that allows the user to specify both a
device voltage trip point and the direction of change from
that point. If the device experiences an excursion past
the trip point in that direction, an interrupt flag is set. If the
interrupt is enabled, the program execution will branch to
the interrupt vector address and the software can then
respond to the interrupt.
REGISTER 22-1:
U-0
R-0
IRVST
R/W-0
R/W-0
R/W-1
R/W-0
R/W-1
HLVDEN
HLVDL3(1)
HLVDL2(1)
HLVDL1(1)
HLVDL0(1)
bit 7
bit 0
bit 7
bit 6
Unimplemented: Read as 0
bit 5
bit 4
bit 3-0
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
DS39631A-page 243
PIC18F2420/2520/4420/4520
The module is enabled by setting the HLVDEN bit.
Each time that the HLVD module is enabled, the circuitry requires some time to stabilize. The IRVST bit is
a read-only bit and is used to indicate when the circuit
is stable. The module can only generate an interrupt
after the circuit is stable and IRVST is set.
22.1
Operation
FIGURE 22-1:
Externally Generated
Trip Point
VDD
VDD
HLVDCON
Register
HLVDEN
HLVDIN
16 to 1 MUX
HLVDIN
HLVDL3:HLVDL0
VDIRMAG
Set
HLVDIF
HLVDEN
BOREN
DS39631A-page 244
Internal Voltage
Reference
PIC18F2420/2520/4420/4520
22.2
HLVD Setup
22.3
22.4
Current Consumption
FIGURE 22-2:
CASE 1:
Enable HLVD
TIVRST
IRVST
CASE 2:
VDD
VLVD
HLVDIF
Enable HLVD
TIVRST
IRVST
Internal Reference is stable
DS39631A-page 245
PIC18F2420/2520/4420/4520
FIGURE 22-3:
CASE 1:
Enable HLVD
TIVRST
IRVST
HLVDIF
Enable HLVD
TIVRST
IRVST
Internal Reference is stable
Applications
DS39631A-page 246
FIGURE 22-4:
TYPICAL LOW-VOLTAGE
DETECT APPLICATION
VA
VB
Voltage
22.5
Time
TA
TB
PIC18F2420/2520/4420/4520
22.6
22.7
TABLE 22-1:
Effects of a Reset
Name
Bit 7
Bit 6
HLVDCON
VDIRMAG
INTCON
GIE/GIEH PEIE/GIEL
Reset
Values
on Page
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IRVST
HLVDEN
HLVDL3
HLVDL2
HLVDL1
HLVDL0
50
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
49
PIR2
OSCFIF
CMIF
EEIF
BCLIF
HLVDIF
TMR3IF
CCP2IF
52
PIE2
OCSFIE
CMIE
EEIE
BCLIE
HLVDIE
TMR3IE
CCP2IE
52
IPR2
OSCFIP
CMIP
EEIP
BCLIP
HLVDIP
TMR3IP
CCP2IP
52
Legend: = unimplemented, read as 0. Shaded cells are unused by the HLVD module.
DS39631A-page 247
PIC18F2420/2520/4420/4520
NOTES:
DS39631A-page 248
PIC18F2420/2520/4420/4520
23.0
SPECIAL FEATURES OF
THE CPU
23.1
Configuration Bits
TABLE 23-1:
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FOSC1
FOSC0
Default/
Unprogrammed
Value
300001h
CONFIG1H
IESO
FCMEN
FOSC3
FOSC2
300002h
CONFIG2L
BORV1
BORV0
BOREN1
300003h
CONFIG2H
WDTPS3
WDTPS2
WDTPS1 WDTPS0
WDTEN
---1 1111
LPT1OSC PBADEN
BOREN0 PWRTEN
00-- 0111
---1 1111
300005h
CONFIG3H MCLRE
CCP2MX
1--- -011
300006h
CONFIG4L
DEBUG
XINST
LVP
STVREN
10-- -1-1
300008h
CONFIG5L
CP3(1)
CP2(1)
CP1
CP0
---- 1111
300009h
CONFIG5H
CPD
CPB
11-- ----
30000Ah
CONFIG6L
WRT3(1)
WRT2(1)
WRT1
WRT0
---- 1111
30000Bh
CONFIG6H
WRTD
WRTB
WRTC
111- ----
30000Ch
CONFIG7L
EBTR3(1)
EBTR2(1)
EBTR1
EBTR0
---- 1111
30000Dh
CONFIG7H
-1-- ----
EBTRB
3FFFFEh DEVID1(1)
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
xxxx xxxx(2)
3FFFFFh
DEVID2(1)
DEV10
DEV9
DEV8
DEV7
DEV6
DEV5
DEV4
DEV3
0000 1100
Legend:
Note 1:
2:
Preliminary
DS39631A-page 249
PIC18F2420/2520/4420/4520
REGISTER 23-1:
R/P-0
U-0
U-0
R/P-0
R/P-1
R/P-1
R/P-1
IESO
FCMEN
FOSC3
FOSC2
FOSC1
FOSC0
bit 7
bit 0
bit 7
bit 6
bit 5-4
Unimplemented: Read as 0
bit 3-0
P = Programmable bit
DS39631A-page 250
Preliminary
PIC18F2420/2520/4420/4520
REGISTER 23-2:
U-0
U-0
R/P-1
BORV1
(1)
R/P-1
BORV0
(1)
R/P-1
R/P-1
(2)
BOREN1
R/P-1
(2)
BOREN0
PWRTEN(2)
bit 7
bit 0
bit 7-5
Unimplemented: Read as 0
bit 4-3
bit 2-1
bit 0
P = Programmable bit
Preliminary
DS39631A-page 251
PIC18F2420/2520/4420/4520
REGISTER 23-3:
U-0
U-0
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
WDTPS3
WDTPS2
WDTPS1
WDTPS0
WDTEN
bit 7
bit 0
bit 7-5
Unimplemented: Read as 0
bit 4-1
bit 0
DS39631A-page 252
Preliminary
PIC18F2420/2520/4420/4520
REGISTER 23-4:
U-0
U-0
U-0
U-0
R/P-0
R/P-1
R/P-1
MCLRE
LPT1OSC
PBADEN
CCP2MX
bit 7
bit 0
bit 7
bit 6-3
Unimplemented: Read as 0
bit 2
bit 1
bit 0
P = Programmable bit
REGISTER 23-5:
R/P-0
U-0
U-0
U-0
R/P-1
U-0
R/P-1
DEBUG
XINST
LVP
STVREN
bit 7
bit 0
bit 7
bit 6
bit 5-3
Unimplemented: Read as 0
bit 2
bit 1
Unimplemented: Read as 0
bit 0
C = Clearable bit
Preliminary
DS39631A-page 253
PIC18F2420/2520/4420/4520
REGISTER 23-6:
U-0
U-0
U-0
R/C-1
R/C-1
R/C-1
R/C-1
CP3(1,2)
CP2(1)
CP1
CP0
bit 7
bit 0
bit 7-4
Unimplemented: Read as 0
bit 3
bit 2
bit 1
bit 0
C = Clearable bit
REGISTER 23-7:
R/C-1
U-0
U-0
U-0
U-0
U-0
U-0
CPD
CPB
bit 7
bit 0
bit 7
bit 6
bit 5-0
Unimplemented: Read as 0
Legend:
R = Readable bit
C = Clearable bit
DS39631A-page 254
Preliminary
PIC18F2420/2520/4420/4520
REGISTER 23-8:
U-0
U-0
U-0
R/C-1
R/C-1
R/C-1
R/C-1
WRT3(1,2)
WRT2(1)
WRT1
WRT0
bit 7
bit 0
bit 7-4
Unimplemented: Read as 0
bit 3
bit 2
bit 1
bit 0
C = Clearable bit
REGISTER 23-9:
R/C-1
WRTB
R-1
(1)
WRTC
U-0
U-0
U-0
U-0
U-0
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4-0
Unimplemented: Read as 0
Legend:
R = Readable bit
C = Clearable bit
Preliminary
DS39631A-page 255
PIC18F2420/2520/4420/4520
REGISTER 23-10: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch)
U-0
U-0
U-0
U-0
R/C-1
R/C-1
EBTR3(1,2) EBTR2(1)
R/C-1
R/C-1
EBTR1
EBTR0
bit 7
bit 0
bit 7-4
Unimplemented: Read as 0
bit 3
bit 2
bit 1
bit 0
C = Clearable bit
R/C-1
U-0
U-0
U-0
U-0
U-0
U-0
EBTRB
bit 7
bit 0
bit 7
Unimplemented: Read as 0
bit 6
bit 5-0
Unimplemented: Read as 0
Legend:
R = Readable bit
C = Clearable bit
DS39631A-page 256
Preliminary
PIC18F2420/2520/4420/4520
REGISTER 23-12: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F2420/2520/4420/4520
R
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
bit 7
bit 0
bit 7-5
bit 4-0
P = Programmable bit
DEV10
DEV9
DEV8
DEV7
DEV6
DEV5
DEV4
DEV3
bit 7
bit 7-0
bit 0
These values for DEV10:DEV3 may be shared with other devices. The specific
device is always identified by using the entire DEV10:DEV0 bit sequence.
Legend:
R = Read-only bit
P = Programmable bit
Preliminary
DS39631A-page 257
PIC18F2420/2520/4420/4520
23.2
FIGURE 23-1:
SWDTEN
WDTEN
23.2.1
CONTROL REGISTER
INTRC Source
128
Wake-up
from Power
Managed Modes
CLRWDT
Reset
WDT
Reset
Sleep
DS39631A-page 258
Preliminary
PIC18F2420/2520/4420/4520
REGISTER 23-14: WDTCON REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
SWDTEN(1)
bit 7
bit 0
bit 7-1
Unimplemented: Read as 0
bit 0
TABLE 23-2:
Name
RCON
WDTCON
R = Readable bit
W = Writable bit
-n = Value at POR
Reset
Values
on page
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
IPEN
SBOREN
RI
TO
PD
POR
BOR
48
SWDTEN
50
Legend: = unimplemented, read as 0. Shaded cells are not used by the Watchdog Timer.
Preliminary
DS39631A-page 259
PIC18F2420/2520/4420/4520
23.3
Two-Speed Start-up
In all other power managed modes, Two-Speed Startup is not used. The device will be clocked by the
currently selected clock source until the primary clock
source becomes available. The setting of the IESO bit
is ignored.
23.3.1
While using the INTOSC oscillator in Two-Speed Startup, the device still obeys the normal command
sequences for entering power managed modes,
including multiple SLEEP instructions (refer to
Section 3.1.4 Multiple Sleep Commands). In
practice, this means that user code can change the
SCS1:SCS0 bit settings or issue SLEEP instructions
before the OST times out. This would allow an
application to briefly wake-up, perform routine
housekeeping tasks and return to Sleep before the
device starts to operate from the primary oscillator.
FIGURE 23-2:
Q3
Q2
Q4
Q2 Q3 Q4 Q1 Q2 Q3
Q1
INTOSC
Multiplexer
OSC1
TOST(1)
TPLL(1)
1
PLL Clock
Output
n-1 n
Clock
Transition(2)
CPU Clock
Peripheral
Clock
Program
Counter
PC
Note 1:
2:
DS39631A-page 260
PC + 2
PC + 6
PC + 4
TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
Clock transition typically occurs within 2-4 TOSC.
Preliminary
PIC18F2420/2520/4420/4520
23.4
FIGURE 23-3:
Peripheral
Clock
INTRC
Source
(32 s)
64
23.4.1
488 Hz
(2.048 ms)
Clock
Failure
Detected
Clock failure is tested for on the falling edge of the sample clock. If a sample clock falling edge occurs while
CM is still set, a clock failure has been detected
(Figure 23-4). This causes the following:
the FSCM generates an oscillator fail interrupt by
setting bit, OSCFIF (PIR2<7>);
the device clock source is switched to the internal
oscillator block (OSCCON is not updated to show
the current clock source this is the fail-safe
condition) and
the WDT is reset.
During switchover, the postscaler frequency from the
internal oscillator block may not be sufficiently stable for
timing sensitive applications. In these cases, it may be
desirable to select another clock configuration and enter
23.4.2
Preliminary
DS39631A-page 261
PIC18F2420/2520/4420/4520
FIGURE 23-4:
Sample Clock
Oscillator
Failure
Device
Clock
Output
CM Output
(Q)
Failure
Detected
OSCFIF
CM Test
Note:
23.4.3
CM Test
23.4.4
CM Test
The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in this
example have been chosen for clarity.
The same logic that prevents false oscillator failure interrupts on POR, or wake from
Sleep, will also prevent the detection of
the oscillators failure to start at all following these events. This can be avoided by
monitoring the OSTS bit and using a
timing routine to determine if the oscillator
is taking too long to start. Even so, no
oscillator failure interrupt will be flagged.
DS39631A-page 262
Preliminary
PIC18F2420/2520/4420/4520
23.5
FIGURE 23-5:
16 Kbytes
32 Kbytes
Address
(PIC18F2420/4420) (PIC18F2520/4520) Range
Boot Block
Boot Block
Block 0
Block 0
000000h
0007FFh
000800h
CP0, WRT0, EBTR0
001FFFh
002000h
Block 1
Block 1
Block 2
005FFFh
006000h
Block 3
Unimplemented
Read 0s
Unimplemented
Read 0s
1FFFFFh
TABLE 23-3:
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CP3(1,2)
CP2(1)
CP1
CP0
300008h
CONFIG5L
300009h
CONFIG5H
CPD
CPB
30000Ah
CONFIG6L
WRT3(1,2)
WRT2(1)
WRT1
WRT0
30000Bh
CONFIG6H
WRTD
WRTB
WRTC
30000Ch
CONFIG7L
30000Dh
CONFIG7H
EBTRB
EBTR3(1,2) EBTR2(1)
EBTR1
EBTR0
Preliminary
DS39631A-page 263
PIC18F2420/2520/4420/4520
23.5.1
PROGRAM MEMORY
CODE PROTECTION
FIGURE 23-6:
Register Values
Program Memory
WRTB, EBTRB = 11
TBLPTR = 0008FFh
WRT0, EBTR0 = 01
PC = 001FFEh
TBLWT*
001FFFh
002000h
WRT1, EBTR1 = 11
003FFFh
004000h
PC = 005FFEh
WRT2, EBTR2 = 11
TBLWT*
005FFFh
006000h
WRT3, EBTR3 = 11
007FFFh
Results: All table writes disabled to Blockn whenever WRTn = 0.
DS39631A-page 264
Preliminary
PIC18F2420/2520/4420/4520
FIGURE 23-7:
Register Values
Program Memory
WRTB, EBTRB = 11
TBLPTR = 0008FFh
WRT0, EBTR0 = 10
001FFFh
002000h
PC = 003FFEh
TBLRD*
WRT1, EBTR1 = 11
003FFFh
004000h
WRT2, EBTR2 = 11
005FFFh
006000h
WRT3, EBTR3 = 11
007FFFh
Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0.
TABLAT register returns a value of 0.
FIGURE 23-8:
Register Values
Program Memory
TBLPTR = 0008FFh
PC = 001FFEh
WRT0, EBTR0 = 10
TBLRD*
001FFFh
002000h
WRT1, EBTR1 = 11
003FFFh
004000h
WRT2, EBTR2 = 11
005FFFh
006000h
WRT3, EBTR3 = 11
007FFFh
Preliminary
DS39631A-page 265
PIC18F2420/2520/4420/4520
23.5.2
DATA EEPROM
CODE PROTECTION
23.5.3
CONFIGURATION REGISTER
PROTECTION
23.6
ID Locations
23.7
23.9
In-Circuit Debugger
TABLE 23-4:
DEBUGGER RESOURCES
I/O pins:
RB6, RB7
Stack:
2 levels
Program Memory:
512 bytes
Data Memory:
10 bytes
DS39631A-page 266
23.8
To use the In-Circuit Debugger function of the microcontroller, the design must implement In-Circuit Serial
Programming connections to MCLR/VPP/RE3, VDD,
VSS, RB7 and RB6. This will interface to the In-Circuit
Debugger module available from Microchip or one of
the third party development tool companies.
Preliminary
PIC18F2420/2520/4420/4520
24.0
24.1
Byte-oriented operations
Bit-oriented operations
Literal operations
Control operations
Preliminary
DS39631A-page 267
PIC18F2420/2520/4420/4520
TABLE 24-1:
Field
Description
bbb
BSR
C, DC, Z, OV, N
dest
Destination: either the WREG register or the specified register file location.
8-bit Register file address (00h to FFh) or 2-bit FSR designator (0h to 3h).
fs
12-bit Register file address (000h to FFFh). This is the source address.
fd
12-bit Register file address (000h to FFFh). This is the destination address.
GIE
Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value).
label
Label name.
mm
The mode of the TBLPTR register for the table read and table write instructions.
Only used with table read and table write instructions:
*+
*-
+*
n
The relative address (2s complement number) for relative branch instructions or the direct address for
Call/Branch and Return instructions.
PC
Program Counter.
PCL
PCH
PCLATH
PCLATU
PD
Power-down bit.
PRODH
PRODL
TBLPTR
TABLAT
TO
Time-out bit.
TOS
Top-of-Stack.
Unused or unchanged.
WDT
Watchdog Timer.
WREG
Dont care (0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for
compatibility with all Microchip software tools.
zs
zd
{
Optional argument.
[text]
(text)
[expr]<n>
Assigned to.
< >
italics
DS39631A-page 268
Preliminary
PIC18F2420/2520/4420/4520
FIGURE 24-1:
10
9 8 7
OPCODE d
a
Example Instruction
0
f (FILE #)
ADDWF MYREG, W, B
0
f (Source FILE #)
12 11
f (Destination FILE #)
1111
12 11
9 8 7
OPCODE b (BIT #) a
0
f (FILE #)
OPCODE
0
k (literal)
MOVLW 7Fh
8 7
OPCODE
15
0
n<7:0> (literal)
12 11
GOTO Label
0
n<19:8> (literal)
1111
8 7
OPCODE
15
0
CALL MYFUNC
n<7:0> (literal)
12 11
0
n<19:8> (literal)
1111
S = Fast bit
15
OPCODE
15
OPCODE
11 10
0
BRA MYFUNC
n<10:0> (literal)
8 7
n<7:0> (literal)
Preliminary
BC MYFUNC
DS39631A-page 269
PIC18F2420/2520/4420/4520
TABLE 24-2:
Mnemonic,
Operands
Cycles
MSb
LSb
Status
Affected
Notes
BYTE-ORIENTED OPERATIONS
ADDWF
ADDWFC
ANDWF
CLRF
COMF
CPFSEQ
CPFSGT
CPFSLT
DECF
DECFSZ
DCFSNZ
INCF
INCFSZ
INFSNZ
IORWF
MOVF
MOVFF
f, d, a
f, d, a
f, d, a
f, a
f, d, a
f, a
f, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
fs, fd
MOVWF
MULWF
NEGF
RLCF
RLNCF
RRCF
RRNCF
SETF
SUBFWB
f, a
f, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, a
f, d, a
SUBWF
SUBWFB
f, d, a
f, d, a
SWAPF
TSTFSZ
XORWF
f, d, a
f, a
f, d, a
Note 1:
When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is 1 for a pin configured as input and is driven low by an
external device, the data will be written back with a 0.
If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned.
If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the
first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory
locations have a valid instruction.
2:
3:
4:
DS39631A-page 270
1
1
1
1
1
1 (2 or 3)
1 (2 or 3)
1 (2 or 3)
1
1 (2 or 3)
1 (2 or 3)
1
1 (2 or 3)
1 (2 or 3)
1
1
2
C, DC, Z, OV, N
C, DC, Z, OV, N
Z, N
Z
Z, N
None
None
None
C, DC, Z, OV, N
None
None
C, DC, Z, OV, N
None
None
Z, N
Z, N
None
1, 2
1, 2
1,2
2
1, 2
4
4
1, 2
1, 2, 3, 4
1, 2, 3, 4
1, 2
1, 2, 3, 4
4
1, 2
1, 2
1
1
1
1
1
1
1
1
1
1
0010 01da0
0010 0da
0001 01da
0110 101a
0001 11da
0110 001a
0110 010a
0110 000a
0000 01da
0010 11da
0100 11da
0010 10da
0011 11da
0100 10da
0001 00da
0101 00da
1100 ffff
1111 ffff
0110 111a
0000 001a
0110 110a
0011 01da
0100 01da
0011 00da
0100 00da
0110 100a
0101 01da
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
1
1
0101
0101
11da
10da
ffff
ffff
1, 2
1
1 (2 or 3)
1
0011
0110
0001
10da
011a
10da
ffff
ffff
ffff
ffff None
ffff None
ffff Z, N
4
1, 2
Preliminary
None
None
C, DC, Z, OV, N
C, Z, N
Z, N
C, Z, N
Z, N
None
C, DC, Z, OV, N
1, 2
1, 2
1, 2
PIC18F2420/2520/4420/4520
TABLE 24-2:
Mnemonic,
Operands
Description
Cycles
MSb
LSb
Status
Affected
Notes
BIT-ORIENTED OPERATIONS
BCF
BSF
BTFSC
BTFSS
BTG
f, b, a
f, b, a
f, b, a
f, b, a
f, d, a
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
Bit Toggle f
1
1
1 (2 or 3)
1 (2 or 3)
1
1001
1000
1011
1010
0111
bbba
bbba
bbba
bbba
bbba
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
None
None
None
None
None
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
1 (2)
2
0010
0110
0011
0111
0101
0001
0100
0nnn
0000
110s
kkkk
0000
0000
1111
kkkk
0000
xxxx
0000
0000
1nnn
0000
0000
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0000
0000
kkkk
kkkk
0000
xxxx
0000
0000
nnnn
1111
0001
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0100
0111
kkkk
kkkk
0000
xxxx
0110
0101
nnnn
1111
000s
None
None
None
None
None
None
None
None
None
None
1
1
1
1
2
1
2
1110
1110
1110
1110
1110
1110
1110
1101
1110
1110
1111
0000
0000
1110
1111
0000
1111
0000
0000
1101
0000
0000
2
2
1
0000
0000
0000
1100
0000
0000
kkkk
0001
0000
1, 2
1, 2
3, 4
3, 4
1, 2
CONTROL OPERATIONS
BC
BN
BNC
BNN
BNOV
BNZ
BOV
BRA
BZ
CALL
n
n
n
n
n
n
n
n
n
n, s
CLRWDT
DAW
GOTO
NOP
NOP
POP
PUSH
RCALL
RESET
RETFIE
n
s
Branch if Carry
Branch if Negative
Branch if Not Carry
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
Branch if Overflow
Branch Unconditionally
Branch if Zero
Call subroutine 1st word
2nd word
Clear Watchdog Timer
Decimal Adjust WREG
Go to address 1st word
2nd word
No Operation
No Operation
Pop top of return stack (TOS)
Push top of return stack (TOS)
Relative Call
Software device Reset
Return from interrupt enable
RETLW
RETURN
SLEEP
k
s
Note 1:
When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is 1 for a pin configured as input and is driven low by an
external device, the data will be written back with a 0.
If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned.
If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the
first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory
locations have a valid instruction.
2:
3:
4:
1
1
2
Preliminary
TO, PD
C
None
None
None
None
None
None
All
GIE/GIEH,
PEIE/GIEL
kkkk None
001s None
0011 TO, PD
DS39631A-page 271
PIC18F2420/2520/4420/4520
TABLE 24-2:
Mnemonic,
Operands
Description
Cycles
MSb
LSb
Status
Affected
Notes
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
LFSR
k
k
k
f, k
MOVLB
MOVLW
MULLW
RETLW
SUBLW
XORLW
k
k
k
k
k
k
1
1
1
2
1
1
1
2
1
1
0000
0000
0000
1110
1111
0000
0000
0000
0000
0000
0000
1111
1011
1001
1110
0000
0001
1110
1101
1100
1000
1010
kkkk
kkkk
kkkk
00ff
kkkk
0000
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
C, DC, Z, OV, N
Z, N
Z, N
None
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1000
1001
1010
1011
1100
1101
1110
1111
None
None
None
None
None
None
None
None
None
None
None
None
C, DC, Z, OV, N
Z, N
2:
3:
4:
Table Read
Table Read with post-increment
Table Read with post-decrement
Table Read with pre-increment
Table Write
Table Write with post-increment
Table Write with post-decrement
Table Write with pre-increment
When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is 1 for a pin configured as input and is driven low by an
external device, the data will be written back with a 0.
If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned.
If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the
first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory
locations have a valid instruction.
DS39631A-page 272
Preliminary
PIC18F2420/2520/4420/4520
24.1.1
ADDLW
ADD literal to W
ADDWF
ADD W to f
Syntax:
ADDLW
Syntax:
ADDWF
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
Status Affected:
N, OV, C, DC, Z
Operands:
0 k 255
Operation:
(W) + k W
Status Affected:
N, OV, C, DC, Z
Encoding:
0000
1111
kkkk
kkkk
Description:
Words:
Cycles:
Encoding:
0010
Q1
Q2
Q3
Q4
Read
literal k
Process
Data
Write to W
Example:
ADDLW
25h
ffff
Words:
Cycles:
Before Instruction
ffff
15h
W
= 10h
After Instruction
01da
Description:
Q Cycle Activity:
Decode
f {,d {,a}}
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
Example:
ADDWF
REG, 0, 0
Before Instruction
W
=
REG
=
After Instruction
W
REG
Note:
=
=
17h
0C2h
0D9h
0C2h
All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).
Preliminary
DS39631A-page 273
PIC18F2420/2520/4420/4520
ADDWFC
ANDLW
Syntax:
ADDWFC
Syntax:
ANDLW
Operands:
0 f 255
d [0,1]
a [0,1]
f {,d {,a}}
Operation:
Status Affected:
Encoding:
0010
Description:
00da
ffff
ffff
Add W, the CARRY flag and data memory location f. If d is 0, the result is
placed in W. If d is 1, the result is
placed in data memory location f.
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words:
Cycles:
Operands:
0 k 255
Operation:
(W) .AND. k W
Status Affected:
N, Z
Encoding:
N,OV, C, DC, Z
0000
1011
kkkk
kkkk
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
k
Process
Data
Write to W
Example:
ANDLW
05Fh
Before Instruction
W
=
After Instruction
W
A3h
03h
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
Example:
ADDWFC
Before Instruction
CARRY bit =
REG
=
W
=
After Instruction
CARRY bit =
REG
=
W
=
DS39631A-page 274
REG, 0, 1
1
02h
4Dh
0
02h
50h
Preliminary
PIC18F2420/2520/4420/4520
ANDWF
AND W with f
BC
Branch if Carry
Syntax:
ANDWF
Syntax:
BC
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
-128 n 127
Operation:
if CARRY bit is 1
(PC) + 2 + 2n PC
None
f {,d {,a}}
Operation:
Status Affected:
Status Affected:
N, Z
Encoding:
Encoding:
0001
Description:
01da
ffff
ffff
Words:
Cycles:
1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
REG, 0, 0
W
REG
=
=
Cycles:
1(2)
nnnn
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
n
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
Q1
Q2
Q3
Q4
Decode
Read literal
n
Process
Data
No
operation
Example:
HERE
Before Instruction
PC
After Instruction
If CARRY
PC
If CARRY
PC
17h
C2h
02h
C2h
nnnn
Words:
Before Instruction
W
=
REG
=
After Instruction
0010
If No Jump:
Q1
ANDWF
1110
Description:
Q Cycle Activity:
Example:
Preliminary
BC
address (HERE)
=
=
=
=
1;
address (HERE + 12)
0;
address (HERE + 2)
DS39631A-page 275
PIC18F2420/2520/4420/4520
BCF
Bit Clear f
BN
Branch if Negative
Syntax:
BCF
Syntax:
BN
Operands:
0 f 255
0b7
a [0,1]
Operands:
-128 n 127
Operation:
if NEGATIVE bit is 1
(PC) + 2 + 2n PC
None
f, b {,a}
Operation:
0 f<b>
Status Affected:
Status Affected:
None
Encoding:
Encoding:
1001
Description:
bbba
ffff
ffff
Words:
Cycles:
1
Q1
Q2
Q3
Q4
Read
register f
Process
Data
Write
register f
Example:
BCF
Before Instruction
FLAG_REG =
After Instruction
FLAG_REG =
DS39631A-page 276
FLAG_REG,
1110
Description:
0110
nnnn
nnnn
Words:
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q Cycle Activity:
Decode
Q1
Q2
Q3
Q4
Decode
Read literal
n
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
7, 0
Q1
Q2
Q3
Q4
Decode
Read literal
n
Process
Data
No
operation
C7h
47h
Example:
HERE
Before Instruction
PC
After Instruction
If NEGATIVE
PC
If NEGATIVE
PC
Preliminary
BN
Jump
address (HERE)
=
=
=
=
1;
address (Jump)
0;
address (HERE + 2)
PIC18F2420/2520/4420/4520
BNC
BNN
Syntax:
BNC
Syntax:
BNN
Operands:
-128 n 127
Operands:
-128 n 127
Operation:
if CARRY bit is 0
(PC) + 2 + 2n PC
Operation:
if NEGATIVE bit is 0
(PC) + 2 + 2n PC
Status Affected:
None
Status Affected:
None
Encoding:
1110
0011
nnnn
nnnn
Encoding:
1110
0111
nnnn
nnnn
Description:
Description:
Words:
Words:
Cycles:
1(2)
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
n
Process
Data
Write to PC
Decode
Read literal
n
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
n
Process
Data
No
operation
Decode
Read literal
n
Process
Data
No
operation
If No Jump:
Example:
If No Jump:
HERE
Before Instruction
PC
After Instruction
If CARRY
PC
If CARRY
PC
BNC
Jump
address (HERE)
=
=
=
=
0;
address (Jump)
1;
address (HERE + 2)
Example:
HERE
Before Instruction
PC
After Instruction
If NEGATIVE
PC
If NEGATIVE
PC
Preliminary
BNN
Jump
address (HERE)
=
=
=
=
0;
address (Jump)
1;
address (HERE + 2)
DS39631A-page 277
PIC18F2420/2520/4420/4520
BNOV
BNZ
Syntax:
BNOV
Syntax:
BNZ
Operands:
-128 n 127
Operands:
-128 n 127
Operation:
if OVERFLOW bit is 0
(PC) + 2 + 2n PC
Operation:
if ZERO bit is 0
(PC) + 2 + 2n PC
Status Affected:
None
Status Affected:
None
Encoding:
1110
0101
nnnn
nnnn
Encoding:
1110
0001
nnnn
nnnn
Description:
Description:
Words:
Words:
Cycles:
1(2)
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
n
Process
Data
Write to PC
Decode
Read literal
n
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
n
Process
Data
No
operation
Decode
Read literal
n
Process
Data
No
operation
If No Jump:
If No Jump:
Example:
HERE
Before Instruction
PC
=
After Instruction
If OVERFLOW =
PC
=
If OVERFLOW =
PC
=
DS39631A-page 278
BNOV Jump
Example:
HERE
Before Instruction
PC
After Instruction
If ZERO
PC
If ZERO
PC
address (HERE)
0;
address (Jump)
1;
address (HERE + 2)
Preliminary
BNZ
Jump
address (HERE)
=
=
=
=
0;
address (Jump)
1;
address (HERE + 2)
PIC18F2420/2520/4420/4520
BRA
Unconditional Branch
BSF
Bit Set f
Syntax:
BRA
Syntax:
BSF
Operands:
0 f 255
0b7
a [0,1]
Operation:
1 f<b>
Status Affected:
None
Operands:
-1024 n 1023
Operation:
(PC) + 2 + 2n PC
Status Affected:
None
Encoding:
1101
Description:
0nnn
nnnn
nnnn
Words:
Cycles:
Encoding:
1000
Q1
Q2
Q3
Q4
Read literal
n
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
Example:
bbba
ffff
ffff
Description:
Words:
Cycles:
Q Cycle Activity:
Decode
f, b {,a}
Q Cycle Activity:
HERE
Before Instruction
PC
After Instruction
PC
BRA
Jump
address (HERE)
address (Jump)
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write
register f
Example:
BSF
Before Instruction
FLAG_REG
After Instruction
FLAG_REG
Preliminary
FLAG_REG, 7, 1
0Ah
8Ah
DS39631A-page 279
PIC18F2420/2520/4420/4520
BTFSC
BTFSS
Syntax:
BTFSC f, b {,a}
Syntax:
BTFSS f, b {,a}
Operands:
0 f 255
0b7
a [0,1]
Operands:
0 f 255
0b<7
a [0,1]
Operation:
skip if (f<b>) = 0
Operation:
skip if (f<b>) = 1
Status Affected:
None
Status Affected:
None
Encoding:
1011
Description:
bbba
ffff
ffff
Encoding:
1010
Description:
Words:
Words:
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Cycles:
1(2)
Note:
Q Cycle Activity:
bbba
ffff
ffff
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
No
operation
Decode
Read
register f
Process
Data
No
operation
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
If skip:
If skip:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
FALSE
TRUE
Before Instruction
PC
After Instruction
If FLAG<1>
PC
If FLAG<1>
PC
DS39631A-page 280
BTFSC
:
:
FLAG, 1, 0
address (HERE)
=
=
=
=
0;
address (TRUE)
1;
address (FALSE)
Example:
HERE
FALSE
TRUE
Before Instruction
PC
After Instruction
If FLAG<1>
PC
If FLAG<1>
PC
Preliminary
BTFSS
:
:
FLAG, 1, 0
address (HERE)
=
=
=
=
0;
address (FALSE)
1;
address (TRUE)
PIC18F2420/2520/4420/4520
BTG
Bit Toggle f
BOV
Branch if Overflow
Syntax:
BTG f, b {,a}
Syntax:
BOV
Operands:
0 f 255
0b<7
a [0,1]
Operands:
-128 n 127
Operation:
if OVERFLOW bit is 1
(PC) + 2 + 2n PC
Status Affected:
None
Operation:
(f<b>) f<b>
Status Affected:
None
Encoding:
0111
Description:
Encoding:
bbba
ffff
ffff
1110
0100
nnnn
nnnn
Description:
Words:
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Words:
Q1
Q2
Q3
Q4
Cycles:
Decode
Read literal
n
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write
register f
Example:
BTG
PORTC,
Q1
Q2
Q3
Q4
Decode
Read literal
n
Process
Data
No
operation
4, 0
Before Instruction:
PORTC =
0111 0101 [75h]
After Instruction:
PORTC =
0110 0101 [65h]
If No Jump:
Example:
HERE
Before Instruction
PC
=
After Instruction
If OVERFLOW =
PC
=
If OVERFLOW =
PC
=
Preliminary
BOV
Jump
address (HERE)
1;
address (Jump)
0;
address (HERE + 2)
DS39631A-page 281
PIC18F2420/2520/4420/4520
BZ
Branch if Zero
CALL
Subroutine Call
Syntax:
BZ
Syntax:
CALL k {,s}
Operands:
-128 n 127
Operands:
Operation:
if ZERO bit is 1
(PC) + 2 + 2n PC
0 k 1048575
s [0,1]
Operation:
Status Affected:
None
(PC) + 4 TOS,
k PC<20:1>,
if s = 1
(W) WS,
(Status) STATUSS,
(BSR) BSRS
Status Affected:
None
Encoding:
1110
Description:
0000
nnnn
nnnn
Words:
Cycles:
1(2)
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
Q1
Q2
Q3
Q4
Read literal
n
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q2
Q3
Q4
Read literal
n
Process
Data
No
operation
HERE
Before Instruction
PC
After Instruction
If ZERO
PC
If ZERO
PC
DS39631A-page 282
BZ
Words:
Cycles:
2
Q1
Decode
Q2
Q3
Q4
Jump
address (HERE)
=
=
=
=
1;
address (Jump)
0;
address (HERE + 2)
kkkk0
kkkk8
Q Cycle Activity:
Q1
Decode
Example:
k7kkk
kkkk
110s
k19kkk
Description:
Q Cycle Activity:
If Jump:
Decode
1110
1111
No
operation
Example:
No
operation
HERE
Before Instruction
PC
=
After Instruction
PC
=
TOS
=
WS
=
BSRS
=
STATUSS =
Preliminary
No
operation
CALL
Read literal
k<19:8>,
Write to PC
No
operation
THERE, 1
address (HERE)
address (THERE)
address (HERE + 4)
W
BSR
Status
PIC18F2420/2520/4420/4520
CLRF
Clear f
Syntax:
CLRF
Operands:
0 f 255
a [0,1]
f {,a}
Operation:
000h f
1Z
Status Affected:
Encoding:
0110
Description:
101a
ffff
ffff
Words:
Cycles:
CLRWDT
Syntax:
CLRWDT
Operands:
None
Operation:
000h WDT,
000h WDT postscaler,
1 TO,
1 PD
Status Affected:
TO, PD
Encoding:
Words:
Cycles:
Q3
Q4
Decode
Read
register f
Process
Data
Write
register f
Example:
CLRF
Before Instruction
FLAG_REG
After Instruction
FLAG_REG
FLAG_REG, 1
5Ah
00h
0000
0100
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
operation
Process
Data
No
operation
Example:
Q2
0000
Q Cycle Activity:
Q1
0000
Description:
Preliminary
CLRWDT
Before Instruction
WDT Counter
After Instruction
WDT Counter
WDT Postscaler
TO
PD
=
=
=
=
00h
0
1
1
DS39631A-page 283
PIC18F2420/2520/4420/4520
COMF
Complement f
CPFSEQ
Syntax:
COMF
Syntax:
CPFSEQ
Operands:
0 f 255
a [0,1]
Operation:
(f) (W),
skip if (f) = (W)
(unsigned comparison)
Status Affected:
None
f {,d {,a}}
0 f 255
d [0,1]
a [0,1]
Operands:
Operation:
(f) dest
Status Affected:
N, Z
Encoding:
0001
11da
ffff
ffff
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
Encoding:
0110
f {,a}
001a
ffff
ffff
Description:
Words:
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Example:
COMF
Before Instruction
REG
=
After Instruction
REG
=
W
=
REG, 0, 0
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
No
operation
13h
If skip:
13h
ECh
Q1
Q2
Q3
No
No
No
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
No
No
No
operation
operation
operation
No
No
No
operation
operation
operation
Example:
DS39631A-page 284
Preliminary
HERE
NEQUAL
EQUAL
Q4
No
operation
Q4
No
operation
No
operation
CPFSEQ REG, 0
:
:
Before Instruction
PC Address
W
REG
After Instruction
=
=
=
HERE
?
?
If REG
PC
If REG
PC
=
=
W;
Address (EQUAL)
W;
Address (NEQUAL)
PIC18F2420/2520/4420/4520
CPFSGT
CPFSLT
Syntax:
CPFSGT
Syntax:
CPFSLT
Operands:
0 f 255
a [0,1]
Operands:
0 f 255
a [0,1]
Operation:
(f) (W),
skip if (f) > (W)
(unsigned comparison)
Operation:
(f) (W),
skip if (f) < (W)
(unsigned comparison)
Status Affected:
None
Status Affected:
None
Encoding:
0110
Description:
f {,a}
010a
ffff
ffff
Words:
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Encoding:
Q2
Read
register f
Q3
Process
Data
Q4
No
operation
Q1
Q2
Q3
No
No
No
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
No
No
No
operation
operation
operation
No
No
No
operation
operation
operation
Q4
No
operation
Example:
HERE
NGREATER
GREATER
=
=
Address (HERE)
?
If REG
PC
If REG
PC
>
=
W;
Address (GREATER)
W;
Address (NGREATER)
ffff
ffff
Words:
Cycles:
1(2)
Note:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
No
operation
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip:
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
CPFSGT REG, 0
:
:
Before Instruction
PC
W
After Instruction
000a
If skip:
Q4
No
operation
No
operation
0110
Description:
Q Cycle Activity:
Q1
Decode
f {,a}
Preliminary
HERE
NLESS
LESS
CPFSLT REG, 1
:
:
Before Instruction
PC
W
After Instruction
=
=
Address (HERE)
?
If REG
PC
If REG
PC
<
=
W;
Address (LESS)
W;
Address (NLESS)
DS39631A-page 285
PIC18F2420/2520/4420/4520
DAW
DECF
Decrement f
Syntax:
DAW
Syntax:
Operands:
None
Operands:
Operation:
0 f 255
d [0,1]
a [0,1]
Operation:
(f) 1 dest
Status Affected:
C, DC, N, OV, Z
Encoding:
0000
0000
0000
0000
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register W
Process
Data
Write
W
ffff
Words:
Cycles:
0111
Description:
ffff
Description:
Encoding:
01da
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
Example1:
DAW
Before Instruction
W
=
C
=
DC
=
After Instruction
W
C
DC
Example 2:
=
=
=
A5h
0
0
Example:
DECF
Before Instruction
CNT
=
Z
=
After Instruction
CNT
=
Z
=
05h
1
0
CNT,
1, 0
01h
0
00h
1
Before Instruction
W
=
C
=
DC
=
After Instruction
W
C
DC
=
=
=
DS39631A-page 286
CEh
0
0
34h
1
0
Preliminary
PIC18F2420/2520/4420/4520
DECFSZ
Decrement f, skip if 0
DCFSNZ
Syntax:
Syntax:
DCFSNZ
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
(f) 1 dest,
skip if result = 0
Operation:
(f) 1 dest,
skip if result 0
Status Affected:
None
Status Affected:
None
Encoding:
0010
11da
ffff
ffff
Description:
Words:
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Encoding:
0100
Description:
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
Words:
Cycles:
1(2)
Note:
ffff
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip:
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
HERE
DECFSZ
GOTO
CNT, 1, 1
LOOP
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
CONTINUE
HERE
ZERO
NZERO
Before Instruction
TEMP
After Instruction
TEMP
If TEMP
PC
If TEMP
PC
Address (HERE)
CNT - 1
0;
Address (CONTINUE)
0;
Address (HERE + 2)
ffff
Q Cycle Activity:
Q1
Before Instruction
PC
=
After Instruction
CNT
=
If CNT
=
PC =
If CNT
PC =
11da
Q Cycle Activity:
Example:
f {,d {,a}}
Preliminary
DCFSNZ
:
:
TEMP, 1, 0
=
=
=
TEMP 1,
0;
Address (ZERO)
0;
Address (NZERO)
DS39631A-page 287
PIC18F2420/2520/4420/4520
GOTO
Unconditional Branch
INCF
Increment f
Syntax:
GOTO k
Syntax:
INCF
Operands:
0 k 1048575
Operands:
Operation:
k PC<20:1>
Status Affected:
None
0 f 255
d [0,1]
a [0,1]
Operation:
(f) + 1 dest
Status Affected:
C, DC, N, OV, Z
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
1110
1111
Description:
1111
k19kkk
k7kkk
kkkk
kkkk0
kkkk8
Encoding:
0010
Cycles:
2
Q1
Q2
Q3
Q4
Read literal
k<7:0>,
No
operation
Read literal
k<19:8>,
Write to PC
No
operation
No
operation
No
operation
No
operation
ffff
ffff
Words:
Cycles:
Q Cycle Activity:
Decode
10da
Description:
f {,d {,a}}
Q Cycle Activity:
Example:
GOTO THERE
After Instruction
PC =
Address (THERE)
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
Example:
INCF
Before Instruction
CNT
=
Z
=
C
=
DC
=
After Instruction
CNT
=
Z
=
C
=
DC
=
DS39631A-page 288
Preliminary
CNT, 1, 0
FFh
0
?
?
00h
1
1
1
PIC18F2420/2520/4420/4520
INCFSZ
Increment f, skip if 0
INFSNZ
Syntax:
INCFSZ
Syntax:
INFSNZ
0 f 255
d [0,1]
a [0,1]
f {,d {,a}}
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
Operation:
(f) + 1 dest,
skip if result = 0
Operation:
(f) + 1 dest,
skip if result 0
Status Affected:
None
Status Affected:
None
Encoding:
0011
11da
ffff
ffff
Encoding:
0100
Description:
ffff
ffff
Description:
Words:
Words:
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Cycles:
1(2)
Note:
Q Cycle Activity:
10da
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
Decode
Read
register f
Process
Data
Write to
destination
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
If skip:
If skip:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
NZERO
ZERO
Before Instruction
PC
=
After Instruction
CNT
=
If CNT
=
PC
=
If CNT
PC
=
INCFSZ
:
:
CNT, 1, 0
Example:
Before Instruction
PC
=
After Instruction
REG
=
If REG
PC
=
If REG
=
PC
=
Address (HERE)
CNT + 1
0;
Address (ZERO)
0;
Address (NZERO)
HERE
ZERO
NZERO
Preliminary
INFSNZ
REG, 1, 0
Address (HERE)
REG + 1
0;
Address (NZERO)
0;
Address (ZERO)
DS39631A-page 289
PIC18F2420/2520/4420/4520
IORLW
IORWF
Inclusive OR W with f
Syntax:
IORLW k
Syntax:
IORWF
Operands:
0 k 255
Operands:
Operation:
(W) .OR. k W
Status Affected:
N, Z
0 f 255
d [0,1]
a [0,1]
Operation:
Status Affected:
N, Z
Encoding:
0000
1001
kkkk
kkkk
Description:
Words:
Cycles:
Encoding:
0001
Q1
Q2
Q3
Q4
Read
literal k
Process
Data
Write to W
Example:
IORLW
ffff
Words:
Cycles:
35h
9Ah
BFh
ffff
Before Instruction
W
=
After Instruction
00da
Description:
Q Cycle Activity:
Decode
f {,d {,a}}
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
Example:
IORWF
Before Instruction
RESULT =
W
=
After Instruction
RESULT =
W
=
DS39631A-page 290
Preliminary
RESULT, 0, 1
13h
91h
13h
93h
PIC18F2420/2520/4420/4520
LFSR
Load FSR
MOVF
Move f
Syntax:
LFSR f, k
Syntax:
MOVF
Operands:
0f2
0 k 4095
Operands:
Operation:
k FSRf
0 f 255
d [0,1]
a [0,1]
Status Affected:
None
Operation:
f dest
Status Affected:
N, Z
Encoding:
1110
1111
1110
0000
00ff
k7kkk
k11kkk
kkkk
Description:
Words:
Cycles:
Encoding:
0101
Q1
Q2
Q3
Q4
Read literal
k MSB
Process
Data
Write
literal k
MSB to
FSRfH
Decode
Read literal
k LSB
Process
Data
Write literal
k to FSRfL
Example:
After Instruction
FSR2H
FSR2L
03h
ABh
ffff
ffff
Words:
Cycles:
LFSR 2, 3ABh
=
=
00da
Description:
Q Cycle Activity:
Decode
f {,d {,a}}
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write W
Example:
MOVF
Before Instruction
REG
W
After Instruction
REG
W
Preliminary
REG, 0, 0
=
=
22h
FFh
=
=
22h
22h
DS39631A-page 291
PIC18F2420/2520/4420/4520
MOVFF
Move f to f
MOVLB
Syntax:
MOVFF fs,fd
Syntax:
MOVLW k
Operands:
0 fs 4095
0 fd 4095
Operands:
0 k 255
Operation:
k BSR
None
Operation:
(fs) fd
Status Affected:
Status Affected:
None
Encoding:
Encoding:
1st word (source)
2nd word (destin.)
1100
1111
Description:
ffff
ffff
ffff
ffff
ffffs
ffffd
Words:
Cycles:
2 (3)
0000
0001
kkkk
kkkk
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal k
Process
Data
Write literal
k to BSR
MOVLB
Example:
Before Instruction
BSR Register =
After Instruction
BSR Register =
02h
05h
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
(src)
Process
Data
No
operation
Decode
No
operation
No
operation
Write
register f
(dest)
No dummy
read
Example:
MOVFF
Before Instruction
REG1
REG2
After Instruction
REG1
REG2
DS39631A-page 292
REG1, REG2
=
=
33h
11h
=
=
33h
33h
Preliminary
PIC18F2420/2520/4420/4520
MOVLW
Move literal to W
MOVWF
Move W to f
Syntax:
MOVLW k
Syntax:
MOVWF
Operands:
0 k 255
Operands:
Operation:
kW
0 f 255
a [0,1]
Status Affected:
None
Encoding:
0000
Description:
1110
kkkk
kkkk
Words:
Cycles:
Operation:
(W) f
Status Affected:
None
Encoding:
0110
Q1
Q2
Q3
Q4
Read
literal k
Process
Data
Write to W
Example:
MOVLW
=
ffff
ffff
Words:
Cycles:
5Ah
After Instruction
W
111a
Description:
Q Cycle Activity:
Decode
f {,a}
5Ah
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write
register f
Example:
MOVWF
REG, 0
Before Instruction
W
=
REG
=
After Instruction
W
REG
Preliminary
=
=
4Fh
FFh
4Fh
4Fh
DS39631A-page 293
PIC18F2420/2520/4420/4520
MULLW
MULWF
Multiply W with f
Syntax:
MULLW
Syntax:
MULWF
Operands:
0 f 255
a [0,1]
Operation:
Status Affected:
None
Operands:
0 k 255
Operation:
(W) x k PRODH:PRODL
Status Affected:
None
Encoding:
0000
Description:
1101
kkkk
kkkk
Words:
Cycles:
Encoding:
0000
Q1
Q2
Q3
Q4
Read
literal k
Process
Data
Write
registers
PRODH:
PRODL
Example:
MULLW
W
PRODH
PRODL
E2h
?
?
=
=
=
E2h
ADh
08h
ffff
Words:
Cycles:
0C4h
=
=
=
ffff
Before Instruction
W
PRODH
PRODL
After Instruction
001a
Description:
Q Cycle Activity:
Decode
f {,a}
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write
registers
PRODH:
PRODL
Example:
MULWF
REG, 1
Before Instruction
W
REG
PRODH
PRODL
After Instruction
W
REG
PRODH
PRODL
DS39631A-page 294
Preliminary
=
=
=
=
C4h
B5h
?
?
=
=
=
=
C4h
B5h
8Ah
94h
PIC18F2420/2520/4420/4520
NEGF
Negate f
NOP
No Operation
Syntax:
NEGF
Syntax:
NOP
Operands:
0 f 255
a [0,1]
f {,a}
Operands:
None
Operation:
No operation
None
Operation:
(f)+1f
Status Affected:
Status Affected:
N, OV, C, DC, Z
Encoding:
Encoding:
0110
Description:
110a
ffff
Words:
Cycles:
0000
1111
ffff
0000
xxxx
Description:
No operation.
Words:
Cycles:
0000
xxxx
0000
xxxx
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
operation
No
operation
No
operation
Example:
None.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write
register f
Example:
NEGF
Before Instruction
REG
=
After Instruction
REG
=
REG, 1
Preliminary
DS39631A-page 295
PIC18F2420/2520/4420/4520
POP
PUSH
Syntax:
POP
Syntax:
PUSH
Operands:
None
Operands:
None
Operation:
Operation:
(PC + 2) TOS
Status Affected:
None
Status Affected:
None
Encoding:
0000
0000
0000
0110
Description:
Words:
Cycles:
Encoding:
Q2
Q3
Q4
Decode
No
operation
POP TOS
value
No
operation
POP
GOTO
NEW
Before Instruction
TOS
Stack (1 level down)
DS39631A-page 296
0000
0101
Words:
Cycles:
Q Cycle Activity:
Q1
After Instruction
TOS
PC
0000
Description:
Q Cycle Activity:
Example:
0000
Q1
Q2
Q3
Q4
Decode
PUSH
PC + 2 onto
return stack
No
operation
No
operation
Example:
=
=
=
=
0031A2h
014332h
014332h
NEW
Preliminary
PUSH
Before Instruction
TOS
PC
=
=
345Ah
0124h
After Instruction
PC
TOS
Stack (1 level down)
=
=
=
0126h
0126h
345Ah
PIC18F2420/2520/4420/4520
RCALL
Relative Call
RESET
Reset
Syntax:
RCALL
Syntax:
RESET
Operands:
-1024 n 1023
Operands:
None
Operation:
(PC) + 2 TOS,
(PC) + 2 + 2n PC
Operation:
Status Affected:
None
Status Affected:
All
Encoding:
1101
Description:
1nnn
nnnn
nnnn
Words:
Cycles:
Encoding:
0000
Q3
Q4
Decode
Read literal
n
Process
Data
Write to PC
No
operation
No
operation
1111
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Start
Reset
No
operation
No
operation
Example:
Q2
1111
Q Cycle Activity:
Q1
0000
Description:
After Instruction
Registers =
Flags*
=
RESET
Reset Value
Reset Value
PUSH PC to
stack
No
operation
Example:
No
operation
HERE
RCALL Jump
Before Instruction
PC =
Address (HERE)
After Instruction
PC =
Address (Jump)
TOS =
Address (HERE + 2)
Preliminary
DS39631A-page 297
PIC18F2420/2520/4420/4520
RETFIE
RETLW
Return literal to W
Syntax:
RETFIE {s}
Syntax:
RETLW k
Operands:
s [0,1]
Operands:
0 k 255
Operation:
(TOS) PC,
1 GIE/GIEH or PEIE/GIEL,
if s = 1
(WS) W,
(STATUSS) Status,
(BSRS) BSR,
PCLATU, PCLATH are unchanged.
Operation:
k W,
(TOS) PC,
PCLATU, PCLATH are unchanged
Status Affected:
None
Status Affected:
0000
0000
0001
Cycles:
Q Cycle Activity:
Q2
Q3
Q4
Decode
No
operation
No
operation
POP PC
from stack
Set GIEH or
GIEL
No
operation
RETFIE
After Interrupt
PC
W
BSR
Status
GIE/GIEH, PEIE/GIEL
DS39631A-page 298
kkkk
kkkk
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal k
Process
Data
POP PC
from stack,
Write to W
No
operation
No
operation
No
operation
No
operation
Example:
Q1
Example:
1100
Description:
000s
Words:
No
operation
0000
GIE/GIEH, PEIE/GIEL.
Encoding:
Description:
Encoding:
No
operation
No
operation
1
=
=
=
=
=
TOS
WS
BSRS
STATUSS
1
CALL TABLE ;
;
;
;
:
TABLE
ADDWF PCL ;
RETLW k0
;
RETLW k1
;
:
:
RETLW kn
;
Before Instruction
W
=
After Instruction
W
=
Preliminary
W contains table
offset value
W now has
table value
W = offset
Begin table
End of table
07h
value of kn
PIC18F2420/2520/4420/4520
RETURN
RLCF
Syntax:
RETURN {s}
Syntax:
RLCF
Operands:
s [0,1]
Operands:
Operation:
(TOS) PC,
if s = 1
(WS) W,
(STATUSS) Status,
(BSRS) BSR,
PCLATU, PCLATH are unchanged
0 f 255
d [0,1]
a [0,1]
Operation:
Status Affected:
C, N, Z
Status Affected:
None
Encoding:
0000
Encoding:
0000
0001
001s
Description:
Words:
Cycles:
0011
Description:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
operation
Process
Data
POP PC
from stack
No
operation
No
operation
No
operation
No
operation
f {,d {,a}}
01da
ffff
ffff
C
Words:
Cycles:
Q Cycle Activity:
Example:
RETURN
After Instruction:
PC = TOS
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
Example:
Before Instruction
REG
=
C
=
After Instruction
REG
=
W
=
C
=
Preliminary
RLCF
REG, 0, 0
1110 0110
0
1110 0110
1100 1100
1
DS39631A-page 299
PIC18F2420/2520/4420/4520
RLNCF
RRCF
Syntax:
RLNCF
Syntax:
RRCF
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
Operation:
Status Affected:
N, Z
Status Affected:
C, N, Z
Encoding:
0100
Description:
f {,d {,a}}
01da
ffff
ffff
Encoding:
0011
Description:
register f
Words:
Cycles:
1
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
Before Instruction
REG
=
After Instruction
REG
=
DS39631A-page 300
00da
RLNCF
Words:
Cycles:
ffff
register f
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
RRCF
REG, 0, 0
REG, 1, 0
1010 1011
ffff
Q Cycle Activity:
Example:
f {,d {,a}}
Example:
Before Instruction
REG
=
C
=
After Instruction
REG
=
W
=
C
=
0101 0111
Preliminary
1110 0110
0
1110 0110
0111 0011
0
PIC18F2420/2520/4420/4520
RRNCF
SETF
Syntax:
RRNCF
Syntax:
SETF
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
0 f 255
a [0,1]
Operation:
FFh f
Operation:
Status Affected:
None
Status Affected:
f {,d {,a}}
Encoding:
N, Z
Encoding:
0100
Description:
00da
ffff
ffff
Cycles:
1
Q2
Q3
Q4
Read
register f
Process
Data
Write to
destination
Example 1:
RRNCF
Before Instruction
REG
=
After Instruction
REG
=
Example 2:
100a
ffff
ffff
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write
register f
Example:
Q1
0110
Q Cycle Activity:
Decode
f {,a}
Description:
register f
Words:
Set f
SETF
Before Instruction
REG
After Instruction
REG
REG, 1
5Ah
FFh
REG, 1, 0
1101 0111
1110 1011
RRNCF
REG, 0, 0
Before Instruction
W
=
REG
=
After Instruction
W
REG
=
=
?
1101 0111
1110 1011
1101 0111
Preliminary
DS39631A-page 301
PIC18F2420/2520/4420/4520
SLEEP
SUBFWB
Syntax:
SLEEP
Syntax:
SUBFWB
Operands:
None
Operands:
Operation:
00h WDT,
0 WDT postscaler,
1 TO,
0 PD
0 f 255
d [0,1]
a [0,1]
Operation:
Status Affected:
N, OV, C, DC, Z
Status Affected:
TO, PD
Encoding:
0000
Encoding:
0000
0000
0011
Description:
Words:
Cycles:
0101
Q1
Q2
Q3
Q4
No
operation
Process
Data
Go to
Sleep
Example:
SLEEP
Before Instruction
TO =
?
?
PD =
DS39631A-page 302
ffff
ffff
Words:
Cycles:
Q Cycle Activity:
After Instruction
1
TO =
0
PD =
If WDT causes wake-up, this bit is cleared.
01da
Description:
Q Cycle Activity:
Decode
f {,d {,a}}
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
SUBFWB
REG, 1, 0
Example 1:
Before Instruction
REG
=
3
W
=
2
C
=
1
After Instruction
REG
=
FF
W
=
2
C
=
0
Z
=
0
N
=
1 ; result is negative
SUBFWB
REG, 0, 0
Example 2:
Before Instruction
REG
=
2
W
=
5
C
=
1
After Instruction
REG
=
2
W
=
3
C
=
1
Z
=
0
N
=
0 ; result is positive
SUBFWB
REG, 1, 0
Example 3:
Before Instruction
REG
=
1
W
=
2
C
=
0
After Instruction
REG
=
0
W
=
2
C
=
1
Z
=
1 ; result is zero
N
=
0
Preliminary
PIC18F2420/2520/4420/4520
SUBLW
SUBWF
Subtract W from f
Syntax:
SUBLW k
Syntax:
SUBWF
Operands:
0 k 255
Operands:
Operation:
k (W) W
Status Affected:
N, OV, C, DC, Z
0 f 255
d [0,1]
a [0,1]
Operation:
Status Affected:
N, OV, C, DC, Z
Encoding:
0000
1000
kkkk
kkkk
f {,d {,a}}
Description
Encoding:
Words:
Description:
Cycles:
Words:
Cycles:
0101
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal k
Process
Data
Write to W
Example 1:
Before Instruction
W
=
C
=
After Instruction
W
=
C
=
Z
=
N
=
Example 2:
Before Instruction
W
=
C
=
After Instruction
W
=
C
=
Z
=
N
=
Example 3:
Before Instruction
W
=
C
=
After Instruction
W
=
C
=
Z
=
N
=
SUBLW
02h
01h
?
01h
1
; result is positive
0
0
SUBLW
ffff
ffff
02h
Q Cycle Activity:
02h
?
00h
1
; result is zero
1
0
SUBLW
11da
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
SUBWF
REG, 1, 0
Example 1:
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
=
C
=
Z
=
N
=
02h
03h
?
FFh ; (2s complement)
0
; result is negative
0
1
Example 2:
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
=
C
=
Z
=
N
=
Example 3:
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
=
C
=
Z
=
N
=
Preliminary
3
2
?
1
2
1
0
0
; result is positive
SUBWF
REG, 0, 0
2
2
?
2
0
1
1
0
SUBWF
; result is zero
REG, 1, 0
1
2
?
FFh ;(2s complement)
2
0
; result is negative
0
1
DS39631A-page 303
PIC18F2420/2520/4420/4520
SUBWFB
SWAPF
Swap f
Syntax:
SUBWFB
Syntax:
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
Operation:
Status Affected:
N, OV, C, DC, Z
(f<3:0>) dest<7:4>,
(f<7:4>) dest<3:0>
Status Affected:
None
Encoding:
0101
Description:
f {,d {,a}}
10da
ffff
ffff
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Q2
Read
register f
Example 1:
SUBWFB
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
=
C
=
Z
=
N
=
Example 2:
Q4
Write to
destination
(0001 1001)
(0000 1101)
0Ch
0Dh
1
0
0
(0000 1011)
(0000 1101)
10da
ffff
ffff
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
REG, 1, 0
19h
0Dh
1
0011
Description:
Example:
SWAPF
Before Instruction
REG
=
After Instruction
REG
=
REG, 1, 0
53h
35h
; result is positive
SUBWFB REG, 0, 0
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
=
C
=
Z
=
N
=
Example 3:
1Bh
1Ah
0
(0001 1011)
(0001 1010)
1Bh
00h
1
1
0
(0001 1011)
SUBWFB
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
C
Z
N
Q3
Process
Data
Encoding:
=
=
=
=
DS39631A-page 304
; result is zero
REG, 1, 0
03h
0Eh
1
(0000 0011)
(0000 1101)
F5h
(1111 0100)
; [2s comp]
(0000 1101)
0Eh
0
0
1
; result is negative
Preliminary
PIC18F2420/2520/4420/4520
TBLRD
Table Read
TBLRD
Syntax:
Example1:
TBLRD
Operands:
None
Operation:
if TBLRD *,
(Prog Mem (TBLPTR)) TABLAT;
TBLPTR No Change;
if TBLRD *+,
(Prog Mem (TBLPTR)) TABLAT;
(TBLPTR) + 1 TBLPTR;
if TBLRD *-,
(Prog Mem (TBLPTR)) TABLAT;
(TBLPTR) 1 TBLPTR;
if TBLRD +*,
(TBLPTR) + 1 TBLPTR;
(Prog Mem (TBLPTR)) TABLAT;
Before Instruction
TABLAT
TBLPTR
MEMORY (00A356h)
After Instruction
TABLAT
TBLPTR
Example2:
0000
0000
0000
TBLRD
=
=
=
55h
00A356h
34h
=
=
34h
00A357h
+* ;
Before Instruction
TABLAT
TBLPTR
MEMORY (01A357h)
MEMORY (01A358h)
After Instruction
TABLAT
TBLPTR
*+ ;
=
=
=
=
AAh
01A357h
12h
34h
=
=
34h
01A358h
10nn
nn=0 *
=1 *+
=2 *=3 +*
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
operation
No
operation
No
operation
No
operation
No operation
(Read Program
Memory)
No
operation
No operation
(Write TABLAT)
Preliminary
DS39631A-page 305
PIC18F2420/2520/4420/4520
TBLWT
Table Write
TBLWT
Syntax:
Example1:
TBLWT *+;
Operands:
None
Operation:
if TBLWT*,
(TABLAT) Holding Register;
TBLPTR No Change;
if TBLWT*+,
(TABLAT) Holding Register;
(TBLPTR) + 1 TBLPTR;
if TBLWT*-,
(TABLAT) Holding Register;
(TBLPTR) 1 TBLPTR;
if TBLWT+*,
(TBLPTR) + 1 TBLPTR;
(TABLAT) Holding Register;
Status Affected:
Before Instruction
TABLAT
=
55h
TBLPTR
=
00A356h
HOLDING REGISTER
(00A356h)
=
FFh
After Instructions (table write completion)
TABLAT
=
55h
TBLPTR
=
00A357h
HOLDING REGISTER
(00A356h)
=
55h
Example 2:
None
Encoding:
0000
0000
0000
11nn
nn=0 *
=1 *+
=2 *=3 +*
Description:
Words:
Cycles:
TBLWT +*;
Before Instruction
TABLAT
=
34h
TBLPTR
=
01389Ah
HOLDING REGISTER
(01389Ah)
=
FFh
HOLDING REGISTER
(01389Bh)
=
FFh
After Instruction (table write completion)
TABLAT
=
34h
TBLPTR
=
01389Bh
HOLDING REGISTER
(01389Ah)
=
FFh
HOLDING REGISTER
(01389Bh)
=
34h
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
No
No
No
operation operation operation
No
No
No
No
operation operation operation operation
(Write to
(Read
Holding
TABLAT)
Register )
DS39631A-page 306
Preliminary
PIC18F2420/2520/4420/4520
TSTFSZ
Test f, skip if 0
XORLW
Syntax:
TSTFSZ f {,a}
Syntax:
XORLW k
Operands:
0 f 255
a [0,1]
Operands:
0 k 255
Operation:
(W) .XOR. k W
Status Affected:
N, Z
Operation:
skip if f = 0
Status Affected:
None
Encoding:
Encoding:
0110
Description:
011a
ffff
ffff
Words:
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
0000
1010
kkkk
kkkk
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal k
Process
Data
Write to W
Example:
XORLW
0AFh
Before Instruction
W
=
After Instruction
W
B5h
1Ah
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
No
operation
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip:
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
NZERO
ZERO
Before Instruction
PC
After Instruction
If CNT
PC
If CNT
PC
TSTFSZ
:
:
CNT, 1
Address (HERE)
=
=
00h,
Address (ZERO)
00h,
Address (NZERO)
Preliminary
DS39631A-page 307
PIC18F2420/2520/4420/4520
XORWF
Exclusive OR W with f
Syntax:
XORWF
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
Status Affected:
N, Z
Encoding:
0001
f {,d {,a}}
10da
ffff
ffff
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
Example:
XORWF
Before Instruction
REG
=
W
=
After Instruction
REG
=
W
=
DS39631A-page 308
REG, 1, 0
AFh
B5h
1Ah
B5h
Preliminary
PIC18F2420/2520/4420/4520
24.2
A summary of the instructions in the extended instruction set is provided in Table 24-3. Detailed descriptions
are provided in Section 24.2.2 Extended Instruction
Set. The opcode field descriptions in Table 24-1
(page 268) apply to both the standard and extended
PIC18 instruction sets.
Note:
24.2.1
Most of the extended instructions use indexed arguments, using one of the File Select Registers and some
offset to specify a source or destination register. When
an argument for an instruction serves as part of
indexed addressing, it is enclosed in square brackets
([ ]). This is done to indicate that the argument is used
as an index or offset. MPASM Assembler will flag an
error if it determines that an index or offset value is not
bracketed.
TABLE 24-3:
Note:
Mnemonic,
Operands
ADDFSR
ADDULNK
CALLW
MOVSF
f, k
k
MOVSS
zs, zd
PUSHL
SUBFSR
SUBULNK
f, k
k
zs, fd
Description
Cycles
MSb
1
2
2
2
LSb
Status
Affected
1000
1000
0000
1011
ffff
1011
xxxx
1010
ffkk
11kk
0001
0zzz
ffff
1zzz
xzzz
kkkk
kkkk
kkkk
0100
zzzz
ffff
zzzz
zzzz
kkkk
None
None
None
None
1110
1110
0000
1110
1111
1110
1111
1110
1
2
1110
1110
1001
1001
ffkk
11kk
kkkk
kkkk
None
None
Preliminary
None
None
DS39631A-page 309
PIC18F2420/2520/4420/4520
24.2.2
ADDFSR
ADDULNK
Syntax:
ADDFSR f, k
Syntax:
ADDULNK k
Operands:
0 k 63
f [ 0, 1, 2 ]
Operands:
0 k 63
Operation:
FSR(f) + k FSR(f)
Status Affected:
None
Encoding:
1110
FSR2 + k FSR2,
Operation:
(TOS) PC
Status Affected:
1000
ffkk
kkkk
Description:
Words:
Cycles:
None
Encoding:
1110
Q1
Q2
Q3
Q4
Read
literal k
Process
Data
Write to
FSR
Example:
ADDFSR 2, 23h
Before Instruction
FSR2
=
03FFh
After Instruction
FSR2
=
0422h
kkkk
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal k
Process
Data
Write to
FSR
No
Operation
No
Operation
No
Operation
No
Operation
Example:
Note:
11kk
Q Cycle Activity:
Decode
1000
Description:
ADDULNK 23h
Before Instruction
FSR2
=
PC
=
03FFh
0100h
After Instruction
FSR2
=
PC
=
0422h
(TOS)
All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s).
DS39631A-page 310
Preliminary
PIC18F2420/2520/4420/4520
CALLW
MOVSF
Syntax:
CALLW
Syntax:
MOVSF [zs], fd
Operands:
None
Operands:
Operation:
(PC + 2) TOS,
(W) PCL,
(PCLATH) PCH,
(PCLATU) PCU
0 zs 127
0 fd 4095
Operation:
((FSR2) + zs) fd
Status Affected:
None
Status Affected:
None
Encoding:
0000
0000
0001
0100
Description
Words:
Cycles:
Move Indexed to f
Encoding:
1st word (source)
2nd word (destin.)
Q1
Q2
Q3
Q4
Read
WREG
PUSH PC to
stack
No
operation
No
operation
No
operation
No
operation
No
operation
HERE
Before Instruction
PC
=
PCLATH =
PCLATU =
W
=
After Instruction
PC
=
TOS
=
PCLATH =
PCLATU =
W
=
Cycles:
Q Cycle Activity:
Q1
Decode
address (HERE)
10h
00h
06h
zzzzs
ffffd
Words:
CALLW
001006h
address (HERE + 2)
10h
00h
06h
0zzz
ffff
Decode
Example:
1011
ffff
Description:
Q Cycle Activity:
Decode
1110
1111
Q2
Q3
Determine
Determine
source addr source addr
No
operation
No
operation
No dummy
read
Example:
MOVSF
Before Instruction
FSR2
Contents
of 85h
REG2
After Instruction
FSR2
Contents
of 85h
REG2
Preliminary
Q4
Read
source reg
Write
register f
(dest)
[05h], REG2
80h
=
=
33h
11h
80h
=
=
33h
33h
DS39631A-page 311
PIC18F2420/2520/4420/4520
MOVSS
PUSHL
Syntax:
Syntax:
PUSHL k
Operands:
Operands:
0 k 255
Operation:
Operation:
k (FSR2),
FSR2 1 FSR2
Status Affected:
None
Status Affected:
None
Encoding:
1st word (source)
2nd word (dest.)
1110
1111
Description
1011
xxxx
1zzz
xzzz
zzzzs
zzzzd
Words:
Cycles:
Encoding:
1111
1010
kkkk
kkkk
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read k
Process
data
Write to
destination
Example:
PUSHL 08h
Before Instruction
FSR2H:FSR2L
Memory (01ECh)
=
=
01ECh
00h
After Instruction
FSR2H:FSR2L
Memory (01ECh)
=
=
01EBh
08h
Q Cycle Activity:
Q1
Decode
Decode
Q2
Q3
Determine
Determine
source addr source addr
Determine
dest addr
Example:
Write
to dest reg
Before Instruction
FSR2
Contents
of 85h
Contents
of 86h
After Instruction
FSR2
Contents
of 85h
Contents
of 86h
DS39631A-page 312
Determine
dest addr
Q4
Read
source reg
80h
33h
11h
80h
33h
33h
Preliminary
PIC18F2420/2520/4420/4520
SUBFSR
SUBULNK
Syntax:
SUBFSR f, k
Syntax:
SUBULNK k
Operands:
0 k 63
Operands:
0 k 63
f [ 0, 1, 2 ]
Operation:
Operation:
FSR(f) k FSRf
Status Affected:
None
Encoding:
1110
FSR2 k FSR2
(TOS) PC
ffkk
kkkk
Description:
Words:
Cycles:
Encoding:
1110
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
SUBFSR 2, 23h
1001
11kk
kkkk
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
Q Cycle Activity:
Before Instruction
FSR2
=
Q1
Q2
Q3
Q4
03FFh
Decode
After Instruction
FSR2
=
Read
register f
Process
Data
Write to
destination
03DCh
No
Operation
No
Operation
No
Operation
No
Operation
Example:
Preliminary
SUBULNK 23h
Before Instruction
FSR2
=
PC
=
03FFh
0100h
After Instruction
FSR2
=
PC
=
03DCh
(TOS)
DS39631A-page 313
PIC18F2420/2520/4420/4520
24.2.3
Note:
BYTE-ORIENTED AND
BIT-ORIENTED INSTRUCTIONS IN
INDEXED LITERAL OFFSET MODE
Enabling the PIC18 instruction set
extension may cause legacy applications
to behave erratically or fail entirely.
DS39631A-page 314
24.2.3.1
24.2.4
CONSIDERATIONS WHEN
ENABLING THE EXTENDED
INSTRUCTION SET
It is important to note that the extensions to the instruction set may not be beneficial to all users. In particular,
users who are not writing code that uses a software
stack may not benefit from using the extensions to the
instruction set.
Additionally, the Indexed Literal Offset Addressing
mode may create issues with legacy applications
written to the PIC18 assembler. This is because
instructions in the legacy code may attempt to address
registers in the Access Bank below 5Fh. Since these
addresses are interpreted as literal offsets to FSR2
when the instruction set extension is enabled, the
application may read or write to the wrong data
addresses.
When porting an application to the PIC18F2420/2520/
4420/4520, it is very important to consider the type of
code. A large, re-entrant application that is written in C
and would benefit from efficient compilation will do well
when using the instruction set extensions. Legacy
applications that heavily use the Access Bank will most
likely not benefit from using the extended instruction
set.
Preliminary
PIC18F2420/2520/4420/4520
ADDWF
ADD W to Indexed
(Indexed Literal Offset mode)
BSF
Syntax:
ADDWF
Syntax:
BSF [k], b
Operands:
0 k 95
d [0,1]
Operands:
0 f 95
0b7
Operation:
Operation:
1 ((FSR2) + k)<b>
Status Affected:
N, OV, C, DC, Z
Status Affected:
None
Encoding:
[k] {,d}
0010
Description:
01d0
kkkk
kkkk
Encoding:
1000
bbb0
kkkk
kkkk
Description:
Words:
Cycles:
Q Cycle Activity:
Words:
Q1
Q2
Q3
Q4
Cycles:
Decode
Read
register f
Process
Data
Write to
destination
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read k
Process
Data
Write to
destination
Example:
ADDWF
Example:
Before Instruction
FLAG_OFST
FSR2
Contents
of 0A0Ah
After Instruction
Contents
of 0A0Ah
[OFST] , 0
Before Instruction
W
OFST
FSR2
Contents
of 0A2Ch
After Instruction
W
Contents
of 0A2Ch
=
=
=
17h
2Ch
0A00h
20h
37h
20h
BSF
[FLAG_OFST], 7
=
=
0Ah
0A00h
55h
D5h
Set Indexed
(Indexed Literal Offset mode)
SETF
Syntax:
SETF [k]
Operands:
0 k 95
Operation:
FFh ((FSR2) + k)
Status Affected:
None
Encoding:
0110
1000
kkkk
kkkk
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read k
Process
Data
Write
register
Example:
SETF
Before Instruction
OFST
FSR2
Contents
of 0A2Ch
After Instruction
Contents
of 0A2Ch
Preliminary
[OFST]
=
=
2Ch
0A00h
00h
FFh
DS39631A-page 315
PIC18F2420/2520/4420/4520
24.2.5
DS39631A-page 316
Preliminary
PIC18F2420/2520/4420/4520
25.0
DEVELOPMENT SUPPORT
25.1
25.2
MPASM Assembler
Preliminary
DS39631A-page 317
PIC18F2420/2520/4420/4520
25.3
25.6
25.4
25.5
DS39631A-page 318
25.7
The MPLAB SIM software simulator allows code development in a PC hosted environment by simulating the
PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user defined key press, to any pin. The execution can be performed in Single-Step, Execute Until
Break or Trace mode.
The MPLAB SIM simulator fully supports symbolic
debugging using the MPLAB C17 and MPLAB C18
C Compilers, as well as the MPASM assembler. The
software simulator offers the flexibility to develop and
debug code outside of the laboratory environment,
making it an excellent, economical software
development tool.
25.8
Preliminary
PIC18F2420/2520/4420/4520
25.9
Preliminary
DS39631A-page 319
PIC18F2420/2520/4420/4520
25.14 PICSTART Plus Development
Programmer
DS39631A-page 320
Preliminary
PIC18F2420/2520/4420/4520
25.20 PICDEM 17 Demonstration Board
The PICDEM 17 demonstration board is an evaluation
board that demonstrates the capabilities of several
Microchip microcontrollers, including PIC17C752,
PIC17C756A, PIC17C762 and PIC17C766. A programmed sample is included. The PRO MATE II device
programmer, or the PICSTART Plus development programmer, can be used to reprogram the device for user
tailored application development. The PICDEM 17
demonstration board supports program download and
execution from external on-board Flash memory. A
generous prototype area is available for user hardware
expansion.
Preliminary
DS39631A-page 321
PIC18F2420/2520/4420/4520
NOTES:
DS39631A-page 322
Preliminary
PIC18F2420/2520/4420/4520
26.0
ELECTRICAL CHARACTERISTICS
Preliminary
DS39631A-page 323
PIC18F2420/2520/4420/4520
FIGURE 26-1:
6.0V
5.5V
Voltage
5.0V
PIC18FX42X/X52X
4.5V
4.2V
4.0V
3.5V
3.0V
2.5V
2.0V
40 MHz
Frequency
FIGURE 26-2:
6.0V
5.5V
5.0V
PIC18LFX42X/X52X
Voltage
4.5V
4.2V
4.0V
3.5V
3.0V
2.5V
2.0V
40 MHz
4 MHz
Frequency
FMAX = (16.36 MHz/V) (VDDAPPMIN 2.0V) + 4 MHz
Note: VDDAPPMIN is the minimum voltage of the PICmicro device in the application.
DS39631A-page 324
Preliminary
PIC18F2420/2520/4420/4520
26.1
PIC18LFX42X/X52X
(Industrial)
PIC18FX42X/X52X
(Industrial)
Param
Symbol
No.
Characteristic
Min
Typ
Max
Units
D001
VDD
Supply Voltage
2.0
5.5
D002
VDR
1.5
D003
VPOR
0.7
D004
SVDD
0.05
D005
VBOR
Conditions
HS, XT, RC and LP Oscillator modes
BORV1:BORV0 = 11
1.94
2.05
2.16
BORV1:BORV0 = 10
2.65
2.79
2.93
BORV1:BORV0 = 01
4.11
4.33
4.55
BORV1:BORV0 = 00
4.36
4.59
4.82
Preliminary
DS39631A-page 325
PIC18F2420/2520/4420/4520
26.2
PIC18LFX42X/X52X
(Industrial)
PIC18FX42X/X52X
(Industrial)
ParamNo.
Device
Power-down Current (IPD)
PIC18LFX42X/X52X
Legend:
Note 1:
2:
3:
4:
5:
Typ
Max
Units
Conditions
(1)
20
950
nA
-40C
0.02
1.0
+25C
0.6
1.1
+85C
PIC18LFX42X/X52X 0.03
1.4
-40C
0.03
1.5
+25C
+85C
0.8
1.6
1.9
-40C
0.04
2.0
+25C
1.7
2.1
+85C
VDD = 2.0V,
(Sleep mode)
VDD = 3.0V,
(Sleep mode)
VDD = 5.0V,
(Sleep mode)
DS39631A-page 326
Preliminary
PIC18F2420/2520/4420/4520
26.2
PIC18LFX42X/X52X
(Industrial)
PIC18FX42X/X52X
(Industrial)
ParamNo.
Device
Supply Current (IDD)
Typ
Max
Units
PIC18LFX42X/X52X
PIC18LFX42X/X52X
All devices
15
31.5
-40C
15
30
+25C
15
28.5
+85C
40
63
-40C
35
60
+25C
+85C
30
57
105
168
-40C
90
160
+25C
+85C
152
PIC18LFX42X/X52X 0.32
630
-40C
0.33
600
+25C
0.33
570
+85C
0.6
1.3
mA
-40C
0.55
1.2
mA
+25C
0.6
1.1
mA
+85C
1.1
2.3
mA
-40C
1.1
2.2
mA
+25C
1.0
2.1
mA
+85C
80
PIC18LFX42X/X52X
All devices
Legend:
Note 1:
2:
3:
4:
5:
Conditions
(2,3)
VDD = 2.0V
VDD = 3.0V
FOSC = 31 kHz
(RC_RUN mode,
INTRC source)
VDD = 5.0V
VDD = 2.0V
VDD = 3.0V
FOSC = 1 MHz
(RC_RUN mode,
INTOSC source)
VDD = 5.0V
Preliminary
DS39631A-page 327
PIC18F2420/2520/4420/4520
26.2
PIC18LFX42X/X52X
(Industrial)
PIC18FX42X/X52X
(Industrial)
ParamNo.
Device
Supply Current (IDD)
PIC18LFX42X/X52X
PIC18LFX42X/X52X
All devices
PIC18LFX42X/X52X
PIC18LFX42X/X52X
All devices
Legend:
Note 1:
2:
3:
4:
5:
Typ
Max
Units
Conditions
0.8
2.1
-40C
(2,3)
0.8
2.0
+25C
0.8
1.9
+85C
1.3
2.7
mA
-40C
1.3
2.6
mA
+25C
1.3
2.5
mA
+85C
2.5
5.3
mA
-40C
2.5
5.0
mA
+25C
2.5
4.8
mA
+85C
2.9
6.5
-40C
3.1
6.2
+25C
+85C
3.6
5.9
4.5
10.1
-40C
4.8
9.6
+25C
5.8
9.1
+85C
9.2
15.8
-40C
9.8
15
+25C
11.4
14.3
+85C
VDD = 2.0V
VDD = 3.0V
FOSC = 4 MHz
(RC_RUN mode,
INTRC source)
VDD = 5.0V
VDD = 2.0V
VDD = 3.0V
FOSC = 31 kHz
(RC_IDLE mode,
INTRC source)
VDD = 5.0V
DS39631A-page 328
Preliminary
PIC18F2420/2520/4420/4520
26.2
PIC18LFX42X/X52X
(Industrial)
PIC18FX42X/X52X
(Industrial)
ParamNo.
Device
Supply Current (IDD)
Typ
PIC18LFX42X/X52X
PIC18LFX42X/X52X
All devices
PIC18LFX42X/X52X
PIC18LFX42X/X52X
All devices
Legend:
Note 1:
2:
3:
4:
5:
Max
Units
Conditions
(2,3)
165
315
-40C
175
300
+25C
190
285
+85C
250
470
-40C
270
450
+25C
290
430
+85C
500
840
-40C
520
800
+25C
550
760
+85C
340
525
-40C
350
500
+25C
360
475
+85C
520
735
-40C
540
700
+25C
580
665
+85C
1.0
1.6
mA
-40C
1.1
1.5
mA
+25C
1.1
1.4
mA
+85C
VDD = 2.0V
VDD = 3.0V
FOSC = 1 MHz
(RC_IDLE mode,
INTOSC source)
VDD = 5.0V
VDD = 2.0V
VDD = 3.0V
FOSC = 4 MHz
(RC_IDLE mode,
INTOSC source)
VDD = 5.0V
Preliminary
DS39631A-page 329
PIC18F2420/2520/4420/4520
26.2
PIC18LFX42X/X52X
(Industrial)
PIC18FX42X/X52X
(Industrial)
ParamNo.
Device
Supply Current (IDD)
Typ
PIC18LFX42X/X52X
PIC18LFX42X/X52X
All devices
5:
420
-40C
260
400
+25C
250
380
+85C
550
740
-40C
480
700
+25C
460
670
+85C
1.2
1.6
mA
-40C
1.1
1.5
mA
+25C
+85C
1.4
mA
mA
-40C
0.74
1.5
mA
+25C
All devices
4:
250
1.6
All devices
3:
Conditions
1.0
All devices
2:
Units
PIC18LFX42X/X52X 0.72
PIC18LFX42X/X52X
Legend:
Note 1:
Max
(2,3)
0.74
1.4
mA
+85C
1.3
2.6
mA
-40C
1.3
2.5
mA
+25C
1.3
2.4
mA
+85C
2.7
4.7
mA
-40C
2.6
4.5
mA
+25C
2.5
4.3
mA
+85C
15
26
mA
-40C
16
25
mA
+25C
16
24
mA
+85C
21
32
mA
-40C
21
30
mA
+25C
21
28
mA
+85C
VDD = 2.0V
VDD = 3.0V
FOSC = 1 MHZ
(PRI_RUN,
EC oscillator)
VDD = 5.0V
VDD = 2.0V
VDD = 3.0V
FOSC = 4 MHz
(PRI_RUN,
EC oscillator)
VDD = 5.0V
VDD = 4.2V
FOSC = 40 MHZ
(PRI_RUN,
EC oscillator)
VDD = 5.0V
DS39631A-page 330
Preliminary
PIC18F2420/2520/4420/4520
26.2
PIC18LFX42X/X52X
(Industrial)
PIC18FX42X/X52X
(Industrial)
ParamNo.
Device
Supply Current (IDD)
All devices
All devices
All devices
All devices
Legend:
Note 1:
2:
3:
4:
5:
Typ
Max
Units
Conditions
7.5
16
mA
-40C
7.4
15
mA
+25C
7.3
14
mA
+85C
(2,3)
10
21
mA
-40C
10
20
mA
+25C
9.7
19
mA
+85C
17
35
mA
-40C
17
34
mA
+25C
17
33
mA
+85C
23
46
mA
-40C
23
45
mA
+25C
23
43
mA
+85C
VDD = 4.2V
FOSC = 4 MHZ
(PRI_RUN HS+PLL)
VDD = 5.0V
FOSC = 4 MHZ
(PRI_RUN HS+PLL)
VDD = 4.2V
FOSC = 10 MHZ
(PRI_RUN HS+PLL)
VDD = 5.0V
FOSC = 10 MHZ
(PRI_RUN HS+PLL)
Preliminary
DS39631A-page 331
PIC18F2420/2520/4420/4520
26.2
PIC18LFX42X/X52X
(Industrial)
PIC18FX42X/X52X
(Industrial)
ParamNo.
Device
Supply Current (IDD)
PIC18LFX42X/X52X
PIC18LFX42X/X52X
All devices
PIC18LFX42X/X52X
PIC18LFX42X/X52X
All devices
All devices
All devices
Legend:
Note 1:
2:
3:
4:
5:
Typ
Max
Units
Conditions
65
130
-40C
65
120
+25C
70
115
+85C
120
270
-40C
120
250
+25C
130
240
+85C
300
480
-40C
240
450
+25C
+85C
(2,3)
300
430
260
475
-40C
255
450
+25C
270
430
+85C
420
900
-40C
430
850
+25C
450
810
+85C
0.9
1.5
mA
-40C
0.9
1.4
mA
+25C
0.9
1.3
mA
+85C
6.0
9.5
mA
-40C
6.2
9.0
mA
+25C
6.6
8.6
mA
+85C
8.1
12.6
mA
-40C
9.1
12.0
mA
+25C
8.3
11.4
mA
+85C
VDD = 2.0V
FOSC = 1 MHz
(PRI_IDLE mode,
EC oscillator)
VDD = 3.0V
VDD = 5.0V
VDD = 2.0V
FOSC = 4 MHz
(PRI_IDLE mode,
EC oscillator)
VDD = 3.0V
VDD = 5.0V
VDD = 4.2 V
FOSC = 40 MHz
(PRI_IDLE mode,
EC oscillator)
VDD = 5.0V
DS39631A-page 332
Preliminary
PIC18F2420/2520/4420/4520
26.2
PIC18LFX42X/X52X
(Industrial)
PIC18FX42X/X52X
(Industrial)
ParamNo.
Device
Supply Current
PIC18LFX42X/X52X
PIC18LFX42X/X52X
All devices
PIC18LFX42X/X52X
PIC18LFX42X/X52X
All devices
Legend:
Note 1:
2:
3:
4:
5:
Typ
Max
Units
Conditions
14
31.5
-10C
15
30
+25C
16
29
+70C
40
74
-10C
35
70
+25C
31
67
+70C
99
126
-10C
81
120
+25C
+70C
(IDD)(2,3)
75
114
2.5
7.4
-10C
3.7
7.0
+25C
4.5
6.7
+70C
5.0
10.5
-10C
5.4
10
+25C
6.3
9.5
+70C
8.5
17
-10C
9.0
16
+25C
10.5
15
+70C
VDD = 2.0V
VDD = 3.0V
FOSC = 32 kHz(4)
(SEC_RUN mode,
Timer1 as clock)
VDD = 5.0V
VDD = 2.0V
VDD = 3.0V
FOSC = 32 kHz(4)
(SEC_IDLE mode,
Timer1 as clock)
VDD = 5.0V
Preliminary
DS39631A-page 333
PIC18F2420/2520/4420/4520
26.2
PIC18LFX42X/X52X
(Industrial)
PIC18FX42X/X52X
(Industrial)
ParamNo.
Device
Typ
Max
Units
Conditions
D022A
(IBOR)
D022B
(ILVD)
D025
(IOSCB)
Watchdog Timer
Brown-out Reset(5)
3:
4:
5:
-40C
1.4
8.0
+25C
2.0
8.4
+85C
1.9
11.4
-40C
2.0
12.0
+25C
2.8
12.6
+85C
4.0
14.3
-40C
5.5
15.0
+25C
5.6
15.8
+85C
VDD = 2.0V
VDD = 3.0V
VDD = 5.0V
35
52
-40C to +85C
VDD = 3.0V
63
-40C to +85C
VDD = 5.0V
40
63
-40C to +85C
VDD = 5.0V
22
47
-40C to +85C
25
58
-40C to +85C
VDD = 3.0V
29
69
-40C to +85C
VDD = 5.0V
4.8
-10C
0.01
5.0
+25C
0.01
5.3
+70C
0.01
7.6
-10C
0.01
8.0
+25C
0.01
8.4
+70C
0.01
9.5
-10C
0.01
10.0
+25C
0.01
10.5
+70C
1.0
2.0
VDD = 2.0V
1.0
2.0
VDD = 3.0V
1.0
2.0
VDD = 5.0V
High/Low-Voltage
Detect(5)
A/D Converter
2:
7.6
40
D026
(IAD)
Legend:
Note 1:
1.3
Sleep mode,
BOREN1:BOREN0 = 10
VDD = 2.0V
VDD = 2.0V
32 kHz on Timer1(4)
VDD = 3.0V
32 kHz on Timer1(4)
VDD = 5.0V
32 kHz on Timer1(4)
DS39631A-page 334
Preliminary
PIC18F2420/2520/4420/4520
26.3
DC CHARACTERISTICS
Param
Symbol
No.
VIL
Characteristic
Min
Max
Units
Conditions
VSS
0.15 VDD
0.8
VSS
VSS
0.2 VDD
0.3 VDD
V
V
D030
D030A
D031
D032
MCLR
VSS
0.2 VDD
D033
OSC1
VSS
0.3 VDD
D033A
D033B
D034
OSC1
OSC1
T13CKI
VSS
VSS
VSS
0.2 VDD
0.3 VDD
0.3 VDD
V
V
V
RC, EC modes(1)
XT, LP modes
VDD
2.0
VDD
0.8 VDD
0.7 VDD
VDD
VDD
V
V
0.8 VDD
VDD
VIH
D040
D040A
D041
D042
MCLR
D043
OSC1
0.7 VDD
VDD
D043A
D043B
D043C
D044
OSC1
OSC1
OSC1
T13CKI
0.8 VDD
0.9 VDD
1.6
1.6
VDD
VDD
VDD
VDD
V
V
V
V
EC mode
RC mode(1)
XT, LP modes
IIL
D060
I/O ports
D061
MCLR
OSC1
50
400
D063
D070
Note 1:
2:
3:
4:
IPU
IPURB
In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the
PICmicro device be driven with an external clock while in RC mode.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
Negative current is defined as current sourced by the pin.
Parameter is characterized but not tested.
Preliminary
DS39631A-page 335
PIC18F2420/2520/4420/4520
26.3
DC CHARACTERISTICS
Param
Symbol
No.
VOL
Characteristic
Min
Max
Units
Conditions
D080
I/O ports
0.6
D083
OSC2/CLKO
(RC, RCIO, EC, ECIO modes)
0.6
VOH
D090
I/O ports
VDD 0.7
D092
OSC2/CLKO
(RC, RCIO, EC, ECIO modes)
VDD 0.7
OSC2 pin
15
pF
D101
CIO
50
pF
D102
CB
SCL, SDA
400
pF
I2C Specification
Note 1:
2:
3:
4:
In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the
PICmicro device be driven with an external clock while in RC mode.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
Negative current is defined as current sourced by the pin.
Parameter is characterized but not tested.
DS39631A-page 336
Preliminary
PIC18F2420/2520/4420/4520
TABLE 26-1:
DC CHARACTERISTICS
Param
No.
Sym
Characteristic
Min
Typ
Max
Units
Conditions
9.00
13.25
10
mA
VPP
D113
IDDP
D120
ED
Byte Endurance
100K
1M
D121
VDRW
VMIN
5.5
(Note 3)
D122
TDEW
D123
40
ms
D124
TREF
1M
10M
D130
EP
Cell Endurance
10K
100K
D131
VPR
VMIN
5.5
D132
VIE
4.5
5.5
D132A VIW
4.5
5.5
D132B VPEW
VMIN
5.5
D133
TIE
ms
D133A
TIW
ms
D133A TIW
D134
40
100
ms
Year Provided no other
specifications are violated
Data in Typ column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: These specifications are for programming the on-chip program memory through the use of table write
instructions.
2: Refer to Section 7.8 Using the Data EEPROM for a more detailed discussion on data EEPROM
endurance.
3: Required only if single-supply programming is disabled.
Preliminary
DS39631A-page 337
PIC18F2420/2520/4420/4520
TABLE 26-2:
COMPARATOR SPECIFICATIONS
Operating Conditions: 3.0V < VDD < 5.5V, -40C < TA < +85C (unless otherwise stated).
Param
No.
Sym
Characteristics
Min
Typ
Max
Units
D300
VIOFF
5.0
10
mV
D301
VICM
VDD 1.5
Comments
D302
CMRR
55
dB
300
TRESP
Response Time(1)*
150
400
ns
PIC18FXXXX
150
600
ns
PIC18LFXXXX,
VDD = 2.0V
10
300A
301
*
Note 1:
TMC2OV
TABLE 26-3:
Operating Conditions: 3.0V < VDD < 5.5V, -40C < TA < +85C (unless otherwise stated).
Param
No.
D310
Sym
Characteristics
VRES
Resolution
Min
Typ
Max
Units
VDD/24
VDD/32
LSb
D311
VRAA
Absolute Accuracy
1/2
LSb
D312
VRUR
2k
310
TSET
Settling Time(1)*
10
*
Note 1:
Comments
DS39631A-page 338
Preliminary
PIC18F2420/2520/4420/4520
FIGURE 26-3:
VLVD
(HLVDIF set by hardware)
HLVDIF
TABLE 26-4:
Characteristic
Min
Typ
Max
Units
2.12
2.17
2.22
2.18
2.23
2.28
LVV = 0010
2.31
2.36
2.42
LVV = 0011
2.38
2.44
2.49
LVV = 0100
2.54
2.60
2.66
LVV = 0101
2.72
2.79
2.85
LVV = 0110
2.82
2.89
2.95
LVV = 0111
3.05
3.12
3.19
LVV = 1000
3.31
3.39
3.47
LVV = 1001
3.46
3.55
3.63
LVV = 1010
3.63
3.71
3.80
LVV = 1011
3.81
3.90
3.99
LVV = 1100
4.01
4.11
4.20
LVV = 1101
4.23
4.33
4.43
LVV = 1110
4.48
4.59
4.69
Conditions
Production tested at TAMB = 25C. Specifications over temperature limits ensured by characterization.
Preliminary
DS39631A-page 339
PIC18F2420/2520/4420/4520
26.4
26.4.1
AC (Timing) Characteristics
TIMING PARAMETER SYMBOLOGY
DS39631A-page 340
3. TCC:ST
4. Ts
Time
osc
rd
rw
sc
ss
t0
t1
wr
OSC1
RD
RD or WR
SCK
SS
T0CKI
T13CKI
WR
P
R
V
Z
Period
Rise
Valid
High-impedance
High
Low
High
Low
SU
Setup
STO
Stop condition
Preliminary
PIC18F2420/2520/4420/4520
26.4.2
TIMING CONDITIONS
Note:
TABLE 26-5:
AC CHARACTERISTICS
FIGURE 26-4:
Load Condition 2
VDD/2
RL
CL
Pin
VSS
CL
Pin
RL = 464
VSS
CL = 50 pF
Preliminary
DS39631A-page 341
PIC18F2420/2520/4420/4520
26.4.3
FIGURE 26-5:
Q1
Q2
Q3
Q4
Q1
OSC1
1
CLKO
TABLE 26-6:
Param.
No.
1A
Symbol
FOSC
TOSC
Characteristic
Min
Max
DC
40
MHz
Oscillator Frequency(1)
DC
MHz
RC Oscillator mode
MHz
XT Oscillator mode
25
MHz
HS Oscillator mode
10
MHz
33
kHz
LP Oscillator mode
25
ns
250
ns
RC Oscillator mode
250
10,000
ns
XT Oscillator mode
40
100
250
250
ns
ns
HS Oscillator mode
HS + PLL Oscillator mode
30
LP Oscillator mode
100
ns
TCY = 4/FOSC
30
ns
XT Oscillator mode
2.5
LP Oscillator mode
10
ns
HS Oscillator mode
Time(1)
TCY
Instruction Cycle
TOSL,
TOSH
Note 1:
0.1
Oscillator Period(1)
TOSR,
TOSF
Conditions
Units
20
ns
XT Oscillator mode
50
ns
LP Oscillator mode
7.5
ns
HS Oscillator mode
Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations
except PLL. All specified values are based on characterization data for that particular oscillator type under
standard operating conditions with the device executing code. Exceeding these specified limits may result
in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested
to operate at min. values with an external clock applied to the OSC1/CLKI pin. When an external clock
input is used, the max. cycle time limit is DC (no clock) for all devices.
DS39631A-page 342
Preliminary
PIC18F2420/2520/4420/4520
TABLE 26-7:
Param
No.
Sym
Characteristic
Min
Typ
Max
Units
Conditions
F10
10
F11
FSYS
16
40
F12
trc
ms
CLK
-2
+2
F13
Data in Typ column is at 5V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
TABLE 26-8:
PIC18LFX42X/X52X
(Industrial)
PIC18FX42X/X52X
(Industrial)
Param
No.
Device
Min
Typ
Max
Units
Conditions
INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz(1)
PIC18LFX42X/X52X
PIC18FX42X/X52X
-2
+/-1
+25C
VDD = 2.7-3.3V
-5
-10C to +85C
VDD = 2.7-3.3V
-10
+/-1
10
-40C to +85C
VDD = 2.7-3.3V
-2
+/-1
+25C
VDD = 4.5-5.5V
-5
-10C to +85C
VDD = 4.5-5.5V
-10
+/-1
10
-40C to +85C
VDD = 4.5-5.5V
PIC18LFX42X/X52X 26.562
35.938
kHz
-40C to +85C
VDD = 2.7-3.3V
PIC18FX42X/X52X 26.562
35.938
kHz
-40C to +85C
VDD = 4.5-5.5V
(2)
Legend:
Note 1:
2:
3:
Preliminary
DS39631A-page 343
PIC18F2420/2520/4420/4520
FIGURE 26-6:
Q4
Q2
Q3
OSC1
11
10
CLKO
13
19
14
12
18
16
I/O pin
(Input)
15
17
I/O pin
(Output)
Note:
20, 21
Refer to Figure 26-4 for load conditions.
TABLE 26-9:
Param
No.
New Value
Old Value
Symbol
Characteristic
Min
Typ
Max
Units Conditions
10
75
200
ns
(Note 1)
11
75
200
ns
(Note 1)
12
TckR
35
100
ns
(Note 1)
13
TckF
35
100
ns
(Note 1)
0.5 TCY + 20
ns
(Note 1)
0.25 TCY + 25
ns
(Note 1)
(Note 1)
14
TckL2ioV
15
16
TckH2ioI
17
18
TosH2ioI
18A
ns
50
150
ns
PIC18FXXXX
100
ns
PIC18LFXXXX
200
ns
19
ns
20
TioR
10
25
ns
TioF
22
TINP
23
TRBP
TCY
24
TRCP
20
20A
21
21A
PIC18FXXXX
PIC18LFXXXX
60
ns
PIC18FXXXX
10
25
ns
60
ns
TCY
ns
ns
PIC18LFXXXX
VDD = 2.0V
VDD = 2.0V
VDD = 2.0V
ns
These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC.
DS39631A-page 344
Preliminary
PIC18F2420/2520/4420/4520
FIGURE 26-7:
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
34
34
I/O pins
Note:
FIGURE 26-8:
VDD
35
VBGAP = 1.2V
VIRVST
Enable Internal
Reference Voltage
Internal Reference
Voltage Stable
36
TABLE 26-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
Symbol
No.
30
31
TmcL
TWDT
32
33
TOST
TPWRT
Characteristic
MCLR Pulse Width (low)
Watchdog Timer Time-out Period
(no postscaler)
Oscillation Start-up Timer Period
Power-up Timer Period
TIOZ
Min
Typ
Max
Units
4.00
TBD
s
ms
65.5
TBD
ms
Conditions
200
20
50
s
s
200
5
10
s
s
ms
VDD VLVD
Preliminary
DS39631A-page 345
PIC18F2420/2520/4420/4520
FIGURE 26-9:
41
40
42
T1OSO/T13CKI
46
45
47
48
TMR0 or
TMR1
Note:
Symbol
Characteristic
40
Tt0H
41
Tt0L
42
Tt0P
T0CKI Period
No prescaler
With prescaler
No prescaler
With prescaler
No prescaler
With prescaler
45
Tt1H
T13CKI
High Time
Tt1L
0.5 TCY + 20
ns
10
ns
0.5 TCY + 20
ns
10
ns
TCY + 10
ns
Greater of:
20 ns or
(TCY + 40)/N
ns
ns
10
ns
25
ns
Asynchronous PIC18FXXXX
30
ns
48
Units Conditions
0.5 TCY + 20
Synchronous, no prescaler
Asynchronous PIC18FXXXX
47
Max
Synchronous, PIC18FXXXX
with prescaler PIC18LFXXXX
PIC18LFXXXX
46
Min
ns
ns
10
ns
25
ns
30
ns
50
ns
VDD = 2.0V
Greater of:
20 ns or
(TCY + 40)/N
ns
N = prescale
value (1, 2, 4, 8)
Asynchronous
60
ns
Ft1
DC
50
kHz
2 TOSC
7 TOSC
Preliminary
VDD = 2.0V
50
T13CKI
Synchronous
Input Period
DS39631A-page 346
VDD = 2.0V
0.5 TCY + 5
Tt1P
N = prescale
value
(1, 2, 4,..., 256)
VDD = 2.0V
PIC18F2420/2520/4420/4520
FIGURE 26-10:
50
51
52
CCPx
(Compare or PWM Mode)
54
53
Note:
51
TccL
TccH
Characteristic
Min
Max
Units
0.5 TCY + 20
ns
10
ns
20
ns
CCPx Input
High Time
0.5 TCY + 20
ns
No prescaler
With
prescaler
52
TccP
53
TccR
54
TccF
Conditions
VDD = 2.0V
PIC18FXXXX
10
ns
PIC18LFXXXX
20
ns
VDD = 2.0V
3 TCY + 40
N
ns
N = prescale
value (1, 4 or 16)
PIC18FXXXX
25
ns
PIC18LFXXXX
45
ns
PIC18FXXXX
25
ns
PIC18LFXXXX
45
ns
Preliminary
VDD = 2.0V
VDD = 2.0V
DS39631A-page 347
PIC18F2420/2520/4420/4520
FIGURE 26-11:
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
62
64
63
Note:
Symbol
Characteristic
62
TdtV2wrH
63
TwrH2dtI
WR or CS to DataIn
Invalid (hold time)
Min
Max
Units
20
ns
PIC18FXXXX
20
ns
PIC18LFXXXX
35
ns
80
ns
ns
TrdL2dtV
65
TrdH2dtI
RD or CS to DataOut Invalid
10
30
66
TibfINH
3 TCY
64
DS39631A-page 348
Preliminary
Conditions
VDD = 2.0V
PIC18F2420/2520/4420/4520
FIGURE 26-12:
SS
70
SCK
(CKP = 0)
71
72
78
79
79
78
SCK
(CKP = 1)
80
bit 6 - - - - - -1
MSb
SDO
LSb
75, 76
SDI
MSb In
bit 6 - - - -1
LSb In
74
73
Note:
Symbol
Characteristic
70
TssL2scH,
TssL2scL
71
TscH
71A
72
TscL
72A
Min
Max Units
TCY
ns
Continuous
1.25 TCY + 30
ns
Single Byte
40
ns
Continuous
1.25 TCY + 30
ns
Single Byte
40
ns
100
ns
1.5 TCY + 40
ns
100
ns
25
ns
73
TdiV2scH,
TdiV2scL
73A
Tb2b
74
TscH2diL,
TscL2diL
75
TdoR
76
TdoF
78
TscR
PIC18FXXXX
PIC18LFXXXX
45
ns
25
ns
PIC18FXXXX
25
ns
PIC18LFXXXX
45
ns
79
TscF
25
ns
80
TscH2doV,
TscL2doV
PIC18FXXXX
50
ns
PIC18LFXXXX
100
ns
Note 1:
2:
Conditions
(Note 1)
(Note 1)
(Note 2)
VDD = 2.0V
VDD = 2.0V
VDD = 2.0V
Preliminary
DS39631A-page 349
PIC18F2420/2520/4420/4520
FIGURE 26-13:
SS
81
SCK
(CKP = 0)
71
72
79
73
SCK
(CKP = 1)
80
78
MSb
SDO
bit 6 - - - - - -1
LSb
bit 6 - - - -1
LSb In
75, 76
SDI
MSb In
74
Note:
Symbol
Characteristic
TscH
TscL
73
TdiV2scH,
TdiV2scL
73A
Tb2b
74
TscH2diL,
TscL2diL
75
TdoR
76
TdoF
78
TscR
71A
72
72A
Continuous
Min
Max Units
1.25 TCY + 30
ns
Single Byte
40
ns
Continuous
1.25 TCY + 30
ns
Single Byte
PIC18FXXXX
40
ns
100
ns
1.5 TCY + 40
ns
100
ns
25
ns
45
ns
25
ns
25
ns
45
ns
PIC18LFXXXX
PIC18FXXXX
PIC18LFXXXX
79
TscF
25
ns
80
TscH2doV,
TscL2doV
50
ns
100
ns
81
TdoV2scH,
TdoV2scL
ns
Note 1:
2:
PIC18FXXXX
PIC18LFXXXX
TCY
Conditions
(Note 1)
(Note 1)
(Note 2)
VDD = 2.0V
VDD = 2.0V
VDD = 2.0V
DS39631A-page 350
Preliminary
PIC18F2420/2520/4420/4520
FIGURE 26-14:
SS
70
SCK
(CKP = 0)
83
71
72
78
79
79
78
SCK
(CKP = 1)
80
MSb
SDO
bit 6 - - - - - -1
LSb
77
75, 76
MSb In
SDI
73
Note:
bit 6 - - - -1
LSb In
74
TABLE 26-16: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
Param
No.
Symbol
Characteristic
70
71
TscH
71A
72
TscL
72A
Min
TCY
ns
Continuous
1.25 TCY + 30
ns
Single Byte
40
ns
Continuous
1.25 TCY + 30
ns
Single Byte
40
ns
100
ns
73A
Tb2b
74
75
TdoR
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40
PIC18FXXXX
ns
100
ns
25
ns
45
ns
PIC18LFXXXX
76
TdoF
77
78
TscR
PIC18FXXXX
25
ns
10
50
ns
25
ns
45
ns
25
ns
50
ns
100
ns
ns
PIC18LFXXXX
79
TscF
80
Note 1:
2:
73
83
1.5 TCY + 40
(Note 1)
(Note 1)
(Note 2)
VDD = 2.0V
VDD = 2.0V
VDD = 2.0V
Preliminary
DS39631A-page 351
PIC18F2420/2520/4420/4520
FIGURE 26-15:
SS
SCK
(CKP = 0)
70
83
71
72
SCK
(CKP = 1)
80
MSb
SDO
bit 6 - - - - - -1
LSb
75, 76
SDI
MSb In
Note:
77
bit 6 - - - -1
LSb In
74
Refer to Figure 26-4 for load conditions.
Symbol
Characteristic
Min
70
71
TscH
TscL
73A
Tb2b
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40
74
75
TdoR
76
TdoF
71A
72
72A
Continuous
TCY
ns
1.25 TCY + 30
ns
Single Byte
40
ns
Continuous
1.25 TCY + 30
ns
Single Byte
40
PIC18FXXXX
ns
(Note 1)
ns
(Note 2)
100
ns
25
ns
45
ns
25
ns
PIC18LFXXXX
77
10
50
ns
78
TscR
PIC18FXXXX
25
ns
PIC18LFXXXX
45
ns
79
TscF
25
ns
80
PIC18FXXXX
50
ns
PIC18LFXXXX
100
ns
82
PIC18FXXXX
50
ns
100
ns
83
1.5 TCY + 40
ns
Note 1:
2:
PIC18LFXXXX
(Note 1)
VDD = 2.0V
VDD = 2.0V
VDD = 2.0V
VDD = 2.0V
DS39631A-page 352
Preliminary
PIC18F2420/2520/4420/4520
I2C BUS START/STOP BITS TIMING
FIGURE 26-16:
SCL
91
93
90
92
SDA
Stop
Condition
Start
Condition
Note:
Characteristic
90
TSU:STA
Start Condition
91
THD:STA
92
TSU:STO
93
Max
Units
Conditions
4700
ns
ns
Setup Time
600
Start Condition
4000
Hold Time
600
Stop Condition
4700
Setup Time
Hold Time
FIGURE 26-17:
Min
600
4000
600
ns
ns
102
100
101
SCL
90
106
107
91
92
SDA
In
110
109
109
SDA
Out
Note:
Preliminary
DS39631A-page 353
PIC18F2420/2520/4420/4520
TABLE 26-19: I2C BUS DATA REQUIREMENTS (SLAVE MODE)
Param.
Symbol
No.
100
THIGH
Characteristic
Clock High Time
Min
Max
Units
4.0
0.6
1.5 TCY
4.7
1.3
SSP Module
101
TLOW
SSP Module
102
91
106
107
92
109
2:
300
ns
300
ns
20 + 0.1 CB
300
ns
CB is specified to be from
10 to 400 pF
4.7
0.6
4.0
0.6
ns
0.9
250
ns
100
ns
4.7
0.6
CB
Note 1:
20 + 0.1 CB
TBUF
D102
ns
TAA
110
1000
TF
90
TR
103
1.5 TCY
Conditions
3500
ns
ns
4.7
1.3
400
pF
CB is specified to be from
10 to 400 pF
(Note 2)
(Note 1)
Time the bus must be free
before a new transmission
can start
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
A fast mode I2C bus device can be used in a standard mode I2C bus system but the requirement,
TSU:DAT 250 ns, must then be met. This will automatically be the case if the device does not stretch the
LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must
output the next data bit to the SDA line, TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the
standard mode I2C bus specification), before the SCL line is released.
DS39631A-page 354
Preliminary
PIC18F2420/2520/4420/4520
FIGURE 26-18:
SCL
93
91
90
92
SDA
Stop
Condition
Start
Condition
Note:
TSU:STA
Characteristic
Start Condition
92
93
Max
Units
2(TOSC)(BRG + 1)
ns
2(TOSC)(BRG + 1)
1 MHz mode(1)
2(TOSC)(BRG + 1)
ns
Setup Time
91
Min
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
1 MHz mode(1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
1 MHz mode(1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
1 MHz mode(1)
2(TOSC)(BRG + 1)
Conditions
ns
ns
FIGURE 26-19:
102
100
101
SCL
90
106
91
107
92
SDA
In
109
109
110
SDA
Out
Note:
Preliminary
DS39631A-page 355
PIC18F2420/2520/4420/4520
TABLE 26-21: MASTER SSP I2C BUS DATA REQUIREMENTS
Param.
Symbol
No.
100
THIGH
Characteristic
Min
Max
Units
2(TOSC)(BRG + 1)
ms
2(TOSC)(BRG
+ 1)
ms
mode(1)
2(TOSC)(BRG + 1)
ms
2(TOSC)(BRG + 1)
ms
2(TOSC)(BRG + 1)
ms
mode(1)
ms
101
TLOW
1 MHz
102
103
90
91
TR
TF
TSU:STA
Start Condition
Setup Time
2(TOSC)(BRG + 1)
1000
ns
20 + 0.1 CB
300
ns
1 MHz mode(1)
300
ns
300
ns
20 + 0.1 CB
300
ns
1 MHz mode(1)
100
ns
2(TOSC)(BRG + 1)
ms
2(TOSC)(BRG
+ 1)
ms
1 MHz mode(1)
2(TOSC)(BRG + 1)
ms
2(TOSC)(BRG + 1)
ms
2(TOSC)(BRG + 1)
ms
1 MHz mode(1)
2(TOSC)(BRG + 1)
ms
ns
106
0.9
ms
107
TSU:DAT
250
ns
92
109
TAA
Data Input
Setup Time
Output Valid
from Clock
100
ns
2(TOSC)(BRG + 1)
ms
2(TOSC)(BRG + 1)
ms
1 MHz mode(1)
2(TOSC)(BRG + 1)
ms
3500
ns
ns
1000
mode(1)
ns
4.7
ms
1.3
ms
400
pF
1 MHz
110
D102
Note 1:
2:
TBUF
CB
Conditions
CB is specified to be from
10 to 400 pF
CB is specified to be from
10 to 400 pF
(Note 2)
I2C
DS39631A-page 356
Preliminary
PIC18F2420/2520/4420/4520
FIGURE 26-20:
RC6/TX/CK
pin
121
121
RC7/RX/DT
pin
120
Note:
122
121
122
Symbol
Characteristic
FIGURE 26-21:
Min
Max
Units
PIC18FXXXX
40
ns
PIC18LFXXXX
100
ns
PIC18FXXXX
20
ns
PIC18LFXXXX
50
ns
PIC18FXXXX
20
ns
PIC18LFXXXX
50
ns
Conditions
VDD = 2.0V
VDD = 2.0V
VDD = 2.0V
RC6/TX/CK
pin
125
RC7/RX/DT
pin
126
Note:
Symbol
Characteristic
Min
Max
Units
125
TdtV2ckl
10
ns
126
TckL2dtl
15
ns
Preliminary
Conditions
DS39631A-page 357
PIC18F2420/2520/4420/4520
TABLE 26-24: A/D CONVERTER CHARACTERISTICS: PIC18FX42X/X52X (INDUSTRIAL)
PIC18LFX42X/X52X (INDUSTRIAL)
Param
Symbol
No.
Characteristic
Min
Typ
Max
Units
10
bit
Conditions
VREF 3.0V
A01
NR
Resolution
A03
EIL
<1
A04
EDL
<1
A06
EOFF
Offset Error
<1
A07
EGN
Gain Error
<1
A10
Monotonicity
A20
VREF
1.8
3
V
V
A21
VREFH
VSS
VREFH
A22
VREFL
VSS 0.3V
VDD 3.0V
A25
VAIN
VREFL
VREFH
A30
ZAIN
Recommended Impedance of
Analog Voltage Source
2.5
A50
IREF
5
150
A
A
Note 1:
2:
Guaranteed(1)
The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
VREFH current is from RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source.
VREFL current is from RA2/AN2/VREF-/CVREF pin or VSS, whichever is selected as the VREFL source.
DS39631A-page 358
Preliminary
PIC18F2420/2520/4420/4520
FIGURE 26-22:
BSF ADCON0, GO
(Note 2)
131
Q4
130
132
A/D CLK
A/D DATA
...
...
NEW_DATA
OLD_DATA
ADRES
TCY
ADIF
GO
DONE
SAMPLING STOPPED
SAMPLE
Note
1:
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.
This allows the SLEEP instruction to be executed.
2:
This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
TAD
Characteristic
A/D Clock Period
Min
Max
Units
PIC18FXXXX
0.7
25.0(1)
PIC18LFXXXX
1.4
25.0(1)
VDD = 2.0V;
TOSC based, VREF full range
PIC18FXXXX
TBD
A/D RC mode
PIC18LFXXXX
TBD
11
12
TAD
1.4
TBD
s
s
131
TCNV
Conversion Time
(not including acquisition time) (Note 2)
132
TACQ
135
TSWC
(Note 4)
TBD
TDIS
Discharge Time
0.2
Legend:
Note 1:
2:
3:
4:
Conditions
-40C to +85C
0C to +85C
TBD = To Be Determined
The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
ADRES register may be read on the following TCY cycle.
The time for the holding capacitor to acquire the New input voltage when the voltage changes full scale
after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50.
On the following cycle of the device clock.
Preliminary
DS39631A-page 359
PIC18F2420/2520/4420/4520
NOTES:
DS39631A-page 360
Preliminary
PIC18F2420/2520/4420/4520
27.0
DC AND AC
CHARACTERISTICS GRAPHS
AND TABLES
Preliminary
DS39631A-page 361
PIC18F2420/2520/4420/4520
NOTES:
DS39631A-page 362
Preliminary
PIC18F2420/2520/4420/4520
28.0
PACKAGING INFORMATION
28.1
Example
PIC18F2520-I/SP
0410017
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
28-Lead SOIC
Example
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
YYWWNNN
40-Lead PDIP
PIC18F2520-E/SO
0410017
Example
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
YYWWNNN
Legend: XX...X
Y
YY
WW
NNN
Note:
PIC18F4420-I/P
0410017
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
Standard PICmicro device marking consists of Microchip part number, year code, week code and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
Preliminary
DS39631A-page 363
PIC18F2420/2520/4420/4520
Package Marking Information (Continued)
28-Lead QFN
Example
XXXXXXXX
XXXXXXXX
YYWWNNN
18F2420
-I/ML
0410017
44-Lead QFN
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
PIC18F4520
-I/ML
0410017
44-Lead TQFP
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
DS39631A-page 364
PIC18F4420
-I/PT
0410017
Preliminary
PIC18F2420/2520/4420/4520
28.2
Package Details
28-Lead Skinny Plastic Dual In-line (SP) 300 mil Body (PDIP)
E1
2
n
A2
A
L
B1
A1
eB
Units
Number of Pins
Pitch
Dimension Limits
n
p
INCHES*
MIN
NOM
MILLIMETERS
MAX
MIN
NOM
28
MAX
28
.100
2.54
.140
.150
.160
3.56
3.81
4.06
A2
.125
.130
.135
3.18
3.30
3.43
8.26
A1
.015
.300
.310
.325
7.62
7.87
E1
.275
.285
.295
6.99
7.24
7.49
Overall Length
1.345
1.365
1.385
34.16
34.67
35.18
L
c
.125
.130
.135
3.18
3.30
3.43
.008
.012
.015
0.20
0.29
0.38
B1
.040
.053
.065
1.02
1.33
1.65
Lead Thickness
Upper Lead Width
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
0.38
.016
.019
.022
0.41
0.48
0.56
eB
.320
.350
.430
8.13
8.89
10.92
10
15
10
15
10
15
10
15
* Controlling Parameter
Significant Characteristic
Notes:
Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010 (0.254mm) per side.
JEDEC Equivalent: MO-095
Preliminary
DS39631A-page 365
PIC18F2420/2520/4420/4520
28-Lead Plastic Small Outline (SO) Wide, 300 mil Body (SOIC)
E
E1
p
B
2
1
n
h
45
c
A2
L
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff
Overall Width
Molded Package Width
Overall Length
Chamfer Distance
Foot Length
Foot Angle Top
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
Significant Characteristic
A
A2
A1
E
E1
D
h
L
c
B
A1
MIN
.093
.088
.004
.394
.288
.695
.010
.016
0
.009
.014
0
0
INCHES*
NOM
28
.050
.099
.091
.008
.407
.295
.704
.020
.033
4
.011
.017
12
12
MAX
.104
.094
.012
.420
.299
.712
.029
.050
8
.013
.020
15
15
MILLIMETERS
NOM
28
1.27
2.36
2.50
2.24
2.31
0.10
0.20
10.01
10.34
7.32
7.49
17.65
17.87
0.25
0.50
0.41
0.84
0
4
0.23
0.28
0.36
0.42
0
12
0
12
MIN
MAX
2.64
2.39
0.30
10.67
7.59
18.08
0.74
1.27
8
0.33
0.51
15
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010 (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-052
DS39631A-page 366
Preliminary
PIC18F2420/2520/4420/4520
40-Lead Plastic Dual In-line (P) 600 mil Body (PDIP)
E1
2
1
n
E
A2
B1
A1
eB
B
Units
Dimension Limits
n
p
MIN
INCHES*
NOM
40
.100
.175
.150
MAX
MILLIMETERS
NOM
40
2.54
4.06
4.45
3.56
3.81
0.38
15.11
15.24
13.46
13.84
51.94
52.26
3.05
3.30
0.20
0.29
0.76
1.27
0.36
0.46
15.75
16.51
5
10
5
10
MIN
Number of Pins
Pitch
Top to Seating Plane
A
.160
.190
Molded Package Thickness
A2
.140
.160
Base to Seating Plane
.015
A1
Shoulder to Shoulder Width
E
.595
.600
.625
Molded Package Width
E1
.530
.545
.560
Overall Length
D
2.045
2.058
2.065
Tip to Seating Plane
L
.120
.130
.135
c
Lead Thickness
.008
.012
.015
Upper Lead Width
B1
.030
.050
.070
Lower Lead Width
B
.014
.018
.022
Overall Row Spacing
eB
.620
.650
.680
Preliminary
MAX
4.83
4.06
15.88
14.22
52.45
3.43
0.38
1.78
0.56
17.27
15
15
DS39631A-page 367
PIC18F2420/2520/4420/4520
28-Lead Plastic Quad Flat No Lead Package (ML) 6x6 mm Body, Saw Singulated (QFN)
E2
EXPOSED
METAL
PAD
D2
1
n
TOP VIEW
ALTERNATE
INDEX
INDICATORS
OPTIONAL
INDEX
AREA
SEE DETAIL
BOTTOM VIEW
A1
A
DETAIL
ALTERNATE
PAD OUTLINE
Number of Pins
Pitch
Overall Height
Standoff
Overall Width
Exposed Pad Width
Overall Length
Exposed Pad Length
Lead Width
Lead Length
Units
Dimension Limits
n
p
A
A1
E
E2
D
D2
B
L
MIN
.031
.000
.232
.140
.232
.140
.009
.020
INCHES
NOM
28
.026 BSC
.035
.001
.236
.146
.236
.146
.011
.022
MAX
.039
.002
.240
.152
.240
.152
.013
.024
MILLIMETERS*
NOM
28
0.65 BSC
0.80
0.90
0.00
0.02
6.00
5.90
3.55
3.70
5.90
6.00
3.55
3.70
0.23
0.28
0.50
0.55
MIN
MAX
1.00
0.05
6.10
3.85
6.10
3.85
0.33
0.60
*Controlling Parameter
Notes:
JEDEC equivalent: MO-220
Drawing No. C04-105
DS39631A-page 368
Preliminary
PIC18F2420/2520/4420/4520
44-Lead Plastic Quad Flat No Lead Package (ML) 8x8 mm Body (QFN)
Preliminary
DS39631A-page 369
PIC18F2420/2520/4420/4520
44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
E
E1
#leads=n1
p
D1
2
1
B
n
CH x 45
A
c
A1
A2
(F)
Units
Dimension Limits
n
p
Number of Pins
Pitch
Pins per Side
Overall Height
Molded Package Thickness
Standoff
Foot Length
Footprint (Reference)
Foot Angle
Overall Width
Overall Length
Molded Package Width
Molded Package Length
Lead Thickness
Lead Width
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
Significant Characteristic
n1
A
A2
A1
L
(F)
E
D
E1
D1
c
B
CH
MIN
.039
.037
.002
.018
0
.463
.463
.390
.390
.004
.012
.025
5
5
INCHES
NOM
44
.031
11
.043
.039
.004
.024
.039
3.5
.472
.472
.394
.394
.006
.015
.035
10
10
MAX
.047
.041
.006
.030
7
.482
.482
.398
.398
.008
.017
.045
15
15
MILLIMETERS*
NOM
44
0.80
11
1.00
1.10
0.95
1.00
0.05
0.10
0.45
0.60
1.00
0
3.5
11.75
12.00
11.75
12.00
9.90
10.00
9.90
10.00
0.09
0.15
0.30
0.38
0.64
0.89
5
10
5
10
MIN
MAX
1.20
1.05
0.15
0.75
7
12.25
12.25
10.10
10.10
0.20
0.44
1.14
15
15
Notes:
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010 (0.254mm) per side.
JEDEC Equivalent: MS-026
Drawing No. C04-076
DS39631A-page 370
Preliminary
PIC18F2420/2520/4420/4520
APPENDIX A:
REVISION HISTORY
APPENDIX B:
TABLE B-1:
DEVICE
DIFFERENCES
DEVICE DIFFERENCES
Features
PIC18F2420
PIC18F2520
PIC18F4420
PIC18F4520
16384
32768
16384
32768
8192
16384
8192
16384
Interrupt Sources
19
19
20
20
Ports A, B, C, (E)
Ports A, B, C, (E)
Ports A, B, C, D, E
Ports A, B, C, D, E
Capture/Compare/PWM Modules
Enhanced
Capture/Compare/PWM Modules
I/O Ports
No
No
Yes
Yes
10 input channels
10 input channels
13 input channels
13 input channels
28-pin PDIP
28-pin SOIC
28-pin QFN
28-pin PDIP
28-pin SOIC
28-pin QFN
40-pin PDIP
44-pin TQFP
44-pin QFN
40-pin PDIP
44-pin TQFP
44-pin QFN
Packages
Preliminary
DS39631A-page 371
PIC18F2420/2520/4420/4520
APPENDIX C:
CONVERSION
CONSIDERATIONS
APPENDIX D:
DS39631A-page 372
MIGRATION FROM
BASELINE TO
ENHANCED DEVICES
Preliminary
PIC18F2420/2520/4420/4520
APPENDIX E:
MIGRATION FROM
MID-RANGE TO
ENHANCED DEVICES
APPENDIX F:
MIGRATION FROM
HIGH-END TO
ENHANCED DEVICES
A detailed discussion of the migration pathway and differences between the high-end MCU devices (i.e.,
PIC17CXXX) and the enhanced devices (i.e.,
PIC18FXXX) is provided in AN726, PIC17CXXX to
PIC18CXXX Migration. This Application Note is
available as Literature Number DS00726.
Preliminary
DS39631A-page 373
PIC18F2420/2520/4420/4520
NOTES:
DS39631A-page 374
Preliminary
PIC18F2420/2520/4420/4520
INDEX
A
A/D ................................................................................... 223
A/D Converter Interrupt, Configuring ....................... 227
Acquisition Requirements ........................................ 228
ADCON0 Register .................................................... 223
ADCON1 Register .................................................... 223
ADCON2 Register .................................................... 223
ADRESH Register ............................................ 223, 226
ADRESL Register .................................................... 223
Analog Port Pins, Configuring .................................. 230
Associated Registers ............................................... 232
Calculating the Minimum Required
Acquisition Time .............................................. 228
Configuring the Module ............................................ 227
Conversion Clock (TAD) ........................................... 229
Conversion Status (GO/DONE Bit) .......................... 226
Conversions ............................................................. 231
Converter Characteristics ........................................ 358
Discharge ................................................................. 231
Operation in Power Managed Modes ...................... 230
Selecting and Configuring Acquisition Time ............ 229
Special Event Trigger (CCP) .................................... 232
Special Event Trigger (ECCP) ................................. 148
Use of the CCP2 Trigger .......................................... 232
Absolute Maximum Ratings ............................................. 323
AC (Timing) Characteristics ............................................. 340
Load Conditions for Device
Timing Specifications ....................................... 341
Parameter Symbology ............................................. 340
Temperature and Voltage Specifications ................. 341
Timing Conditions .................................................... 341
AC Characteristics
Internal RC Accuracy ............................................... 343
Access Bank
Mapping with Indexed Literal Offset Mode ................. 72
ACKSTAT ........................................................................ 191
ACKSTAT Status Flag ..................................................... 191
ADCON0 Register ............................................................ 223
GO/DONE Bit ........................................................... 226
ADCON1 Register ............................................................ 223
ADCON2 Register ............................................................ 223
ADDFSR .......................................................................... 310
ADDLW ............................................................................ 273
ADDULNK ........................................................................ 310
ADDWF ............................................................................ 273
ADDWFC ......................................................................... 274
ADRESH Register ............................................................ 223
ADRESL Register .................................................... 223, 226
Analog-to-Digital Converter. See A/D.
ANDLW ............................................................................ 274
ANDWF ............................................................................ 275
Assembler
MPASM Assembler .................................................. 317
Auto-Wake-up on Sync Break Character ......................... 214
B
Bank Select Register (BSR) ............................................... 59
Baud Rate Generator ....................................................... 187
BC .................................................................................... 275
BCF .................................................................................. 276
BF .................................................................................... 191
BF Status Flag ................................................................. 191
Block Diagrams
A/D ........................................................................... 226
Analog Input Model .................................................. 227
Baud Rate Generator .............................................. 187
Capture Mode Operation ......................................... 141
Comparator Analog Input Model .............................. 237
Comparator I/O Operating Modes ........................... 234
Comparator Output .................................................. 236
Comparator Voltage Reference ............................... 240
Compare Mode Operation ....................................... 142
Device Clock .............................................................. 28
Enhanced PWM ....................................................... 149
EUSART Receive .................................................... 213
EUSART Transmit ................................................... 211
External Power-on Reset Circuit
(Slow VDD Power-up) ........................................ 43
Fail-Safe Clock Monitor (FSCM) .............................. 261
Generic I/O Port ....................................................... 105
High/Low-Voltage Detect with External Input .......... 244
Interrupt Logic ............................................................ 92
MSSP (I2C Master Mode) ........................................ 185
MSSP (I2C Mode) .................................................... 170
MSSP (SPI Mode) ................................................... 161
On-Chip Reset Circuit ................................................ 41
PIC18F2420/2520 ..................................................... 10
PIC18F4420/4520 ..................................................... 11
PLL (HS Mode) .......................................................... 25
PORTD and PORTE (Parallel Slave Port) ............... 120
PWM Operation (Simplified) .................................... 144
Reads from Flash Program Memory ......................... 77
Single Comparator ................................................... 235
Table Read Operation ............................................... 73
Table Write Operation ............................................... 74
Table Writes to Flash Program Memory .................... 79
Timer0 in 16-Bit Mode ............................................. 124
Timer0 in 8-Bit Mode ............................................... 124
Timer1 ..................................................................... 128
Timer1 (16-Bit Read/Write Mode) ............................ 128
Timer2 ..................................................................... 134
Timer3 ..................................................................... 136
Timer3 (16-Bit Read/Write Mode) ............................ 136
Voltage Reference Output Buffer Example ............. 241
Watchdog Timer ...................................................... 258
BN .................................................................................... 276
BNC ................................................................................. 277
BNN ................................................................................. 277
BNOV .............................................................................. 278
BNZ ................................................................................. 278
BOR. See Brown-out Reset.
BOV ................................................................................. 281
BRA ................................................................................. 279
Break Character (12-Bit) Transmit and Receive .............. 216
BRG. See Baud Rate Generator.
Brown-out Reset (BOR) ..................................................... 44
Detecting ................................................................... 44
Disabling in Sleep Mode ............................................ 44
Software Enabled ...................................................... 44
BSF .................................................................................. 279
BTFSC ............................................................................. 280
BTFSS ............................................................................. 280
BTG ................................................................................. 281
BZ .................................................................................... 282
Preliminary
DS39631A-page 375
PIC18F2420/2520/4420/4520
C
C Compilers
MPLAB C17 ............................................................. 318
MPLAB C18 ............................................................. 318
MPLAB C30 ............................................................. 318
CALL ................................................................................ 282
CALLW ............................................................................. 311
Capture (CCP Module) ..................................................... 141
Associated Registers ............................................... 143
CCP Pin Configuration ............................................. 141
CCPRxH:CCPRxL Registers ................................... 141
Prescaler .................................................................. 141
Software Interrupt .................................................... 141
Timer1/Timer3 Mode Selection ................................ 141
Capture (ECCP Module) .................................................. 148
Capture/Compare/PWM (CCP) ........................................ 139
Capture Mode. See Capture.
CCP Mode and Timer Resources ............................ 140
CCPRxH Register .................................................... 140
CCPRxL Register ..................................................... 140
Compare Mode. See Compare.
Interaction of Two CCP Modules ............................. 140
Module Configuration ............................................... 140
Clock Sources .................................................................... 28
Selecting the 31 kHz Source ...................................... 29
Selection Using OSCCON Register ........................... 29
CLRF ................................................................................ 283
CLRWDT .......................................................................... 283
Code Examples
16 x 16 Signed Multiply Routine ................................ 90
16 x 16 Unsigned Multiply Routine ............................ 90
8 x 8 Signed Multiply Routine .................................... 89
8 x 8 Unsigned Multiply Routine ................................ 89
Changing Between Capture Prescalers ................... 141
Computed GOTO Using an Offset Value ................... 56
Data EEPROM Read ................................................. 85
Data EEPROM Refresh Routine ................................ 86
Data EEPROM Write ................................................. 85
Erasing a Flash Program Memory Row ..................... 78
Fast Register Stack .................................................... 56
How to Clear RAM (Bank 1) Using
Indirect Addressing ............................................ 68
Implementing a Real-Time Clock Using
a Timer1 Interrupt Service ............................... 131
Initializing PORTA .................................................... 105
Initializing PORTB .................................................... 108
Initializing PORTC .................................................... 111
Initializing PORTD .................................................... 114
Initializing PORTE .................................................... 117
Loading the SSPBUF (SSPSR) Register ................. 164
Reading a Flash Program Memory Word .................. 77
Saving Status, WREG and
BSR Registers in RAM ..................................... 103
Writing to Flash Program Memory ....................... 8081
Code Protection ............................................................... 249
COMF ............................................................................... 284
Comparator ...................................................................... 233
Analog Input Connection Considerations ................. 237
Associated Registers ............................................... 237
Configuration ............................................................ 234
Effects of a Reset ..................................................... 236
Interrupts .................................................................. 236
Operation ................................................................. 235
Operation During Sleep ........................................... 236
Outputs .................................................................... 235
DS39631A-page 376
D
Data Addressing Modes .................................................... 68
Comparing Addressing Modes with the
Extended Instruction Set Enabled ..................... 71
Direct ......................................................................... 68
Indexed Literal Offset ................................................ 70
Instructions Affected .......................................... 70
Indirect ....................................................................... 68
Inherent and Literal .................................................... 68
Data EEPROM
Code Protection ....................................................... 266
Data EEPROM Memory ..................................................... 83
Associated Registers ................................................. 87
EEADR Register ........................................................ 83
EECON1 and EECON2 Registers ............................. 83
Operation During Code-Protect ................................. 86
Protection Against Spurious Write ............................. 86
Reading ..................................................................... 85
Using ......................................................................... 86
Write Verify ................................................................ 85
Writing ....................................................................... 85
Data Memory ..................................................................... 59
Access Bank .............................................................. 62
and the Extended Instruction Set .............................. 70
Bank Select Register (BSR) ...................................... 59
General Purpose Registers ....................................... 62
Map for PIC18F2420/4420 ........................................ 60
Map for PIC18F2520/4520 ........................................ 61
Special Function Registers ........................................ 63
DAW ................................................................................ 286
DC and AC Characteristics
Graphs and Tables .................................................. 361
Preliminary
PIC18F2420/2520/4420/4520
DC Characteristics ........................................................... 335
Power-Down and Supply Current ............................ 326
Supply Voltage ......................................................... 325
DCFSNZ .......................................................................... 287
DECF ............................................................................... 286
DECFSZ ........................................................................... 287
Demonstration Boards
PICDEM 1 ................................................................ 320
PICDEM 17 .............................................................. 321
PICDEM 18R ........................................................... 321
PICDEM 2 Plus ........................................................ 320
PICDEM 3 ................................................................ 320
PICDEM 4 ................................................................ 320
PICDEM LIN ............................................................ 321
PICDEM USB ........................................................... 321
PICDEM.net Internet/Ethernet ................................. 320
Development Support ...................................................... 317
Device Differences ........................................................... 371
Device Overview .................................................................. 7
Details on Individual Family Members ......................... 8
Features (table) ............................................................ 9
New Core Features ...................................................... 7
Other Special Features ................................................ 8
Device Reset Timers .......................................................... 45
Oscillator Start-up Timer (OST) ................................. 45
PLL Lock Time-out ..................................................... 45
Power-up Timer (PWRT) ........................................... 45
Time-out Sequence .................................................... 45
Direct Addressing ............................................................... 69
E
Effect on Standard PIC Instructions ................................. 314
Effects of Power Managed Modes on
Various Clock Sources ............................................... 31
Electrical Characteristics .................................................. 323
Enhanced Capture/Compare/PWM (ECCP) .................... 147
Associated Registers ............................................... 160
Capture and Compare Modes .................................. 148
Capture Mode. See Capture (ECCP Module).
Outputs and Configuration ....................................... 148
Pin Configurations for ECCP1 ................................. 148
PWM Mode. See PWM (ECCP Module).
Standard PWM Mode ............................................... 148
Timer Resources ...................................................... 148
Enhanced PWM Mode. See PWM (ECCP Module).
Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART). See EUSART.
Equations
A/D Acquisition Time ................................................ 228
A/D Minimum Charging Time ................................... 228
Errata ................................................................................... 6
EUSART
Asynchronous Mode ................................................ 211
12-Bit Break Transmit and Receive ................. 216
Associated Registers, Receive ........................ 214
Associated Registers, Transmit ....................... 212
Auto-Wake-up on Sync Break ......................... 214
Receiver ........................................................... 213
Setting up 9-Bit Mode with
Address Detect ........................................ 213
Transmitter ....................................................... 211
Baud Rate Generator
Operation in Power Managed Mode ................ 205
F
Fail-Safe Clock Monitor ........................................... 249, 261
Exiting Operation ..................................................... 261
Interrupts in Power Managed Modes ....................... 262
POR or Wake from Sleep ........................................ 262
WDT During Oscillator Failure ................................. 261
Fast Register Stack ........................................................... 56
Firmware Instructions ...................................................... 267
Flash Program Memory ..................................................... 73
Associated Registers ................................................. 81
Control Registers ....................................................... 74
EECON1 and EECON2 ..................................... 74
TABLAT (Table Latch) Register ........................ 76
TBLPTR (Table Pointer) Register ...................... 76
Erase Sequence ........................................................ 78
Erasing ...................................................................... 78
Operation During Code-Protect ................................. 81
Reading ..................................................................... 77
Table Pointer
Boundaries Based on Operation ....................... 76
Table Pointer Boundaries .......................................... 76
Table Reads and Table Writes .................................. 73
Write Sequence ......................................................... 79
Writing To .................................................................. 79
Protection Against Spurious Writes ................... 81
Unexpected Termination ................................... 81
Write Verify ........................................................ 81
FSCM. See Fail-Safe Clock Monitor.
G
General Call Address Support ......................................... 184
GOTO .............................................................................. 288
Preliminary
DS39631A-page 377
PIC18F2420/2520/4420/4520
H
Hardware Multiplier ............................................................ 89
Introduction ................................................................ 89
Operation ................................................................... 89
Performance Comparison .......................................... 89
High/Low-Voltage Detect ................................................. 243
Applications .............................................................. 246
Associated Registers ............................................... 247
Characteristics ......................................................... 339
Current Consumption ............................................... 245
Effects of a Reset ..................................................... 247
Operation ................................................................. 244
During Sleep .................................................... 247
Setup ........................................................................ 245
Start-up Time ........................................................... 245
Typical Application ................................................... 246
HLVD. See High/Low-Voltage Detect.
I
I/O Ports ........................................................................... 105
I2C Mode (MSSP)
Acknowledge Sequence Timing ............................... 194
Baud Rate Generator ............................................... 187
Bus Collision
During a Repeated Start Condition .................. 198
During a Stop Condition ................................... 199
Clock Arbitration ....................................................... 188
Clock Stretching ....................................................... 180
10-Bit Slave Receive Mode (SEN = 1) ............. 180
10-Bit Slave Transmit Mode ............................. 180
7-Bit Slave Receive Mode (SEN = 1) ............... 180
7-Bit Slave Transmit Mode ............................... 180
Clock Synchronization and the CKP Bit (SEN = 1) .. 181
Effects of a Reset ..................................................... 195
General Call Address Support ................................. 184
I2C Clock Rate w/BRG ............................................. 187
Master Mode ............................................................ 185
Operation ......................................................... 186
Reception ......................................................... 191
Repeated Start Condition Timing ..................... 190
Start Condition Timing ..................................... 189
Transmission .................................................... 191
Multi-Master Communication, Bus Collision
and Arbitration .................................................. 195
Multi-Master Mode ................................................... 195
Operation ................................................................. 174
Read/Write Bit Information (R/W Bit) ............... 174, 175
Registers .................................................................. 170
Serial Clock (RC3/SCK/SCL) ................................... 175
Slave Mode .............................................................. 174
Addressing ....................................................... 174
Reception ......................................................... 175
Transmission .................................................... 175
Sleep Operation ....................................................... 195
Stop Condition Timing .............................................. 194
ID Locations ............................................................. 249, 266
INCF ................................................................................. 288
INCFSZ ............................................................................ 289
In-Circuit Debugger .......................................................... 266
In-Circuit Serial Programming (ICSP) ...................... 249, 266
Indexed Literal Offset Addressing
and Standard PIC18 Instructions ............................. 314
Indexed Literal Offset Mode ............................................. 314
Indirect Addressing ............................................................ 69
INFSNZ ............................................................................ 289
DS39631A-page 378
Preliminary
PIC18F2420/2520/4420/4520
RRCF ....................................................................... 300
RRNCF .................................................................... 301
SETF ........................................................................ 301
SETF (Indexed Literal Offset Mode) ........................ 315
SLEEP ..................................................................... 302
SUBFWB .................................................................. 302
SUBLW .................................................................... 303
SUBWF .................................................................... 303
SUBWFB .................................................................. 304
SWAPF .................................................................... 304
TBLRD ..................................................................... 305
TBLWT ..................................................................... 306
TSTFSZ ................................................................... 307
XORLW .................................................................... 307
XORWF .................................................................... 308
INTCON Registers ....................................................... 9395
Inter-Integrated Circuit. See I2C.
Internal Oscillator Block ..................................................... 26
Adjustment ................................................................. 26
INTIO Modes .............................................................. 26
INTOSC Frequency Drift ............................................ 26
INTOSC Output Frequency ........................................ 26
OSCTUNE Register ................................................... 26
PLL in INTOSC Modes .............................................. 26
Internal RC Oscillator
Use with WDT .......................................................... 258
Interrupt Sources ............................................................. 249
A/D Conversion Complete ....................................... 227
Capture Complete (CCP) ......................................... 141
Compare Complete (CCP) ....................................... 142
Interrupt-on-Change (RB7:RB4) .............................. 108
INTn Pin ................................................................... 103
PORTB, Interrupt-on-Change .................................. 103
TMR0 ....................................................................... 103
TMR0 Overflow ........................................................ 125
TMR1 Overflow ........................................................ 127
TMR2 to PR2 Match (PWM) ............................ 144, 149
TMR3 Overflow ................................................ 135, 137
Interrupts ............................................................................ 91
Interrupts, Flag Bits
Interrupt-on-Change (RB7:RB4) Flag
(RBIF Bit) ......................................................... 108
INTOSC, INTRC. See Internal Oscillator Block.
IORLW ............................................................................. 290
IORWF ............................................................................. 290
IPR Registers ................................................................... 100
L
LFSR ................................................................................ 291
Low-Voltage ICSP Programming.
See Single-Supply ICSP Programming
M
Master Clear (MCLR) ......................................................... 43
Master Synchronous Serial Port (MSSP). See MSSP.
Memory Organization ......................................................... 53
Data Memory ............................................................. 59
Program Memory ....................................................... 53
Memory Programming Requirements .............................. 337
Migration from Baseline to Enhanced Devices ................ 372
Migration from High-End to Enhanced Devices ............... 373
Migration from Mid-Range to Enhanced Devices ............ 373
MOVF ............................................................................... 291
MOVFF ............................................................................ 292
N
NEGF ............................................................................... 295
NOP ................................................................................. 295
O
Oscillator Configuration ..................................................... 23
EC .............................................................................. 23
ECIO .......................................................................... 23
HS .............................................................................. 23
HSPLL ....................................................................... 23
Internal Oscillator Block ............................................. 26
INTIO1 ....................................................................... 23
INTIO2 ....................................................................... 23
LP .............................................................................. 23
RC ............................................................................. 23
RCIO .......................................................................... 23
XT .............................................................................. 23
Oscillator Selection .......................................................... 249
Oscillator Start-up Timer (OST) ................................... 31, 45
Oscillator Switching ........................................................... 28
Oscillator Transitions ......................................................... 29
Oscillator, Timer1 ..................................................... 127, 137
Oscillator, Timer3 ............................................................. 135
P
Packaging Information ..................................................... 363
Marking .................................................................... 363
Parallel Slave Port (PSP) ......................................... 114, 120
Associated Registers ............................................... 121
CS (Chip Select) ...................................................... 120
PORTD .................................................................... 120
RD (Read Input) ...................................................... 120
Select (PSPMODE Bit) .................................... 114, 120
WR (Write Input) ...................................................... 120
PICkit 1 Flash Starter Kit ................................................. 321
PICSTART Plus Development Programmer .................... 320
PIE Registers ..................................................................... 98
Preliminary
DS39631A-page 379
PIC18F2420/2520/4420/4520
Pin Functions
MCLR/VPP/RE3 .................................................... 12, 16
OSC1/CLKI/RA7 .................................................. 12, 16
OSC2/CLKO/RA6 ................................................ 12, 16
RA0/AN0 .............................................................. 13, 17
RA1/AN1 .............................................................. 13, 17
RA2/AN2/VREF-/CVREF ........................................ 13, 17
RA3/AN3/VREF+ ................................................... 13, 17
RA4/T0CKI/C1OUT .............................................. 13, 17
RA5/AN4/SS/HLVDIN/C2OUT ............................. 13, 17
RB0/INT0/FLT0/AN12 .......................................... 14, 18
RB1/INT1/AN10 ................................................... 14, 18
RB2/INT2/AN8 ..................................................... 14, 18
RB3/AN9/CCP2 ................................................... 14, 18
RB4/KBI0/AN11 ................................................... 14, 18
RB5/KBI1/PGM .................................................... 14, 18
RB6/KBI2/PGC .................................................... 14, 18
RB7/KBI3/PGD .................................................... 14, 18
RC0/T1OSO/T13CKI ........................................... 15, 19
RC1/T1OSI/CCP2 ................................................ 15, 19
RC2/CCP1 ................................................................. 15
RC2/CCP1/P1A ......................................................... 19
RC3/SCK/SCL ..................................................... 15, 19
RC4/SDI/SDA ...................................................... 15, 19
RC5/SDO ............................................................. 15, 19
RC6/TX/CK .......................................................... 15, 19
RC7/RX/DT .......................................................... 15, 19
RD0/PSP0 .................................................................. 20
RD1/PSP1 .................................................................. 20
RD2/PSP2 .................................................................. 20
RD3/PSP3 .................................................................. 20
RD4/PSP4 .................................................................. 20
RD5/PSP5/P1B .......................................................... 20
RD6/PSP6/P1C .......................................................... 20
RD7/PSP7/P1D .......................................................... 20
RE0/RD/AN5 .............................................................. 21
RE1/WR/AN6 ............................................................. 21
RE2/CS/AN7 .............................................................. 21
VDD ....................................................................... 15, 21
VSS ....................................................................... 15, 21
Pinout I/O Descriptions
PIC18F2420/2520 ...................................................... 12
PIC18F4420/4520 ...................................................... 16
PIR Registers ..................................................................... 96
PLL Frequency Multiplier ................................................... 25
HSPLL Oscillator Mode .............................................. 25
Use with INTOSC ....................................................... 25
POP .................................................................................. 296
POR. See Power-on Reset.
PORTA
Associated Registers ............................................... 107
LATA Register .......................................................... 105
PORTA Register ...................................................... 105
TRISA Register ........................................................ 105
PORTB
Associated Registers ............................................... 110
LATB Register .......................................................... 108
PORTB Register ...................................................... 108
RB7:RB4 Interrupt-on-Change Flag
(RBIF Bit) ......................................................... 108
TRISB Register ........................................................ 108
DS39631A-page 380
PORTC
Associated Registers ............................................... 113
LATC Register ......................................................... 111
PORTC Register ...................................................... 111
RC3/SCK/SCL Pin ................................................... 175
TRISC Register ........................................................ 111
PORTD
Associated Registers ............................................... 116
LATD Register ......................................................... 114
Parallel Slave Port (PSP) Function .......................... 114
PORTD Register ...................................................... 114
TRISD Register ........................................................ 114
PORTE
Associated Registers ............................................... 119
LATE Register ......................................................... 117
PORTE Register ...................................................... 117
PSP Mode Select (PSPMODE Bit) .......................... 114
TRISE Register ........................................................ 117
Power Managed Modes ..................................................... 33
and A/D Operation ................................................... 230
and EUSART Operation .......................................... 205
and Multiple Sleep Commands .................................. 34
and PWM Operation ................................................ 159
and SPI Operation ................................................... 169
Clock Transitions and Status Indicators .................... 34
Effects on Clock Sources ........................................... 31
Entering ..................................................................... 33
Exiting Idle and Sleep Modes .................................... 39
by Interrupt ........................................................ 39
by Reset ............................................................ 39
by WDT Time-out .............................................. 39
Without a Start-up Delay ................................... 40
Idle Modes ................................................................. 37
PRI_IDLE ........................................................... 38
RC_IDLE ........................................................... 39
SEC_IDLE ......................................................... 38
Run Modes ................................................................ 34
PRI_RUN ........................................................... 34
RC_RUN ............................................................ 35
SEC_RUN ......................................................... 34
Selecting .................................................................... 33
Sleep Mode ............................................................... 37
Summary (table) ........................................................ 33
Power-on Reset (POR) ...................................................... 43
Power-up Timer (PWRT) ........................................... 45
Time-out Sequence ................................................... 45
Power-up Delays ............................................................... 31
Power-up Timer (PWRT) ................................................... 31
Prescaler
Timer2 ..................................................................... 150
Prescaler, Timer0 ............................................................ 125
Prescaler, Timer2 ............................................................ 145
PRI_IDLE Mode ................................................................. 38
PRI_RUN Mode ................................................................. 34
PRO MATE II Universal Device Programmer .................. 319
Program Counter ............................................................... 54
PCL, PCH and PCU Registers .................................. 54
PCLATH and PCLATU Registers .............................. 54
Preliminary
PIC18F2420/2520/4420/4520
Program Memory
and Extended Instruction Set ..................................... 72
Code Protection ....................................................... 264
Instructions ................................................................. 58
Two-Word .......................................................... 58
Interrupt Vector .......................................................... 53
Look-up Tables .......................................................... 56
Map and Stack (diagram) ........................................... 53
Reset Vector .............................................................. 53
Program Verification and Code Protection ....................... 263
Associated Registers ............................................... 263
Programming, Device Instructions ................................... 267
PSP. See Parallel Slave Port.
Pulse-Width Modulation. See PWM (CCP Module)
and PWM (ECCP Module).
PUSH ............................................................................... 296
PUSH and POP Instructions .............................................. 55
PUSHL ............................................................................. 312
PWM (CCP Module)
Associated Registers ............................................... 146
Auto-Shutdown (CCP1 only) .................................... 145
CCPR1H:CCPR1L Registers ................................... 149
Duty Cycle ........................................................ 144, 150
Example Frequencies/Resolutions .................. 145, 150
Period ............................................................... 144, 149
Setup for PWM Operation ........................................ 145
TMR2 to PR2 Match ........................................ 144, 149
PWM (ECCP Module) ...................................................... 149
Direction Change in Full-Bridge
Output Mode .................................................... 154
Effects of a Reset ..................................................... 159
Enhanced PWM Auto-Shutdown ............................. 156
Full-Bridge Application Example .............................. 154
Full-Bridge Mode ...................................................... 153
Half-Bridge Mode ..................................................... 152
Half-Bridge Output Mode
Applications Example ...................................... 152
Operation in Power Managed Modes ...................... 159
Operation with Fail-Safe Clock Monitor ................... 159
Output Configurations .............................................. 150
Output Relationships (Active-High) .......................... 151
Output Relationships (Active-Low) ........................... 151
Programmable Dead-Band Delay ............................ 156
Setup for PWM Operation ........................................ 159
Start-up Considerations ........................................... 158
Q
Q Clock .................................................................... 145, 150
R
RAM. See Data Memory.
RBIF Bit ............................................................................ 108
RC Oscillator ...................................................................... 25
RCIO Oscillator Mode ................................................ 25
RC_IDLE Mode .................................................................. 39
RC_RUN Mode .................................................................. 35
RCALL ............................................................................. 297
RCON Register
Bit Status During Initialization .................................... 48
Register File ....................................................................... 62
Register File Summary ................................................ 6466
Registers
ADCON0 (A/D Control 0) ......................................... 223
ADCON1 (A/D Control 1) ......................................... 224
ADCON2 (A/D Control 2) ......................................... 225
BAUDCON (Baud Rate Control) .............................. 204
CCP1CON (Enhanced
Capture/Compare/PWM Control 1) ................. 147
CCPxCON (Standard
Capture/Compare/PWM Control) .................... 139
CMCON (Comparator Control) ................................ 233
CONFIG1H (Configuration 1 High) .......................... 250
CONFIG2H (Configuration 2 High) .......................... 252
CONFIG2L (Configuration 2 Low) ........................... 251
CONFIG3H (Configuration 3 High) .......................... 253
CONFIG4L (Configuration 4 Low) ........................... 253
CONFIG5H (Configuration 5 High) .......................... 254
CONFIG5L (Configuration 5 Low) ........................... 254
CONFIG6H (Configuration 6 High) .......................... 255
CONFIG6L (Configuration 6 Low) ........................... 255
CONFIG7H (Configuration 7 High) .......................... 256
CONFIG7L (Configuration 7 Low) ........................... 256
CVRCON (Comparator Voltage
Reference Control) .......................................... 239
DEVID1 (Device ID 1) .............................................. 257
DEVID2 (Device ID 2) .............................................. 257
ECCP1AS (ECCP Auto-Shutdown Control) ............ 157
EECON1 (Data EEPROM Control 1) ................... 75, 84
HLVDCON (High/Low-Voltage Detect Control) ....... 243
INTCON (Interrupt Control) ....................................... 93
INTCON2 (Interrupt Control 2) .................................. 94
INTCON3 (Interrupt Control 3) .................................. 95
IPR1 (Peripheral Interrupt Priority 1) ....................... 100
IPR2 (Peripheral Interrupt Priority 2) ....................... 101
OSCCON (Oscillator Control) .................................... 30
OSCTUNE (Oscillator Tuning) ................................... 27
PIE1 (Peripheral Interrupt Enable 1) ......................... 98
PIE2 (Peripheral Interrupt Enable 2) ......................... 99
PIR1 (Peripheral Interrupt Request (Flag) 1) ............. 96
PIR2 (Peripheral Interrupt Request (Flag) 2) ............. 97
PWM1CON (PWM Configuration) ........................... 156
RCON (Reset Control) ....................................... 42, 102
RCSTA (Receive Status and Control) ..................... 203
SSPCON1 (MSSP Control 1, I2C Mode) ................. 172
SSPCON1 (MSSP Control 1, SPI Mode) ................ 163
SSPCON2 (MSSP Control 2, I2C Mode) ................. 173
SSPSTAT (MSSP Status, I2C Mode) ...................... 171
SSPSTAT (MSSP Status, SPI Mode) ...................... 162
Status ........................................................................ 67
STKPTR (Stack Pointer) ............................................ 55
T0CON (Timer0 Control) ......................................... 123
T1CON (Timer1 Control) ......................................... 127
T2CON (Timer2 Control) ......................................... 133
T3CON (Timer3 Control) ......................................... 135
TRISE (PORTE/PSP Control) ................................. 118
TXSTA (Transmit Status and Control) ..................... 202
WDTCON (Watchdog Timer Control) ...................... 259
RESET ............................................................................. 297
Reset State of Registers .................................................... 48
Resets ....................................................................... 41, 249
Brown-out Reset (BOR) ........................................... 249
Oscillator Start-up Timer (OST) ............................... 249
Power-on Reset (POR) ............................................ 249
Power-up Timer (PWRT) ......................................... 249
Preliminary
DS39631A-page 381
PIC18F2420/2520/4420/4520
RETFIE ............................................................................ 298
RETLW ............................................................................. 298
RETURN .......................................................................... 299
Return Address Stack ........................................................ 54
Return Stack Pointer (STKPTR) ........................................ 55
Revision History ............................................................... 371
RLCF ................................................................................ 299
RLNCF ............................................................................. 300
RRCF ............................................................................... 300
RRNCF ............................................................................. 301
S
SCK .................................................................................. 161
SDI ................................................................................... 161
SDO ................................................................................. 161
SEC_IDLE Mode ................................................................ 38
SEC_RUN Mode ................................................................ 34
Serial Clock, SCK ............................................................. 161
Serial Data In (SDI) .......................................................... 161
Serial Data Out (SDO) ..................................................... 161
Serial Peripheral Interface. See SPI Mode.
SETF ................................................................................ 301
Single-Supply ICSP Programming.
Slave Select (SS) ............................................................. 161
Slave Select Synchronization ........................................... 167
SLEEP .............................................................................. 302
Sleep
OSC1 and OSC2 Pin States ...................................... 31
Sleep Mode ........................................................................ 37
Software Simulator (MPLAB SIM) .................................... 318
Software Simulator (MPLAB SIM30) ................................ 318
Special Event Trigger. See Compare (ECCP Mode).
Special Event Trigger. See Compare (ECCP Module).
Special Features of the CPU ............................................ 249
Special Function Registers ................................................ 63
Map ............................................................................ 63
SPI Mode (MSSP)
Associated Registers ............................................... 169
Bus Mode Compatibility ........................................... 169
Effects of a Reset ..................................................... 169
Enabling SPI I/O ...................................................... 165
Master Mode ............................................................ 166
Master/Slave Connection ......................................... 165
Operation ................................................................. 164
Operation in Power Managed Modes ...................... 169
Serial Clock .............................................................. 161
Serial Data In ........................................................... 161
Serial Data Out ........................................................ 161
Slave Mode .............................................................. 167
Slave Select ............................................................. 161
Slave Select Synchronization .................................. 167
SPI Clock ................................................................. 166
Typical Connection .................................................. 165
SS .................................................................................... 161
SSPOV ............................................................................. 191
SSPOV Status Flag .......................................................... 191
SSPSTAT Register
R/W Bit ............................................................. 174, 175
Stack Full/Underflow Resets .............................................. 56
Standard Instructions ....................................................... 267
SUBFSR ........................................................................... 313
SUBFWB .......................................................................... 302
SUBLW ............................................................................ 303
DS39631A-page 382
T
Table Pointer Operations (table) ........................................ 76
Table Reads/Table Writes ................................................. 56
TBLRD ............................................................................. 305
TBLWT ............................................................................. 306
Time-out in Various Situations (table) ................................ 45
Timer0 .............................................................................. 123
Associated Registers ............................................... 125
Operation ................................................................. 124
Overflow Interrupt .................................................... 125
Prescaler ................................................................. 125
Prescaler Assignment (PSA Bit) .............................. 125
Prescaler Select (T0PS2:T0PS0 Bits) ..................... 125
Prescaler. See Prescaler, Timer0.
Reads and Writes in 16-Bit Mode ............................ 124
Source Edge Select (T0SE Bit) ............................... 124
Source Select (T0CS Bit) ......................................... 124
Switching Prescaler Assignment ............................. 125
Timer1 .............................................................................. 127
16-Bit Read/Write Mode .......................................... 129
Associated Registers ............................................... 131
Interrupt ................................................................... 130
Operation ................................................................. 128
Oscillator .......................................................... 127, 129
Oscillator Layout Considerations ............................. 130
Overflow Interrupt .................................................... 127
Resetting, Using the CCP
Special Event Trigger ...................................... 130
Special Event Trigger (ECCP) ................................. 148
TMR1H Register ...................................................... 127
TMR1L Register ....................................................... 127
Use as a Real-Time Clock ....................................... 130
Timer2 .............................................................................. 133
Associated Registers ............................................... 134
Interrupt ................................................................... 134
Operation ................................................................. 133
Output ...................................................................... 134
PR2 Register ................................................... 144, 149
TMR2 to PR2 Match Interrupt .......................... 144, 149
Timer3 .............................................................................. 135
16-Bit Read/Write Mode .......................................... 137
Associated Registers ............................................... 137
Operation ................................................................. 136
Oscillator .......................................................... 135, 137
Overflow Interrupt ............................................ 135, 137
Special Event Trigger (CCP) ................................... 137
TMR3H Register ...................................................... 135
TMR3L Register ....................................................... 135
Timing Diagrams
A/D Conversion ........................................................ 359
Acknowledge Sequence .......................................... 194
Asynchronous Reception ......................................... 214
Asynchronous Transmission .................................... 212
Asynchronous Transmission (Back to Back) ........... 212
Automatic Baud Rate Calculation ............................ 210
Auto-Wake-up Bit (WUE) During
Normal Operation ............................................ 215
Auto-Wake-up Bit (WUE) During Sleep ................... 215
Preliminary
PIC18F2420/2520/4420/4520
Baud Rate Generator with Clock Arbitration ............ 188
BRG Overflow Sequence ......................................... 210
BRG Reset Due to SDA Arbitration
During Start Condition ..................................... 197
Brown-out Reset (BOR) ........................................... 345
Bus Collision During a Repeated
Start Condition (Case 1) .................................. 198
Bus Collision During a Repeated
Start Condition (Case 2) .................................. 198
Bus Collision During a Start Condition
(SCL = 0) ......................................................... 197
Bus Collision During a Stop Condition
(Case 1) ........................................................... 199
Bus Collision During a Stop Condition
(Case 2) ........................................................... 199
Bus Collision During Start Condition
(SDA only) ....................................................... 196
Bus Collision for Transmit and Acknowledge ........... 195
Capture/Compare/PWM (CCP) ................................ 347
CLKO and I/O .......................................................... 344
Clock Synchronization ............................................. 181
Clock/Instruction Cycle .............................................. 57
Example SPI Master Mode (CKE = 0) ..................... 349
Example SPI Master Mode (CKE = 1) ..................... 350
Example SPI Slave Mode (CKE = 0) ....................... 351
Example SPI Slave Mode (CKE = 1) ....................... 352
External Clock (All Modes except PLL) .................... 342
Fail-Safe Clock Monitor (FSCM) .............................. 262
First Start Bit Timing ................................................ 189
Full-Bridge PWM Output .......................................... 153
Half-Bridge PWM Output ......................................... 152
High/Low-Voltage Detect Characteristics ................ 339
High/Low-Voltage Detect Operation
(VDIRMAG = 0) ................................................ 245
High/Low-Voltage Detect Operation
(VDIRMAG = 1) ................................................ 246
I2C Bus Data ............................................................ 353
I2C Bus Start/Stop Bits ............................................. 353
I2C Master Mode (7 or 10-Bit Transmission) ........... 192
I2C Master Mode (7-Bit Reception) .......................... 193
I2C Slave Mode (10-Bit Reception, SEN = 0) .......... 178
I2C Slave Mode (10-Bit Reception, SEN = 1) .......... 183
I2C Slave Mode (10-Bit Transmission) ..................... 179
I2C Slave Mode (7-bit Reception, SEN = 0) ............. 176
I2C Slave Mode (7-Bit Reception, SEN = 1) ............ 182
I2C Slave Mode (7-Bit Transmission) ....................... 177
I2C Slave Mode General Call Address
Sequence (7 or 10-Bit Address Mode) ............ 184
I2C Stop Condition Receive or
Transmit Mode ................................................. 194
Master SSP I2C Bus Data ........................................ 355
Master SSP I2C Bus Start/Stop Bits ........................ 355
Parallel Slave Port (PIC18F4420/4520) ................... 348
Parallel Slave Port (PSP) Read ............................... 121
Parallel Slave Port (PSP) Write ............................... 121
PWM Auto-Shutdown (PRSEN = 0,
Auto-Restart Disabled) .................................... 158
PWM Auto-Shutdown (PRSEN = 1,
Auto-Restart Enabled) ..................................... 158
PWM Direction Change ........................................... 155
PWM Direction Change at Near
100% Duty Cycle ............................................. 155
Preliminary
DS39631A-page 383
PIC18F2420/2520/4420/4520
PLL Clock ................................................................. 343
Reset, Watchdog Timer, Oscillator Start-up Timer,
Power-up Timer and Brown-out Reset
Requirements ................................................... 345
Timer0 and Timer1 External
Clock Requirements ......................................... 346
USART Synchronous Receive Requirements ......... 357
USART Synchronous Transmission
Requirements ................................................... 357
Top-of-Stack Access .......................................................... 54
TRISE Register
PSPMODE Bit .......................................................... 114
TSTFSZ ............................................................................ 307
Two-Speed Start-up ................................................. 249, 260
Two-Word Instructions
Example Cases .......................................................... 58
TXSTA Register
BRGH Bit ................................................................. 205
DS39631A-page 384
V
Voltage Reference Specifications .................................... 338
W
Watchdog Timer (WDT) ........................................... 249, 258
Associated Registers ............................................... 259
Control Register ....................................................... 258
During Oscillator Failure .......................................... 261
Programming Considerations .................................. 258
WCOL ...................................................... 189, 190, 191, 194
WCOL Status Flag ................................... 189, 190, 191, 194
WWW, On-Line Support ...................................................... 6
X
XORLW ............................................................................ 307
XORWF ........................................................................... 308
Preliminary
PIC18F2420/2520/4420/4520
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip
World Wide Web site.
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape or Microsoft
Internet Explorer. Files are also available for FTP
download from our FTP site.
042003
Preliminary
DS39631A-page 385
PIC18F2420/2520/4420/4520
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information and use this outline to provide us with your comments about this document.
To:
RE:
Reader Response
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
Application (optional):
Would you like a reply?
Device: PIC18F2420/2520/4420/4520
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
DS39631A-page 386
Preliminary
PIC18F2420/2520/4420/4520
PIC18F2420/2520/4420/4520 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
/XX
XXX
Device
Temperature
Range
Package
Pattern
Examples:
a)
b)
Device
PIC18F2420/2520(1), PIC18F4420/4520(1),
PIC18F2420/2520T(2), PIC18F4420/4520T(2);
VDD range 4.2V to 5.5V
PIC18LF2420/2520(1), PIC18LF4420/4520(1),
PIC18LF2420/2520T(2), PIC18LF4420/4520T(2);
VDD range 2.0V to 5.5V
Temperature Range
I
E
=
=
Package
PT
SO
SP
P
ML
=
=
=
=
=
Pattern
c)
Note 1:
2:
Preliminary
DS39631A-page 387
China - Beijing
Korea
Corporate Office
Unit 706B
Wan Tai Bei Hai Bldg.
No. 6 Chaoyangmen Bei Str.
Beijing, 100027, China
Tel: 86-10-85282100
Fax: 86-10-85282104
China - Chengdu
Boston
China - Fuzhou
Atlanta
Chicago
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 630-285-0071
Fax: 630-285-0075
Dallas
4570 Westgrove Drive, Suite 160
Addison, TX 75001
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250
Fax: 248-538-2260
Kokomo
2767 S. Albright Road
Kokomo, IN 46902
Tel: 765-864-8360
Fax: 765-864-8387
Los Angeles
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 949-263-1888
Fax: 949-263-1338
San Jose
1300 Terra Bella Avenue
Mountain View, CA 94043
Tel: 650-215-1444
Fax: 650-961-0286
Toronto
6285 Northam Drive, Suite 108
Mississauga, Ontario L4V 1X5, Canada
Tel: 905-673-0699
Fax: 905-673-6509
ASIA/PACIFIC
Australia
Suite 22, 41 Rawson Street
Epping 2121, NSW
Australia
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Singapore
Taiwan
Kaohsiung Branch
30F - 1 No. 8
Min Chuan 2nd Road
Kaohsiung 806, Taiwan
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Taiwan
Taiwan Branch
11F-3, No. 207
Tung Hua North Road
Taipei, 105, Taiwan
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
EUROPE
China - Shanghai
Austria
Durisolstrasse 2
A-4600 Wels
Austria
Tel: 43-7242-2244-399
Fax: 43-7242-2244-393
Denmark
China - Shenzhen
China - Shunde
Room 401, Hongjian Building, No. 2
Fengxiangnan Road, Ronggui Town, Shunde
District, Foshan City, Guangdong 528303, China
Tel: 86-757-28395507 Fax: 86-757-28395571
China - Qingdao
Rm. B505A, Fullhope Plaza,
No. 12 Hong Kong Central Rd.
Qingdao 266071, China
Tel: 86-532-5027355 Fax: 86-532-5027205
India
Divyasree Chambers
1 Floor, Wing A (A3/A4)
No. 11, OShaugnessey Road
Bangalore, 560 025, India
Tel: 91-80-22290061 Fax: 91-80-22290062
Japan
Benex S-1 6F
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa, 222-0033, Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
France
Parc dActivite du Moulin de Massy
43 Rue du Saule Trapu
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany
Steinheilstrasse 10
D-85737 Ismaning, Germany
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Italy
Via Quasimodo, 12
20025 Legnano (MI)
Milan, Italy
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands
Waegenburghtplein 4
NL-5152 JR, Drunen, Netherlands
Tel: 31-416-690399
Fax: 31-416-690340
United Kingdom
505 Eskdale Road
Winnersh Triangle
Wokingham
Berkshire, England RG41 5TU
Tel: 44-118-921-5869
Fax: 44-118-921-5820
05/28/04
DS39631A-page 388
Preliminary