IMPLEMENT J k flip flop

entity jk is
port (j,k,clk,clr:in bit;q:inout bit);
end jk;
architecture arc_jk of jk is
begin
process(clk,clr)
begin
if(clr='1') then
q<='0';
elsif(clk'event and clk='1') then
if(j='0' and k='0') then
q<=q;
elsif(j='0' and k='1') then
q<='0';
elsif(j='1' and k='0') then
q<='1';
elsif(j='1' and k='1') then
q<=(not q);
end if;
end if;
end process;
end architecture;
test bench
entity tb is
end tb;
architecture testbench of tb is
component jk is
port (j,k,clk,clr:in bit;q:inout bit);
end component;
signal j1,k1,clk1,clr1,q1:bit;
begin
jk1:jk port map(j1,k1,clk1,clr1,q1);
process
begin
clk1<=not clk1; wait for 20 ps;
j1<=not j1 after 40 ps;
k1<=not k1 after 80 ps;
clr1<=not clr1 after 160 ps;
end process;
end architecture;

IMPLEMENT T FLIP FLOP

entity tff is
port(t,clk:in bit;q:inout bit);
end tff;
architecture tff_arch of tff is
begin
process(clk,t)-- for behavioral
begin
if(clk='1'and clk'event)then
if(t='1')then
q<=not q;
end if;
end if;
end process;
end tff_arch;

test bench
entity tb is
end tb;
architecture tb_arch of tb is
component tff
port(t,clk:in bit;q:inout bit);
end component;
signal t,clk,q:bit;
begin
process(t,clk)
begin
t<=not t after 20 ps;
clk<=not clk after 20 ps;
end process;
inst:tff port map(t,clk,q);
end tb_arch;

IMPLEMENT D FLIP FLOP

entity dff is
port(d,clk,clr:in bit;q: out bit);
end dff;
architecture dff_arch of dff is
begin
process(clk,clr)
begin
if(clr='1')then
q <='0';
end if;
if(clk 'event and clk='1') then
q <=d;
end if ;
end process ;
end dff_arch ;

entity testbench is
end testbench;
architecture test_arch of testbench is
component dff
port(d,clk,clr:in bit;q:out bit);
end component;
signal d1,clk1,clr1,q1:bit;
begin
inst1: dff port map(d1,clk1,clr1,q1);
process
begin
d1<=not d1;wait for 20 ps;
clk1<=not clk1;wait for 100 ps;
clr1<=not clr1;wait for 20 ps;
end process;
end test_arch;

IMPLEMENT 4 bit comparator

--libraries to be used are specified here

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--entity declaration with port definitions
entity compare is
port( num1 : in std_logic_vector(3 downto 0); --input 1
num2 :
in std_logic_vector(3 downto 0); --input
2
less :
out std_logic; -- indicates first
number is small
equal :
out std_logic; -- both are equal
greater : out std_logic -- indicates first number is
bigger
);
end compare;
--architecture of entity
architecture Behavioral of compare is
begin
process(num1,num2)
begin -- process starts with a 'begin' statement
if (num1 > num2 ) then --checking whether num1 is
greater than num2
less <= '0';
equal <= '0';
greater <= '1';
elsif (num1 < num2) then --checking whether num1 is
less than num2
less <= '1';
equal <= '0';
greater <= '0';
else
--checking whether num1 is equal to num2
less <= '0';
equal <= '1';
greater <= '0';
end if;

end process; -- process ends with a 'end process'

statement
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
test bench
entity testbench is
end testbench;
architecture behavior of testbench is
--signal declarations.
signal num1,num2 : std_logic_vector(3 downto 0)
:=(others => '0');
signal less,equal,greater : std_logic:='0';
begin
--entity instantiation
UUT : entity work.compare port
map(num1,num2,less,equal,greater);
--definition of simulation process
tb : process
begin
num1<="0010"; --num1 =2
num2<="1001"; --num2 =9
wait for 20 ps;
num1<="1001"; --num1 =9
num2<="0010"; --num2 =2
wait for 20 ps;
num1<="1010"; --num1 =10
num2<="1010"; --num2 =10
--more input combinations can be given here.

wait for 20 ps;

end process tb;
end;

8 BIT SHIFT REGISTER

entity shifter is
port (si,clk,clr:in bit;s1,s2,s3,s4,s5,s6,s7,s8:inout bit);
end shifter;
architecture arc of shifter is
component dff is
port (d,clk,clr:in bit;q :out bit);
end component;
begin
d1: dff port map(si,clk,clr,s1);
d2:dff port map(s1,clk,clr,s2);
d3:dff port map(s2,clk,clr,s3);
d4:dff port map(s3,clk,clr,s4);
d5:dff port map(s4,clk,clr,s5);
d6:dff port map(s5,clk,clr,s6);
d7:dff port map(s6,clk,clr,s7);
d8:dff port map(s7,clk,clr,s8);
end architecture;
test bench
entity tb is
end tb;
architecture test of tb is
component shifter is
port (si,clk,clr:in bit;s1,s2,s3,s4,s5,s6,s7,s8:inout bit);
end component;
signal si1,clk1,clr1:bit;
signal s:bit_vector(7 downto 0);
begin
shift1: shifter port
map(si1,clk1,clr1,s(0),s(1),s(2),s(3),s(4),s(5),s(6),s(7));
process
begin

si1<=not si1 after 30 ps;

clk1<=not clk1;
wait for 10 ps;
end process;
end architecture;

ALU
entity alu is
port (L,M:in bit_vector(3 downto 0);
CIN,SEL1,SEL2,SEL3: in bit;
FOUT: out bit_vector(3 downto 0));
end entity;
architecture alu_arch of alu is
component arthm_comp is
port (x,y: in bit_vector(3 downto 0);
cin,op1,op2: in bit;
f1: out bit_vector(3 downto 0));
end component;
component logical is
port(x: in bit_vector(3 downto 0);
y: in bit_vector(3 downto 0);
op1,op2: in bit;
f2: out bit_vector(3 downto 0));
end component;
component mux2x1 is
port (i1,i2: in bit;
s1: in bit;
e: out bit);
end component;
signal val1,val2: bit_vector(3 downto 0);
begin
AC: arthm_comp port map(L,M,CIN,SEL1,SEL2,val1);
LC: logical port map(L,M,SEL1,SEL2,val2);
MUX1: mux2x1 port map(val1(0),val2(0),SEL3,FOUT(0));
MUX2: mux2x1 port map(val1(1),val2(1),SEL3,FOUT(1));
MUX3: mux2x1 port map(val1(2),val2(2),SEL3,FOUT(2));
MUX4: mux2x1 port map(val1(3),val2(3),SEL3,FOUT(3));
end alu_arch;
test bench

entity alu_testbench is
end entity;
architecture alu_test_arch of alu_testbench is
component alu is
port (L,M:in bit_vector(3 downto 0);
CIN,SEL1,SEL2,SEL3: in bit;
FOUT: out bit_vector(3 downto 0));
end component;
signal in1,in2,out1:bit_vector(3 downto 0);
signal cin,s1,s2,s3 :bit;
begin
inst1: alu port map(in1,in2,cin,s1,s2,s3,out1);
process
begin
in1 <= "0001";
in2 <= "0101";
cin <='0';
s1 <= '0';
s2 <= '0';
s3 <= '0';
wait for 20 ps;
s1 <= '0';
s2 <= '1';
wait for 20 ps;
s1 <= '1';
s2 <= '0';
wait for 20 ps;
s1 <= '1';
s2 <= '1';
wait for 20 ps;
s1 <= '0';
s2 <= '0';
s3 <= '1';
wait for 20 ps;
end process;
end alu_test_arch;

IMPLEMENTATION OF SHIFT REGISTERS

LEFTSHIFTER
entity leftshifter is
port(a:in bit_vector;al:out bit_vector);
end leftshifter;
architecture leftsh_arch of leftshifter is begin
al(1)<=a(0);
al(2)<=a(1);
al(3)<=a(2);
al(0)<='0';
end leftsh_arch;
LOGICAL
entity logical is
port(a,b,s1,s0:in bit;z:out bit);
end logical;
architecture logical_arch of logical is
component mux4x1
port(a,b,c,d,s1,s0:in bit;z:out bit);
end component;
signal y0,y1,y2,y3:bit;
Begin y0<=a and b;
y1<=a or b;

y2<=not a;
y3<=a nand b;
inst:mux4x1 port map(y0,y1,y2,y3,s1,s0,z);
end logical_arch;

RIGHTSHIFTER
entity rightshifter is
port(a:in bit_vector;ar:out bit_vector);
end rightshifter;
architecture rightsh_arch of rightshifter is begin
ar(0)<=a(1);
ar(1)<=a(2);
ar(2)<=a(3);
ar(3)<='0';
end rightsh_arch;

TEST BENCH

entity tb is
end tb;
architecture tb_arch of tb is
component alu
port(s,a,b:in bit_vector;f:out bit_vector);

end component;
signal s,a,b,f:bit_vector(3 downto 0);
begin
inst:alu port map(s,a,b,f);
process
begin s<="0011";
wait for 20 ps;
a<="1100";
wait for 20 ps;
b<="0011";
wait for 20 ps;
s<="1100";
wait for 20 ps;
a<="1001";
wait for 20 ps;
b<="0000";
wait for 20 ps;
end process;
end tb_arch;

Implement up down counter

8 bit updown counter
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity counter is
port ( src1: in std_logic_vector(7 downto 0);
inc,clk,up: in std_logic;
dest: out std_logic_vector(7 downto 0));
end entity;
architecture counter_arch of counter is
signal count: std_logic_vector(7 downto 0);
begin
process(clk)
begin
if(clk = '1') then
if(up = '1') then
count <= src1 + inc;
else
count <= src1 - inc;
end if;
end if;
end process;
process(count)
--the code was needed to be entered in process so that it
executes
--only when count value is computed. Otherwise both the
if condition and
--the count assignment will take place simultaneously.
begin
dest <= count;
end process;
end counter_arch;
test bench
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

use IEEE.std_logic_unsigned.all;
entity counter_test is
end entity;
architecture counter_test_arch of counter_test is
component counter is
port ( src1: in std_logic_vector(7 downto 0);
inc,clk,up: in std_logic;
dest: out std_logic_vector(7 downto 0));
end component;
signal in_count: std_logic_vector(7 downto
0):="00000000";
signal out_count: std_logic_vector(7 downto 0);
signal inc,clk,sel: std_logic;
begin
inst2: counter port map(in_count,inc,clk,sel,out_count);
process
begin
inc <= '1';
clk <= '1';
wait for 10 ps;
clk <= '0';
in_count <= out_count;
wait for 10 ps;
end process;
process
begin
sel <= '1';
wait for 400 ps;
sel <= '0';
wait for 400 ps;
end process;
end counter_test_arch;

Ring Counter

D- Flip Flop
entity dflipflop is
port (d,clk:in bit;
q:buffer bit);
end entity;
architecture dflipflop_arch of dflipflop is
begin
process (clk)
begin
if (clk='1')and (clk'event) then
q<=d;
end if;
end process;
end dflipflop_arch;

Ring Counter
entity ringcounter is
port (clk:in bit;
input:in bit_vector(3 downto 0);
output:buffer bit_vector(3 downto 0));
end entity;
architecture arch of ringcounter is
component dflipflop is
port (d,clk:in bit;
q:buffer bit);
end component;
begin
inst3:dflipflop port map(input(0),clk,output(3));
inst2:dflipflop port map(input(3),clk,output(2));
inst1:dflipflop port map(input(2),clk,output(1));
inst0:dflipflop port map(input(1),clk,output(0));
end arch;

Test Bench
entity testbench is
end entity;
architecture test of testbench is
component ringcounter is
port (clk:in bit;
input:in bit_vector(3 downto 0);
output:buffer bit_vector(3 downto 0));
end component;
signal clk,init:bit;
signal input,output:bit_vector(3 downto 0);
begin
inst:ringcounter port map(clk,input,output);
clk<=not clk after 20 ps;
process
begin
init<='1';

wait for 20 ps;

init<='0';
wait for 400 ps;
end process;
process(clk,init)
begin
if clk='1' and clk'event then
if (init='1') then
input<="0001";
else if init='0' then
input<=output;
end if;
end if;
end if;
end process;
end test;