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The Hardware Book' PDF
The Hardware Book' PDF
Welcome to the Hardware Book. Internet's largest free collection of connector pinouts and cable
descriptions.
Newsflash! A new version of The Hardware Book has been released as of 2001-06-08! See News for
more details.
This is an offline version, the latest release of HwB can be found at http://www.hardwarebook.net/.
Connectors
Cables
Adapters
Circuits
Tables
Wanted
About
Comment
Audio/Video
Audio
ActionMedia 2 Audio/Video Capture
Amiga 1000 RF Monitor
Apple AudioVision
CBM 1902A
NeoGeo Audio/Video
Sony RGB Multi Input
TI-99/4A Video/Audio
Consoles
Atari Jaguar A/V
N64 Video
PlayStation A/V
Sega Dreamcast A/V
Sega Genesis 2/32X/Nomad A/V
Sega Genesis/Master A/V
Sega Saturn A/V
SNES Video
SNES2 Video
Digital
Digital Flat Panel (DFP)
Digital Visual Interface (DVI)
Enhanced Video Connector (EVC)
OpenLDI
Plug and Display Analog/Digital (P&D-A/D)
Plug and Display Digital (P&D-D)
Home Audio/Video
3.5 mm Mono Tele
3.5 mm Stereo Tele
6.25 mm Mono Tele
6.25 mm Stereo Tele
DIN Audio
S-Video
SCART
TurboVision Turbo Express TV Tuner
VHS Video Camera
Home computers
Amstrad CPC6128 Monitor
Amstrad CPC6128 Plus Monitor
Amstrad CPC6128 Stereo
Atari Falcon030 RGB/VGA
Atari ST Monitor Connector
C128 RGBI
C128/C64C Video
C16/C116/+4 Audio/Video
C64 Audio/Video
C65 Video
CDTV Video Slot
CM-8/CoCo RGB
Spectravideo SVI318/328 Audio/Video
ZX Spectrum 128 RGB
Video
3b1/7300 Video
ActionMedia 2 Audio/Video Capture
Amiga 1000 RF Modulator
Amiga 1000 RF Monitor
Amiga Video
Apple AudioVision
Apple II Video Expansion
Apple Macintosh II/IIci Video
Apple Macintosh LC External Video
Apple S-Video Input
Buses
Accelerated Graphics Port (AGP)
Amiga 1200 CPU-port
Amiga Video Expansion
Apple Duo Dock
Apple Macintosh Portable Processor-Direct Slot (PPDS)
Apple Macintosh Processor-Direct Slot (PDS)
C-bus II
CardBus
CompactPCI
CompactPCI (technical)
ECBbus
EISA
EISA (technical)
Electrocoin
IEEE1394
IEEE1394 (technical)
ISA
ISA (technical)
IndustrialPCI
JAMMA
MCA
Miniature Card
Miniature Card (technical)
NuBus
NuBus 90
PC Card
PC/104
PCI
PCI (technical)
PCMCIA
SSFDC
SUN SBus
SmallPCI
Unibus
Universal Serial Bus (USB)
Universal Serial Bus (USB) (technical)
VESA LocalBus (VLB)
VESA LocalBus (VLB) (technical)
VME64x
VME64x (technical)
VMEbus
Zorro II
Zorro II/III
Cartridges/Expansions
Audio
Apple Digital Audio/Video (DAV)
Video
Apple Digital Audio/Video (DAV)
Apple Digital Video Application (DVA)
+4 User Port
Amiga 1000 Ramex
Apple Communication Slot
Apple Macintosh Portable ROM Expansion
Atari 2600 Cartridge
Atari 5200 Cartridge
Atari 5200 Expansion
Atari 7800 Cartridge
Atari 7800 Expansion
Atari Cartridge Port
Atari Falcon030 DSP Port
C128 Expansion Bus
C16/+4 Expansion Bus
C64 Cartridge Expansion
C64 RS232 User Port
C64 User Port
CD32 Expansion-port
CDTV Diagnostic Slot
CDTV Expansion Slot
Commodore PET Parallel User Port
GameBoy Cartridge
GameBoy Cartridge
GeekPort
MSX Expansion
PC-Engine Cartridge
Psion Organiser II Connector Top Slot (D)
SNES Cartridge
SUN SROMBO
SUN SROMBOlite
Spectravideo SVI318/328 Expansion Bus
Cellular Phones
Alcatel HC600/800/1000
Ericsson 218/337/318/388
Ericsson 628/788
Ericsson 688/888
Motorola 6200/7500/8200/8400/8700
NEC P3
Nokia 1610
Nokia 2110
Nokia 31xx/81xx
Nokia 5110/6110
Panasonic G500
Phillips Fizz/Spark
Siemens C25/S25
Sony CMD 1000
Memories
DIMM
144 pin SO DIMM
168 pin DRAM DIMM (Unbuffered)
168 pin SDRAM DIMM (Unbuffered)
SIMM
30 pin SIMM
72 pin ECC SIMM
72 pin SIMM
Smartcard
SmartCard AFNOR
SmartCard ISO
SmartCard ISO 7816-2
72 pin SO DIMM
CDTV Memory Card
CompactFlash
Power Mac L2 Cache
Misc
Harddrive
Atari ACSI DMA
Printer
Atari ACSI DMA
UPS
Triplite OmniPro 675 UPS
UPS YUNTO P Series (250/500/750/1250)
Networks
AUI
Apple AUI (AAUI)
AUI
Media Independent Interface (MII)
SUN AUI
Ethernet
Ethernet 10/100Base-T
Ethernet 1000Base-T
Ethernet 100Base-T4
Network Information
Parallel
Parallel
ECP Parallel
ECP Parallel (technical)
IEEE1284-B
IEEE1284-C
MSX Parallel
Parallel (Amiga 1000)
Parallel (Amiga)
Parallel (Olivetti M10)
Parallel (PC)
Parallel (SUN)
Printer
Amstrad CPC6128 Printer Port
Centronics
Dataproducts D-Sub 50 Parallel
Dataproducts M/50 Parallel
DEC Printer
Video
IndyCam Digital Video Port
IEEE488
PC
3.5" Power
5.25" Power
AT Backup Battery
AT LED/Keylock
Motherboard CPU Cooling fan
Motherboard IrDA
Motherboard Power
PC Speaker
Turbo LED
Power Supply
Amiga
Amiga 2000 Power Supply
Amiga 3000 Power Supply
Amiga 3000T Power Supply
Amiga 500/600/1200 Power Supply
ATX
ATX +12V Power Supply
ATX Aux Power Supply
ATX Optional Power
ATX Power Supply
SFX
SFX Optional Power
SFX Power Supply
WTX
WTX 12V CPU (P3)
WTX 12V CPU (P4/P5)
WTX Additional (P2)
WTX Main (P1)
Apple Macintosh Classic Internal Power
C64 Power Supply
SUN Power
Sun Aux Power
Serial
Apple 300/1200 Modem
Apple Duo Dock Modem Adapter Card
Apple ImageWriter Serial
Apple LaserWriter AppleTalk
Apple LaserWriter Serial
Apple Macintosh XL Serial A
Apple Macintosh XL Serial B
file:///C|/tmp/tech/HwB/connector/index.html (9 of 14) [6/14/2001 11:59:22 PM]
AppleLine RS232
C64 Serial I/O
Cisco Console Port
CoCo Serial Printer
Conrad Electronics MM3610D
DEC DLV11-J Serial
DEC Dual RS-232
DEC MMJ
EIA-449 (RS-449)
EIA-449 (RS-449) Secondary
EIA530 (RS530)
HP 4S Scanner
HP48/HP95
ITU-TSS V.35
ITU-TSS X.21
Lowrance AirMap 100, GlobalMap 100, GlobalNav 12, GlobalNav 200, GlobalNav 212
Lowrance AirMap, AirMap 300, GlobalMap 12, GlobalMap Sport
Lowrance GlobalNav 310
MIDI In
MIDI Out
Macintosh RS-422
Macintosh Serial
Minuteman UPS
RS-232D
RS232
RS366
RS422 37pin
RS422 9pin
RocketPort Serialport
SUN LX/Classic/SS4/5/10/20 Serial Port
Serial (15)
Serial (Amiga 1000)
Serial (Amiga)
Serial (MSX)
Serial (PC 25)
Serial (PC 9)
Serial (Printer)
Serial (SGI MiniDIN)
Serial (SUN)
Storage
Cassette
Amstrad CPC6128 Tape
C16/C116/+4 Cassette
C64 Cassette
Cassette TI-99/4a
CoCo Cassette
MSX Cassette
Spectravideo SVI318/328 Cassette
CD-ROM
Mitsumi CD-ROM
Panasonic CD-ROM
Sony CD-ROM
Floppy
8" Floppy Diskdrive
Amiga External Diskdrive
Amstrad CPC6128 Diskdrive 2
Amstrad CPC6128 Plus External Diskdrive
Apple Macintosh External Drive
Apple Macintosh Internal Floppy disk drive
Atari Floppy Port
Internal Diskdrive
Macintosh External Drive
MSX External Diskdrive
SUN Internal Floppydrive
Harddrive
ESDI
PC Card ATA
ST506/412
IDE/ATA
ATA (44) Internal
ATA Internal
IDE Internal
Paravision SX-1 External IDE
PC Card ATA
SCSI
Information
SCSI Information
Apple SCSI HDI-30
Novell and Procomp External SCSI
SCSI External Centronics 50 (Differential)
SCSI External Centronics 50 (Single-ended)
SCSI External D-Sub (Future Domain)
SCSI External D-Sub (PC/Amiga/Mac)
SCSI External IBM Burndy
SCSI Internal (2.5")
SCSI Internal (Differential)
SCSI Internal (Single-ended)
SCSI-II External Hi D-Sub (Differential)
SCSI-II External Hi D-Sub (Single-ended)
SCSI-III External Hi D-Sub (Differential)
SCSI-III External Hi D-Sub (Differential)
SCSI-III External Hi D-Sub (Single-ended)
SCSI-III External Hi D-Sub (Single-ended)
Adaptec RAIDport
IEEE488
Mice/Keyboards/Joysticks
Joystick
Amstrad Digital Joystick
Apple IIc Joystick
Atari 2600 Controller Pinouts
Atari 2600 Joystick
Atari 5200 Joystick
file:///C|/tmp/tech/HwB/connector/index.html (12 of 14) [6/14/2001 11:59:22 PM]
Keyboard
AT&T 6300 Keyboard
Keyboard (5 Amiga)
Keyboard (5 PC)
Keyboard (6 Amiga)
Keyboard (6 PC)
Keyboard (Amiga CD32)
Keyboard (XT)
Macintosh Keyboard
Macintosh Keyboard Connector
SUN Keyboard/Mouse
TI-99/4A Keyboard
Mouse
Amiga Mouse/Joy
Apple Macintosh Mouse Connector
Macintosh Mouse
Mouse (PS/2)
SGI Mouse (Model 021-0004-002) Connector
SUN Keyboard/Mouse
Serial
Apple Desktop Bus (ADB)
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-08
Short tutorial
Heading
First at each page there a short heading describing what the connector is.
Pin table
The pin table is perhaps the information you are looking for. Should be simple to read. Contains mostly
the following three columns; Pin, Name & Description.
Pin
1
2
3
4
5
Name
CLOCK
GND
DATA
VCC
n/c
Description
Key Clock
GND
Key Data
+5 VDC
Not connected
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Connector pinouts.
Cable & adapters descriptions.
Circuits for the Circuit section.
Error/bugs found in HwB.
Apply to become a mirror of HwB.
General info for HwB.
Please don't send questions like "Do you have the pinout to Xyz", "Can you help us to repair my Xyz" or
"Where can I buy an Xyz", please redirect these to a UseNet newsgroup instead. Try Groups.Google.com
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
Description
Composite Sync Input
Blue Video Input
Red Video Input
Video Ground
Left Audio Input
Green Video Input
Right Audio Input
Audio Ground
Name Dir
Description
n/c
Not connected
GND
Ground
AUDL
Audio Left
CVIDEO
Composite Video
GND
Ground
n/c
Not connected
+12V
+12 VDC
AUDR
Audio Right
Apple AudioVision
45 PIN UNKNOWN CONNECTOR ??
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
24
25
26
27
28
29
30
31
Name
Analog audio ground
Audio input shield
Left channel audio input
Right channel audio input
Left channel audio output
Right channel audio output
Reserved
Monitor ID sense line 1
Monitor ID sense line 2
Green ground (shield)
Green video output (75 )
Video input power ground
Power for camera +5 V
Reserved
Reserved
Reserved
Reserved
Monitor ID sense line 3
S-video input shield
S-video input luminance (Y)
S-video input chroma (C)
Reserved
Reserved
Reserved
Red ground (shield)
Red video output (75 )
I2C data signal
I2C clock signal
Reserved
Monitor ID
32
33
34
35
36
37
38
39
40
41
42
43
44
45
Monitor ID
Vertical sync signal
Composite sync signal
ADB power +5 V
ADB ground
ADB data
Keyboard switch
Reserved
Reserved
Monitor ID
Horizontal sync signal
Video sync ground
Blue ground (shield)
Blue video output (75 )
CBM 1902A
Available on the Commodore CBM 1902A monitor.
NeoGeo Audio/Video
Available on the NeoGeo videogame.
Name Dir
Description
AOUT
Audio out
GND
Ground
VIDEO
Composite Video Out
+5V
+5 VDC
GREEN
Green Video
RED
Red Video
NSYNC
Negative Sync
BLUE
Blue Video
Description
+5V power supply
+5V power supply
Audio (R) input GND
GND
Remote control GND
Composite video output GND
Audio (L) input GND
Red Return (GND)
Green Return (GND)
Blue Return (GND)
GND
Blanking input Return (GND)
H.sync Return (GND)
N.C.
V.sync Return (GND)
GND
N.C.
N.C.
N.C.
Audio (R) Input
Mode Select
N.C.
Composite Video Output
Audio (L) Input
Red Input
26
27
28
29
30
31
32
33
34
Green Input
Blue input
N.C.
Blanking Input
H.sync or composite sync
V.sync
N.C.
RGB/NORMAL mode select
Audio Select
TI-99/4A Video/Audio
(At the Computer)
at the Computer.
Pin
1
2
3
4
5
U
Name
12V vid
R-Y
AUDIO
Y
B-Y
GND
Description
color burst clock
Sound output
external video input?
GROUND
2A
3A
4A
5A
6A
7A
8A
9A
10A
11A
12A
1B
2B
3B
4B
5B
6B
7B
8B
9B
10B
11B
12B
Name
Description
AL
Audio Left
AGND
Audio Ground
GND
Ground
GND (chroma) Ground (Chroma)
B
RGB Blue
HSYNC
Horizontal sync
G
RGB Green
CHROMA
Chroma
GND ???
Ground ???
+5V ???
+5 VDC ???
+5V ???
+5 VDC ???
?
?
1B
2B
3B
4B
5B
6B
7B
8B
AR
AGND
GND
R
CSYNC
?
LGND
LUM
Right audio
Audio GND
Ground
RGB Red
Composite (Vertical) Sync
?
Luminance Ground
Luminance
9B
10B
11B
12B
GND
CVBSGND
CVBS
?
Ground
Composite Video Ground
Composite Video
?
N64 Video
Available on the Nintendo N64.
Name
n/c
n/c
n/c
n/c
GND
GND
Y
C
CVBS
+5V
L+R
L-R
Description
Not connected
Not connected
Not connected
Not connected
Ground
Ground
S-Video Y
S-Video C
Composite Video
+5 VDC
Left+Right Audio (Mono)
Left-Right Audio (Used to calculate Stereo)
PlayStation A/V
Available on the Sony PlayStation Videogame.
+--------------+
| oooooooooooo |
+--------------+
1
12
Name
GND
RT
GND
LT
Y
SYNC
C
VGND
B
+5V
R
G
Description
Ground
Right Audio
Ground
Left Audio
S-Video Y
Composite Sync
S-Video C
Video Ground
Blue
+5 VDC
Red
Green
Description
Ground
Right Audio
Left Audio
+12v
+5v
31 kHz RGB - (VGA rate) Connect to GND with pin 7
15 kHz RGB - (TV rate) Connect to GND
Vertical Sync (for VGA)
Horizontal Sync (for VGA)
Composite Sync
S-video
S-video
Composite Video
Blue (Use 220uf cap)
Green (Use 220uf cap)
Red (use 220uf cap)
Description
Blue
+5VDC
Green
Composite Video
Sync
Audio Mono
Red
Stereo L
Stereo R
Description
Composite Video
Ground
Audio Mono
Green
+5VDC
Sync
Red
Blue
Description
Sync
Stereo L
Stereo R
+5VDC
Red
Green
Blue
Composite Video
Luminance
Chrominance
SNES Video
Available on the Nintendo SNES.
Name
R
G
CSYNC
B
GND
GND
Y
C
CVBS
+5V
L+R
L-R
Description
Red (Requires 200 uF in series)
Green (Requires 200 uF in series)
Composite Sync
Blue (Requires 200 uF in series)
Ground
Ground
S-Video Y
S-Video C
Composite Video
+5 VDC
Left+Right Audio (Mono)
Left-Right Audio (Used to calculate Stereo)
SNES2 Video
Available on the newer models of Nintendo SNES.
Name
R
G
CSYNC
B
GND
GND
n/c
n/c
CVBS
+5V
L+R
L-R
Description
Red (Requires 200 uF in series)
Green (Requires 200 uF in series)
Composite Sync
Blue (Requires 200 uF in series)
Ground
Ground
Not connected
Not connected
Composite Video
+5 VDC
Left+Right Audio (Mono)
Left-Right Audio (Used to calculate Stereo)
Name
TX1+
TX1SHLD1
SHLDC
TXC+
TXCGND
+5V
NC
NC
TX2+
TX2SHLD2
SHLD0
TX0+
TX0NC
HPD
DDC_DAT
DDC_CLK
Name
TMDS Data2TMDS Data2+
TMDS Data2 Shield
No Connection
No Connection
DDC Clock
DDC Data
No Connection
TMDS Data1TMDS Data2+
TMDS Data1 Shield
No Connection
No Connection
+5 V Power
Ground (for +5 V)
Hot Plug Detect
TMDS Data0TMDSData0+
TMDS Data0Shield
No Connection
No Connection
TMDS Clock Shield
TMDS Clock +
TMDS Clock <
Name
Audio output, Right
Audio output, Left
Audio output return
Sync return
Horizontal sync (TTL)
Vertical sync (TTL)
Reserved
Reserved
1394 pair A, data 1394 pair A, data +
Reserved
Reserved
Video input, Y or composite in
Video input, return
Video input, C in
USB data +
USB data USB/1394 common mode shield
1394 Vg
1394 Vp
21
22
23
24
25
26
27
28
29
30
C1
C2
C3
C4
C5
OpenLDI
36 PIN MDR36 FEMALE
Used on SGI digital flat panel monitors.
Standard by VICI
Protocol: LVDS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Name
Link2 D0Link2 DO+
Link2 D1Link2 D1+
Link2 D2Link2 D2+
NC NC
NC NC
GND GND
GND GND
NC NC
NC NC
Link1 D0Link1 D0+
Link1 D1Link1 D1+
Link1 D2Link1 D2+
Link2 D3Link2 D3+
Link2 CLKLink2 CLK+
NC NC
NC NC
25
26
27
28
29
30
31
32
33
34
35
36
NC NC
GND GND
NC NC
GND GND
NC NC
NC NC
NC NC
GND GND
Link1 CLKLink1 CLK+
Link1 D3Link1 D3+
Name
TMDS Data 2 +
TMDS Data 2 TMDS Data return
Hz and Vt Sync return
Horizontal sync/Composite sync
Vertical sync
TMDS Clock return
Charge power
1394 pair A, data 1394 pair A, data +
TMDS Data 1 +
TMDS Data 1 TMDS Data 1 return
TMDS Clock +
TMDS Clock USB data +
USB data 1394 outer shield (optional) & Charge Power return
19
20
21
22
23
24
25
26
27
28
29
30
C1
C2
C3
C4
C5
1394 Vg
1394 Vp
TMDS Data 0 +
TMDS Data 0 TMDS Data 0 return
Stereo sync (TTL)
DDC return & Stereo Sync return
DDC data (SDA)
DDC clock (SCL)
+5 VDC
1394 pair B, clock +
1394 pair B, clock Red Video
Green Video
Pixel clock (optional)
Blue Video
Video / Pixel Clock Ground
Name
TMDS Data 2 +
TMDS Data 2 TMDS Data return
Unused
Unused
Unused
TMDS Clock return
Charge power (optional)
1394 pair A, data 1394 pair A, data +
TMDS Data 1 +
TMDS Data 1 TMDS Data 1 return
TMDS Clock +
TMDS Clock USB data +
USB data 1394 outer shield (optional) & Charge Power return
1394 Vg
1394 Vp
21
22
23
24
25
26
27
28
29
30
TMDS Data 0 +
TMDS Data 0 TMDS Data 0 return
Unused
DDC return
DDC data (SDA)
DDC clock (SCL)
+5 VDC
1394 pair B, clock +
1394 pair B, clock -
Description
L
Left Signal
R
Right Signal
GROUND Ground
Contributor: Joakim gren, Uwe Hartmann
Source:
?
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
Description
L
Left Signal
R
Right Signal
GROUND Ground
Contributor: Joakim gren
Source:
?
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
DIN Audio
(at the peripheral)
Connected
Pickup, tuner
Taperecorder
Amplifier
Taperecorder
Amplifier
Amplifier
Receiver
Microphone
In L In R Out L
3
5
3
5
1
3
1
3
1
4
3
1
4
3
1
4
Out R Ground
2
4
2
5
2
4
2
5
2
5
2
5
2
2
S-Video
(at the peripheral)
4 PIN MINI-DIN FEMALE at the peripheral.
Pin
1
2
3
4
Name
GND
GND
Y
C
Description
Ground (Y)
Ground (C)
Intensity (Luminance)
Color (Chrominance)
SCART
Name
AOR
AIR
AOL
AGND
B GND
AIL
B
Description
Audio Out Right
Audio In Right
Audio Out Left + Mono
Audio Ground
RGB Blue Ground
Audio In Left + Mono
RGB Blue In
SWTCH
G GND
Signal Level
0.5 V rms
0.5 V rms
0.5 V rms
Impedance
<1k ohm
>10k ohm
<1k ohm
0.5 V rms
0.7 V
0-2 V=TV, 5-8 V=WideScreen,
9.5-12 V=AV Mode
>10k ohm
75 ohm
0.7 V
75 ohm
75 ohm
75 ohm
1V
75 ohm
>10 kohm
20 VIN
21 SHIELD
75 ohm
Name
GND
tvsnd
V-5
G
R
B
csync
V-30
Description
Ground
Sound Output
+5v Input
Green Out
Red Video
Blue
Composite Sync
???
Wire Colour
brown
blue
yellow
orange
black
red
grey
white
There seems to be no clear standard for VHS Video Cameras. Column "Name" is the most common
function. Three alternative functions that could apply for some cameras is presented in columns named
"Alt Name X".
Pin
1
2
3
4
5
6
7
8
9
10
Name
video out
video gnd
pause
audio out
audio out left
audio gnd
power gnd
+12V power
Name
RED
GREEN
BLUE
SYNC
GND
LUM
Name Dir
Description
NSYNC
Sync?
GREEN
Green
LUM
Lumninace
RED
Red
BLUE
Blue
AOL
Audio Output Left
AOR
Audio Output Right
GND
Ground
Description
Left Channel
Right Channel
Ground
Description
Red
Green
Blue
Monochrome / Overlay
Ground
Red Ground
Green Ground
Blue Ground
Audio Out
Ground
Ground
Composite Sync
Horizontal Sync
Vertikal Sync
External Clock Input
External Sync Enable
+12V for Scart
Videomode 1
Videomode 2
Settings:
M0
0
0
1
1
M1
0
1
0
1
Monitor
mono
VGA
RGB
TV via CINCH
Source:
?
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2000-07-11
Name
AO
CVIDEO
CS
MD
AI
G
R
+12V
HSYNC
B
MVIDEO
VSYNC
GND
Description
Audio Out
Composite Video
Clock Select
Monochrome Detect / Clock In
Audio In
Green
Red
+12 VDC (520ST has GND)
Horizontal Sync
Blue
Monochrome Video
Vertical Sync
Ground
C128 RGBI
Name Dir
Description
GND
Ground
GND
Ground
R
Red
G
Green
B
Blue
I
Intensity
VIDEO
Composite Video
HSYNC
Horizontal Sync
VSYNC
Vertical Sync
C128/C64C Video
Seems to be available on the C128 and the C64C (white color). Compatible with cables for the 5 pin
D-SUB on C64's.
Name Dir
Description
LUM
Luminance (monochrome video)
GND
Ground
AOUT
Audio out
VOUT
Composite Video out
AIN
Audio in (into the SID chip)
n/c
Not connected
n/c
Not connected
C
Chroma
C16/C116/+4 Audio/Video
Available on Commodore C16/C116/+4 computers.
Name Dir
Description
LUM
Luminance (monochrome video)
GND
Ground
AOUT
Audio out
VOUT
Composite Video out
AIN
Audio in (into the SID chip)
COLOR Color ?
n/c
Not connected
+5VDC
+5 VDC
C64 Audio/Video
(at the computer)
C65 Video
Available on the Commodore C65 computer.
Name Dir
Description
GND
Ground
?
?
R
Red
G
Green
B
Blue
?
?
CSYNC
Composite Sync
HSYNC
Horizontal Sync
VSYNC
Vertical Sync
14
--13
16
--15
18
--17
20
--19
22
--21
24
--24
26
--25
28
--27
30
--29
Name
GND
GND
XCLK
R
/XCLKEN
BR
GND
G
GMS0
BG
GMS1
B
/PIXELSW
BB
VSYNC
CSYNC
HSYNC
BCSYNC
GND
AUDR
DGND
AUDL
Description
Video Ground
Video Ground
External Genlock Clock (in)
Red (in to video card)
Enables External Clock on XCLK.
Buffered Red (out from video card)
Video Ground
Green (in to video card)
Genlock mode 0 (from computer, genlock button)
Buffered Green (out from video card)
Genlock mode 1 (from computer, genlock button)
Blue (in to video card)
Genlock signal
Buffered Blue (out from video card)
Vertical Sync (in to video card)
Horizontal Sync (in to video card)
Composite Sync (in to video card)
Buffered Composite Sync (out from video card)
Video Ground
Audio Right Output (from computer to RF modulator)
Digital Ground
Audio Left Output (from computer to RF modulator)
23
24
25
26
27
28
29
30
-12V
DGND
+12V
/CD/TV
VCC
/CCK
GND
VCC
CM-8/CoCo RGB
Available on the Tandy/Radio Shack Color Computer (CoCo).
+-----------+
| 1 3 5 7 9 |
| 2 4
8 10|
+-----------+
Name
GND
GND
R
G
B
KEY
AUDIO
HSYNC
VSYNC
n/c
Description
Ground
Ground
Red
Green
Blue
No Pin
Audio
Horizontal Sync
Vertical Sync
No Connection
Name
+5v
GND
AUDIO
VIDEO
RF VID
Description
Power
System ground
Audio out
Composite Video out
RF Video out
Name Dir
Description
CVBS
Composite Video (PAL, 75 ohms, 1.2V p-p)
GND
Ground
BOUT
Bright Output
CSYNC
Composite Sync
VSYNC
Vertical Sync
G
Green
R
Red
B
Blue
3b1/7300 Video
(at the computer)
12 PIN IDC MALE at the computer.
Pin
1
2
3
4
5
6
7
8
9
10
11
12
Name
VSYNC
GND
HSYNC
GND
VIDEO
GND
+12V
GND
+12V
SPK
SPK
?
Description
Vertical Sync
Ground
Horizontal Sync
Ground
Video
Ground
+12 VDC
Ground
+12 VDC
Speaker
Speaker
?
Name
N.C.
GND
AUDIO LEFT
COMP VIDEO
GND
N.C.
+12V
AUDIO RIGHT
Amiga Video
Name
Dir
Description
/XCLK
Extern Clock
/XCLKEN
Extern Clock Enable (47 Ohm)
RED
Analog Red (75 Ohm)
GREEN
Analog Green (75 Ohm)
BLUE
Analog Blue (75 Ohm)
DI
Digital Intensity (47 Ohm)
DR
Digital Red (47 Ohm)
DG
Digital Green (47 Ohm)
DB
Digital Blue (47 Ohm)
/CSYNC
Composite Sync (47 Ohm)
/HSYNC
Horizontal Sync (47 Ohm)
/VSYNC
Vertical Sync (47 Ohm)
GNDRTN
Digital Ground (for /XCLKEN) Don't connect with pin 16-20.
/PIXELSW
Genlock overlay (47 Ohm)
/C1
Clock out (47 Ohm)
GND
Video Ground
GND
Video Ground
GND
Video Ground
GND
Video Ground
GND
Video Ground
-12V
-12 Volts DC (10 mA max) (A500/A600/A1200)
-5V
-5 Volts DC (10 mA max) (A1000/A2000/A3000/A4000)
22 +12V
+12 Volts DC (100 mA max)
23 +5V
+5 Volts DC (100 mA max)
Note: Direction is Computer relative Monitor.
Name
Description
Video text signal from TMG; set to inverse of GR, except in double high-resolution
1 TEXT
mode.
2 14M
14M master timing signal from the system oscillator.
3 SYNC*
Displays horizontal and vertical synchronization signal from IOU pin 39.
Displays vertical counter bit from IOU pin 4; in text mode, indicates second low-order
4 SEGB
vertical counter; in graphics mode, indicates low-resolution.
5 1VSOUND One-volt sound signal from pin 5 of the audio hybrid circuit (AUD).
6 LDPS*
Video shift-register load enable from pin 12 of TMG.
7 WNDW* Active area display blanking; includes both horizontal and vertical blanking.
8 +12V
Regulated +12 volts DC; can drive 300mA.
9 PRAS*
RAM row-address strobe from TMG pin 19.
10 GR
Graphics mode enable from IOU pin 2.
11 SEROUT* Serialized character generator output from pin 1 of the 74LS166 shift register.
12 NTSC
Composite NTSC video signal from VID hybrid chip.
13 GND
Ground reference and supply.
14 VIDD7
From 74LS374 video latch; causes half-dot shift high.
15 CREF
Color reference signal from TMG pin 3; 3.58 MHz.
Note:
The signals at the DB-15 on the Apple IIc are not the same as those at the DB-15 end of the Apple III,
Apple IIGS, and Macintosh II. Do not attempt to plug a cable intended for one into the other.
Note:
Several of these signals, such as the 14 MHz, must be buffered within about 4 inches of the back panel
connector--preferably inside a container directly connected to the back panel.
Contributor: Joakim gren
Source:
Apple Tech Info Library 1419: Apple IIc, External Pinouts at Apple TIL homepage
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2000-07-08
Name
RED.GND
RED.VID
/CSYNC
SENSE0
GRN.VID
GRN.GND
SENSE1
n/c
BLU.VID
SENSE2
C&VSYNC.GND
/VSYNC
BLU.GND
HSYNC.GND
/HSYNC
CHASSIS.GND
Description
Red ground
Red video signal
Composite synchronization signal
Monitor sense signal 0
Green video signal (with sync)
Green ground
Monitor sense signal 1
Not connected
Blue video signal
Monitor sense signal 2
Ground for CSYNC & VSYNC
Vertical synchronization signal
Blue ground
HSYNC ground
Horizontal synchronization signal
Chassis ground
Name
RED.GND
RED.VID
/CSYNC
SENSE0
GRN.VID
GRN.GND
SENSE1
n/c
BLU.VID
SENSE2
C&VSYNC.GND
/VSYNC
BLU.GND
HSYNC.GND
/HSYNC
CHASSIS.GND
Description
Red ground
Red video signal
Composite synchronization signal
Monitor sense signal 0
Green video signal
Green ground
Monitor sense signal 1 (grounded internally)
Not connected
Blue video signal
Monitor sense signal 2
Ground for CSYNC & VSYNC
Vertical synchronization signal
Blue ground
HSYNC ground
Horizontal synchronization signal
Chassis ground
Description
Analog GND
Analog GND
Video Y (Luminance)
Video C (Chroma)
I2C Clock
+12 VDC (max 250mA)
I2C Data
Description
Analog GND
Analog GND
Video Y (Luminance)
Video C (Chroma)
Composite Video
Unused
Unused
Name
VID.GND
RED
GREEN
VID.GND
VID.GND
BLUE
CSYNC
VSYNC
MLB.SYNC.EN.L
HSYNC
DAC.ISET.1
DAC.ISET.2
SND.GND
SND.RIGHT
SND.LEFT
+5V
GND
SDAT
SCLK
+12V
-12V
Dot
Description
Video ground
Red signal
Green signal
Video ground
Video ground
Blue signal
C sync
Vertical sync
Not used (reserved)
Horizontal sync
Not used(reserved)
Not used (reserved)
Not used (reserved)
Not used (reserved)
Not used (reserved)
+5 volts
Ground
Not used (reserved)
Not used (reserved)
+12 volts
-12 volts
Clock Scaled dot clock (scaled to 10 percent)
AT&T 53D410
Name
Description
?
VSYNC
HSYNC
?
VIDEO
?
?
?
?
?
?
?
GND
GND
GND
?
?
?
?
?
?
?
?
?
?
?
Vertical Sync
Horizontal Sync
?
Video
?
?
?
?
?
?
?
Ground
Ground
Ground
?
?
?
?
?
?
?
?
?
?
Name
TEXT
R
G
B
I
GND
HSYNC/CSYNC
VSYNC
Description
Special TEXT signal (??)
Red
Green
Blue
Intensity
Signal Ground
Horizontal or Composite Sync
Vertical Sync
AT&T PC6300
Name
HSYNC
ID0
VSYNC
R
G
B
n/c
n/c
ID1
MODE0
n/c
/DEGAUSS
GND
GND
GND
GND
GND
GND
GND
GND
n/c
n/c
+15V
+15V
Description
Horizontal Sync
Monitor ID 0
Vertical Sync
Red
Green
Blue
Not connected
Not connected
Monitor ID 1
Mode 0
Not connected
Degauss
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Not connected
Not connected
+15 VDC
+15 VDC
CGA
CGA=Color Graphics Adapter.
Videotype: TTL, 16 colors.
Also known as IBM RGBI.
Name
GND
GND
R
G
B
I
RES
HSYNC
VSYNC
Description
Ground
Ground
Red
Green
Blue
Intensity
Reserved
Horizontal Sync
Vertical Sync
Name
G
HSYNC
GND
R
B
VSYNC
Description
Green
Horizontal Sync
Ground
Red
Blue
Vertical Sync
Name
n/c
R
G
B
I
GND
HSYNC
VSYNC
Description
Not connected
Red
Green
Blue
Intensity
Ground
Horizontal Sync
Vertical Sync
Name
GND
GND
R
G
B
I
CSYNC
HSYNC
VSYNC
Analog Mode
Ground
Ground
Red
Green
Blue
n/c
Composite Sync
n/c
n/c
Digital Mode
Ground
Ground
Red
Green
Blue
Intensity
n/c
Horizontal Sync
Vertical Sync
ECL
Name
ECL
ECLGND
HSYNC
VSYNC
+5V
ECLGND
ECLGND
SYNCGND
+5GND
Description
ECL?
ECL Video Ground
Horizontal Sync
Vertical Sync
+5 VDC
ECL Video Ground
ECL Video Ground
Sync Ground
Ground (for +5V)
EGA
EGA=Enhanced Graphics Adapter.
Videotype: TTL, 16/64 colors.
Name
GND
SR
PR
PG
PB
SG/I
SB
H
V
Description
Ground
Secondary Red
Primary Red
Primary Green
Primary Blue
Secondary Green / Intensity
Secondary Blue
Horizontal Sync
Vertical Sync
Description
TV vertical drive (not for display)
Ground
TV horizontal drive (not for display)
Blue (CGA pin 5)
Red (CGA pin3)
Intensity (CGA pin 6)
Green (CGA pin 4)
Comp Sync Drive (not for display)
Audio
+ Vertical drive (CGA pin 9)
Ground
+ Horizontal drive (CGA pin 8)
Ground
Ground
Ground
Ground
Ground
Frame ground (CGA pin 1)
Description
ID Bit 2
ID Bit 3
Self test
Digital Ground
Horizontal Sync
ID Bit 0
ID Bit 1
n/c
Vertical Sync
Digital Ground
Macintosh Video
Name
Dir
Description
RGND
Red Ground
R
Red
CSYNC
Composite sync
SENSE0
Monitor Sense 0
G
Green
GGND
Green Ground
SENSE1
Monitor Sense 1
n/c
No connection
B
Blue
SENSE2
Monitor sense 2
SGND
Sync Ground
VSYNC
Vertical Sync
BGND
Blue Ground
HSYNCGND
Horizontal Sync Ground
HSYNC
Horizontal Sync
MDA (Hercules)
Name
GND
GND
n/c
n/c
n/c
I
M
H
V
Description
Ground
Ground
Intensity
Mono Video
Horizontal Sync
Vertical Sync
Name
GND
I
VID
HSYNC
VSYNC
Description
Ground
Intensity
Video
Horizontal Sync TTL Positive
Vertical Sync TTL Negative
Description
+12 VDC
Power Switch Control
Monitor Clock
Monitor Out
Monitor In
-12 VDC
Monitor Type 2
Ground
Ground
Ground
PGA
Videotype: Analogue.
Name
R
G
B
CSYNC
MODE
RGND
GGND
BGND
GND
Description
Red
Green
Blue
Composite Sync
Mode Control
Red Ground
Green Ground
Blue Ground
Ground
SGI Video
Normal Monitor
Pin
1
2
3
4
5
6
7
8
9
10
Description
Monitor ID Bit 3, TTL
Monitor ID Bit 0, TTL
Composite Sync (Active Low), TTL
Horizontal Drive (Active High), TTL
Vertical Drive (Active High), TTL
Monitor ID Bit 1, TTL
Monitor ID Bit 2, TTL
Digital Ground
Digital Ground
Sync Ground
DDC Monitor
Pin
1
2
3
4
5
6
7
8
9
Description
Data Clock (SCL)
Bi-directional Data (SDA)
Composite Sync
Horizontal Sync
Vertical Sync
DDC (+5VInput)
DDC Ground
Chassis Ground
Chassis Ground
10
R
G
B
Chassis Ground
Red
Green
Blue
Sun Video
Name
HSYNCGND
VSYNC
SENSE2
SENSEGND
CSYNC
HSYNC
VSYNCGND
SENSE1
SENSE0
CGND
RED
GREEN/GRAY
BLUE
Description
Horizontal Sync Ground*
Vertical Sync*
Sense #2
Sense Ground
Composite Sync
Horizontal Sync*
Vertical Sync Ground*
Sense #1
Sense #0
Composite Ground
Red
Green/Gray
Blue
Bit 2
0
0
0
0
1
1
1
1
Bit 1
0
0
1
1
0
0
1
1
Bit 0
0
1
0
1
0
1
0
1
Resolution
?
Reserved
1280 x 1024 76Hz
1152 x 900 66Hz
1152 x 900 76Hz 19"
Reserved
1152 x 900 76Hz 16-17"
No monitor connected
VESA Feature
(at the videocard)
26 PIN IDC at the Video card.
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Name
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
CLK
BLK
HSYNC
VSYNC
GND
GND
GND
GND
n/c
GND
GND
GND
GND
n/c
n/c
Description
DAC Pixel Data Bit 0 (PB)
DAC Pixel Data Bit 1 (PG)
DAC Pixel Data Bit 2 (PR)
DAC Pixel Data Bit 3 (PI)
DAC Pixel Data Bit 4 (SB)
DAC Pixel Data Bit 5 (SG)
DAC Pixel Data Bit 6 (SR)
DAC Pixel Data Bit 7 (SI)
DAC Clock
DAC Blanking
Horizontal Sync
Vertical Sync
Ground
Ground
Ground
Ground
Select Internal Video
Select Internal Sync
Select Internal Dot Clock
Not used
Ground
Ground
Ground
Ground
Not used
Not used
VGA (15)
VGA=Video Graphics Adapter or Video Graphics Array.
Videotype: Analogue.
Name
RED
GREEN
BLUE
ID2
GND
RGND
GGND
BGND
KEY
SGND
ID0
ID1 or SDA
HSYNC or CSYNC
VSYNC
ID3 or SCL
Dir
Description
Red Video (75 ohm, 0.7 V p-p)
Green Video (75 ohm, 0.7 V p-p)
Blue Video (75 ohm, 0.7 V p-p)
Monitor ID Bit 2
Ground
Red Ground
Green Ground
Blue Ground
Key (No pin)
Sync Ground
Monitor ID Bit 0
Monitor ID Bit 1
Horizontal Sync (or Composite Sync)
Vertical Sync
Monitor ID Bit 3
?
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
VGA (9)
VGA=Video Graphics Adapter or Video Graphics Array.
Videotype: Analogue.
Name Dir
Description
RED
Red Video
GREEN
Green Video
BLUE
Blue Video
HSYNC
Horizontal Sync
VSYNC
Vertical Sync
RGND
Red Ground
GGND
Green Ground
BGND
Blue Ground
SGND
Sync Ground
Name
RED
GREEN
BLUE
RES
GND
RGND
GGND
BGND
+5V
SGND
ID0
SDA
HSYNC or CSYNC
VSYNC
SCL
Dir
Description
Red Video (75 ohm, 0.7 V p-p)
Green Video (75 ohm, 0.7 V p-p)
Blue Video (75 ohm, 0.7 V p-p)
Reserved
Ground
Red Ground
Green Ground
Blue Ground
+5 VDC
Sync Ground
Monitor ID Bit 0 (optional)
DDC Serial Data Line
Horizontal Sync (or Composite Sync)
Vertical Sync
DDC Data Clock Line
Vic 20 Video
(at the computer)
Name Dir
Description
+6V
+6 VDC (10 mA max)
GND
Ground
AUDIO
Audio
VLOW
Video Low (Unconnected ?)
VHIGH
Video High
Name
+12 V dc
spare
Reserved* Ground
USBGround
INTA#
RST#
GNT#
VCC 3.3
ST1
Reserved
PIPE#
Ground
Spare
SBA1
VCC 3.3
SBA3
Reserved
Ground
SBA5
SBA7
Key
Key
Key
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
Key
AD30
AD28
VCC 3.3
AD26
AD24
Ground
Reserved
C/BE3#
Vddq 3.3
AD22
AD20
Ground
AD18
AD16
Vddq 3.3
FRAME#
Spare
Ground
Spare
VCC 3.3
TRDY#
STOP#
Spare
Ground
PAR
AD15
Vddq 3.3
AD13
AD11
Ground
AD9
C/BE0#
Vddq 3.3
Reserved
AD6
Ground
AD4
A63
A64
A65
A66
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
AD2
Vddq 3.3
AD0
SMB1
spare
+5 V dc
+5 V dc
USB+
Ground
INTB#
CLK
REQ#
VCC 3.3
ST0
ST2
RBF#
Ground
Spare
SBA0
VCC 3.3
SBA2
SB_STB
Ground
SBA4
SBA6
Key
Key
Key
Key
AD31
AD29
VCC 3.3
AD27
AD25
Ground
AD STB1
AD23
Vddq 3.3
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
AD21
AD19
Ground
AD17
C/BE2#
Vddq 3.3
IRDY#
Spare
Ground
Spare
VCC 3.3
DEVSEL#
Vddq 3.3
PERR#
Ground
SERR#
C/BE1#
Vddq 3.3
AD14
AD12
Ground
AD10
AD8
Vddq 3.3
AD STB0
AD7
Ground
AD5
AD3
Vddq 3.3
AD1
SMB0
Name
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
GND
+5V
A23
A22
A21
A20
A19
A18
A17
A16
GND
+5V
A15
A14
A13
A12
A11
A10
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Ground
+5 Volts DC
Address 23
Address 22
Address 21
Address 20
Address 19
Address 18
Address 17
Address 16
Ground
+5 Volts DC
Address 15
Address 14
Address 13
Address 12
Address 11
Address 10
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
A9
A8
GND
+5V
A7
A6
A5
A4
A3
A2
A1
A0
GND
+5V
D31
D30
D29
D28
D27
D26
D25
D24
GND
+5V
D23
D22
D21
D20
D19
D18
D17
D16
GND
+5V
D15
D14
D13
D12
Address 9
Address 8
Ground
+5 Volts DC
Address 7
Address 6
Address 5
Address 4
Address 3
Address 2
Address 1
Address 0
Ground
+5 Volts DC
Data 31
Data 30
Data 29
Data 28
Data 27
Data 26
Data 25
Data 24
Ground
+5 Volts DC
Data 23
Data 22
Data 21
Data 20
Data 19
Data 18
Data 17
Data 16
Ground
+5 Volts DC
Data 15
Data 14
Data 13
Data 12
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
D11
D10
D9
D8
GND
+5V
D7
D6
D5
D4
D3
D2
D1
D0
GND
+5V
/IPL2
/IPL1
/IPL0
n/c
/RST
/HLT
n/c
n/c
SIZE1
SIZE0
/AS
/DS
R/W
/BERR
n/c
/AVEC
/DSACK1
/DSACK2
CPUCKLA
ECLOCK
GND
+5V
Data 11
Data 10
Data 9
Data 8
Ground
+5 Volts DC
Data 7
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
Data 0
Ground
+5 Volts DC
Reserved
Reset
Halt
Reserved
Reserved
Address Strobe
Data Strobe
Read/Write
Bus Error
Reserved
EClock pulse
Ground
+5 Volts DC
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
FC2
FC1
FC0
/RMC
n/c
n/c
n/c
n/c
/BR
/BG
n/c
/BOSS
/FPUCS
/FPUSENSE
CCKA
/RESET
GND
+5V
/NETCS
/SPARECS
/RTCCS
/FLASH
/REG
/CCENA
/WAIT
/KBRESET
/IORD
/IOWR
/OE
/WE
/OVR
XRDY
/ZORRO
/WIDE
/INT2
/INT6
GND
+5V
Processor Status 2
Processor Status 1
Processor Status 0
Reserved
Reserved
Reserved
Reserved
Slot specific Bus Arbitration
Slot specific Bus Arbitration
Reserved
FPU Chip select
FPU Sense
Reset
Ground
+5 Volts DC
Keyboard reset
IO Read
IO Write
Output enable
/DTACK Override
External Ready
Interrupt level 2
Interrupt level 6
Ground
+5 Volts DC
141
142
143
144
145
146
147
148
149
150
SYSTEM1
SYSTEM0
/xRxD
/xTxD
/CONFIG OUT
AGND
ALEFT
ARIGHT
+12V
-12V
System1 Ground
System0 Ground
Audio Ground
Audio Left
Audio Right
+12 Volts DC
-12 Volts DC
Name
RGB16
RGB17
LINELF
LINERT
C28D
+5V
ARED
+5V
GND
+12V
AGREEN
GND
GND
/CSYNC
ABLUE
/XCLKEN
GND
BURST
/C4
GND
GND
/HSYNC
RGB4
GND
RGB7
/VSYNC
Dir
Description
Red Bit 0
Red Bit 1
Audio Line Out Left
Audio Line Out Right
Pixel-Synchronous Clock
+5 Volts DC (1 A)
Analog Red
+5 Volts DC (1 A)
Digital Ground
+12 Volts DC (40 mA)
Analog Green
Digital Ground
Digital Ground
Composite Sync
Analog Blue
Genlock Clock Enable
Digital Ground
Burst Gate
3.55/3.58 MHz Clock
Digital Ground
Digital Ground
Horizontal Sync (47 Ohm)
Blue Bit 4
Digital Ground
Blue Bit 7
Vertical Sync (47 Ohm)
27
28
29
30
31
32
33
34
35
36
RGB15
BLANK
RGB23
/PIXELSW
-5V
GND
/XCLK
/C1
+5V
PSTROBE
Green Bit 7
Video Blank
Red 7
Genlock Overlay (47 Ohm)
-5 Volts DC
Digital Ground
Genlock Clock
C1 Clock
+5 Volts DC (1 A)
Printer Port Handshake
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
GND
RGB20
RGB21
RGB22
GND
RGB12
RGB13
RGB14
GND
RGB5
RGB6
GND
SOG
TBASE
CDAC
PPOUT
/C3
PBUSY
/LPEN
/PACK
PSEL
GND
PPD0
PPD1
PPD2
PPD3
PPD4
Digital Ground
Red Bit 4
Red Bit 5
Red Bit 6
Digital Ground
Green Bit 4
Green Bit 5
Green Bit 6
Digital Ground
Blue Bit 5
Blue Bit 6
Ground
Sync-On-Green Indicator
50/60 Hz Software Clock Timebase
7.09/7.16 MHz Clock
Printer Port Paper Out
3.55/3.58 MHz Clock
Printer Port Busy
Light Pen Input
Printer Port Acknowledge Handshake
Printer Port Select
Digital Ground
Printer Port Data Bit 0
Printer Port Data Bit 1
Printer Port Data Bit 2
Printer Port Data Bit 3
Printer Port Data Bit 4
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
PPD5
PPD6
PPD7
/LED
GND
RAWLF
AGND
RAWRT
AGND
n/c
n/c
GND
GND
n/c
n/c
GND
GND
RGB18
RGB19
RGB8
RGB9
RGB10
RGB11
RGB0
RGB1
RGB2
RGB3
Name
PR +24V EXT
PR +24V EXT
/PLUG IN
GND
/ON/OFF OUT
/STERM
/DS
/AS
+5V MAIN OUT
/HALT
/BERR
/BGACK
GND
GND
ADDR[0]
ADDR[2]
ADDR[4]
ADDR[6]
ADDR[8]
ADDR[10]
ADDR[12]
ADDR[14]
+5V MAIN OUT
GND
ADDR[18]
ADDR[20]
ADDR[22]
ADDR[24]
Description
Raw +24 V from AC adapter
Raw +24 V from AC adapter
Power surge control (grounded in the expansion device)
Logic ground
On/off button
Synchronous termination
Data strobe
Address strobe
+5 V regulated power
Halt
Bus error
Bus grant acknowledge
Logic ground
Logic ground
Address bit 0
Address bit 2
Address bit 4
Address bit 6
Address bit 8
Address bit 10
Address bit 12
Address bit 14
+5 V regulated power
Logic ground
Address bit 18
Address bit 20
Address bit 22
Address bit 24
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
56
57
58
59
61
62
63
65
66
67
68
69
70
72
73
74
75
76
ADDR[26]
ADDR[28]
ADDR[30]
GND
GND
IOCLK
SIZ[1]
+5V MAIN OUT
DATA[0]
DATA[1]
DATA[2]
DATA[3]
DATA[4]
DATA[5]
DATA[6]
DATA[7]
GND
DATA[17]
DATA[18]
DATA[19]
DATA[20]
DATA[21]
DATA[22]
DATA[23]
GND
/SCC IRQ
SERVEE
GND
GND
+8V SOUND
+5V MODEM
LINET/R
+5V SOUND
SND OUT L
EXT MIC FILT R
EXT MIC FILT L
DAA GND
DAA GND
Address bit 26
Address bit 28
Address bit 30
Logic ground
Logic ground
15.6672 MHz I/O clock
Transfer size bit 1
+5 V regulated power
Data bit 0
Data bit 1
Data bit 2
Data bit 3
Data bit 4
Data bit 5
Data bit 6
Data bit 7
Logic ground
Data bit 17
Data bit 18
Data bit 19
Data bit 20
Data bit 21
Data bit 22
Data bit 23
Logic ground
SCC interrupt request
-5 V for SCC transceivers
Logic ground
Logic ground
Special "clean" +8 V power for sound output
+5 V power for modem
Modem DAA line talk/receive
+5 V power for sound output
Sound output left channel
Right input signal from external microphone
Left input signal from external microphone
Modem ground
Modem ground
77
78
79
80
81
83
84
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
PR +24V EXT
PR +24V EXT
PR +24V EXT
GND
GND
ADB DATA
/ADBPWRON
/CBREQ
/DSACK1
/DSACK0
/BR
/BG
/SLEEP
FC[1]
FC[0]
/RMC
CPUCLK
/CPURESET
ADDR[1]
ADDR[3]
ADDR[5]
ADDR[7]
ADDR[9]
ADDR[11]
ADDR[13]
ADDR[15]
ADDR[16]
ADDR[17]
ADDR[19]
ADDR[21]
ADDR[23]
ADDR[25]
ADDR[27]
ADDR[29]
ADDR[31]
/SLOT IN
GND
RD
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
137
138
139
140
141
142
143
144
145
146
147
148
151
152
SIZ[0]
DATA[8]
DATA[9]
DATA[10]
DATA[11]
+5VEXTSENSE
DATA[12]
DATA[13]
DATA[14]
DATA[15]
DATA[16]
DATA[24]
DATA[25]
DATA[26]
DATA[27]
DATA[28]
DATA[29]
DATA[30]
DATA[31]
/SWIM CS
/SLOT E IRQ
/PFW
/IO RESET
GND
GND
DAA CNTLF
DAA ID IN
/RING DET
/RB DVR
/RA DVR
EXT MIC SEL
DAA GND
DAA GND
panel, giving the Duo Dock direct access to the microprocessor's 32-bit address bus, 32-bit data bus, and
control signals. It also provides access to power, control, and status signals in other parts of the
computer, and allows the Duo Dock to provide power to the PowerBook Duo.
Contributor: Joakim gren
Source:
Apple Tech Info Library 12929: Duo Dock/Duo Dock II, External Pinouts at Apple TIL homepage
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
Name
GND
+5V
+5V
+5V
/DELAY.CS
/VMA
/BG
/LDS
GND
A2
A5
A8
A11
A14
A17
reserved
n/c
reserved
reserved
D1
D4
D7
D10
D13
+5/3.7V
A19
A22
FC0
a29
a30
a31
a32
b1
b2
b3
b4
b5
b6
b7
b8
b9
b10
b11
b12
b13
b14
b15
b16
b17
b18
b19
b20
b21
b22
b23
b24
b25
b26
b27
b28
b29
b30
b31
b32
c1
c2
/IPL0
/BERR
GND
GND
GND
+5V
+5V
+5V
/SYS.PWR
/BR
/DTACK
/UDS
+5/0V
A3
A6
A9
A12
A15
A18
reserved
reserved
reserved
+12V
D2
D5
D8
D11
D14
+5V
A20
A23
FC1
/IPL1
/EXT.DTACK
16M
GND
GND
+5V
c3
c4
c5
c6
c7
c8
c9
c10
c11
c12
c13
c14
c15
c16
c17
c18
c19
c20
c21
c22
c23
c24
c25
c26
c27
c28
c29
c30
c31
c32
+5V
+5V
/VPA
/BGACK
R/W
/AS
A1
A4
A7
A10
A13
A16
reserved
n/c
reserved
reserved
D0
D3
D6
D9
D12
D15
GND
A21
E
FC2
/IPL2
/SYS.RST
GND
GND
D0-D15
Unbuffered data bus, bits 0 through 15
A1-A23
Unbuffered address bus, bits 1 through 23
16M
16 MHz clock
/EXT.DTACK
External data transfer acknowledge. This signal is an input to the processor logic glue. Assertion delays
external generation of the /DTACK signal.
E
E(enable) clock
/BERR
Bus error signal generated whenever /AS remains low for more than about 250 us.
/IPL0-/IPL2
Input priority level lines 0 through 2.
/SYS.RST
Initiates a system reset.
/SYS.PWR
A signal from the Power Manager indicated that associated circuits should tri-state their outputs and go
inte idle state; /SYS.PWR is pulled high (deasserted) during sleep state.
/AS
Address strobe
/UDS
Upper data strobe
/LDS
Lower data strobe
R/W
Defines bus transfer as read or write signal
/DTACK
Data transfer acknowledge
/DELAY.CS
Indicates that a wait state is inserted into the current memory cycle and that you can delay a CS.
/BG
Bus grant
/BGACK
Bus grant acknowledge
/BR
Bus request
/VMA
Valid memory access
/VPA
Valid peripheral address
FC0-FC2
Function code lines 0 through 2
+5/0V
Provides +5V when the system is running normally and 0V when the system is in sleep mode.
+5/3.7V
Provides +5V when the system is running normally and 3.7V when the system is in sleep mode.
Contributor: Joakim gren
Source:
Technote HW12: Macintosh Portable PDS Development at Apple Technical Notes
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2000-07-07
Name
Description
res
Reserved
res
Reserved
/BUSLOCK Bus Clock
/IRQ3
Interrupt Request 3
/IPL2*
68030 IPL2
/CIOUT*
68030 Cache inhibit out
/STERM*
Sync.cycle termination
/DSACK1* 68030 Data ack 1
SIZ1
transfer size bit 1
/BGACK* 68030 bus grant ack
FC2
68030 function code 2
/RESET*
System reset
D0
Data bit 0
D2
Data bit 2
D5
Data bit 5
D8
Data bit 8
D10
Data bit 10
D13
Data bit 13
D16
Data bit 16
D18
Data bit 18
D21
Data bit 21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
D24
D26
D29
A31
A29
A26
A23
A21
A18
A15
A13
A10
A7
A5
A2
+5V
CPUCLOCK
GND
-12V
res
GND
/TM1A
/IRQ2
/IPL1*
/DS*
/CBACK*
/DSACK0*
SIZ0
/BG*
FC1
/BERR*
+5V
D3
D6
GND
D11
D14
+5V
Data bit 24
Data bit 26
Data bit 29
address bit 31
address bit 29
address bit 26
address bit 23
address bit 21
address bit 18
address bit 15
address bit 13
address bit 10
address bit 7
address bit 5
address bit 2
+5 VDC
CPU Clock
Ground
-12 VDC
Reserved
Ground
?
Interrupt Request 2
68030 IPL1
68030 Data Strobe
cache burst ack
68030 Data ack 0
Transfer Size bit 0
68030 bus grant
68030 function code 1
Bus error
+5 VDC
Data bit 3
Data bit 6
Ground
Data bit 11
Data bit 14
+5 VDC
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
D19
D22
GND
D27
D30
+5V
A28
A25
GND
A20
A17
+5V
A12
A9
GND
A4
A1
+5V
ECLK
GND
-5V
PWROFF
/NUBUS
/TM0A
/IRQ1
/IPL0*
/RMC*
/CBREQ*
R/W*
/AS*
/BR*
FC0
/HALT*
D1
D4
D7
D9
D12
Data bit 19
Data bit 22
Ground
Data bit 27
Data bit 30
+5 VDC
address bit 28
address bit 25
Ground
address bit 20
address bit 17
+5 VDC
address bit 12
address bit 9
Ground
address bit 4
address bit 1
+5 VDC
?
Ground
-5 VDC
Power Off?
?
?
Interrupt Request 1
68030 IPL0
68030 read modify cycle
68030 cache burst req
68030 read write
68030 address strobe
68030 bus request
68030 function code 0
68030 Halt
Data bit 1
Data bit 4
Data bit 7
Data bit 9
Data bit 12
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
D15
D17
D20
D23
D25
D28
D31
A30
A27
A24
A22
A19
A16
A14
A11
A8
A6
A3
A0
+5V
C16M
GND
+12V
Data bit 15
Data bit 17
Data bit 20
Data bit 23
Data bit 25
Data bit 28
Data bit 31
address bit 30
address bit 27
address bit 24
address bit 22
address bit 19
address bit 16
address bit 14
address bit 11
address bit 8
address bit 6
address bit 3
address bit 0
+5 VDC
16 MHz Clock
Ground
+12 VDC
Below a table with differences found in the Apple Macintosh IIfx computers:
Pin
A1
A2
A3
A4
A38
B1
B2
B3
B4
B38
B39
C1
Name
GND*
/PDS.MASTER
res
n.c.
Reserved
ECS
n.c.
/PDS.BG
/IRQ15
n.c.
/SLOT.E
/PFW
Description
Ground
?
Reserved
Not connected
by Apple
Early cycle start
Not connected
?
?
Not connected
68030 slot E replace in address map
Shutdown bit
C2
C3
C4
C38
n.c.
/PDS.BR
/IRQ6
CPUCLK*
Not connected
Bus request
?
20 MHz clock
C-bus II
Developed by Corolla
C-bus II is the successor to C-bus & Extended C-bus.
Name
GND
AUX18
AUX16
GND
AUX14
AUX12
GND
AUX10
AUX8
GND
AUX6
AUX4
GND
AUX2
AUX0
GND
RESERVED8
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
PA32
PA33
PA34
PA35
PA36
PA37
PA38
PA39
PA40
PA41
PA42
PA43
PA44
PA45
PA46
PA47
PA48
PA49
PA50
PA51
PA52
PA53
PA54
PA55
RESERVED6
RESERVED4
RESERVED2
RESERVED0
GND
GND
AGND
CID1
CBCLK
GND
CRST#
LED#
GND
CARB2
CARB0
GND
TM2#
TM0#
GND
STRT#
CD31
GND
CD30
CD29
GND
CD28
CD27
GND
CD26
CD25
GND
CD24
CD23
GND
CD22
CD21
GND
CD20
PA56
PA57
PA58
PA59
PA60
PA61
PA62
PA63
PA64
PA65
PA66
PA67
PA68
PA69
PA70
PA71
PA72
PA73
PA74
PA75
PA76
PA77
PA78
PA79
PA80
PA81
PA82
PA83
PA84
PA85
PA86
PA87
PA88
PA89
PA90
PA91
CD19
GND
CD18
CD17
GND
CD16
E3
GND
E2
CD15
GND
CD14
CD13
GND
CD12
CD11
GND
CD10
CD9
GND
CD8
CD7
GND
CD6
CD5
GND
CD4
CD3
GND
CD2
CD1
GND
CD0
E1
GND
E0
PB1 +5V
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
PB28
PB29
PB30
PB31
PB32
PB33
PB34
PB35
PB36
PB37
PB38
PB39
AUX19
AUX17
+5V
AUX15
AUX13
+5V
AUX11
AUX9
+5V
AUX7
AUX5
+5V
AUX3
AUX1
+5V
RESERVED9
RESERVED7
RESERVED5
RESERVED3
RESERVED1
VTERM
+5V
CID3
CID2
CID0
+5V
FAULT#
LOCKCB#
+5V
CARB3
CARB1
+5V
TM3#
TM1#
+5V
ACK#
CD63
+5V
PB40
PB41
PB42
PB43
PB44
PB45
PB46
PB47
PB48
PB49
PB50
PB51
PB52
PB53
PB54
PB55
PB56
PB57
PB58
PB59
PB60
PB61
PB62
PB63
PB64
PB65
PB66
PB67
PB68
PB69
PB70
PB71
PB72
PB73
PB74
PB75
PB76
PB77
CD62
CD61
+5V
CD60
CD59
+5V
CD58
CD57
+5V
CD56
CD55
+3.3V
CD54
CD53
+3.3V
CD52
CD51
+3.3V
CD50
CD49
+3.3V
CD48
E7
+3.3V
E6
CD47
+3.3V
CD46
CD45
+3.3V
CD44
CD43
+3.3V
CD42
CD41
+3.3V
CD40
CD39
PB78
PB79
PB80
PB81
PB82
PB83
PB84
PB85
PB86
PB87
PB88
PB89
PB90
PB91
+3.3V
CD38
CD37
+3.3V
CD36
CD35
+3.3V
CD34
CD33
+3.3V
CD32
E5
+3.3V
E4
CardBus
32-bit bus defined by PCMCIA.
Name
GND
CAD0
CAD1
CAD3
CAD5
CAD7
CCBE0#
CAD9
CAD11
CAD12
CAD14
CCBE1#
CPAR
CPERR#
CGNT#
CINT#
Vcc
Vpp1
CCLK
CIRDY#
Description
Ground
Address/Data 0
Address/Data 1
Address/Data 3
Address/Data 5
Address/Data 7
Command/Byte Enable 0
Address/Data 9
Address/Data 11
Address/Data 12
Address/Data 14
Command/Byte Enable 1
Parity
Parity error
Grant
Interrupt
Vcc
Vpp1
CCLK
Initiator Ready
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
CCBE2#
CAD18
CAD20
CAD21
CAD22
CAD23
CAD24
CAD25
CAD26
CAD27
CAD29
RSRVD
CCLKRUN#
GND
GND
CCD1#
CAD2
CAD4
CAD6
RSRVD
CAD8
CAD10
CVS1
CAD13
CAD15
CAD16
RSRVD
CBLOCK#
CSTOP#
CDEVSEL#
Vcc
Vpp2
CTRDY#
CFRAME#
CAD17
CAD19
CVS2
CRST#
Command/Byte Enable 2
Address/Data 18
Address/Data 20
Address/Data 21
Address/Data 22
Address/Data 23
Address/Data 24
Address/Data 25
Address/Data 26
Address/Data 27
Address/Data 29
Reserved
CCLKRUN#
Ground
Ground
Card Detect 1
Address/Data 2
Address/Data 4
Address/Data 6
Reserved
Address/Data 8
Address/Data 10
Address/Data 13
Address/Data 15
Address/Data 16
Reserved
Block ???
Stop transfer cycle
Device Select
Vcc
Vpp2
Target Ready
Address or Data phase
Address/Data 17
CAD19
Reset
59
60
61
62
63
64
65
66
67
68
CSERR#
CREQ#
CCBE3#
CAUDIO
CSTSCHG
CAD28
CAD30
CAD31
CCD2#
GND
System Error
Request ???
Command/Byte Enable 3
Audio ???
Address/Data 28
Address/Data 30
Address/Data 31
Card Detect 2
Ground
CompactPCI
PCI=Peripheral Component Interconnect.
CompactPCI is a version of PCI adapted for industrial and/or embedded applications.
Name
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
KEY
KEY
KEY
GND
GND
GND
GND
GND
Description
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Keyed (no pin)
Keyed (no pin)
Keyed (no pin)
Ground
Ground
Ground
Ground
Ground
Z20
Z21
Z22
Z23
Z24
Z25
Z26
Z27
Z28
Z29
Z30
Z31
Z32
Z33
Z34
Z35
Z36
Z37
Z38
Z39
Z40
Z41
Z42
Z43
Z44
Z45
Z46
Z47
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
A1
A2
A3
A4
A5
A6
A7
A8
A9
5V
TCK
INTA#
BRSV
BRSV
REQ#
AD(30)
AD(26)
C/BE(3)#
+5 VDC
Test Clock
Interrupt A
Bused Reserved (don't use)
Bused Reserved (don't use)
Request PCI transfer
Address/Data 30
Address/Data 26
Command: Byte Enable
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
AD(21)
AD(18)
KEY
KEY
KEY
3.3V
DEVSEL#
3.3V
SERR#
3.3V
AD(12)
3.3V
AD(7)
3.3V
AD(1)
5V
CLK1
CLK2
CLK4
V(I/O)
C/BE(5)#
AD(63)
AD(59)
AD(56)
AD(52)
AD(49)
AD(45)
AD(42)
AD(38)
AD(35)
BRSV
BRSV
BRSV
USR
USR
USR
USR
USR
Address/Data 21
Address/Data 18
Keyed (no pin)
Keyed (no pin)
Keyed (no pin)
+3.3 VDC
Device Select
+3.3 VDC
System Error
+3.3 VDC
Address/Data 12
+3.3 VDC
Address/Data 7)
+3.3 VDC
Address/Data 1)
+5 VDC
Clock ?? MHz
Clock ?? MHz
Clock ?? MHz
+3.3 VDC or +5 VDC
Command: Byte Enable
Address/Data 63
Address/Data 59
Address/Data 56
Address/Data 52
Address/Data 49
Address/Data 45
Address/Data 42
Address/Data 38
Address/Data 35
Bused Reserved (don't use)
Bused Reserved (don't use)
Bused Reserved (don't use)
User Defined
User Defined
User Defined
User Defined
User Defined
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
-12V
5V
INTB#
GND
BRSV
GND
AD(29)
GND
IDSEL
GND
AD(17)
KEY
KEY
KEY
FRAME#
GND
SDONE
GND
AD(15)
GND
AD(9)
GND
AD(4)
5V
REQ64#
GND
CLK3
GND
BRSV
GND
AD(62)
GND
AD(55)
GND
AD(48)
GND
AD(41)
-12 VDC
+5 VDC
Interrupt B
Ground
Bused Reserved (don't use)
Ground
Address/Data 29
Ground
Initialization Device Select
Ground
Address/Data 17
Keyed (no pin)
Keyed (no pin)
Keyed (no pin)
Address or Data phase
Ground
Snoop Done
Ground
Address/Data 15
Ground
Address/Data 9)
Ground
Address/Data 4)
+5 VDC
Ground
Clock ?? MHz
Ground
Bused Reserved (don't use)
Ground
Address/Data 62
Ground
Address/Data 55
Ground
Address/Data 48
Ground
Address/Data 41
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
GND
AD(34)
GND
BRSV
GND
USR
USR
USR
USR
USR
Ground
Address/Data 34
Ground
Bused Reserved (don't use)
Ground
User Defined
User Defined
User Defined
User Defined
User Defined
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
TRST#
TMS
INTC#
V(I/O)
RST
3.3V
AD(28)
V(I/O)
AD(23)
3.3V
AD(16)
KEY
KEY
KEY
IRDY#
V(I/O)
SBO#
3.3V
AD(14)
V(I/O)
AD(8)
3.3V
AD(3)
V(I/O)
BRSV
REQ1#
SYSEN#
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
C41
C42
C43
C44
C45
C46
C47
GNT3#
C/BE(7)
V(I/O)
AD(61)
V(I/O)
AD(54)
V(I/O)
AD(47)
V(I/O)
AD(40)
V(I/O)
AD(33)
FAL#
DEG#
PRST#
USR
USR
USR
USR
USR
Grant
Command: Byte Enable
+3.3 VDC or +5 VDC
Address/Data 61
+3.3 VDC or +5 VDC
Address/Data 54
+3.3 VDC or +5 VDC
Address/Data 47
+3.3 VDC or +5 VDC
Address/Data 40
+3.3 VDC or +5 VDC
Address/Data 33
Power Supply Status FAL (CompactPCI specific)
Power Supply Status DEG (CompactPCI specific)
Push Button Reset (CompactPCI specific)
User Defined
User Defined
User Defined
User Defined
User Defined
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
+12V
TDO
5V
INTP
GND
CLK
GND
AD(25)
GND
AD(20)
GND
KEY
KEY
KEY
GND
STOP#
GND
+12 VDC
Test Data Output
+5 VDC
Ground
Ground
Address/Data 25
Ground
Address/Data 20
Ground
Keyed (no pin)
Keyed (no pin)
Keyed (no pin)
Ground
Stop transfer cycle
Ground
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
PAR
GND
AD(11)
M66EN
AD(6)
5V
AD(0)
3.3V
GNT1#
GNT2#
REQ4#
GND
C/BE(4)#
GND
AD(58)
GND
AD(51)
GND
AD(44)
GND
AD(37)
GND
REQ5#
GND
REQ6#
USR
USR
USR
USR
USR
E1
E2
E3
E4
E5
E6
E7
5V
TDI
INTD#
INTS
GNT#
AD(31)
AD(27)
+5 VDC
Test Data Input
Interrupt D
Address/Data 6)
+5 VDC
Address/Data 0)
+3.3 VDC
Grant
Grant
Request PCI transfer
Ground
Command: Byte Enable
Ground
Address/Data 58
Ground
Address/Data 51
Ground
Address/Data 44
Ground
Address/Data 37
Ground
Request PCI transfer
Ground
Request PCI transfer
User Defined
User Defined
User Defined
User Defined
User Defined
Grant
Address/Data 31
Address/Data 27
E8
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
E27
E28
E29
E30
E31
E32
E33
E34
E35
E36
E37
E38
E39
E40
E41
E42
E43
E44
E45
AD(24)
AD(22)
AD(19)
C/BE(2)#
KEY
KEY
KEY
TRDY#
LOCK#
PERR#
C/BE(1)#
AD(13)
AD(10)
C/BE(0)#
AD(5)
AD(2)
ACK64#
5V
REQ2#
REQ3#
GNT4#
C/BE(6)#
PAR64
AD(60)
AD(57)
AD(53)
AD(50)
AD(46)
AD(43)
AD(39)
AD(36)
AD(32)
GNT5#
BRSV
GNT6#
USR
USR
USR
Address/Data 24
Address/Data 22
Address/Data 19
Command: Byte Enable
Keyed (no pin)
Keyed (no pin)
Keyed (no pin)
Target Ready
Lock resource
Parity Error
Command: Byte Enable
Address/Data 13
Address/Data 10
Command: Byte Enable
Address/Data 5)
Address/Data 2)
+5 VDC
Request PCI transfer
Request PCI transfer
Grant
Command: Byte Enable
Address/Data 60
Address/Data 57
Address/Data 53
Address/Data 50
Address/Data 46
Address/Data 43
Address/Data 39
Address/Data 36
Address/Data 32
Grant
Bused Reserved (don't use)
Grant
User Defined
User Defined
User Defined
E46 USR
E47 USR
User Defined
User Defined
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
F27
F28
F29
F30
F31
F32
F33
F34
F35
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Keyed (no pin)
Keyed (no pin)
Keyed (no pin)
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
KEY
KEY
KEY
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
F36
F37
F38
F39
F40
F41
F42
F43
F44
F45
F46
F47
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
CompactPCI (technical)
This section does not currently contain so much in depth information as I would like.
Since CompactPCI is based on PCI you should first refer to the PCI standard. This only explains the
extensions CompactPCI specifies.
For a copy of the full CompactPCI standard, contact:
PCI Industrial Computer Manufacturers Group (PICMG)
c/o Roger Communications
301 Edgewater place
Suite 220
Wakewater
MA01880
Phone: 1-617-224-1100
Fax: 1-617-224-1239
Overview:
A CompactPCI system is composed of up to eight CompactPCI card locations:
One System Slot
Up to seven Peripheral Slots
The connector has 7 columns with 47 rows. They are divided into groups:
Row 1-25: 32-bit PCI
Row 26-47: Additional pins for 64-bit PCI (System Slot boards must use it).
Row 26-28 and 40-42: Primarily implemented on System Slot boards.
The following signals must be terminated:
AD0-31
C/BE0#-C/BE3#
PAR
FRAME#
IRDY#
TRDY#
STOP#
LOCK#
IDSEL
DEVSEL#
PERR#
SERR#
RST#
Connector:
1
2
3
4
GND
GND
GND
GND
5V
TCK
INTA#
BRSV
-12V
5V
INTB#
GND
TRST#
TMS
INTC#
V(I/O)
12V
DO
5V
INTP
5V
TDI
INTD#
INTS
GND
GND
GND
GND
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
GND
GND
GND
GND
GND
GND
GND
KEY
KEY
KEY
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
BRSV
REQ#
AD(30)
AD(26)
C/BE(3)#
AD(21)
AD(18)
KEY
KEY
KEY
3.3V
DEVSEL#
3.3V
SERR#
3.3V
AD(12)
3.3V
AD(7)
3.3V
AD(1)
5V
CLK1
CLK2
CLK4
V(I/O)
C/BE(5)#
AD(63)
AD(59)
AD(56)
AD(52)
AD(49)
AD(45)
AD(42)
AD(38)
AD(35)
BRSV
BRSV
BRSV
BRSV
GND
AD(29)
GND
IDSEL
GND
AS(17)
KEY
KEY
KEY
FRAME#
GND
SDONE
GND
AD(15)
GND
AD(9)
GND
AD(4)
5V
REQ64#
GND
CLK3
GND
BRSV
GND
AD(62)
GND
AD(55)
GND
AD(48)
GND
AD(41)
GND
AD(34)
GND
BRSV
GND
RST
3.3V
AD(28)
V(I/O)
AD(23)
3.3V
AD(16)
KEY
KEY
KEY
IRDY#
V(I/O)
SBO#
3.3V
AD(14)
V(I/O)
AD(8)
3.3V
AD(3)
V(I/O)
BRSV
REQ1#
SYSEN#
GNT3#
C/BE(7 )
V(I/O)
AD(61)
V(I/O)
AD(54)
V(I/O)
AD(47)
V(I/O)
AD(40)
V(I/O)
AD(33)
FAL#
DEG#
PRST#
GND
CLK
GND
AD(25)
GND
AD(20)
GND
KEY
KEY
KEY
GND
STOP#
GND
PAR
GND
AD(11)
M66EN
AD(6)
5V
AD(0)
3.3V
GNT1#
GNT2#
REQ4#
GND
C/BE(4)#
GND
AD(58)
GND
AD(51)
GND
AD(44)
GND
AD(37)
GND
REQ5#
GND
REQ6#
GNT#
AD(31)
AD(27)
AD(24)
AD(22)
AD(19)
C/BE(2)#
KEY
KEY
KEY
TRDY#
LOCK#
PERR#
C/BE(1)#
AD(13)
AD(10)
C/BE(0)#
AD(5)
AD(2)
ACK64#
5V
REQ2#
REQ3#
GNT4#
C/BE(6)#
PAR64
AD(60)
AD(57)
AD(53)
AD(50)
AD(46)
AD(43)
AD(39)
AD(36)
AD(32)
GNT5#
BRSV
GNT6#
GND
GND
GND
GND
GND
GND
GND
KEY
KEY
KEY
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
43
44
45
46
47
GND
GND
GND
GND
GND
Z
USR
USR
USR
USR
USR
A
USR
USR
USR
USR
USR
B
USR
USR
USR
USR
USR
C
USR
USR
USR
USR
USR
D
USR
USR
USR
USR
USR
E
GND
GND
GND
GND
GND
F
Signal Descriptions:
PRST
Push Button Reset.
DEG
Power Supply Status DEG
FAL
Power Supply Status FAL
SYSEN
System Slot Identification
Contributor: Joakim gren, Mark Sokos
Sources:
CompactPCI specifications v1.0 at CompactPCI's homepage
Mark Sokos PCI page
"Inside the PCI Local Bus" by Guy W. Kendall, Byte, February 1994 v 19 p. 177-180
"The Indispensible PC Hardware Book" by Hans-Peter Messmer, ISBN 0-201-8769-3
Info: CompactPCI - An Open Industrial Computer Standard article by Joseph S. Pavlat
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-08
ECBbus
Name
5V +
5D
D6
D3
D4
A2
A4
A5
A6
WAIT/
BUSRQ/
Desciption
5 volts dc
ata line bit 5
Data line bit 6
Data line bit 3
Data line bit 4
Address 2
Address 4
Address 5
Address 6
CPU wait
bus request
a14
a15
a16
a17
a18
a19
a20
a21
a22
a23
a24
a25
a26
a27
a28
a29
a30
a31
a32
Pin
c1
c2
c3
c4
c5
c6
c7
c8
c9
c10
c11
c12
c13
c14
c15
c16
c17
c18
A14
address 14
M1/
first cycle
IORQ/
RFSH/
A13
A9
BUSAK/
GND
in/out request
refresh cycle
address 13
address 9
bus acknowledge
signal ground
Name
+5V
D0
D7
D2
A0
A3
A1
A8
A7
Desciption
+5 volts dc
Data line bit 0
Data line bit 7
Data line bit 2
Address 0
Address 3
Address 1
Address 8
Address 7
IEI
interrupt enable in
D1
IEO
A11
A10
c19
c20
c21
c22
c23
c24
c25
c26
c27
c28
c29
c30
c31
c32
NMI/
INT/
WR/
RD/
read cycle
HALT/ cpu stopped
A12
A15
address 12
address 15
Name
+5V
A20
A21
A22
A23
D8
D9
D10
D11
D12
D13
D14
D15
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
IRQ2
IRQ1
Desciption
+5 volts dc
address 20
address 21
address 22
address 23
data line bit 8
data line bit 9
data line bit 10
data line bit 11
data line bit 12
data line bit 13
data line bit 14
data line bit 15
interrupt 7
interrupt 6
interrupt 5
interrupt 4
interrupt 3
interrupt 2
interrupt 1
b21
b22
b23
b24
b25
b26
b27
b28
b29
b30
b31
b32
IRQ0
IOWR
??
IORC
MRDC
??
MWRC
DS0
DS1
OFF
LOCK
GND
DS0
0
0
1
1
DS1
0
1
0
1
interrupt 0
I/O write
??
I/O read
Mem read
??
Mem write
Data Select 0
Data Select 1
bus driver tristate
bus driver tristate disabled
signal ground
Description
data transfer 16-bit
only bit 0-7
only bit 8-15
no data transfer
EISA
EISA=Extended Industry Standard Architecture.
Developed by Compaq, AST, Zenith, Tandy...
+---------------------------------------------+
|
(component side)
|
|
|
|___________ ISA-16bit __
ISA-8bit
__|
||||||||||| ||||||||||||||||||| A1(front)/B1(back)
| | | | |
| | | | | | | | | EISA: E1(front)/F1(back)
C1/D1
G1/H1
A,C,E,G=Component Side
A,B,F,H=Sold Side
Name
CMD#
START#
EXRDY
EX32#
GND
KEY
EX16#
SLBURST#
MSBURST#
W/R#
GND
RES
RES
RES
GND
Description
Command Phase
Start Phase
EISA Ready
EISA Slave Size 32
Ground
Access Key
EISA Slave Size 16
Slave Burst
Master Burst
Write/Read
Ground
Reserved
Reserved
Reserved
Ground
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
E27
E28
E29
E30
E31
KEY
BE1#
LA31#
GND
LA30#
LA28#
LA27#
LA25#
GND
KEY
LA15
LA13
LA12
LA11
GND
LA9
Access Key
Byte Enable 1
Latchable Addressline 31
Ground
Latchable Addressline 30
Latchable Addressline 28
Latchable Addressline 27
Latchable Addressline 25
Ground
Access Key
Latchable Addressline 15
Latchable Addressline 13
Latchable Addressline 12
Latchable Addressline 11
Ground
Latchable Addressline 9
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
GND
+5V
+5V
----KEY
----+12V
M/IO#
LOCK#
RES
GND
RES
BE3#
KEY
BE2#
BE0#
GND
+5V
LA29#
Ground
+5 VDC
+5 VDC
Access Key
+12 VDC
Memory/Input-Output
Lock bus
Reserved
Ground
Reserved
Byte Enable 3
Access Key
Byte Enable 2
Byte Enable 0
Ground
+5 VDC
Latchable Addressline 29
F22
F23
F24
F25
F26
F27
F28
F29
F30
F31
GND
LA26#
LA24#
KEY
LA16
LA14
+5V
+5V
GND
LA10
Ground
Latchable Addressline 26
Latchable Addressline 24
Access Key
Latchable Addressline 16
Latchable Addressline 14
+5 VDC
+5 VDC
Ground
Latchable Addressline 10
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
LA7
GND
LA4
LA3
GND
KEY
D17
D19
D20
D22
GND
D25
D26
D28
KEY
GND
D30
D31
MREQx
Latchable Addressline 7
Ground
Latchable Addressline 4
Latchable Addressline 3
Ground
Access Key
Data 17
Data 19
Data 20
Data 22
Ground
Data 25
Data 26
Data 28
Access Key
Ground
Data 30
Data 31
Master Request
H1
H2
H3
H4
H5
H6
H7
LA8
LA6
LA5
+5V
LA2
KEY
D16
Latchable Addressline 8
Latchable Addressline 6
Latchable Addressline 5
+5 VDC
Latchable Addressline 2
Access Key
Data 16
H8
H9
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
D18
GND
D21
D23
D24
GND
D27
KEY
D29
+5V
+5V
MAKx
Data 18
Ground
Data 21
Data 23
Data 24
Ground
Data 27
Access Key
Data 29
+5 VDC
+5 VDC
Master Acknowledge
EISA (technical)
This section is currently based solely on the work by Mark Sokos.
This file is intended to provide a basic functional overview of the EISA Bus, so that hobbyists and
amateurs can design their own EISA compatible cards.
It is not intended to provide complete coverage of the EISA standard.
EISA is an acronym for Extended Industry Standard Architecture. It is an extension of the ISA
architecture, which is a standardized version of the bus originally developed by IBM for their PC
computers. EISA is upwardly compatible, which means that cards originally designed for the 8 bit IBM
bus (often referred to as the XT bus) and cards designed for the 16 bit bus (referred to as the AT bus, and
also as the ISA bus), will work in an EISA slot. EISA specific cards will not work in an AT or an XT
slot.
The EISA connector uses multiple rows of connectors. The upper row is the same as a regular ISA slot,
and the lower row contains the EISA extension. The slot is keyed so that ISA cards cannot be inserted to
the point where they connect with the EISA signals.
Signal Descriptions
+5, -5, +12, -12
Power supplies. -5 is often not implemented.
AEN
Address Enable. This is asserted when a DMAC has control of the bus. This prevents an I/O device from
responding to the I/O command lines during a DMA transfer.
BALE
Bus Address Latch Enable. The address bus is latched on the rising edge of this signal. The address on
the SA bus is valid from the falling edge of BALE to the end of the bus cycle. Memory devices should
latch the LA bus on the falling edge of BALE.
BCLK
Bus Clock, 33% Duty Cycle. Frequency Varies. 8.33 MHz is specified as the maximum, but many
systems allow this clock to be set to 10 MHz and higher.
BE(x)
Byte Enable. Indicates to the slave device which bytes on the data bus contain valid data. A 16 bit
transfer would assert BE0 and BE1, for example, but not BE2 or BE3.
CHCHK
Channel Check. A low signal generates an NMI. The NMI signal can be masked on a PC, externally to
the processor (of course). Bit 7 of port 70(hex) (enable NMI interrupts) and bit 3 of port 61 (hex)
(recognition of channel check) must both be set to zero for an NMI to reach the CPU.
CHRDY
Channel Ready. Setting this low prevents the default ready timer from timing out. The slave device may
then set it high again when it is ready to end the bus cycle. Holding this line low for too long can cause
problems on some systems. CHRDY and NOWS should not be used simultaneously. This may cause
problems with some bus controllers.
CMD
Command Phase. This signal indicates that the current bus cycle is in the command phase. After the start
phase (see START), the data is transferred during the CMD phase. CMD remains asserted from the
falling edge of START until the end of the bus cycle.
SD0-SD16
System Data lines. They are bi-directional and tri-state.
DAKx
DMA Acknowledge.
DRQx
DMA Request.
EX16
EISA Slave Size 16. This is used by the slave device to inform the bus master that it is capable of 16 bit
transfers.
EX32
EISA Slave Size 32. This is used by the slave device to inform the bus master that it is capable of 32 bit
transfers.
EXRDY
EISA Ready. If this signal is asserted, the cycle will end on the next rising edge of BCLK. The slave
device drives this signal low to insert wait states.
IO16
I/O size 16. Generated by a 16 bit slave when addressed by a bus master.
IORC
I/O Read Command line.
IOWC
I/O Write Command line.
IRQx
Interrupt Request. IRQ2 has the highest priority.
LAxx
Latchable Address lines.
LOCK
Asserting this signal prevents other bus masters from requesting control of the bus.
MAKx
Master Acknowledge for slot x: Indicates that the bus master request (MREQx) has been granted.
MASTER16
16 bit bus master. Generated by the ISA bus master when initiating a bus cycle.
M/IO
Memory/Input-Output. This is used to indicate whether the current bus cycle is a memory or an I/O
operation.
M16
Memory Access, 16 bit
MRDC
Memory Read Command line.
MREQx
Master Request for Slot x: This is a slot specific request for the device to become the bus master.
MSBURST
Master Burst. The bus master asserts this signal in response to SLBURST. This tells the slave device that
the bus master is also capable of burst cycles.
MWTC
Memory Write Command line.
NOWS
No Wait State. Used to shorten the number of wait states generated by the default ready timer. This
causes the bus cycle to end more quickly, since wait states will not be inserted. Most systems will ignore
NOWS if CHRDY is active (low). However, this may cause problems with some bus controllers, and
both signals should not be active simultaneously.
OSC
Oscillator, 14.318 MHz, 50% Duty Cycle. Frequency varies.
REFRESH
Refresh. Generated when the refresh logic is bus master.
RESDRV
This signal goes low when the machine is powered up. Driving it low will force a system reset.
SA0-SA19
System Address Lines, tri-state.
SBHE
System Bus High Enable, tri-state. Indicates a 16 bit data transfer.
SLBURST
Slave Burst. The slave device uses this to indicate that it is capable of burst cycles. The bus master will
respond with MSBURST if it is also capable of burst cycles.
SMRDC
Standard Memory Read Command line. Indicates a memory read in the lower 1 MB area.
SMWTC
Standard Memory Write Command line. Indicates a memory write in the lower 1 MB area.
START
Start Phase. This signal is low when the current bus cycle is in the start phase. Address and M/IO signals
are decoded during this phase. Data is transferred during the command phase (indicated by CMD).
TC
Terminal Count. Notifies the CPU that that the last DMA data transfer operation is complete.
W/R
Write or Read. Used to indicate if the current bus cycle is a read or a write operation.
Contributor: Joakim gren, Mark Sokos
Sources:
Mark Sokos EISA page
"EISA System Architecture, 2nd Edition" by Tom Shanley and Don Anderson, ISBN 0-201-40995-X
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-08
Electrocoin
The Electrocoin standard was introduced before JAMMA (Japanese Arcade Machine Manufacturers
Association) to allow various games to be connected to generic cabinets such as Silverline and Goliaths.
They use the same 28 way connector, but the designations are different. Pins 16 and 18 were 3 player and
4 player start buttons, and were superseded when 3 button games became popular. Pins 14 and 20 were
free, but were used by us to allow for easy servicing of games.
28 PIN UNKNOWN CONNECTOR on the arcade machine
Lower side:
Pin
A
B
C
D
E
F
H
J
K
L
M
N
P
R
S
T
U
V
W
X
Y
Z
Description
Ground
Ground
+5V
+5V
+12V
-5V
Not used
-12V
Keyway
Speaker 1
Speaker 1
Speaker 2
Player 2 Up
Speaker 2
Player 2 Right
Player 2 Button 1
Player 2
Player 2 Button 2
Player 2 Left
(Horizontal Sync)
Player 2 Start
Video Red
Aa
Ab
Ac
Ad
Ae
Af
Video Green
Video Blue
Video Sync
Ground
Ground
Ground
Upper side:
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Description
Ground
Ground
+5V
+5V
+12V
-5V
Not used
-12V
Keyway
Meter 1
Meter 2
Credit Board Meter
Player 1 Up
Test
Player 1 Right
Player 2 Button 3
Player 1 Down
Player 1 Button 3
Player 1 Left
Service
Player 1 Start
Player 1 Button 1
Player 1 Button 2
Coin 1
Coin 2
Ground
Ground
Ground
IEEE1394
Name
Power
Ground
TPBTPB+
TPATPA+
Outer
Description
Unregulated DC; 30 V no load
Ground return for power and inner cable shield
Twisted-pair B, differential signals
Twisted-pair B, differential signals
Twisted-pair A, differential signals
Twisted-pair A, differential signals
cable shield
IEEE1394 (technical)
IEEE1394 was originally developed by Apple under the name Firewire.
Features:
Bandwidth:
ISA
ISA=Industry Standard Architecture
Name
Dir
Description
/I/O CH CK
I/O channel check; active low=parity error
D7
Data bit 7
D6
Data bit 6
D5
Data bit 5
D4
Data bit 4
D3
Data bit 3
D2
Data bit 2
D1
Data bit 1
D0
Data bit 0
I/O CH RDY
I/O Channel ready, pulled low to lengthen memory cycles
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
AEN
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
GND
RESET
+5V
IRQ2
-5VDC
DRQ2
-12VDC
/NOWS
+12VDC
GND
/SMEMW
/SMEMR
/IOW
/IOR
/DACK3
DRQ3
/DACK1
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
DRQ1
/REFRESH
CLOCK
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
/DACK2
T/C
ALE
+5V
OSC
GND
DMA Request 1
Refresh
System Clock (67 ns, 8-8.33 MHz, 50% duty cycle)
Interrupt Request 7
Interrupt Request 6
Interrupt Request 5
Interrupt Request 4
Interrupt Request 3
DMA Acknowledge 2
Terminal count; pulses high when DMA term. count reached
Address Latch Enable
+5 VDC
High-speed Clock (70 ns, 14.31818 MHz, 50% duty cycle)
Ground
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
D1
D2
D3
D4
D5
SBHE
LA23
LA22
LA21
LA20
LA18
LA17
LA16
/MEMR
/MEMW
SD08
SD09
SD10
SD11
SD12
SD13
SD14
SD15
/MEMCS16
/IOCS16
IRQ10
IRQ11
IRQ12
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
IRQ15
IRQ14
/DACK0
DRQ0
/DACK5
DRQ5
/DACK6
DRQ6
/DACK7
DRQ7
+5 V
/MASTER
GND
Interrupt Request 15
Interrupt Request 14
DMA Acknowledge 0
DMA Request 0
DMA Acknowledge 5
DMA Request 5
DMA Acknowledge 6
DMA Request 6
DMA Acknowledge 7
DMA Request 7
Used with DRQ to gain control of system
Ground
ISA (technical)
This file is designed to give a basic overview of the bus found in most IBM clone computers, often
referred to as the XT or AT bus. The AT version of the bus is upwardly compatible, which means that
cards designed to work on an XT bus will work on an AT bus. This bus was produced for many years
without any formal standard. In recent years, a more formal standard called the ISA bus (Industry
Standard Architecture) has been created, with an extension called the EISA (Extended ISA) bus also now
as a standard. The EISA bus extensions will not be detailed here.
This file is not intended to be a thorough coverage of the standard. It is for informational purposes only,
and is intended to give designers and hobbyists sufficient information to design their own XT and AT
compatible cards.
Physical Design:
ISA cards can be either 8-bit or 16-bit. 8-bit cards only uses the first 62 pins and 16-bit cards uses all 98
pins. Some 8-bit cards uses some of the 16-bit extension pins to get more interrupts.
8-bit card:
16-bit card:
Signal Descriptions:
+5, -5, +12, -12
Power supplies. -5 is often not implemented.
AEN
Address Enable. This is asserted when a DMAC has control of the bus. This prevents an I/O device from
responding to the I/O command lines during a DMA transfer. When AEN is active, the DMA Controller
has control of the address bus as the memory and I/O read/write command lines.
BALE
Bus Address Latch Enable. The address bus is latched on the rising edge of this signal. The address on the
SA bus is valid from the falling edge of BALE to the end of the bus cycle. Memory devices should latch
the LA bus on the falling edge of BALE. Some references refer to this signal as Buffered Address Latch
Enable, or just Address Latch Enable (ALE). The Buffered-Address Latch Enable is used to latch SA0-19
on the falling edge. This signal is forced high during DMA cycles.
BCLK
Bus Clock, 33% Duty Cycle. Frequency Varies. 4.77 to 8 MHz typical. 8.3 MHz is specified as the
maximum, but many systems allow this clock to be set to 12 MHz and higher.
DACKx
DMA Acknowledge. The active-low DMA Acknowledge 0 to 3 and 5 to 7 are the corresponding
acknowledge signals for DRQ 0-3, 5-7.
DRQx
DMA Request. These signals are asynchronous channel requests used by I/O channel devices to gain
DMA service. DMA request channels 0-3 are for 8-bit data transfer. DAM request channels 5-7 are for
16-bit data transfer. DMA request channel 4 is used internally on the system board. DMA requests should
be held high until the corresponding DACK line goes active. DMA requests are serviced in the following
priority sequence:
High: DRQ 0, 1, 2, 3, 5, 6, 7 Lowest
IOCS16
I/O size 16. Generated by a 16 bit slave when addressed by a bus master. The active-low I/O Chip Select
16 indicates that the current transfer is a 1 wait state, 16 bit I/O cycle. Open Collector.
I/O CH CK
Channel Check. A low signal generates an NMI. The NMI signal can be masked on a PC, externally to
the processor (of course). Bit 7 of port 70(hex) (enable NMI interrupts) and bit 3 of port 61 (hex)
(recognition of channel check) must both be set to zero for an NMI to reach the cpu. The I/O Channel
Check is an active-low signal which indicates that a parity error exists in a device on the I/O channel.
I/O CH RDY
Channel Ready. Setting this low prevents the default ready timer from timing out. The slave device may
then set it high again when it is ready to end the bus cycle. Holding this line low for too long (15
microseconds, typical) can prevent RAM refresh cycles on some systems. This signal is called IOCHRDY
(I/O Channel Ready) by some references. CHRDY and NOWS should not be used simultaneously. This
may cause problems with some bus controllers. This signal is pulled low by a memory or I/O device to
lengthen memory or I/O read/write cycles. It should only be held low for a minimum of 2.5 microseconds.
IOR
The I/O Read is an active-low signal which instructs the I/O device to drive its data onto the data bus,
SD0-SD15.
IOW
The I/O Write is an active-low signal which instructs the I/O device to read data from the data bus,
SD0-SD15.
IRQx
Interrupt Request. IRQ2 has the highest priority. IRQ 10-15 are only available on AT machines, and are
higher priority than IRQ 3-7. The Interrupt Request signals which indicate I/O service attention. They are
prioritized in the following sequence: Highest IRQ 9(2),10,11,12,14,3,4,5,6,7
LAxx
Latchable Address lines. Combine with the lower address lines to form a 24 bit address space (16 MB)
These unlatched address signals give the system up to 16 MB of address ability. The are valid when
"BALE" is high.
MASTER
16 bit bus master. Generated by the ISA bus master when initiating a bus cycle. This active-low signal is
used in conjunction with a DRQ line by a processor on the I/O channel to gain control of the system. The
I/O processor first issues a DRQ, and upon receiving the corresponding DACK, the I/O processor may
assert MASTER, which will allow it to control the system address, data and control lines. This signal
should not be asserted for more than 15 microseconds, or system memory may be corrupted du to the lack
of memory refresh activity.
MEMCS16
The active-low Memory Chip Select 16 indicates that the current data transfer is a 1 wait state, 16 bit data
memory cycle.
MEMR
The Memory Read is an active-low signal which instructs memory devices to drive data onto the data bus
SD0-SD15. This signal is active on all memory read cycles.
MEMW
The Memory Write is an active-low signal which instructs memory devices to store data present on the
data bus SD0-SD15. This signal is active on all memory write cycles.
NOWS
No Wait State. Used to shorten the number of wait states generated by the default ready timer. This
causes the bus cycle to end more quickly, since wait states will not be inserted. Most systems will ignore
NOWS if CHRDY is active (low). However, this may cause problems with some bus controllers, and both
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OSC
Oscillator, 14.31818 MHz, 50% Duty Cycle. Frequency varies. This was originally divided by 3 to
provide the 4.77 MHz cpu clock of early PCs, and divided by 12 to produce the 1.19 MHz system clock.
Some references have placed this signal as low as 1 MHz (possibly referencing the system clock), but
most modern systems use 14.318 MHz.
This frequency (14.318 MHz) is four times the television colorburst frequency. Refresh timing on many
PC's is based on OSC/18, or approximately one refresh cycle every 15 microseconds. Many modern
motherboards allow this rate to be changed, which frees up some bus cycles for use by software, but also
can cause memory errors if the system RAM cannot handle the slower refresh rates.
REFRESH
Refresh. Generated when the refresh logic is bus master. This active-low signal is used to indicate a
memory refresh cycle is in progress. An ISA device acting as bus master may also use this signal to
initiate a refresh cycle.
RESET
This signal goes low when the machine is powered up. Driving it low will force a system reset. This
signal goes high to reset the system during powerup, low line-voltage or hardware reset. ??????????????
SA0-SA19
System Address Lines, tri-state. The System Address lines run from bit 0 to bit 19. They are latched on to
the falling edge of "BALE".
SBHE
System Bus High Enable, tri-state. Indicates a 16 bit data transfer. The System Bus High Enable indicates
high byte transfer is occurring on the data bus SD8-SD15. This may also indicate an 8 bit transfer using
the upper half of the bus data (if an odd address is present).
SD0-SD16
System Data lines, or Standard Data Lines. They are bidrectional and tri-state. On most systems, the data
lines float high when not driven. These 16 lines provide for data transfer between the processor, memory
and I/O devices.
SMEMR
System Memory Read Command line. Indicates a memory read in the lower 1 MB area. This System
Memory Read is an active-low signal which instructs memory devices to drive data onto the data bus
SD0-SD15. This signal is active only when the memory address is within the lowest 1MB of memory
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address space.
SMEMW
System Memory Write Commmand line. Indicates a memory write in the lower 1 MB area. The System
Memory Write is an active-low signal which instructs memory devices to store data preset on the data bus
SD0-SD15. This signal is active only when the memory address is within the lowest 1MB of memory
address space.
T/C
Terminal Count. Notifies the cpu that that the last DMA data transfer operation is complete. Terminal
Count provides a pulse when the terminal count for any DMA channel is reached.
___|
__
|___|
__
__
__
__
__
|__
__
BALE
_______|
AEN
__________________________________________________
SA0-SA19
|_______________________________________
______________________________________
---------<______________________________________>_____________
_____
|______________________________|
Command Line
(IORC,IOWC,
SMRDC, or SMWTC)
SD0-SD7
(READ)
SD0-SD7
(WRITE)
_____
---------------------------------------<_____>----
___________________________________
---------<___________________________________>----
memory commands, read and write respectively). For write operations, the data remains on the SD bus for
the remainder of the transfer cycle. For read operations, the data must be valid on the falling edge of the
last cycle.
NOWS is sampled at the midpoint of each wait cycle. If it is low, the transfer cycle terminates without
further wait states. CHRDY is sampled during the first half of the clock cycle. If it is low, further wait
cycles will be inserted.
The default for 8 bit transfers is 4 wait states. Some computers allow the number of default wait states to
be changed.
__
__
__
__
__
BCLK
AEN [2]
LA17-LA23
_____________
-------<_____________>-[1]----------------__
BALE
______________|
|________________________
________________
_______
SBHE
|__________________|
__________________
---------------<__________________>-------
SA0-SA19
_________________
M16
____________________
|____|
* * [4]
_________________
IO16 [3]
___________
|_____________|
*
_________________
Command Line
(IORC,IOWC,
MRDC, or MWTC)
SD0-SD7
___________
|____________|
____
---------------------------<____>---------
(READ)
SD0-SD7
(WRITE)
______________
-----------------<______________>---------
It is also possible for an 8 bit bus cycle to use the upper portion of the bus. In this case, the timing will be
similar to a 16 bit cycle, but an odd address will be present on the bus. This means that the bus is
transferring 8 bits using the upper data bits (SD8-SD15).
__
|______________|
__
|____________________|
__
|______________|
_______________________
|__________________|__________________|
SA0-SA19
_________________ _____________________ _________________
----------<_________________><_____________________><_________________>
IO16
___________
___
___________________________
|_____________|
|_____________|
*
*
CHRDY
________________________________
_______________________________
|______|
*
[1]
NOWS
______________________________________________________
_____
|__________|
* [2]
IORC
______________
_______
|_________|
_______
|_______________|
____
|_________|
SD0-SD15
____
____
____
--------------------<____>------------------<____>------------<____>--*
*
*
An asterisk (*) denotes the point where the signal is sampled.
W=Wait Cycle
This timing diagram shows three different transfer cycles. The first is a 16 bit standard I/O read. This is
followed by an almost identical 16 bit I/O read, with one wait state inserted. The I/O device pulls
CHRDY low to indicate that it is not ready to complete the transfer (see [1]). This inserts a wait cycle,
and CHRDY is again sampled. At this second sample, the I/O device has completed its operation and
released CHRDY, and the bus cycle now terminates. The third cycle is an 8 bit transfer, which is
shortened to 1 wait state (the default is 4) by the use of NOWS.
Port Assignments
DMA Controller
DMA Controller (PS/2)
Master Programmable Interrupt Controller (PIC)
Slave PIC
Programmable Interval Timer (PIT)
Keyboard Controller
Real Time Clock
DMA Page Register
Programmable Option Select (PS/2)
PIC #2
DMAC #2
reserved
Math coprocessor, PCJr Disk Controller
Programmable Option Select (PS/2)
AVAILABLE
Hard Drive 1 (AT)
AVAILABLE
Hard Drive 0 (AT)
Game Adapter
Expansion Card Ports
AVAILABLE
Parallel Port 3
AVAILABLE
clock
EGA/Video
Data Acquisition Adapter (AT)
Serial Port COM4
2F0-2F7
2F8-2FF
300-31F
320-32F
330-33F
340-35F
360-36F
370-377
378-37F
380-38F
390-39F
3A0-3AF
3B0-3BF
3BC-3BF
3C0-3CF
3D0-3DF
3E0-3EF
3F0-3F7
3F8-3FF
Reserved
Serial Port COM2
Prototype Adapter, Periscope Hardware Debugger
AVAILABLE
Reserved for XT/370
AVAILABLE
Network
Floppy Disk Controller
Parallel Port 2
SDLC Adapter
Cluster Adapter
reserved
Monochrome Adapter
Parallel Port 1
EGA/VGA
Color Graphics Adapter
Serial Port COM3
Floppy Disk Controller
Serial Port COM1
0008
0009
000A
000B
000C
000D
Port
DMA CH0 Memory Address Register
Contains the lower 16 bits of the memory address, written as two consecutive bytes.
DMA CH0 Transfer Count
Contains the lower 16 bits of the transfer count, written as two consecutive bytes.
DMA CH1 Memory Address Register
DMA CH1 Transfer Count
DMA CH2 Memory Address Register
DMA CH2 Transfer Count
DMA CH3 Memory Address Register
DMA CH3 Transfer Count
DMAC Status/Control Register
Status (I/O read) bits 0-3: Terminal Count, CH 0-3
- bits 4-7: Request CH0-3
Control (write)
- bit 0: Mem to mem enable (1 = enabled)
- bit 1: ch0 address hold enable (1 = enabled)
- bit 2: controller disable (1 = disabled)
- bit 3: timing (0 = normal, 1 = compressed)
- bit 4: priority (0 = fixed, 1 = rotating)
- bit 5: write selection (0 = late, 1 = extended)
- bit 6: DRQx sense asserted (0 = high, 1 = low)
- bit 7: DAKn sense asserted (0 = low, 1 = high)
Software DRQn Request
- bits 0-1: channel select (CH0-3)
- bit 2: request bit (0 = reset, 1 = set)
DMA mask register
- bits 0-1: channel select (CH0-3)
- bit 2: mask bit (0 = reset, 1 = set)
DMA Mode Register
- bits 0-1: channel select (CH0-3)
- bits 2-3: 00 = verify transfer, 01 = write transfer, 10 = read transfer, 11 = reserved
- bit 4: Auto init (0 = disabled, 1 = enabled)
- bit 5: Address (0 = increment, 1 = decrement)
- bits 6-7: 00 = demand transfer mode, 01 = single transfer mode, 10 = block transfer mode, 11 =
cascade mode
DMA Clear Byte Pointer
Writing to this causes the DMAC to clear the pointer used to keep track of 16 bit data transfers
into and out of the DMAC for hi/low byte sequencing.
DMA Master Clear (Hardware Reset)
00D0
00D2
00D4
Port
DMA CH4 Memory Address Register
Contains the lower 16 bits of the memory address, written as two consecutive bytes.
DMA CH4 Transfer Count
Contains the lower 16 bits of the transfer count, written as two consecutive bytes.
DMA CH5 Memory Address Register
DMA CH5 Transfer Count
DMA CH6 Memory Address Register
DMA CH6 Transfer Count
DMA CH7 Memory Address Register
DMA CH7 Transfer Count
DMAC Status/Control Register
Status (I/O read) bits 0-3: Terminal Count, CH 4-7
- bits 4-7: Request CH4-7
Control (write)- bit 0: Mem to mem enable (1 = enabled)
- bit 1: ch0 address hold enable (1 = enabled)
- bit 2: controller disable (1 = disabled)
- bit 3: timing (0 = normal, 1 = compressed)
- bit 4: priority (0 = fixed, 1 = rotating)
- bit 5: write selection (0 = late, 1 = extended)
- bit 6: DRQx sense asserted (0 = high, 1 = low)
- bit 7: DAKn sense asserted (0 = low, 1 = high)
Software DRQn Request
- bits 0-1: channel select (CH4-7)
- bit 2: request bit (0 = reset, 1 = set)
DMA mask register
- bits 0-1: channel select (CH4-7)
- bit 2: mask bit (0 = reset, 1 = set)
00D6
00D8
00DA
00DC
00DE
___|
__
|___|
__
|___|
__
|__|
__
|___|
__
|___|
|___
_______
DRQx
_|
|___________________________________
______________________________
AEN
____|
|________
_______
DAKx
________
|___________________________|
____________________________
SA0-SA15
Command Line
(IORC, MRDC)
SD0-SD7
(READ)
SD0-SD7
(WRITE)
-------<____________________________>------___________
____________
|___________________|
_____________
----------------------<_____________>-------
____________________________
-------<____________________________>-------
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ8
IRQ9
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
8
9
A
B
C
D
E
F
F
F
F
F
F
F
F
F
Bus Mastering:
An ISA device may take control of the bus, but this must be done with caution. There are no safety
mechanisms involved, and so it is easily possible to crash the entire system by incorrectly taking control
of the bus. For example, most systems require bus cycles for DRAM refresh. If the ISA bus master does
not relinquish control of the bus or generate its own DRAM refresh cycles every 15 microseconds, the
system RAM can become corrupted. The ISA adapter card can generate refresh cycles without
relinquishing control of the bus by asserting REFRESH. MRDC can be then monitored to determine when
the refresh cycle ends.
To take control of the bus, the device first asserts its DRQ line. The DMAC sends a hold request to the
cpu, and when the DMAC receives a hold acknowledge, it asserts the appropriate DAK line
corresponding to the DRQ line asserted. The device is now the bus master. AEN is asserted, so if the
device wishes to access I/O devices, it must assert MASTER16 to release AEN. Control of the bus is
returned to the system board by releasing DRQ.
Contributor: Joakim gren, Niklas Edmundsson, Mark Sokos, Pieter Hollants
Source:
Mark Sokos ISA page
"ISA System Architecture, 3rd Edition" by Tom Shanley and Don Anderson ISBN 0-201-40996-8
"Eisa System Architecture, 2nd Edition" by Tom Shanley and Don Anderson ISBN 0-201-40995-X
"Microcomputer Busses" by R.M. Cram ISBN 0-12-196155-9
HelpPC v2.10 Quick Reference Utility, by David Jurgens
ZIDA 80486 Mother Board User's Manual, OPTi 486, 82C495sx
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-08
IndustrialPCI
PCI=Peripheral Component Interconnect.
IndustrialPCI is a version of PCI adapted for industrial and/or embedded applications.
The IPCI connector has three parts:
Optional 60 pin PCI 64 bit extension (Top)
Mandatory 120 pin PCI 32 bit (Middle)
Optional 60 pin Custom I/O (Bottom)
Name
+3,3V
AD2
AD6
GND
AD10
AD13
GND
SDONE
GND
FRAME#
AD18
GND
Description
Note
+3.3 VDC
Address 2
Address 6
Ground
Address 10
Address 13
Ground
Snoop Done
1
Ground
Indicate Address or Data phase 1
Address 18
Ground
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
C1
C2
+5V
AD24
AD27
GND
REQ2
GND
CLK1
CLK2
GND
CLK3
CLK4
+3,3V
REQ64#
AD3
+5V
AD8
+3,3V
AD14
PAR
+3,3V
STOP#
C/BE2#
V(I/O)
AD21
+3,3V
V(I/O)
AD28
AD31
+3,3V
GNT3
RST#
NMI#
X6
+5V
RSTIN#
USB+
ACK64#
GND
+5 VDC
Address 24
Address 27
Ground
Request 2
Ground
33 or 66 MHz Clock
Ground
+3.3 VDC
Request 64 ???
Address 3
+5 VDC
Address 8
+3.3 VDC
Address 14
Parity
+3.3 VDC
Stop
Command, Byte Enable 2
+3.3 or +5 VDC
Address 21
+3.3 VDC
+3.3 or +5 VDC
Address 28
Address 31
+3.3 VDC
Grant 3
Reset
Non Maskable Interrupt
Reserved (6)
+5 VDC
:
2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
AD7
AD9
AD11
GND
SERR#
PERR#
DEVSEL#
GND
AD19
AD22
GND
AD25
GND
X1
GNT2
REQ4
SLEEP#/SDAT
X4
INTD#
INTB#
+5V
USBAD0
AD4
C/BE0#
+3,3V
AD12
AD15
V(I/O)
LOCK#
TRDY#
AD16
AD20
+5V
+5V
AD26
AD29
REQ1
Address 7
Address 9
Address 11
Ground
System Error
Parity Error
Device Select
Ground
Address 19
Address 22
Ground
Address 25
Ground
Reserved (1)
Grant 2
Request 4
Sleep/Serial Data (I2C)
Reserved (4)
Interrupt D
Interrupt B
+5 VDC
Universal Serial Bus (USB)(-)
Address 0
Address 4
Command, Byte Enable 0
+3.3 VDC
Address 12
Address 15
+3.3 or +5 VDC
Resource Lock
Test Logic Ready
Address 16
Address 20
+5 VDC
+5 VDC
Address 26
Address 29
Request 1
1
1
1
1
3
1
1
1
1
D17
D18
D19
D20
D21
D22
D23
D24
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
REQ3
V(I/O)
X2
X5
+3,3V
INTA#
ICPEN#/SCLK
OSC (PWDN)
AD1
AD5
GND
M66EN
GND
C/BE1#
SBO#
+5V
IRDY#
AD17
GND
AD23
C/BE3#
GND
AD30
GNT1
+5V
GNT4
X3
GND
INTC#
-12V
+12V
VBATT
Request 3
+3.3 or +5 VDC
Reserved (2)
Reserved (5)
+3.3 VDC
Interrupt A
ICPEN/Serial Clock (I2C)
Address 1
Address 5
Ground
Enable 66Mhz PCI-bus
Ground
Command, Byte Enable 1
Snoop Backoff
+5 VDC
Initiator Ready
Address 17
Ground
Address 23
Command, Byte Enable 3
Ground
Address 30
Grant 1
+5 VDC
Grant 4
Reserved (3)
Ground
Interrupt C
-12 VDC
+12 VDC
1
3
1
1
Name
+3,3V
AD2
AD6
GND
AD10
AD13
GND
SDONE
GND
FRAME#
AD18
GND
+5V
AD24
AD27
GND
REQ2
CLKM
CLK1
CLK2
GND
CLK3
CLK4
+3,3V
REQ64#
AD3
+5V
AD8
+3,3V
AD14
PAR
+3,3V
STOP#
C/BE2#
V(I/O)
Description
+3.3 VDC
Address 2
Address 6
Ground
Address 10
Address 13
Ground
Snoop Done
Ground
Indicate Address or Data phase
Address 18
Ground
+5 VDC
Address 24
Address 27
Ground
Request 2
Note
1
1
33 or 66 MHz Clock
Ground
+3.3 VDC
Request 64 ???
Address 3
+5 VDC
Address 8
+3.3 VDC
Address 14
Parity
+3.3 VDC
Stop
Command, Byte Enable 2
+3.3 or +5 VDC
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
D1
AD21
+3,3V
V(I/O)
AD28
AD31
+3,3V
GNT3
RST#
NMI#
X6
+5V
RSTIN#
USB+
ACK64#
GND
AD7
AD9
AD11
GND
SERR#
PERR#
DEVSEL#
GND
AD19
AD22
GND
AD25
GND
X1
GNT2
REQ4
SLEEP#/SDAT
X4
INTD#
INTB#
+5V
USBAD0
Address 21
+3.3 VDC
+3.3 or +5 VDC
Address 28
Address 31
+3.3 VDC
Grant 3
Reset
Non Maskable Interrupt
Reserved (6)
+5 VDC
Universal Serial Bus (USB)(+)
Acknowledge 64 ???
Ground
Address 7
Address 9
Address 11
Ground
System Error
Parity Error
Device Select
Ground
Address 19
Address 22
Ground
Address 25
Ground
Reserved (1)
Grant 2
Request 4
Sleep/Serial Data (I2C)
Reserved (4)
Interrupt D
Interrupt B
+5 VDC
Universal Serial Bus (USB)(-)
Address 0
1
1
1
1
1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
AD4
C/BE0#
+3,3V
AD12
AD15
V(I/O)
LOCK#
TRDY#
AD16
AD20
+5V
+5V
AD26
AD29
REQ1
REQ3
V(I/O)
X2
X5
+3,3V
INTA#
ICPEN#/SCLK
OSC (PWDN)
AD1
AD5
GND
M66EN
GND
C/BE1#
SBO#
+5V
IRDY#
AD17
GND
AD23
C/BE3#
GND
AD30
Address 4
Command, Byte Enable 0
+3.3 VDC
Address 12
Address 15
+3.3 or +5 VDC
Resource Lock
Test Logic Ready
Address 16
Address 20
+5 VDC
+5 VDC
Address 26
Address 29
Request 1
Request 3
+3.3 or +5 VDC
Reserved (2)
Reserved (5)
+3.3 VDC
Interrupt A
ICPEN/Serial Clock (I2C)
Address 1
Address 5
Ground
Enable 66Mhz PCI-bus
Ground
Command, Byte Enable 1
Snoop Backoff
+5 VDC
Initiator Ready
Address 17
Ground
Address 23
Command, Byte Enable 3
Ground
Address 30
1
1
1
1
1
3
1
1
E16
E17
E18
E19
E20
E21
E22
E23
E24
GNT1
+5V
GNT4
X3
GND
INTC#
-12V
+12V
VBATT
Grant 1
+5 VDC
Grant 4
Reserved (3)
Ground
Interrupt C
-12 VDC
+12 VDC
Name
+3,3V
AD2
AD6
GND
AD10
AD13
GND
SDONE
GND
FRAME#
AD18
GND
+5V
AD24
AD27
GND
IDSEL0
GND
CLK1
GND
GND
GND
GND
+3,3V
Description
+3.3 VDC
Address 2
Address 6
Ground
Address 10
Address 13
Ground
Snoop Done
Ground
Indicate Address or Data phase
Address 18
Ground
+5 VDC
Address 24
Address 27
Ground
IDSEL0
Ground
33 or 66 MHz Clock
Ground
Ground
Ground
Ground
+3.3 VDC
Note
1
1
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
REQ64#
AD3
+5V
AD8
+3,3V
AD14
PAR
+3,3V
STOP#
C/BE2#
V(I/O)
AD21
+3,3V
V(I/O)
AD28
AD31
+3,3V
GND
RST#
NMI#
X6
+5V
RSTIN#
USB+
ACK64#
GND
AD7
AD9
AD11
GND
SERR#
PERR#
DEVSEL#
GND
AD19
AD22
GND
AD25
Request 64 ???
Address 3
+5 VDC
Address 8
+3.3 VDC
Address 14
Parity
+3.3 VDC
Stop
Command, Byte Enable 2
+3.3 or +5 VDC
Address 21
+3.3 VDC
+3.3 or +5 VDC
Address 28
Address 31
+3.3 VDC
Ground
Reset
Non Maskable Interrupt
Reserved (6)
+5 VDC
Universal Serial Bus (USB)(+)
Acknowledge 64 ???
Ground
Address 7
Address 9
Address 11
Ground
System Error
Parity Error
Device Select
Ground
Address 19
Address 22
Ground
Address 25
1
1
1
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
E1
E2
E3
E4
GND
X1
IDSEL1
GND
SLEEP#/SDAT
X4
INTD#
INTB#
+5V
USBAD0
AD4
C/BE0#
+3,3V
AD12
AD15
V(I/O)
LOCK#
TRDY#
AD16
AD20
+5V
+5V
AD26
AD29
REQ1
IDSEL2
V(I/O)
X2
X5
+3,3V
INTA#
ICPEN#/SCLK
OSC (PWDN)
AD1
AD5
GND
M66EN
Ground
Reserved (1)
Initialization Device Select 1
Ground
Sleep/Serial Data (I2C)
Reserved (4)
Interrupt D
Interrupt B
+5 VDC
Universal Serial Bus (USB)(-)
Address 0
Address 4
Command, Byte Enable 0
+3.3 VDC
Address 12
Address 15
+3.3 or +5 VDC
Resource Lock
Test Logic Ready
Address 16
Address 20
+5 VDC
+5 VDC
Address 26
Address 29
Request 1
Initialization Device Select 2
+3.3 or +5 VDC
Reserved (2)
Reserved (5)
+3.3 VDC
Interrupt A
ICPEN/Serial Clock (I2C)
1
1
1
1
1
3
Address 1
Address 5
Ground
Enable 66Mhz PCI-bus
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
GND
C/BE1#
SBO#
+5V
IRDY#
AD17
GND
AD23
C/BE3#
GND
AD30
GNT1
+5V
GNT4
X3
GND
INTC#
-12V
+12V
VBATT
Ground
Command, Byte Enable 1
Snoop Backoff
+5 VDC
Initiator Ready
Address 17
Ground
Address 23
Command, Byte Enable 3
Ground
Address 30
Grant 1
+5 VDC
Grant 4
Reserved (3)
Ground
Interrupt C
-12 VDC
+12 VDC
1
1
Name
GND
X10
AD35
AD38
AD42
V(I/O)
V(I/O)
AD52
AD56
AD60
AD63
GND
X7
Description
Ground
Reserved (10)
Address 35
Address 38
Address 42
+3.3 or +5 VDC
+3.3 or +5 VDC
Address 52
Address 56
Address 60
Address 63
Ground
Reserved (7)
Note
2
2
2
2
2
2
2
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
E1
E2
E3
GND
AD36
AD39
AD43
AD46
AD49
AD53
AD57
AD61
GND
C/BE6#
X8
AD32
GND
AD40
AD44
GND
GND
AD54
AD58
GND
PAR64
C/BE7#
X9
AD33
AD37
GND
AD45
AD47
AD50
AD55
GND
AD62
C/BE4#
X11
GND
AD34
V(I/O)
Ground
Address 36
Address 39
Address 43
Address 46
Address 49
Address 53
Address 57
Address 61
Ground
Command, Byte Enable 6
Reserved (8)
Address 32
Ground
Address 40
Address 44
Ground
Ground
Address 54
Address 58
Ground
Parity 64 ???
Command, Byte Enable 7
Reserved (9)
Address 33
Address 37
Ground
Address 45
Address 47
Address 50
Address 55
Ground
Address 62
Command, Byte Enable 4
Reserved (11)
Ground
Address 34
+3.3 or +5 VDC
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
E4
E5
E6
E7
E8
E9
E10
E11
E12
AD41
GND
AD48
AD51
GND
AD59
V(I/O)
C/BE5#
X12
Address 41
Ground
Address 48
Address 51
Ground
Address 59
+3.3 or +5 VDC
Command, Byte Enable 5
Reserved (12)
2
2
2
2
2
2 = Pullup resistor of 2,7 kOhm (5V bus system) or 8,2 kOhm (3,3V bus system) on the backplane.
ISA96/AT96 (Bottom)
Pin
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
Name
RSTDRV
IRQ9
SD11
SD9
IOCHRDY
IOW#
SA15
CLK
SA10
SA7
T/C
SA2
SD15
SD13
SD3
SD1
SMEMW#
SA18
SA14
DACK6#
SA9
IRQ3
IOCS16#
SA1
Description
Note
Interrupt 9
Data 11
Data 9
1
I/O Write
Address 15
Clock
Address 10
Address 7
Address 2
Data 15
Data 13
Data 3
Data 1
System Memory Write
Address 18
Address 14
DMA Acknowledge 6
Address 9
Interrupt 3
I/O 16-bit chip select 1
Address 1
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
SD7
SD5
SD10
SD8
AEN
IOR#
SA13
SA11
IRQ5
SA6
SA4
IRQ11
SD14
SD12
SD2
SD0
SMEMR#
SA17
REF#
IRQ7
SA8
MCS16#
BALE
SA0
SD6
SD4
0WS
SBHE#
SA19
SA16
SA12
DRQ6
IRQ4
SA5
SA3
IRQ10
Data 7
Data 5
Data 10
Data 8
Address Enable
I/O Read
Address 13
Address 11
Interrupt 5
Address 6
Address 4
Interrupt 11
Data 14
Data 12
Data 2
Data 0
System Memory Read
Address 17
Interrupt 7
Address 8
1
Address 0
Data 6
Data 4
1
Address 19
Address 16
Address 12
DMA Request 6
Interrupt 4
Address 5
Address 3
Interrupt 10
VMEbus (Bottom)
Pin
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
Name
D0
D2
D12
D7
DS1#
BR3#
AM1
AM3
IACKOUT#
A14
A12
A10
BBSY#
D10
D5
D15
SYSRES#
A23
A21
A19
A16
A6
A4
A2
D8
D3
D13
SYSCLK
DS0#
DTACK#
AS#
IACK#
AM4
A13
A11
Description
Data 0
Data 2
Data 12
Data 7
Address 14
Address 12
Address 10
Data 10
Data 5
Data 15
Address 23
Address 21
Address 19
Address 16
Address 6
Address 4
Address 2
Data 8
Data 3
Data 13
Address 13
Address 11
C12
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
A9
D1
D11
D6
BG3OUT#
WR#
AM0
AM2
A18
A15
A5
A3
A1
D9
D4
D14
BERR#
AM5
A22
A20
A17
A7
IRQ5#
IRQ3#
A8
Address 9
Data 1
Data 11
Data 6
Write
Address 18
Address 15
Address 5
Address 3
Address 1
Data 9
Data 4
Data 14
Bus Error
Address 22
Address 20
Address 17
Address 7
Interrupt 5
Interrupt 3
Address 8
ECB (Bottom)
Pin
A1
A2
A3
A4
A5
A6
A7
A8
A9
Name
D5
D2
A4
A7
BAI
2F
A10
INT#
VCMOS
Description
Data 5
Data 2
Data 4
Address 7
Address 10
A10
A11
A12
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
PWRCLR#
A13
RESET#
D0
D4
A1
WAIT#
A17
IEO
n/c
DMARDY
RD#
IORQ#
?
n/c
D6
A0
A5
A16
A18
BAO
M1#
WR#
n
A12
A9
n/c
D7
A2
A8
BUSRQ#
A19
A11
NMI#
PF
HALT#
RFSH#
MRQ#
Address 13
Reset
Data 0
Data 4
Address 1
Address 17
Not connected
Read
Not connected
Data 6
Address 0
Address 5
Address 16
Address 18
Address 12
Address 9
Not connected
Data 7
Address 2
Address 8
Address 19
Address 11
Non Maskable Interrupt
D12
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
n/c
D3
A3
A6
IEI
D1
A14
n/c
n/c
DESLCT#
A15
BUSAK#
n/c
Not connected
Data 3
Address 3
Address 6
Data 1
Address 14
Not connected
Not connected
Address 15
Not connected
SMP16 (Bottom)
Pin
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
B1
B2
B3
B4
B5
B6
B7
B8
B9
Name
NMI#
IRQ0#
D11
D9
RDYIN
IOW#
A15
CLK
A10
A7
TC/EOP#
A2
D15
D13
D3
D1
MEMW#
A18
A14
DACKx#
A9
Description
Non Maskable Interrupt
Interrupt 0
Data 11
Data 9
Address 15
Address 10
Address 7
Address 2
Data 15
Data 13
Data 3
Data 1
Address 18
Address 14
Address 9
B10
B11
B12
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
IRQ3#
IOCS16#
A1
D7
D5
D10
D8
BUSEN
IOR#
A13
A11
IRQ1#
A6
A4
IRQ4#
D14
D12
D2
D0
MEMR#
A17
INTA#
INT#
A8
MECS16#
ALE
A0
D6
D4
MMIO#
BHEN
A19
A16
A12
DRQx#
IRQ2#
A5
A3
Interrupt 3
Address 1
Data 7
Data 5
Data 10
Data 8
Address 13
Address 11
Interrupt 1
Address 6
Address 4
Interrupt 4
Data 14
Data 12
Data 2
Data 0
Address 17
Address 8
Address 0
Data 6
Data 4
Address 19
Address 16
Address 12
Interrupt 2
Address 5
Address 3
E12 IRQ5#
Interrupt 5
Floppy/EIDE (Bottom)
Pin
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
C1
C2
C3
C4
C5
C6
C7
C8
C9
Name
FDSEL1
FDSEL0
FDME1
DIR
STEP
WRDATA
WE
TRK0
WP
RDDATA
HDSEL
DSKCHG
DRVDEN1
DRVDEN0
IDECS3P#
IDEA2
IDEIRQS
IDEPUS
IDEDRQP
IDED14
IDED8
IDED6
IDED11
IDED3
FDME0
INDX
IDECS3S#
IDEA0
IDEDAKS#
IDEIOR#
IDEDRQS
IDED1
#IDERST
Description
Floppy Select 1
Floppy Select 0
Floppy ?
Floppy Direction
Floppy Step
Floppy Write Data
Floppy Write?
Floppy Track 0
Floppy Write?
Floppy ?
Floppy HD Select
Floppy DiskChange
?
?
IDE ?
IDE ?
IDE ?
IDE ?
IDE ?
IDE Data 14
IDE Data 8
IDE Data 6
IDE Data 11
IDE Data 3
Floppy Me?
Floppy Index
IDE ?
IDE ?
IDE ?
IDE ?
IDE ?
IDE Data 1
IDE ?
C10
C11
C12
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
IDED10
IDED4
IDED2
IDELEDS#
IDELEDP#
IDECS1S#
IDEIRQP
IDEPUP
IDEIOW#
IDED15
IDED13
IDED7
GND
GND
GND
GND
GND
IDECS1P#
IDEA1
IDEDAKP#
IDEIORDY
IDED0
IDED12
IDED9
IDED5
GND
GND
IDE Data 10
IDE Data 4
IDE Data 2
IDE LED ?
IDE LED ?
IDE ?
IDE ?
IDE Pull Up ?
IDE ?
IDE Data 15
IDE Data 13
IDE Data 7
Ground
Ground
Ground
Ground
Ground
IDE ?
IDE ?
IDE ?
IDE ?
IDE Data 0
IDE Data 12
IDE Data 9
IDE Data 5
Ground
Ground
SCSI (Bottom)
Pin
A1
A2
A3
A4
A5
A6
A7
Name
TERM
GND
I/O#
REQ#
ATN#
D8
D9
Description
Ground
Data 8
Data 9
A8
A9
A10
A11
A12
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D2
D4
DP0
GND
TERM
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
TERM
GND
C/D#
MSG#
ACK#
D12
DP1
D13
D1
D5
D7
GND
TERM
GND
GND
GND
GND
GND
GND
GND
GND
Data 10
Data 2
Data 4
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Data 12
Data P1
Data 13
Data 1
Data 5
Data 7
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
D10
D11
D12
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
GND
GND
GND
TERM
GND
SEL#
RST#
BSY#
D14
D15
D11
D0
D3
D6
GND
Ground
Ground
Ground
Ground
Data 14
Data 15
Data 11
Data 0
Data 3
Data 6
Ground
JAMMA
JAMMA=Japanese Arcade Machine Manufacturers Association
An old group trying to set standards for board pinouts (at arcade machines). This was designed to make
board changes easy, just take out the old game and plug in the new. Unfortunately games have evolved,
and the Jamma standard is no longer up to the job as it can`t handle more than 4 buttons or two players.
Also replacing a board from a different manufacturer meant readjusting the picture on the monitor as it
would not be centred in the same position.
28 PIN UNKNOWN CONNECTOR on the arcade machine
Sold side
Pin
A
B
C
D
E
F
H
J
K
L
M
N
P
R
S
T
U
V
W
X
Y
Description
Ground
Ground
+5V
+5V
-5V
+12V
Key (no connection)
Meter 2
Lockout 2
Speaker Audio Ground
Video Green
Video Sync
Service Switch
Tilt Switch "Pinball Slam"
Coin 2
2 Player start
Player 2 Up
Player 2 Down
Player 2 Left
Player 2 Right
Z
Aa
Ab
Ac
Ad
Ae
Af
Player 2 Button 1
Player 2 Button 2
Player 2 Button 3
(Player 2 Button 4)
Not used
Ground
Ground
Component side
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Description
Ground
Ground
+5V
+5V
-5V
+12V
Key (no connection)
Meter 1
Lockout 1
Speaker +
Audio +
Video Red
Video Blue
Video Ground
Test Switch
Coin 1
1 Player start
Player 1 Up
Player 1 Down
Player 1 Left
Player 1 Right
Player 1 Button 1
Player 1 Button 2
Player 1 Button 3
(Player 1 Button 4)
Not used
Ground
28 Ground
Note: All signals are active low.
Contributor: Joakim gren
Source:
JAMMA pinout at Technick.net
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-08
MCA
MCA=
62+36 PIN EDGE CONNECTOR MALE at the card.
62+36 PIN EDGE CONNECTOR FEMALE at the computer.
-----------------------------------|
|
[]
[]
[]
|]
|
[]
[]
[]
|
|_
___
_|
|||||||||
|||||||||||||||||||||
C11....C1
D11....D1
Pin
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
Name
VSYNC
HSYNC
BLANC
GND
P6
EDCLK
DCLK
GND
P7
EVIDEO
CD/SETUP
MADE24
GND
A11
A10
A9
+5V
A8
A7
A6
+5V
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
B1
B2
B3
B4
A5
A4
A3
+5V
A2
A1
A0
+12V
ADL
PREEMPT
BURST
-12V
ARB0
ARB1
ARB2
-12V
ARB3
ARB/GNT
TC
+5V
S0
S1
M/IO
+12V
CD CHRDY
D0
D2
+5V
D5
D6
D7
GND
DS 16 RIN
REFRESH
ESYNC
GND
P5
P4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
P3
GND
P2
P1
P0
GND
Audio/GND
Audio
GND
OsciLlator
GND
A23
A22
A21
GND
A20
A19
A18
GND
A17
A16
A15
GND
A14
A13
A12
GND
IRQ9
IRQ3
IRQ4
GND
IRQ5
IRQ6
IRQ7
GND
Reserved
Reserved
CHCK
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
GND
CMD
CHROYRTN
CD SFDBK
GND
D1
D3
D4
GND
CHRESET
Reserved
Reserved
GND
+5V
D10
D11
D13
+12V
Reserved
SBHE
CD DS 16
+5V
IRQ14
IRQ15
D8
D9
GND
D12
D14
D15
GND
IORQ10
IORQ11
IORQ12
GND
Miniature Card
Developed by Intel.
Miniature Card is a memory-only expansion card.
Name
A18
A16
A14
Vccr
CEH#
A11
A9
A8
A6
A5
A3
A2
A0
RAS#
A24
A23
A22
OE#
D15
Description
Address Bus
Address Bus
Address Bus
Voltage Refresh
Card Enable High Byte
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Row Address Strobe
Address Bus
Address Bus
Address Bus
Output Enable
Data Bus
Dir
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
D13
D12
D10
D9
D0
D2
D4
RFU
D7
SDA
SCL
A19
A17
A15
A13
A12
RESET#
A10
VS1#
A7
BS8#
A4
CEL#
A1
CASL#
CASH#
CD#
A21
BUSY#
WE#
D14
RFU
D11
VS2#
D8
D1
D3
D5
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Reserved for future use
Data Bus
Serial Data and Address
Serial Clock
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Reset
Address Bus
Voltage Sense 1
Address Bus
Bus Size 8
Address Bus
Card Enable Low Byte
Address Bus
Column Address Strobe Low Byte
Column Address Strobe High Byte
Card Detect
Address Bus
Ready/Busy
Write Enable
Data Bus
Reserved for future use
Data Bus
Voltage Sense 2
Data Bus
Data Bus
Data Bus
Data Bus
58 D6
59 RFU
60 A20
Data Bus
Reserved for future use
Address Bus
Description Dir
Ground
Power
Card Insertion
Signal Descriptions:
A0-A24
Address A0 to A24 are the address bus lines that can address up to 32 Mwords (64 MBytes). The
Miniature Card specification does not require the Miniature Card to decode the upper address lines. A 2
Mbyte Miniature Card that does not decode the upper address lines would repeat its address space every
2 Mbytes. Address 0h would access the same physical location as 200000h, 400000h, 600000h, etc.
D0-D15
Data lines D0 through D15 constitute the data bus. The data bus is composed of two bytes, the low byte
D[7:0] and the high byte D[15:8].
OE#
OE# indicates that the current bus cycle is a read cycle.
WE#
WE# indicates that the current bus cycle is a write cycle.
VS1#
Voltage Sense 1 signal. The card grounds this signal to indicate it can operate at 3.3 Volts. This signal
must either be connected to card GND or left open.
VS2#
Voltage Sense 2 signal. The card grounds this signal to indicate it can operate at x.x Volts (the value to
be determined at a later date). This signal must either be connected to card GND or left open.
CEL#
CEL# enables the low byte of the data bus (D[7:0]) on the card. This signal is not used in DRAM cards.
CEH#
CEH# enables the high byte of the data bus (D[15:8]) on the card. This signal is not used in DRAM
cards.
RAS#
RAS# strobes in the row address for DRAM cards.
CASL#
CASL# strobes in the low byte column address for DRAM cards.
CASH#
CASH# strobes in the high byte column address for DRAM cards.
RESET#
RESET# controls card initialization. When RESET# transitions from a low state to a high state, the
Miniature Card must reset to a predetermined state.
BUSY#
BUSY# is a signal generated by the card to indicate the status of operations within the Miniature Card.
When BUSY# is high, the Miniature Card is ready to accept the next command from the host. When
BUSY# is low, the Miniature Card is busy and unable to accept some data operations from the host. For
example, in Flash Miniature Cards the BUSY# signal is tied to the components RY/BY# signal.
However, ROM Miniature Cards would always drive BUSY# high since the host will always be able to
read from a ROM Miniature Card.
Vccr
Vccr provides a low current (refresh) voltage supply. Vccr is a feature used by DRAM Miniature Cards
to "self-refresh" during "sleep" mode.
SDA
I2C: Serial Data/Address.
SCL
I2C: Serial Clock are used to read the attribute information structure (AIS) from the serial EEPROM in a
DRAM card.
CD#
CD# is a grounded interface signal. After a Miniature Card has been inserted, CD# will be forced low.
The card detect signal is located in the center of the second row of interface signals, and should be one of
the last interface signals to connect to the host. Do not confuse CD# with CINS#. CINS# is an early card
detect that is one of the first signals to connect to the host.
BS8#
BS8# is a signal driven by the host to indicate if the data bus is x8 or x16. An 8-bit host must drive BS8#
low and tie the high byte data bus D[15:8] to the low byte data bus D[7:0]. A 16-bit host must drive this
signal high.
GND
Ground
Vcc
Vcc is used to supply power to the card.
CINS#
CINS# is a grounded signal on the front of the Miniature Card that can be used for early detection of a
card insertion. CINS# makes contact on the host when the front of the card is inserted into the socket,
before the interface signals connect.
Contributor: Joakim gren
Source:
Minicature Card v1.1 spec at Miniature Card Implementers Forum's homepage
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-08
NuBus
Available on old Apple Macintosh computers and on NeXT computers.
Standard: IEEE 1196, "Nubus-A simple 32-bit backplane bus".
Texas Instruments owns the standard today.
Row A
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Name
-12 V
/SPV
/SP
/TM1
/AD1
/AD3
/AD5
/AD7
/AD9
/AD11
/AD13
/AD15
/AD17
/AD19
Description
-12 VDC
Address/Data 1
Address/Data 3
Address/Data 5
Address/Data 7
Address/Data 9
Address/Data 11
Address/Data 13
Address/Data 15
Address/Data 17
Address/Data 19
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
/AD21
/AD23
/AD25
/AD27
/AD29
/AD31
GND
GND
/ARB1
/ARB3
/ID1
/ID3
/ACK
+5 V
/RQST
/NMRQ
+12 V
Address/Data 21
Address/Data 23
Address/Data 25
Address/Data 27
Address/Data 29
Address/Data 31
Ground
Ground
+5 VDC
+12 VDC
Row B
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Name
-12 V
GND
GND
+5 V
+5 V
+5 V
+5 V
*
*
*
*
GND
GND
GND
GND
GND
GND
Description
-12 VDC
Ground
Ground
+5 VDC
+5 VDC
+5 VDC
+5 VDC
Reserved ?
Reserved ?
Reserved ?
Reserved ?
Ground
Ground
Ground
Ground
Ground
Ground
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
GND
GND
GND
GND
GND
GND
**
**
**
**
+5 V
+5 V
GND
GND
+12 V
Ground
Ground
Ground
Ground
Ground
Ground
Reserved ?
Reserved ?
Reserved ?
Reserved ?
+5 VDC
+5 VDC
Ground
Ground
Row C
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Name
/RESET
+5 V
+5 V
/TM0
/AD0
/AD2
/AD4
/AD6
/AD8
/AD10
/AD12
/AD14
/AD16
/AD18
/AD20
/AD22
/AD24
/AD26
Description
Reset
+5 VDC
+5 VDC
Address/Data 0
Address/Data 2
Address/Data 4
Address/Data 6
Address/Data 8
Address/Data 10
Address/Data 12
Address/Data 14
Address/Data 16
Address/Data 18
Address/Data 20
Address/Data 22
Address/Data 24
Address/Data 26
20
21
22
23
24
25
26
27
28
29
30
31
32
/AD28
/AD30
GND
/PFW
/ARB0
/ARB2
/ID0
/ID2
/START
+5 V
+5 V
GND
/CLK
Address/Data 28
Address/Data 30
Ground
+5 VDC
+5 VDC
Ground
Clock
+5V
Power to slot; 2 amps per slot maximum continuous.
+12V
Power to slot; 0.25 amps per slot maximum continuous.
-12V
Power to slot; 0.1 amps per slot maximum continuous.
-5.2V
Unused
GND
Power return for +5V, +12V, and -12V
RESET
Open collector signal; card should use to reset circuitry.
SPV
Slot Parity Valid; asserted if card provides parity. Never asserted under Apple NuBus.
SP
Slot Parity; odd parity of AD0-AD3 if SPV asserted.
TM0 - TM1
Transaction modifiers.
AD<31:0>
Address/Data bits 31 to 0.
PFW
Power Fail Warning given 2ms before AC power is lost.
ARB<3:0>
Arbitration bits 3 to 0; arbitrates system mastership.
ID<3:0>
Geographical address 3 to 0; hard-coded to slot.
START
Asserted to indicate an address on AD lines.
ACK
Acknowledge of START cycle.
RQST
Request; asserted to request bus mastership.
NMRQ
Non-master request; used to signal an interrupt.
CLK
Clock. Asymmetrical 10MHz clock; synchronous transactions on NuBus.
Contributor: Joakim gren, Karsten Wenke, Michael Van den Acker, Godel?
Source:
Apple Tech Info Library 2194: Macintosh II NuBus Slots, Pinout at Apple TIL homepage
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
NuBus 90
Available on old Apple Macintosh computers.
Row A
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Name
-12 V
SB0
/SPV
/SP
/TM1
/AD1
/AD3
/AD5
/AD7
/AD9
/AD11
/AD13
/AD15
/AD17
/AD19
/AD21
/AD23
Description
-12 VDC
Address/Data 1
Address/Data 3
Address/Data 5
Address/Data 7
Address/Data 9
Address/Data 11
Address/Data 13
Address/Data 15
Address/Data 17
Address/Data 19
Address/Data 21
Address/Data 23
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
/AD25
/AD27
/AD29
/AD31
GND
GND
/ARB1
/ARB3
/ID1
/ID3
/ACK
+5 V
/RQST
/NMRQ
+12 V
Address/Data 25
Address/Data 27
Address/Data 29
Address/Data 31
Ground
Ground
+5 VDC
+12 VDC
Row B
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Name
-12 V
GND
GND
+5 V
+5 V
+5 V
+5 V
/TM2
/CM0
/CM1
/CM2
GND
GND
GND
GND
GND
GND
GND
GND
Description
-12 VDC
Ground
Ground
+5 VDC
+5 VDC
+5 VDC
+5 VDC
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
20
21
22
23
24
25
26
27
28
29
30
31
32
GND
GND
GND
GND
/CLK2X
STDBYPWR
/CLK2XEN
/CBUSY
+5 V
+5 V
GND
GND
+12 V
Ground
Ground
Ground
Ground
+5 VDC
+5 VDC
Ground
Ground
+12 VDC
Row C
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Name
/RESET
SB1
+5 V
+5 V
/TM0
/AD0
/AD2
/AD4
/AD6
/AD8
/AD10
/AD12
/AD14
/AD16
/AD18
/AD20
/AD22
/AD24
/AD26
/AD28
/AD30
Description
Reset
+5 VDC
+5 VDC
Address/Data 0
Address/Data 2
Address/Data 4
Address/Data 6
Address/Data 8
Address/Data 10
Address/Data 12
Address/Data 14
Address/Data 16
Address/Data 18
Address/Data 20
Address/Data 22
Address/Data 24
Address/Data 26
Address/Data 28
Address/Data 30
22
23
24
25
26
27
28
29
30
31
32
GND
/PFW
/ARB0
/ARB2
/ID0
/ID2
/START
+5 V
+5 V
GND
/CLK
Ground
+5 VDC
+5 VDC
Ground
Clock
PC Card
16-bit bus defined by PCMCIA.
Memory
GND
D3
D4
D5
D6
D7
CE1#
A10
OE#
A11
A9
A8
A13
A14
WE#
READY
Vcc
Vpp1
A16
A15
I/O+Mem
GND
D3
D4
D5
D6
D7
CE1#
A10
OE#
A11
A9
A8
A13
A14
WE#
IREQ#
Vcc
Vpp1
A16
A15
Description
Ground
Data 3
Data 4
Data 5
Data 6
Data 7
Address 10
Output Enable
Address 11
Address 9
Address 8
Address 13
Address 14
Write Enable ???
Vcc
Vpp1
Address 16
Address 15
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
A12
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
WP
GND
GND
CD1#
D11
D12
D13
D14
D15
CE2#
VS1#
RSRVD
RSRVD
A17
A18
A19
A20
A21
Vcc
Vpp2
A22
A23
A24
A25
VS2#
RESET
A12
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
IOIS16#
GND
GND
CD1#
D11
D12
D13
D14
D15
CE2#
VS1#
IORD#
IOWR#
A17
A18
A19
A20
A21
Vcc
Vpp2
A22
A23
A24
A25
VS2#
RESET
Address 12
Address 7
Address 6
Address 5
Address 4
Address 3
Address 2
Address 1
Address 0
Data 0
Data 1
Data 2
Ground
Ground
Card Detect 1
Data 11
Data 12
Data 13
Data 14
Data 15
Reserved / IORD#
Reserved / IOWR#
Address 17
Address 18
Address 19
Address 20
Address 21
Vcc
Vpp2
Address 22
Address 23
Address 24
Address 25
Reset
59
60
61
62
63
64
65
66
67
68
WAIT#
RSRVD
REG#
BVD2
BVD1
D8
D9
D10
CD2#
GND
WAIT#
INPACK#
REG#
SPKR#
STSCHG#
D8
D9
D10
CD2#
GND
Reserved / ???
Battery Voltage 2 / Speaker ???
Battery Voltage 1 / ???
Data 8
Data 9
Data 10
Ground
PC/104
J1/P1
Row A
J1/P1
Row B
J2/P2
Row C1
--0V
IOCHCHK* 0V
SBHE*
SD7
RESETDRV LA23
SD6
+5V
LA22
SD5
IRQ9
LA21
SD4
-5V
LA20
SD3
DRQ2
LA19
SD2
-12V
LA18
SD1
ENDXFR* LA17
SD0
+12V
MEMR*
IOCHRDY (KEY)2
MEMW*
AEN
SMEMW* SD8
SA19
SMEMR* SD9
SA18
IOW*
SD10
SA17
IOR*
SD11
SA16
DACK3*
SD12
SA15
DRQ3
SD13
SA14
DACK1*
SD14
SA13
DRQ1
SD15
SA12
REFRESH*
J2/P2
Row D1
0V
MEMCS16*
IOCS16*
IRQ10
IRQ11
IRQ12
IRQ15
IRQ14
DACK0*
DRQ0
DACK5*
DRQ5
DACK6*
DRQ6
DACK7*
DRQ7
+5V
MASTER*
0V
(KEY)2 0V
20
21
22
23
24
25
26
27
28
29
30
31
32
SA11
SA10
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
0V
SYSCLK
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
DACK2*
TC
BALE
+5V
OSC
0V
0V
--------------
--------------
PCI
PCI=Peripheral Component Interconnect
PCI Universal Card 32/64 bit
---------------------------------------------------------------|
PCI
Component Side (side B)
|
|
|
|
|
|
optional
|
|
____
mandatory 32-bit pins
64-bit pins _____|
|___|
|||||||--|||||||||||||||||--|||||||--||||||||||||||
^
^ ^
^ ^
^ ^
^
b01
b11 b14
b49 b52 b62 b63
b94
PCI 5V Card 32/64 bit
|
optional
|
|
____
mandatory 32-bit pins
64-bit pins _____|
|___|
||||||||||||||||||||||||||--|||||||--||||||||||||||
PCI 3.3V Card 32/64 bit
|
optional
|
|
____
mandatory 32-bit pins
64-bit pins _____|
|___|
|||||||--||||||||||||||||||||||||||--||||||||||||||
+5V
TRST
+12V
TMS
TDI
+5V
INTA
INTC
+5V
RESV01
+3.3V Universal
Description
Test Logic Reset
+12 VDC
Test Mde Select
Test Data Input
+5 VDC
Interrupt A
Interrupt C
+5 VDC
Reserved VDC
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
+5V
RESV03
GND03
GND05
RESV05
RESET
+5V
GNT
GND08
RESV06
AD30
+3.3V01
AD28
AD26
GND10
AD24
IDSEL
+3.3V03
AD22
AD20
GND12
AD18
AD16
+3.3V05
FRAME
GND14
TRDY
GND15
STOP
+3.3V07
SDONE
SBO
GND17
PAR
AD15
+3.3V10
AD13
AD11
+3.3V
A48
A49
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
GND19
AD9
C/BE0
+3.3V11
AD6
AD4
GND21
AD2
AD0
+5V
+3.3V
REQ64
VCC11
VCC13
Ground
Address/Data 9
Command, Byte Enable 0
+3.3 VDC
Address/Data 6
Address/Data 4
Ground
Address/Data 2
Address/Data 0
Signal Rail +V I/O (+5 V or +3.3 V)
Request 64 bit ???
+5 VDC
+5 VDC
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
A83
A84
A85
A86
GND
C/BE[7]#
C/BE[5]#
+5V
+3.3V
PAR64
AD62
GND
AD60
AD58
GND
AD56
AD54
+5V
+3.3V
AD52
AD50
GND
AD48
AD46
GND
AD44
AD42
+5V
+3.3V
AD40
AD38
Ground
Command, Byte Enable 7
Command, Byte Enable 5
Signal Rail +V I/O (+5 V or +3.3 V)
Parity 64 ???
Address/Data 62
Ground
Address/Data 60
Address/Data 58
Ground
Address/Data 56
Address/Data 54
Signal Rail +V I/O (+5 V or +3.3 V)
Address/Data 52
Address/Data 50
Ground
Address/Data 48
Address/Data 46
Ground
Address/Data 44
Address/Data 42
Signal Rail +V I/O (+5 V or +3.3 V)
Address/Data 40
Address/Data 38
A87
A88
A89
A90
A91
A92
A93
A94
GND
AD36
AD34
GND
AD32
RES
GND
RES
Ground
Address/Data 36
Address/Data 34
Ground
Address/Data 32
Reserved
Ground
Reserved
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
-12V
TCK
GND
TDO
+5V
+5V
INTB
INTD
PRSNT1
RES
PRSNT2
GND
(OPEN) (OPEN)
GND
(OPEN) (OPEN)
RES
GND
CLK
GND
REQ
+5V
+3.3V Signal Rail
AD31
AD29
GND
AD27
AD25
+3.3V
C/BE3
AD23
GND
AD21
-12 VDC
Test Clock
Ground
Test Data Output
+5 VDC
+5 VDC
Interrupt B
Interrupt D
Reserved
+V I/O (+5 V or +3.3 V)
??
Ground or Open (Key)
Ground or Open (Key)
Reserved VDC
Reset
Clock
Ground
Request
+V I/O (+5 V or +3.3 V)
Address/Data 31
Address/Data 29
Ground
Address/Data 27
Address/Data 25
+3.3VDC
Command, Byte Enable 3
Address/Data 23
Ground
Address/Data 21
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
AD19
+3.3V
AD17
C/BE2
GND13
IRDY
+3.3V06
DEVSEL
GND16
LOCK
PERR
+3.3V08
SERR
+3.3V09
C/BE1
AD14
GND18
AD12
AD10
GND20
(OPEN) GND
(OPEN) GND
AD8
AD7
+3.3V12
AD5
AD3
GND22
AD1
VCC08
ACK64
VCC10
VCC12
B63
B64
B65
B66
RES
GND
C/BE[6]#
C/BE[4]#
(OPEN)
(OPEN)
Address/Data 19
+3.3 VDC
Address/Data 17
Command, Byte Enable 2
Ground
Initiator Ready
+3.3 VDC
Device Select
Ground
Lock bus
Parity Error
+3.3 VDC
System Error
+3.3 VDC
Command, Byte Enable 1
Address/Data 14
Ground
Address/Data 12
Address/Data 10
Ground
Ground or Open (Key)
Ground or Open (Key)
Address/Data 8
Address/Data 7
+3.3 VDC
Address/Data 5
Address/Data 3
Ground
Address/Data 1
+5 VDC
Acknowledge 64 bit ???
+5 VDC
+5 VDC
Reserved
Ground
Command, Byte Enable 6
Command, Byte Enable 4
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82
B83
B84
B85
B86
B87
B88
B89
B90
B91
B92
B93
B94
GND
AD63
AD61
+5V
AD59
AD57
GND
AD55
AD53
GND
AD51
AD49
+5V
AD47
AD45
GND
AD43
AD41
GND
AD39
AD37
+5V
AD35
AD33
GND
RES
RES
GND
+3.3V
+3.3V
+3.3V
Ground
Address/Data 63
Address/Data 61
Signal Rail +V I/O (+5 V or +3.3 V)
Address/Data 59
Address/Data 57
Ground
Address/Data 55
Address/Data 53
Ground
Address/Data 51
Address/Data 49
Signal Rail +V I/O (+5 V or +3.3 V)
Address/Data 47
Address/Data 45
Ground
Address/Data 43
Address/Data 41
Ground
Address/Data 39
Address/Data 37
Signal Rail +V I/O (+5 V or +3.3 V)
Address/Data 35
Address/Data 33
Ground
Reserved
Reserved
Ground
PCI (technical)
This section is currently based solely on the work by Mark Sokos.
This file is not intended to be a thorough coverage of the PCI standard. It is for informational purposes only,
and is intended to give designers and hobbyists an overview of the bus so that they might be able to design
their own PCI cards. Thus, I/O operations are explained in the most detail, while memory operations, which
will usually not be dealt with by an I/O card, are only briefly explained. Hobbyists are also warned that, due to
the higher clock speeds involved, PCI cards are more difficult to design than ISA cards or cards for other
slower busses. Many companies are now making PCI prototyping cards, and, for those fortunate enough to
have access to FPGA programmers, companies like Xilinx are offering PCI compliant designs which you can
use as a starting point for your own projects.
For a copy of the full PCI standard, contact:
PCI Special Interest Group (SIG)
PO Box 14070
Portland, OR 97214
1-800-433-5177
1-503-797-4207
Signal Descriptions:
AD(x)
Address/Data Lines.
CLK
Clock. 33 MHz maximum.
C/BE(x)
Command, Byte Enable.
FRAME
Used to indicate whether the cycle is an address phase or a data phase.
DEVSEL
Device Select.
IDSEL
Initialization Device Select
INT(x)
Interrupt
IRDY
Initiator Ready
LOCK
Used to manage resource locks on the PCI bus.
REQ
Request. Requests a PCI transfer.
GNT
Grant. indicates that permission to use PCI is granted.
PAR
Parity. Used for AD0-31 and C/BE0-3.
PERR
Parity Error.
RST
Reset.
SBO
Snoop Backoff.
SDONE
Snoop Done.
SERR
System Error. Indicates an address parity error for special cycles or a system error.
STOP
Asserted by Target. Requests the master to stop the current transfer cycle.
TCK
Test Clock
TDI
Test Data Input
TDO
Test Data Output
TMS
Test Mode Select
TRDY
Target Ready
TRST
Test Logic Reset
The PCI bus treats all transfers as a burst operation. Each cycle begins with an address phase followed by one
or more data phases. Data phases may repeat indefinitely, but are limited by a timer that defines the maximum
amount of time that the PCI device may control the bus. This timer is set by the CPU as part of the
configuration space. Each device has its own timer (see the Latency Timer in the configuration space).
The same lines are used for address and data. The command lines are also used for byte enable lines. This is
done to reduce the overall number of pins on the PCI connector.
The Command lines (C/BE3 to C/BE0) indicate the type of bus transfer during the address phase.
C/BE
Command Type
0000 Interrupt Acknowledge
0001 Special Cycle
file:///C|/tmp/tech/HwB/connector/bus/pci_tech.html (3 of 7) [6/15/2001 12:00:20 AM]
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
I/O Read
I/O Write
reserved
reserved
Memory Read
Memory Write
reserved
reserved
Configuration Read
Configuration Write
Multiple Memory Read
Dual Address Cycle
Memory-Read Line
Memory Write and Invalidate
The three basic types of transfers are I/O, Memory, and Configuration.
___|
___
|___|
___
|___|
___
|___|
___
|___|
___
|___|
_______
FRAME
|___
_________
|_________________________________|
AD
C/BE
______ _______________________________
-------<______><_______________________________>--Command
Byte Enable Signals
____________
IRDY
___
|_________________________________|
_____________
TRDY
___
|________________________________|
______________
DEVSEL
___
|_______________________________|
PCI transfer cycle, 4 data phases, no wait states. Data is transferred on the rising edge of CLK.
[1]
[2]
[3]
file:///C|/tmp/tech/HwB/connector/bus/pci_tech.html (4 of 7) [6/15/2001 12:00:20 AM]
___
CLK
___
___|
___
|___|
___
|___|
|___|
___
|___|
___
|___|
___
|___|
___
|___|
_______
FRAME
AD
C/BE
|__
_________
|________________________________________________|
A
B
C
______
______________ ______ _____________
-------<______>---------<______________><______><_____________>--Address
Data1
Data2
Data3
______ ______________________________________________
-------<______><______________________________________________>--Command
Byte Enable Signals
Wait
_____
____________
IRDY
|__________________________________|
Wait
______________________
TRDY
___
|_______|
Wait
______
|_______|
___
|_______________________|
______________
DEVSEL
___
|______________________________________________|
PCI transfer cycle, with wait states. Data is transferred on the rising edge of CLK at points labelled A, B, and
C.
Bus Cycles:
Interrupt Acknowledge (0000)
The interrupt controller automatically recognizes and reacts to the INTA (interrupt acknowledge) command.
In the data phase, it transfers the interrupt vector to the AD lines.
Description
Processor Shutdown
Processor Halt
x86 Specific Code
Reserved
Unit ID
| Manufacturer ID
Status
| Command
Class Code
| Revision
BIST | Header | Latency | CLS
Base Address Register
Reserved
Reserved
Expansion ROM Base Address
Reserved
Reserved
MaxLat|MnGNT
| INT-pin | INT-line
available for PCI unit
CPU.
Bus Arbitration:
This section is under construction.
PCI BIOS:
This section is under construction.
Contributor: Joakim gren, Mark Sokos
Sources:
Mark Sokos PCI page
"Inside the PCI Local Bus" by Guy W. Kendall, Byte, February 1994 v 19 p. 177-180
"The Indispensible PC Hardware Book" by Hans-Peter Messmer, ISBN 0-201-8769-3
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-08
PCMCIA
PCMCIA=Personal Computer Memory Card International Association.
Name
GND
D3
D4
D5
D6
D7
/CE1
A10
/OE
A11
A9
A8
A13
A14
/WE:/P
/READY:/IREQ
VCC
VPP1
A16
A15
Dir
Description
Ground
Data 3
Data 4
Data 5
Data 6
Data 7
Card Enable 1
Address 10
Output Enable
Address 11
Address 9
Address 8
Address 13
Address 14
Write Enable : Program
Ready : Busy (IREQ)
+5V
Programming Voltage (EPROM)
Address 16
Address 15
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
A12
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
/WP:/IOIS16
GND
GND
/CD1
D11
D12
D13
D14
D15
/CE2
/VS1
/IORD
/IOWR
A17
A18
A19
A20
A21
VCC
VPP2
A22
A23
A24
A25
/VS2
RESET
?
?
?
?
Address 12
Address 7
Address 6
Address 5
Address 4
Address 3
Address 2
Address 1
Address 0
Data 0
Data 1
Data 2
Write Protect : IOIS16
Ground
Ground
Card Detect 1
Data 11
Data 12
Data 13
Data 14
Data 15
Card Enable 2
Refresh
I/O Read
I/O Write
Address 17
Address 18
Address 19
Address 20
Address 21
+5V
Programming Voltage 2 (EPROM)
Address 22
Address 23
Address 24
Address 25
RFU
RESET
59
60
61
62
63
64
65
66
67
68
/WAIT
?
/INPACK
?
/REG
/BVD2:SPKR
/BVD1:STSCHG
D8
D9
D10
/CD2
GND
WAIT
Register Select
Battery Voltage Detect 2 : SPKR
Battery Voltage Detect 1 : STSCHG
Data 8
Data 9
Data 10
Card Detect 2
Ground
SSFDC
SSFDC=Solid State Floppy Disk Card.
SUN SBus
96 PIN UNKNOWN FEMALE CONNECTOR (Fujitsu FCN 234P096-G/Y) at the Motherboard
96 PIN UNKNOWN MALE CONNECTOR (Fujitsu FCN 234P096-G) at the Motherboard
Available on the SUN SPARCengine 5 motherboard
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Name
GND
sb_br*
sb_sel*
sb_irql*
sb_d(0)
sb_d(2)
sb_d(4)
sb_irq2*
sb_d(6)
sb_d(8)
sb_d(10)
sb_irq3*
sb_d(12)
sb_d(14)
sb_d(16)
sb_irq4*
sb_d(19)
sb_d(21)
sb_d(23)
sb_irq5*
sb_d(25)
sb_d(27)
sb_d(29)
sb_irq6*
sb_d(31)
sb_siz(0)
sb_siz(2)
sb_irq7*
Description
Ground
sb_br
sb_sel
?
Data bit 0
Data bit 2
Data bit 4
Interrupt Request 2
Data bit 6
Data bit 8
Data bit 10
Interrupt Request 3
Data bit 12
Data bit 14
Data bit 16
Interrupt Request 4
Data bit 19
Data bit 21
Data bit 23
Interrupt Request 5
Data bit 25
Data bit 27
Data bit 29
Interrupt Request 6
Data bit 31
sb_siz(0
sb_siz(2
Interrupt Request 7
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
sb_a(0)
sb_a(2)
sb_a(4)
sb_merr*
sb_a(6)
sb_a(8)
sb_a(10)
sb_err*
sb_pa(12)
sb_pa(14)
sb_pa(16)
sb_ack8*
sb_pa(18)
sb_pa(20)
sb_pa(22)
sb_ack32*
sb_pa(24)
sb_pa(26)
N/C
-12V
sb_clk
sb_bg*
sb_as*
GND
sb_d(1)
sb_d(3)
sb_d(5)
+5V
sb_d(7)
sb_d(9)
sb_d(11)
GND
sb_d(13)
sb_d(15)
sb_d(17)
+5V
sb_d(18)
sb_d(20)
Address bit 0
Address bit 2
Address bit 4
sb_merr
Address bit 6
Address bit 8
Address bit 10
sb_err
Address bit 12
Address bit 14
Address bit 16
sb_ack8
Address bit 18
Address bit 20
Address bit 22
sb_ack32
Address bit 24
Address bit 26
Not connected
-12 VDC
Clock
sb_bg
sb_as
Ground
Data bit 1
Data bit 3
Data bit 5
+5 VDC
Data bit 7
Data bit 9
Data bit 11
Ground
Data bit 13
Data bit 15
Data bit 17
+5 VDC
Data bit 18
Data bit 20
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
sb_d(22)
GND
sb_d(24)
sb_d(26)
sb_d(28)
+5V
sb_d(30)
sb_siz(1)
sb_rd
GND
sb_a(1)
sb_a(3)
sb_a(5)
+5V
sb_a(7)
sb_a(9)
sb_a(11)
GND
sb_pa(13)
sb_pa(15)
sb_pa(17)
+5V
sb_pa(19)
sb_pa(21)
sb_pa(23)
GND
sb_pa(25)
sb_pa(27)
sb_reset*
+12V
Data bit 22
Ground
Data bit 24
Data bit 26
Data bit 28
+5 VDC
Data bit 30
sb_siz(1
sb_rd
Ground
Address bit 1
Address bit 3
Address bit 5
+5 VDC
Address bit 7
Address bit 9
Address bit 11
Ground
Address bit 13
Address bit 15
Address bit 17
+5 VDC
Address bit 19
Address bit 21
Address bit 23
Ground
Address bit 25
Address bit 27
Reset
+12 VDC
SmallPCI
PCI=Peripheral Component Interconnect.
SmallPCI is a version of PCI adapted for small computers and PDAs.
Unibus
Available on the old Digital PDP-11.
+------------//--------+
|AA1 AB1 AC1 // AU1 AV1|
|AA2 AB2 AC2 // AU2 AV2|
+------------//--------+
+------------//--------+
|BA1 BB1 BC1 // BU1 BV1|
|BA2 BB2 BC2 // BU2 BV2|
+------------//--------+
Name
/INIT
POWER(+5v)
/INTR
GROUND
/D00
GROUND
/D02
/D01
/D04
/D03
/D06
/D05
/D08
/D07
/D10
/D09
/D12
/D11
/D14
/D13
AM1
AM2
AN1
AN2
AP1
AP2
AR1
AR2
AS1
AS2
AT1
AT2
AU1
AU2
AV1
AV2
/PA
/D15
GROUND
/PB
GROUND
/BBSY
GROUND
/SACK
GROUND
/NPR
GROUND
/BR7
NPG
/BR6
BG7
GROUND
BA1
BA2
BB1
BB2
BC1
BC2
BD1
BD2
BE1
BE2
BF1
BF2
BH1
BH2
BJ1
BJ2
BK1
BK2
BL1
BL2
BM1
BG6
POWER(+5v)
BG5
GROUND
/BR5
GROUND
GROUND
/BR4
GROUND
BG4
/ACLO
/DCLO
/A01
/A00
/A03
/A02
/A05
/A04
/A07
/A06
/A09
BM2
BN1
BN2
BP1
BP2
BR1
BR2
BS1
BS2
BT1
BT2
BU1
BU2
BV1
BV2
/A08
/A11
/A10
/A13
/A12
/A15
/A14
/A17
/A16
GROUND
/C1
/SSYN
/CO
/MSYN
GROUND
USB A
USB B
Series "A" plugs are used towards the host system and series "B" plugs are used towards the USB device.
Pin
1
2
3
4
Name
VBUS
DD+
GND
Description
+5 VDC
Data Data +
Ground
Features:
True Plug'n'Play.
Hot plug and unplug
Low cost
Easy of use
127 physical devices
Low cost cables and connectors
Bandwidth:
High speed: 480 Mbps speed (in USB 2.0 and above)
Full speed: 12 Mbps speed (requires shielded cable)
Low speed: 1.5 Mbps speed (non-shielded cable)
Definitions:
USB Host = The computer, only one host per USB system.
USB Device = A hub or a Function.
Power usage:
Bus-powered hubs: Draw Max 100 mA at power up and 500 mA normally.
Self-powered hubs: Draw Max 100 mA, must supply 500 mA to each port.
Low power, bus-powered functions: Draw Max 100 mA.
High power, bus-powered functions: Self-powered hubs: Draw Max 100 mA, must supply 500 mA to
each port.
Self-powered functions: Draw Max 100 mA.
Suspended device: Max 0.5 mA
Voltage:
Supplied voltage by a host or a powered hub ports is between 4.75 V and 5.25 V.
Maximum voltage drop for bus-powered hubs is 0.35 V from it's host or hub to the hubs output
port.
All hubs and functions must be able to send configuration data at 4.4 V, but only low-power
functions need to be working at this voltage.
Normal operational voltage for functions is minimum 4.75 V.
Shielding:
Shield should only be connected to Ground at the host. No device should connect Shield to Ground.
Cable:
Shielded:
Data: 28 AWG twisted
Power: 28 AWG - 20 AWG non-twisted
Non-shielded:
Data: 28 AWG non-twisted
Power: 28 AWG - 20 AWG non-twisted
Power Gauge
28
26
24
22
20
Max length
0.81 m
1.31 m
2.08 m
3.33 m
5.00 m
Cable colors:
Pin
1
2
3
4
Name
VBUS
DD+
GND
Cable color
Red
White
Green
Black
Description
+5 VDC
Data Data +
Ground
(at
the card)
Name
D1
D3
GND
D5
D7
D9
D11
D13
D15
Description
Data 1
Data 3
Ground
Data 5
Data 7
Data 9
Data 11
Data 13
Data 15
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
GND
D17
Vcc
D19
D21
D23
D25
GND
D27
D29
D31
A30
A28
A26
GND
A24
A22
VCC
A20
A18
A16
A14
A12
A10
A8
GND
A6
A4
WBACK#
BE0#
VCC
BE1#
BE2#
GND
BE3#
ADS#
A48 LRDY#
Ground
Data 17
+5 VDC
Data 19
Data 21
Data 23
Data 25
Ground
Data 27
Data 2
Data 31
Address 30
Address 28
Address 26
Ground
Address 24
Address 22
+5 VDC
Address 20
Address 18
Address 16
Address 14
Address 12
Address 10
Address 8
Ground
Address 6
Address 4
Write Back
Byte Enable 0
+5 VDC
Byte Enable 1
Byte Enable 2
Ground
Byte Enable 3
Address Strobe
Local Ready
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
LDEV
LREQ
GND
LGNT
VCC
ID2
ID3
ID4
LKEN#
LEADS#
Local Device
Local Request
Ground
Local Grant
+5 VDC
Identification 2
Identification 3
Identification 4
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
D0
D2
D4
D6
D8
GND
D10
D12
VCC
D14
D16
D18
D20
GND
D22
D24
D26
D28
D30
VCC
A31
GND
A29
A27
A25
A23
A21
Data 0
Data 2
Data 4
Data 6
Data 8
Ground
Data 10
Data 12
+5 VDC
Data 14
Data 16
Data 18
Data 20
Ground
Data 22
Data 24
Data 26
Data 28
Data 30
+5 VDC
Address 31
Ground
Address 29
Address 27
Address 25
Address 23
Address 21
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
A19
GND
A17
A15
VCC
A13
A11
A9
A7
A5
GND
A3
A2
n/c
RESET#
DC#
M/IO#
W/R#
Address 19
Ground
Address 17
Address 15
+5 VDC
Address 13
Address 11
Address 9
Address 7
Address 5
Ground
Address 3
Address 2
Not connected
Reset
Data/Command
Memory/IO
Write/Read
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
RDYRTN#
GND
IRQ9
BRDY#
BLAST#
ID0
ID1
GND
LCLK
VCC
LBS16#
Ready Return
Ground
Interrupt 9
Burst Ready
Burst Last
Identification 0
Identification 1
Ground
Local Clock
+5 VDC
Local Bus Size 16
Signal Descriptions
A2-A31
Address Bus
ADS
Address Strobe
BE0-BE3
Byte Enable. Indicates that the 8 data lines corresponding to each signal will deliver valid data.
BLAST
Burst Last. Indicates a VLB Burst Cycle, which will complete with *BRDY. The VLB Burst cycle
consists of an address phase followed by four data phases.
BRDY
Burst Ready. Indicates the end of the current burst transfer.
D0-D31
Data Bus. Valid bytes are indicated by *BE(x) signals.
D/C
Data/Command. Used with M/IO and W/R to indicate the type of cycle.
M/IO
0
0
0
0
1
1
1
1
D/C
0
0
1
1
0
0
1
1
W/R
0
1
0
1
0
1
0
1
INTA sequence
Halt/Special (486)
I/O Read
I/O Write
Instruction Fetch
Halt/Shutdown (386)
Memory Read
Memory Write
ID0-ID4
Identification Signals.
ID0
0
0
0
0
1
1
1
1
ID1
0
0
1
1
0
0
1
1
ID4
0
1
0
1
0
1
0
1
CPU
(res)
(res)
486
486
386
386
(res)
486
Bus Width
Burst
16/32
16/32
16/32
16/32
Burst Possible
Read Burst
None
None
16/32/64
Read/Write Burst
IRQ9
Interrupt Request. Connected to IRQ9 on ISA bus. This allows standalone VLB adapters (not connected
to ISA portion of the bus) to have one IRQ.
LEADS
Local Enable Address Strobe. Set low by VLB master (not CPU). Also used for cache invalidation
signal.
LBS16
Local Bus Size 16. Used by slave device to indicate that it has a transfer width of only 16 bits.
LCLK
Local Clock. Runs at the same frequency as the cpu, up to 50 MHz. 66 MHz is allowed for on-board
devices.
LDEV
Local Device: When appropriate address and M/IO signals are present on the bus, the VLB device must
pull this line low to indicate that it is a VLB device. The VLB controller will then use the VLB bus for
the transfer.
LRDY
Local Ready. Indicates that the VLB device has completed the cycle. This signal is only used for single
cycle transfers. *BRDY is used for burst transfers.
LGNT
Local Grant. Indicates that an *LREQ signal has been granted, and control is being transferred to the new
VLB master.
LREQ
Local Request. Used by VLB Master to gain control of the bus.
M/IO
Memory/IO. See D/C for signal description.
RDYRTN
Ready Return. Indicates VLB cycle has been completed. May precede LRDY by one cycle.
RESET
Reset. Resets all VLB devices.
WBACK
Write Back.
BE4-BE7
Byte Enable. Indicates which bytes are valid (similar to BE0-BE3).
D32-D63
Upper 32 bits of data bus. Multiplexed with address bus.
LBS64
Local Bus Size 64 bits. Used by VLB Master to indicate that it desires a 64 bit transfer.
W/R
Write/Read. See D/C for signal description.
___|
Data
Phase
_______
|_______|
____
*ADS
_______
|_______|
|_______
______________________________________
|_______|
A2-A31
D34-D63
_______________ _______________
----<_______________><_______________>------------Address
Data D34-D63
_______________ _______________
D/C
----<_______________><_______________>------------M/IO, W/R
M/IO, W/R
Data D32-33
_____
*LDEV
_____________________________
|_______________|
_____
*LBS64
_____________________________
*ACK64
|_______________|
______
_____________________________
|______________|
D0-D31
_______________
--------------------<_______________>------------_____________________
LRDY
_____________
|______________|
VME64x
P1/J1 (Required)
Pin
z1
z2
z3
z4
z5
z6
z7
z8
z9
z10
z11
z12
z13
z14
z15
z16
Name
MPR
GND
MCLK
GND
MSD
GND
MMD
GND
MCTL
GND
RESP*
GND
RsvBus
GND
RsvBus
GND
z17
z18
z19
z20
z21
z22
z23
z24
z25
z26
z27
z28
z29
z30
z31
z32
RsvBus
GND
RsvBus
GND
RsvBus
GND
RsvBus
GND
RsvBus
GND
RsvBus
GND
RsvBus
GND
RsvBus
GND
b21 SERA
b22 SERB
Pin
d1
d2
d3
d4
d5
d6
d7
d8
d9
d10
d11
d12
d13
d14
d15
d16
d17
d18
d19
Name
VPC
GND
+V1
+V2
RsvU
-V1
-V2
RsvU
GAP*
GA0*
GA1*
+3.3V
GA2*
+3.3V
GA3*
+3.3V
GA4*
+3.3V
RsvBus
d20
d21
d22
d23
d24
d25
d26
d27
d28
d29
d30
d31
d32
+3.3V
RsvBus
+3.3V
RsvBus
+3.3V
RsvBus
+3.3V
LI/I*
+3.3V
LI/O*
+3.3V
GND
VPC
P2/J2 (Optional)
Pin
z1
z2
z3
z4
z5
z6
z7
z8
z9
z10
z11
z12
z13
z14
z15
z16
z17
z18
z19
z20
z21
Name
UsrDef
GND
UsrDef
GND
UsrDef
GND
UsrDef
GND
UsrDef
GND
UsrDef
GND
UsrDef
GND
UsrDef
GND
UsrDef
GND
UsrDef
GND
UsrDef
z22
z23
z24
z25
z26
z27
z28
z29
z30
z31
z32
GND
UsrDef
GND
UsrDef
GND
UsrDef
GND
UsrDef
GND
UsrDef
GND
b3 RETRY*
Pin
d1
d2
d3
d4
d5
d6
d7
d8
d9
d10
d11
d12
d13
d14
d15
d16
d17
d18
d19
d20
d21
d22
d23
d24
d25
Name
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
d26
d27
d28
d29
d30
d31
d32
UsrDef
UsrDef
UsrDef
UsrDef
UsrDef
GND
VPC
*) Active Low
Contributor: Joakim gren, Kevin D. Plymel
Source:
VMEbus Connector Pin Assignment at VITA's VMEbus FAQ
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
VMEbus
P1/J1 (Required)
Pin
a1
a2
a3
a4
a5
a6
a7
a8
a9
a10
a11
a12
a13
a14
a15
a16
a17
Name
D00
D01
D02
D03
D04
D05
D06
D07
GROUND
SYSCLK
GROUND
DS1*
DS0*
WRITE*
GROUND
DTACK*
GROUND
a18
a19
a20
a21
a22
a23
a24
a25
a26
a27
a28
a29
a30
a31
a32
AS*
GROUND
IACK*
IACKIN*
IACKOUT*
AM4
A07
A06
A05
A04
A03
A02
A01
-12V
+5V
Pin
b1
b2
b3
b4
b5
b6
b7
b8
b9
b10
b11
b12
b13
b14
b15
b16
b17
b18
b19
b20
b21
b22
Name
BBSY*
BCLR*
ACFAIL*
BG0IN*
BG0OUT*
BG1IN*
BG1OUT*
BG2IN*
BG2OUT*
BG3IN*
BG3OUT*
BR0*
BR1*
BR2*
BR3*
AM0
AM1
AM2
AM3
GROUND
SERCLK*
SERDAT*
b23
b24
b25
b26
b27
b28
b29
b30
b31
b32
GROUND
IRQ7*
IRQ6*
IRQ5*
IRQ4*
IRQ3*
IRQ2*
IRQ1*
+5V STDBY
+5V
Pin
c1
c2
c3
c4
c5
c6
c7
c8
c9
c10
c11
c12
c13
c14
c15
c16
c17
c18
c19
c20
c21
c22
c23
c24
c25
c26
c27
Name
D08
D09
D10
D11
D12
D13
D14
D15
GROUND
SYSFAIL*
BERR*
SYSRESET*
LWORD*
AM5
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
c28
c29
c30
c31
c32
A10
A09
A08
+12V
+5V
P2/J2 (Optional)
Pin
b1
b2
b3
b4
b5
b6
b7
b8
b9
b10
b11
b12
b13
b14
b15
b16
b17
b18
b19
b20
b21
b22
b23
b24
b25
b26
b27
b28
b29
Name
+5v
GROUND
RESERVED
A24
A25
A26
A27
A28
A29
A30
A31
GROUND
+5V
D16
D17
D18
D19
D20
D21
D22
D23
GROUND
D24
D25
D26
D27
D28
D29
D30
b30 D31
b31 GROUND
b32 +5V
*) Active Low
Contributor: Joakim gren, Kevin D. Plymel, And many more!
Source:
VMEbus Connector Pin Assignment at VITA's VMEbus FAQ
comp.arch.bus.vmebus FAQ by Robert J. Boys
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
VME64x (technical)
Signal Descriptions:
A01 - A31
Address lines [A01 - A31] carry a binary address.
AM0 - AM5
The address modifier code [AM0 - AM5] is a 'tag' that indicates the type of VMEbus cycle in progress.
BG0IN* - BG3IN*
BG0OUT* - BG3OUT*
The bus grant signals [BG0IN* - BG3IN* and BG0OUT* - BG3OUT*] are part of the bus grant daisy
chain and are driven by arbiters and requesters. The slot 01 arbiter asserts a bus grant in response to a bus
request on the same level [BR0* - BR3*]. The bus grant daisy-chain starts at the slot 01 system
controller and propagates from module to module until it reaches the module that initially requested the
bus. Each VMEbus module has a bus grant input and a bus grant output. They are standard totem-pole
class signals.
BR0* - BR3*
Bus requests [BR0* - BR3*] are asserted by a requester whenever its master or interrupt han-dler needs
the bus. Before accepting the bus, the master waits until the arbiter grants the bus by way of the bus grant
daisy-chain [BG0IN* - BG3IN*]. They are open-collector class signals.
D00-D31
Data bus [D00-D31] is driven by masters, slaves or interrupters. These are bi-directional sig-nals and are
used for data transfers. Different portions of the data bus are used de-pending upon the state of DS0*,
DS1*, A01 and LWORD* pins. They are standard three-state signals. The data lines can also be used to
transfer a portion of the address during MD32, MBLT and 2eVME cycles.
DS0*, DS1*
Data strobes DS0* and DS1* are driven by masters and interrupt handlers. These sig-nals serve not only
to qualify data, but also to indicate the size and position of the data transfer. When combined with
LWORD* and A01, the data strobes indicate the size and type of data transfer. DS0* - DS1* are high
current three-state class signals.
DTACK*
Data transfer acknowledge [DTACK*] is driven by slaves or interrupters. During write cycles DTACK*
is asserted by a slave after it has latched data. During read and inter-rupt acknowledge cycles, DTACK*
is asserted by a slave after data is placed onto the bus. DTACK* can be an open-collector or a high
current three-state class signal.
GA0* - GA4*
The geographical address [GA0*-GA4*] is a binary code that indicates the slot number of the backplane.
They are open collector signals, and were added to the 160 pin P1/J1 connector in the VME64x
specification.
GAP*
The geographical address parity [GAP*] is tied high or floating, depending upon the parity of the
geographical address lines [GA0*-GA4*]. It is an open collector signal, and was added to the 160 pin
P1/J1 connector in the VME64x specification.
GND
Ground [GND] is used both as a signal reference and a power return path.
IACK*
Interrupt acknowledge [IACK*] is driven by interrupt handlers in response to interrupt re-quests. It is
connected to IACKIN* at slot 01 (on the backplane), and used by the IACK* daisy-chain driver to start
propagation of the [IACKIN* - IACKOUT*] daisy-chain. IACK* can be either an open-collector or a
standard three-state class signal.
IACKIN*, IACKOUT*
The interrupt acknowledge daisy chain [IACKIN* - IACKOUT*] is driven by the IACK* daisy-chain
driver. These signals are used both to indicate that an interrupt acknowledge cycle is in progress, and to
determine which interrupters should return a STATUS/ID. They are standard totem-pole class signals.
IRQ1*-IRQ7*
Priority interrupt requests [IRQ1*-IRQ7*] are asserted by interrupters. Level seven is the high-est
priority, and level one the lowest. They are open-collector class signals.
LI/I*
The live insertion input [LI/I*] signal is used to carry hot swap (live insertion) control information. It is a
three state driven signal and was added to the 160 pin P1/J1 connector in the VME64x specification.
LI/O*
The live insertion output [LI/O*] signal is used to carry hot swap (live insertion) control information. It is
a three state driven signal and was added to the 160 pin P1/J1 connector in the VME64x specification.
LWORD*
Long word [LWORD*] is driven by masters. It is used in conjunction with A01, DS0* and DS1* to
indicate the size of the current data transfer. LWORD* is a standard three-state class signal. During
64-bit address transfers, LWORD* doubles as address bit A00. During 64-bit data transfers, LWORD*
doubles as a data bit.
RESERVED
The RESERVED signal pin is obsolete and is no longer used. Under the IEEE 1014-1987 version of the
bus specification there was a single reserved pin. This pin was redefined under VME64 as the RETRY*
pin. The VME64x specification uses the names RsvB and RsvU for reserved pins.
RESP*
The response [RESP*] signal is used to carry the information as defined by the 2eVME protocol. It was
added to the 160 pin P1/J1 connector in the VME64x specification.
RsvB
The reserved/bused [RsvB] signal should not be used. VME64x backplanes must bus and terminate this
signal. It was added to the 160 pin P1/J1 connector in the VME64x specification.
RsvU
The reserved/unbused [RsvU] signal should not be used. VME64x backplanes must not bus or terminate
this signal. It was added to the 160 pin P1/J1 connector in the VME64x specification.
RETRY*
[RETRY*], together with [BERR*], can be asserted by a slave to postpone a data transfer. The master
must then attempt the cycle again at a later time. The retry cycle prevents deadlock (deadly embrace)
conditions in bus-to-bus links and sec-ondary buses. RETRY* is a standard three-state signal. The
[RETRY*] signal was added in the ANSI/VITA 1-1994 (VME64) version of the bus spec-ification. This
pin was RESERVED in earlier versions. However, boards that support [RETRY*] should work just fine
with older backplanes, as they were required to bus and terminate this signal line.
SERA, SERB
The [SERA] and [SERB] signals are used for an (optional) serial bus such as the AUTOBAHN (IEEE
1394) or VMSbus. Under the ANSI/VITA 1-1994 (VME64) bus specification, these pins can be used for
any user defined serial bus. Earlier versions of the VMEbus specification defined these pins as
[SERCLK] and [SERDAT*], which were originally intended for a serial bus called VMSbus. However,
they were rarely used for that purpose.
SERCLK, SERDAT*
The [SERCLK] and [SERDAT*] signals were made obsolete under the ANSI/VITA 1-1994 (VME64)
bus specification. Refer to [SERA] and [SERB] for more details.
SYSCLK
16 MHz utility clock [SYSCLK] is driven by the slot 01 system controller. This clock can be used for
any purpose, and has no timing relationship to other VMEbus signals. SYSCLK* is a high current
totem-pole class signal.
SYSFAIL*
System fail [SYSFAIL*] can be asserted or monitored by any module. It indicates that a failure has
occurred in the system. Implementation of [SYSFAIL*] is user de-fined, and its use is optional.
SYSFAIL* is an open-collector class signal.
SYSRESET*
System reset [SYSRESET*] can be driven by any module and indicates that a reset (such as power-up) is
in progress. SYSRESET* is an open-collector class signal.
UsrDef, UD
Pins that are user defined [specified as 'UsrDef' or 'UD'] can be specified by the user. Generally, they are
routed directly through the backplane so that they can be connected to cables or to rear I/O transition
modules.
VPC
Voltage pre-charge [VPC] pins forma a 'make first / break last' contact. They are intended to be used as
pre-charge power sources for live insertion logic. These pins were added to the 160 pin P1/J1 and P2/J2
connectors in the VME64x specification. The VPC pins are connected to the +5 VDC power supply on
VME64x backplanes. These pins may also be used as additional +5 VDC power pins in boards that do
not support live insertion.
WRITE*
The read / write signal [WRITE*] is driven by masters. It indicates the direction of data transfer over the
bus. It is asserted during a write cycle and negated during a read cycle. WRITE* is a stan-dard three-state
class signal.
+5V STDBY
[+5V STDBY] is an optional +5 VDC standby power supply. This power pin is often connected to a
rechargable battery. This eliminates the need for individual batteries on VMEbus modules. Individual
batteries are often used for real time clock and static RAM chips.
+3.3 V
Main +3.3 VDC power source. These pins were added to the 160 pin P1/J1 connector in the VME64x
specification.
+5 VDC
+12 VDC, -12 VDC
The main system power supplies are [+5 VDC], [+12 VDC] and [-12 VDC].
Contributor: Joakim gren, Kevin D. Plymel
Source:
VMEbus Connector Pin Assignment at VITA's VMEbus FAQ
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-06
Zorro II
A500
X
X
X
X
X
X
X
X
X
10 X
11 X
12
13
14
15
16
17
18
19
20
X
X
X
X
X
X
X
X
X
A1000
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A2000
X
X
X
X
X
X
X
X
A2000B
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
21 X
22 X
X
X
X
X
X
X
X
Name
GND
GND
GND
GND
+5V
+5V
n/c
-5V
n/c
28CLOCK
+12V
n/c
/COPCFG
CONFIG IN, Grounded
GND
/C3
CDAC
/C1
/OVR
RDY
/INT2
/PALOPE
n/c
/BOSS
A5
/INT6
Description
Ground
Ground
Ground
Ground
+5 Volts DC
+5 Volts DC
-5 Volts DC
28MHz Clock
+12 Volts DC
Configuration Out
Ground
C3 Clock
Clock
C1 Clock
Ready
Interrupt 2
Address 5
Interrupt 6
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A6
A4
GND
A3
A2
A7
A1
A8
FC0
A9
FC1
A10
FC2
A11
GND
A12
A13
/IPL0
A14
/IPL1
A15
/IPL2
A16
/BEER
A17
/VPA
GND
ECLK
/VMA
A18
RST
A19
/HLT
A20
A22
A21
A23
/BR
Address 6
Address 4
Ground
Address 3
Address 2
Address 7
Address 1
Address 8
Processor status 0
Address 9
Processor status 1
Address 10
Processor status 2
Address 11
Ground
Address 12
Address 13
Address 14
Address 15
Address 16
Bus Error
Address
Ground
E Clock
Address 18
Reset
Address 19
Halt
Address 20
Address 22
Address 21
Address 23
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
/CBR
GND
/BGACK
D15
/BG
/CBG
D14
/DTACK
D13
R/W
D12
/LDS
D11
/UDS
GND
/AS
D0
D10
D1
D9
D2
D8
D3
D7
D4
D6
GND
D5
Ground
Data 15
Data 14
Data 13
Read/Write
Data 12
Data 11
Ground
Data 0
Data 10
Data 1
Data 9
Data 2
Data 8
Data 3
Data 7
Data 4
Data 6
Ground
Data 5
Zorro II/III
Physical
Name
Ground
Ground
Ground
Ground
+5VDC
+5VDC
/OWN
-5VDC
/SLAVEn
+12VDC
/CFGOUTn
/CFGINn
Ground
/C3
CDAC
/C1
/CINH
/MTCR
/INT2
-12VDC
A5
/INT6
A6
A4
Ground
Zorro II
Name
Ground
Ground
Ground
Ground
+5VDC
+5VDC
/OWN
-5VDC
/SLAVEn
+12VDC
/CFGOUTn
/CFGINn
Ground
/C3 Clock
CDAC Clock
/C1 Clock
/OVR
XRDY
/INT2
-12VDC
A5
/INT6
A6
A4
Ground
Zorro III
Address Phase
Ground
Ground
Ground
Ground
+5VDC
+5VDC
/OWN
-5VDC
/SLAVEn
+12VDC
/CFGOUTn
/CFGINn
Ground
/C3 Clock
CDAC Clock
/C1 Clock
/CINH
/MTCR
/INT2
-12VDC
A5
/INT6
A6
A4
Ground
Zorro III
Data Phase
Ground
Ground
Ground
Ground
+5VDC
+5VDC
/OWN
-5VDC
/SLAVEn
+12VDC
/CFGOUTn
/CFGINn
Ground
/C3 Clock
CDAC Clock
/C1 Clock
/CINH
/MTCR
/INT2
-12VDC
A5
/INT6
A6
A4
Ground
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
A3
A2
A7
/LOCK
AD8
FC0
AD9
FC1
AD10
FC2
AD11
Ground
AD12
AD13
Reserved
AD14
Reserved
AD15
Reserved
AD16
/BERR
AD17
/MTACK
Ground
E Clock
/DS0
AD18
/RESET
AD19
/HLT
AD20
AD22
AD21
AD23
/BRn
Ground
/BGACK
AD31
A3
A2
A7
A1
A8
FC0
A9
FC1
A10
FC2
A11
Ground
A12
A13
(/EINT7)
A14
(/EINT5)
A15
(/EINT4)
A16
/BERR
A17
(/VPA)
Ground
E Clock
(/VMA)
A18
/RST
A19
/HLT
A20
A22
A21
A23
/BRn
Ground
/BGACK
D15
A3
A2
A7
/LOCK
A8
FC0
A9
FC1
A10
FC2
A11
Ground
A12
A13
Reserved
A14
Reserved
A15
Reserved
A16
/BERR
A17
/MTACK
Ground
E Clock
/DS0
A18
/RESET
A19
/HLT
A20
A22
A21
A23
/BRn
Ground
/BGACK
A31
A3
A2
A7
/LOCK
D0
FC0
D1
FC1
D2
FC2
D3
Ground
D4
D5
Reserved
D6
Reserved
D7
Reserved
D8
/BERR
D9
/MTACK
Ground
E Clock
/DS0
D10
/RESET
D11
/HLT
D12
D14
D13
D15
/BRn
Ground
/BGACK
D31
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
/BGn
AD30
/DTACK
AD29
READ
AD28
/DS2
AD27
/DS3
Ground
/CCS
SD0
AD26
SD1
AD25
SD2
AD24
SD3
SD7
SD4
SD6
Ground
SD5
Ground
Ground
Ground
Ground
SenseZ3
7M
DOE
/IORST
/BCLR
Reserved
/FCS
/DS1
Ground
Ground
/BGn
D14
/DTACK
D13
READ
D12
/LDS
D11
/UDS
Ground
/AS
D0
D10
D1
D9
D2
D8
D3
D7
D4
D6
Ground
D5
Ground
Ground
Ground
Ground
Ground
E7M
DOE
/BUSRST
/GBG
(/EINT1)
No Connect
No Connect
Ground
Ground
/BGn
A30
/DTACK
A29
READ
A28
/DS2
A27
/DS3
Ground
/CCS
Reserved
A26
Reserved
A25
Reserved
A24
Reserved
Reserved
Reserved
Reserved
Ground
Reserved
Ground
Ground
Ground
Ground
SenseZ3
7M
DOE
/IORST
/BCLR
Reserved
/FCS
/DS1
Ground
Ground
/BGn
D30
/DTACK
D29
READ
D28
/DS2
D27
/DS3
Ground
/CCS
D16
D26
D17
D25
D18
D24
D19
D23
D20
D22
Ground
D21
Ground
Ground
Ground
Ground
SenseZ3
7M
DOE
/IORST
/BCLR
Reserved
/FCS
/DS1
Ground
Ground
Source:
Amiga 4000 User's Guide from Commodore
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
Description
Ground
Reserved (or GeoPort Clock)
Ground
Reserved (or LLC_OUT)
Ground
Reserved (or PXQ_OUT)
Ground
Reserved (or VS_OUT)
Ground
Reserved (or HS_OUT)
UV bit 7
UV bit 6
UV bit 5
UV bit 4
UV bit 3
UV bit 2
UV bit 1
UV bit 0
Y bit 7
Y bit 6
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
Y bit 5
Y bit 4
Y bit 3
Y bit 2
Y bit 1
Y bit 0
Ground
Line-locked clock (LLC) in
Ground
Clock reference qualifier (PXQ) In
Ground
Vertical sync (VS) In
Ground
Reserved (or Horizontal Sync (HS) In)
Ground
HRef In
Ground
DIR * (or FLD)
IIC Data *
IIC Clock
Ground
Analog audio input left
Analog audio input common
Analog audio input right
Ground
Digital audio input
Ground
Digital audio output
Ground
Digital audio clock
Ground
Digital audio sync
Ground
S video input C component
Video input ground
S video input Y component
Video input ground
Reserved
59 Reserved
60 Reserved
Contributor: Joakim gren
Source:
Apple Tech Info Library 18547: Power Macintosh 7200, 7500, 8500, 9500 Pinouts at Apple TIL homepage
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2000-07-09
Description
Y bit 7
Y bit 6
Y bit 5
Y bit 4
Y bit 3
Y bit 2
Y bit 1
Y bit 0
UV bit 7
UV bit 6
UV bit 5
UV bit 4
UV bit 3
UV bit 2
UV bit 1
UV bit 0
Ground
Line-locked clock (LLC) in
Ground
Clock reference (CREF) in
Ground
Vertical sync (VS) In
Ground
Horizontal Sync (HS) In
Ground
Horizontal Reference Signal (HREF) In
Ground
28
29
30
31
32
33
34
+4 User Port
Available on Commodore +4 computer.
Name
GND
+5V
/BRESET
P2/CSE
P3
P4
P5
RxC
ATN
+9V
+9V
GND
GND
P0
RxD
RTS
DTR
P7
DCD
P6
CTS
DSR
TxD
GND
Description
Ground
+5 VDC
?
Data 2/Cassette Sense
Data 3
Data 4
Data 5
Receive Clock
Attention?
+9 VAC
+9 VAC
Ground
Ground
Data 0
Receive Data
Request to Send
Data Terminal Ready
Data 7
Data Carrier Detect
Data 6
Clear to Send
Data Set Ready
Transmit Data
Ground
Name
GND
D15
+5V
D12
GND
D11
+5V
D8
GND
D7
+5V
D4
GND
D3
+5V
D0
GND
DRA4
DRA5
DRA6
DRA7
GND
/RAS
GND
GND
/CASU0
Description
Ground
Data 15
+5 Volts DC
Data 12
Ground
Data 11
+5 Volts DC
Data 8
Ground
Data 7
+5 Volts DC
Data 4
Ground
Data 3
+5 Volts DC
Data 0
Ground
Ground
Ground
Ground
27
28
29
30
GND
Ground
/CASL0
+5V
+5 Volts DC
+5V
+5 Volts DC
A
B
C
D
E
F
H
J
K
L
M
N
P
R
S
T
U
V
W
X
Y
Z
AA
BB
CC
DD
EE
FF
HH
JJ
GND
D14
+5V
D13
GND
D10
+5V
D9
GND
D6
+5V
D5
GND
D2
+5V
D1
GND
DRA3
DRA2
DRA1
DRA0
GND
/RRW
GND
GND
/CASU1
GND
/CASL1
+5V
+5V
Ground
Data 14
+5 Volts DC
Data 13
Ground
Data 10
+5 Volts DC
Data 9
Ground
Data 6
+5 Volts DC
Data 5
Ground
Data 2
+5 Volts DC
Data 1
Ground
Ground
Ground
Ground
Ground
+5 Volts DC
+5 Volts DC
Name
Description
Audio MODEM to Host
Audio Host to MODEM
Audio MH GND
MIC to MODEM
R/W*
DS*
BERR*
DSACK1*
DSACK0*
GND
IOSIZE0*
C16M
IOSIZE1*
GND
RESET*
Bus Grant-Sacramento
IOD[31]
IOD[30]
IOD[29]
IOD[28]
IOD[27]
IOD[26]
IOD[25]
IOD[24]
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
IOD[23]
IOD[22]
+5V
IOD[21]
IOD[20]
IOD[19]
IOD[18]
IOD[17]
IOD[16]
IOD[15]
IOD[14]
IOD[13]
IOD[12]
IOD[11]
IOD[10]
IOD[9]
IOD[8]
GND
IOD[7]
IOD[6]
IOD[5]
IOD[4]
IOD[3]
IOD[2]
IOD[1]
IOD[0]
BGACK*
Bus Request-Sacramento
IO_CS_TIMED*
IO_CS_DSACK*
+5V
Sacramento IRQ*
IOA[1]
IOA[0]
A[2]
A[3]
A[4]
A[5]
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
A[6]
A[7]
A[8]
A[9]
A[10]
A[11]
A[12]
GND
A[13]
A[14]
A[15]
A[16]
A[17]
A[18]
A[19]
A[20]
A[21]
A[22]
A[23]
A[24]
+5V
A[25]
A[26]
A[27]
A[28]
A[29]
A[30]
A[31]
CPU_AS*
GND
TRICKLE+5V
System wakeup
'040 bus clock
-5V
+12V
GND
spare
C32M
101
102
103
104
105
106
107
108
109
110
111
112
spare
GND
spare
spare
SCC port A enable
spare
TxDA
RxDA
RTSA*
CTSA*
DTRA*
DCDA*
Name
+5V
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
GND
GND
/DTACK
/AS
Description
+5 VDC
Address bit 1
Address bit 2
Address bit 3
Address bit 4
Address bit 5
Address bit 6
Address bit 7
Address bit 8
Address bit 9
Address bit 10
Address bit 11
Address bit 12
Address bit 13
Address bit 14
Address bit 15
Address bit 16
Address bit 17
Address bit 18
Address bit 19
Address bit 20
Address bit 21
Address bit 22
Address bit 23
Ground
Ground
Data Transfer Acknowledge
Address Strobe
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
/ROM_CS
16M
/EXT_DTACK
/DELAY_CS
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
+5V
+5V
D0-D15
Unbuffered data bus, bits 0 through 15
A1-A23
Unbuffered 68HC000 address bus, bits 1 through 23
16M
16 MHz system clock
/EXT.DTACK
External data transfer acknowledge that disables main system /DTACK.
/AS
68HC000 Address strobe
/DTACK
Data transfer acknowledge, /DTACK input to 68HC000.
/DELAY_CS
This signal is generated by the addressing PAL and is used to put the ROM board into the idle mode by
inserting multiple wait states.
/ROM_CS
Permanent ROM chip select signal. Selects in range $90 0000 through $9F FFFF.
Contributor: Joakim gren
Source:
Technote HW13: Macintosh Portable ROM Expansion at Apple Technical Notes
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2000-07-09
Top Row
Pin
1
2
3
4
5
6
7
8
9
10
11
12
2716 Pin
13
14
15
16
17
*
19
n/c
22
23
24
12
CPU Name
D3
D4
D5
D6
D7
A12
A10
A11
A9
A8
+5V
SGND
Description
Data 3
Data 4
Data 5
Data 6
Data 7
Address 12
Address 10
Address 11
Address 9
Address 8
+5 VDC
Shield Ground
Bottom Row
Pin
1
2
3
4
5
6
7
8
9
10
11
12
2716 Pin
1
2
3
4
5
6
7
8
9
10
11
n/c
CPU Name
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
GND
Description
Address 7
Address 6
Address 5
Address 4
Address 3
Address 2
Address 1
Address 0
Data 0
Data 1
Data 2
Ground
Name
D0
D1
D2
D3
D4
D5
D6
D7
Enable 80-8F
Enable 40-7F
Not Connected
Ground
Ground
Ground (System Clock 02 on 2 port)
A6
A5
A2
Interlock
A0
A1
A3
A4
Ground
Ground (Video In on 2 port)
Ground
+5 VDC
27
28
29
30
31
32
33
34
35
36
A7
Not Connected
A8
Audio In (2 port)
A9
A13
A10
A12
A11
Interlock
Name
+5 VDC
Audio Out (2 port)
Ground
R/W Early
Enable E0-EF
D6
D4
D2
D0
IRQ
Ground
Serial Data In
Serial In Clock
Serial Out Clock
Serial Data Out
Audio In
A14
System Clock 01
A11
A7
A6
A5
A4
A3
A2
A1
27
28
29
30
31
32
33
34
35
36
A0
Ground
D1
D3
D5
D7
Not connected
Ground
Not connected
+5 VDC
Name
R/W
HALT
D3
D4
D5
D6
D7
A12
A10
A11
A9
A8
+5V
GND
A13
A14
A15
EAUDIO
A7
A6
A5
A4
A3
A2
A1
A0
Description
Read/Write
Halt
Data 3
Data 4
Data 5
Data 6
Data 7
Address 12
Address 10
Address 11
Address 9
Address 8
+5 VDC
Ground
Address 13
Address 14
Address 15
EAudio ???
Address 7
Address 6
Address 5
Address 4
Address 3
Address 2
Address 1
Address 0
27
28
29
30
31
32
D0
D1
D2
Gnd
IRQ
CLK2
Data 0
Data 1
Data 2
Gnd
Interrupt
Clock 2 ???
Name
GND
+5V
CVIDEO
MLUM0
MLUM3
BLANK
OSCDIS
EXTMEN
GND
EXTOSC
CLK2
MSYNC
MLUM1
MLUM2
MCOL
RDY
AUDIO
GND
Description
Ground
+5 VDC
Input to RF modulator (Video+Audio)
Maria Luminance Bit 0
Maria Luminance Bit 3
Blanking output
Disable 14.31818 MHz Master Clock
External Maria Enable Input
Ground
External clock to replace Master Clock
Phase 2 Clock from the 6502
Maria Composite Sync
Maria Luminance Bit 1
Maria Luminance Bit 2
Maria Color Phase Angle
Input to the 6502
Audio
Ground
Name
+5V
+5V
D14
D15
D12
D13
D10
D11
D8
D9
D6
D7
D4
D5
D2
D3
D0
D1
A13
A15
A8
Description
+5 VDC
+5 VDC
Data 14
Data 15
Data 12
Data 13
Data 10
Data 11
Data 8
Data 9
Data 6
Data 7
Data 4
Data 5
Data 2
Data 3
Data 0
Data 1
Address 13
Address 15
Address 8
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
A14
A7
A9
A6
A10
A5
A12
A11
A4
RS3
A3
RS4
A2
UDS
A1
LDS
GND
GND
GND
Address 14
Address 7
Address 9
Address 6
Address 10
Address 5
Address 12
Address 11
Address 4
ROM Select 3
Address 3
ROM Select 4
Address 2
Upper Data Strobe
Address 1
Lower Data Strobe
Ground
Ground
Ground
Description
General Purpose 0
General Purpose 2
General Purpose 1
SDMA Play Data
SDMA Play Clock
SDMA Play Sync
Not Connect
Ground
+12V
Ground
Sync Serial I/F Ctrl 0
Sync Serial I/F Ctrl 1
Sync Serial I/F Ctrl 2
Ground
Sync Serial Data In
Ground
+12V
Ground
SDMA Record Data
SDMA Record Clock
SDMA Record Sync
DSP Interrupt
Sync Serial I/F Data Out
Sync Serial I/F Clock
Ground
External Clock Input
Name
GND
+5V
+5V
/IRQ
R/W
DClock
I/O1
/GAME
/EXROM
I/O2
/ROML
BA
/DMA
D7
D6
D5
D4
D3
D2
D1
D0
GND
Description
System Ground
System Vcc
System Vcc
Interrupt request
System Read/Write Signal
8.18MHz Video Dot Clock
I/O Chip select $de00-deff
Sensed for memory map configuration
Sensed for memory map configuration
I/O Chip select $df00-dfff
External ROM select $8000-Bfff
Bus available output
Direct memory access input
Data bit 7
Data bit 6
Data bit 5
Data bit 4
Data bit 3
Data bit 2
Data bit 1
Data bit 0
System Ground
GND
System Ground
B
C
D
E
F
H
J
K
L
M
N
P
R
S
T
U
V
W
X
Y
Z
/ROMH
/RESET
/NMI
1MHz
TA15
TA14
TA13
TA12
TA11
TA10
TA9
TA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
GND
Name
GND
+5V
+5V
/IRQ
R/W
C1HIGH
C2LOW
C2HIGH
/CS1
/CS0
/CAS
MUX
BA
D7
D6
D5
D4
D3
D2
D1
D0
AEC
EAI
PHI 2
Description
Ground
+5 VDC
+5 VDC
Interrupt
Read/Write (1=Read, 0=Write)
External Cartridge Chip Selects C1 High
External Cartridge Chip Selects C2 Low (reserved)
External Cartridge Chip Selects C2 High (reserved)
Chip Select Line 1
Chip Select Line 0
Column Address Strobe
DRAM address multiplex control signal
Bus Available (Low=DMA)
Data 7
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
Data 0
Address Enable Code
External Audio In
Artificial Phi 2 signal
25
A
B
C
D
E
F
H
J
K
L
M
N
P
R
S
T
U
V
W
X
Y
Z
AA
BB
CC
GND
GND
C1LOW
/RESET
/RAS
PHI 0
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
n/c
n/c
n/c
GND
Ground
Ground
External Cartridge Chip Selects C1 Low
Reset
Row Address Strobe
Artificial Phi 0 Signal
Address 15
Address 14
Address 13
Address 12
Address 11
Address 10
Address 9
Address 8
Address 7
Address 6
Address 5
Address 4
Address 3
Address 2
Address 1
Address 0
Not connected
Not connected
Not connected
Ground
PHI 2: Address valid on the rising edge, data valid on the falling edge
Contributor: Joakim gren, Arwin Vosselman
Sources:
Usenet posting in comp.sys.cbm, Pinout specs for cbm machines needed by Lonnie McClure
SAMS Computerfacts CC8 Commodore 16
Article in C'T September 1986
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-08
Name
GND
+5V
+5V
/IRQ
/CR/W
DOTCLK
I/O 1
/GAME
/EXROM
I/O 2
/ROML
BA
/DMA
CD7
CD6
CD5
CD4
CD3
CD2
CD1
CD0
GND
Description
Ground
+5 Volts DC
+5 Volts DC
Interrupt Request
A
B
C
GND
/ROMH
/RESET
Ground
ROM High
Reset
Dot Clock
Game
ROM Low
Cartridge Data 7
Cartridge Data 7
Cartridge Data 7
Cartridge Data 7
Cartridge Data 7
Cartridge Data 7
Cartridge Data 7
Cartridge Data 7
Ground
D
E
F
H
J
K
L
M
N
P
R
S
T
U
V
W
X
Y
Z
/NMI
S02
CA15
CA14
CA13
CA12
CA11
CA10
CA9
CA8
CA7
CA6
CA5
CA4
CA3
CA2
CA1
CA0
GND
Name
GND
FLAG2+PB0
PB1
PB2
PB3
PB4
PB6
PB7
PA2
GND
RS232
GND
RxD
RTS
DTR
RI
DCD
CTS
DSR
TxD
GND
Description
Protective Ground
Receive Data (Must be applied to both pins!)
Ready To Send
Data Terminal Ready
Ring Indicator
Data Carrier Detect
Clear To Send
Data Set Ready
Transmit Data
Signal Ground
Name
GND
+5V
/RESET
CNT1
SP1
CNT2
SP2
/PC2
ATN
+9V AC
+9V AC
GND
Description
Ground
+5 VDC (100 mA max)
Reset, will force a Cold Start. Also a reset output for devices.
Counter 1, from CIA #1
Serial Port 1, from CIA #1
Counter 2, from CIA #2
Serial Port 2, from CIA #2
Handshaking line, from CIA #2
Serial Attention In
+9 VAC (+ phase) (100 mA max)
+9 VAC (- phase) (100 mA max)
Ground
A
B
C
D
E
F
H
J
K
L
M
N
GND
/FLAG2
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PA2
GND
Ground
Flag 2
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
PA2
Ground
CD32 Expansion-port
Name
A31
A30
A29
A28
A27
A26
A25
A24
DGND
VCC
A23
A22
A21
A20
A19
A18
A17
A16
DGND
VCC
A15
A14
A13
A12
A11
A10
Description
Address 31
Address 30
Address 29
Address 28
Address 27
Address 26
Address 25
Address 24
Data Ground
+5 VDC
Address 23
Address 22
Address 21
Address 20
Address 19
Address 18
Address 17
Address 16
Data Ground
+5 VDC
Address 15
Address 14
Address 13
Address 12
Address 11
Address 10
Comment
Probably not connected since 68EC020
Probably not connected since 68EC020
Probably not connected since 68EC020
Probably not connected since 68EC020
Probably not connected since 68EC020
Probably not connected since 68EC020
Probably not connected since 68EC020
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
A9
A8
DGND
VCC
A7
A6
A5
A4
A3
A2
A1
A0
DGND
VCC
D31
D30
D29
D28
D27
D26
D25
D24
DGND
VCC
D23
D22
D21
D20
D19
D18
D17
D16
DGND
VCC
D15
D14
D13
D12
Address 9
Address 8
Data Ground
+5 VDC
Address 7
Address 6
Address 5
Address 4
Address 3
Address 2
Address 1
Address 0
Data Ground
+5 VDC
Data 31
Data 30
Data 29
Data 28
Data 27
Data 26
Data 25
Data 24
Data Ground
+5 VDC
Data 23
Data 22
Data 21
Data 20
Data 19
Data 18
Data 17
Data 16
Data Ground
+5 VDC
Data 15
Data 14
Data 13
Data 12
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
D11
D10
D9
D8
DGND
VCC
D7
D6
D5
D4
D3
D2
D1
D0
DGND
VCC
/IPL2
/IPL1
/IPL0
Data 11
Data 10
Data 9
Data 8
Data Ground
+5 VDC
Data 7
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
Data 0
Data Ground
+5 VDC
Interrupt Priority Level 2
Interrupt Priority Level 1
Interrupt Priority Level 0
/RST
/HALT
/ECS
/OCS
SIZE1
SIZE0
/AS
/DS
/R/W
/BERR
Reset
Halt
ECS??
OCS??
Size 1
Size 0
Address Strobe
Data Strobe
Read/Write
Bus Error
/AVEC
/DSACK1
/DSACK0
CPUCLK_A
Autovector Req
Data Ack 1
Data Ack 0
DGND
VCC
Data Ground
+5 VDC
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
FC2
FC1
FC0
Function Codes 2
Function Codes 1
Function Codes 0
/CPU_BR
/EXP_BG
/CPU_BG
/EXP_BR
/PUNT
/RESET
/INT2
/INT6
/KB_CLOCK
/KB_DATA
/FIRE0
/FIRE1
/LED
/ACTIVE
/RXD
/TXD
/DKRD
/DKWD
SYSTEM
/DKWE
CONFIG_OUT
DGND
+12V
DGND
+12V
17MHZ
EXT_AUDIO
68020 RESET
Interrupt 2
Interrupt 2
Keyboard clock
Keyboard data
Fire Button 0??
Fire Button 1??
Power On LED ??
Disk active LED
Serial Receive
Serial Transmit
Serial data in
Serial data out
Floppy interface (Paula?)
Floppy interface (Paula?)
Floppy interface (Paula?)
Data Ground
+12V DC
Data Ground
+12V DC
For FMV interface ??
For FMV interface ??
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
DA_DATA
/MUTE
DA_LRCLK
DA_BCLK
DGND
VCC
DR
DG
DB
DI
/PIXELSW_EXT
/PIXELSW
/BLANK
PIXELCLK
DGND
VCC
/CSYNC
CCK_B
/HSYNC
/VSYNC
VGND
VGND
AR_EXT
AR
AG_EXT
AG
AB_EXT
AB
VGND
VGND
/NTSC
/XCLKEN
XCLK
/EXT_VIDEO
DGND
VCC
AGND
+12V
Pixelclock
Data Ground
+5 VDC
Composite sync
Color clock ??
Horizontal sync
Vertical sync
Video ground
Video ground
Analog Red External
Analog Red
Analog Green External
Analog Green
Analog Blue External
Analog Blue
Video ground
Video ground
Not buffered.
179
180
181
182
LEFT_EXT
LEFT
RIGHT_EXT
RIGHT
Name
GND
GND
VCC
VCC
/CFGOUT
/CFGIN
GND
CCKQ
CDAC
CCK
/OVR
XRDY
/INT2
n/c
A5
/INT6
A6
A4
GND
A3
A2
A7
A1
A8
/FC0
A9
Description
Ground
Ground
+5 VDC
+5 VDC
Configout AutoConfig signal (not connected)
Configin AutoConfig signal (grounded)
Ground
3.58 MHz CCKQ clock (C3)
7.16 MHz CDAC clock (90 before system clock)
3.58 MHz CCK clock (C1)
Override (Disables /DTACK generation of Gary)
External Ready (Generates wait states while low).
Level 2 Interrupt
not connected
Address Bus 5
Level 6 Interrupt
Address Bus 6
Address Bus 4
Ground
Address Bus 3
Address Bus 2
Address Bus 7
Address Bus 1
Address Bus 8
Processor Function Code Status (bit 0)
Address Bus 9
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
/FC1
A10
/FC2
A11
GND
A12
A13
/IPL0
A14
/IPL1
A15
/IPL2
A16
/BERR
A17
/VPA
GND
E
/VMA
A18
/RST
A19
/HLT
A20
A22
A21
A23
/BR
GND
/BGACK
D15
/BG
D14
/DTACK
D13
R/W
D12
/LDS
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
D11
/UDS
GND
/AS
D0
D10
D1
D9
D2
D8
D3
D7
D4
D6
GND
D5
Data Bus 11
Upper Data Strobe
Ground
Address Strobe
Data Bus 0
Data Bus 10
Data Bus 1
Data Bus 9
Data Bus 2
Data Bus 8
Data Bus 3
Data Bus 7
Data Bus 4
Data Bus 6
Ground
Data Bus 5
Note: Pin 7-80 is equivalent with the Amiga 500's pin 13-86 at the 86 pin Amiga 500 connector.
Contributor: Joakim gren
Source:
Darren Ewaniuk's CDTV Technical Information
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-08
14
--13
16
--15
18
--17
20
--19
22
--21
24
--24
26
--25
28
--27
30
--29
Name
GND
GND
VCC
VCC
SD1
SD0
SD3
SD2
SD5
SD4
SD7
SD6
/SDREQ
/INTX
/CSS
/SDACK
/IOR
/IOW
A8
7M
A6
A7
Description
Ground
Ground
+5 VDC
+5 VDC
Data Bus 1
Data Bus 0
Data Bus 3
Data Bus 2
Data Bus 5
Data Bus 4
Data Bus 7
Data Bus 6
DMA Request
Interrupt Request
Chip Select
DMA Acknowledge
I/O Read
I/O Write
Address Bus 8
7.16 MHz System Clock
Address Bus 6
Address Bus 7
23
24
25
26
27
28
29
30
A4
A5
A2
A3
/IFRST
A1
GND
GND
Address Bus 4
Address Bus 5
Address Bus 2
Address Bus 3
+5 VDC
Address Bus 1
Ground
Ground
Name
System Ground
TV Video
IEEE-SRQ
IEEE-EOI
Diagnostic Sense
Cass.1 Read
Cass.2 Read
Diag Tape Wrt.
TV Vertical
TV Horizontal
GND
GND
GND
CA1
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PA2 (CB2)
GND
GameBoy Cartridge
Available on the Nintendo GameBoy.
Name
VCC
?
/RESET
/WR
?
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
/CS
D0
D1
D2
Description
+5 VDC
? Connected on Gameboy, but not used on GamePaks.
Reset
Write
? Used by paging PAL on high capacity GamePaks.
Address 0
Address 1
Address 2
Address 3
Address 4
Address 5
Address 6
Address 7
Address 8
Address 9
Address 10
Address 11
Address 12
Address 13
Address 14
Chip Select
Data 0
Data 1
Data 2
25
26
27
28
29
30
31
32
D3
D4
D5
D6
D7
/RD
?
GND
Data 3
Data 4
Data 5
Data 6
Data 7
Read
? Connected on Gameboy, but not used on Game-Paks.
Ground
GameBoy Cartridge
Available on the Nintendo GameBoy.
UNKNOWN CONNECTOR at the GameBoy.
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Name
VCC
?
/RESET
/WR
?
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
/CS
D0
D1
D2
D3
D4
D5
D6
D7
Description
+5 VDC
? Connected on Gameboy, but not used on GamePaks.
Reset
Write
? Used by paging PAL on high capacity GamePaks.
Address 0
Address 1
Address 2
Address 3
Address 4
Address 5
Address 6
Address 7
Address 8
Address 9
Address 10
Address 11
Address 12
Address 13
Address 14
Chip Select
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
30 /RD
31 ?
32 GND
Read
? Connected on Gameboy, but not used on Game-Paks.
Ground
GeekPort
The GeekPort is a connector available at Be's BeBox computers.
This is a dream for all hobby engineers who like to connect the computer to the coffee machine.
Name
GND
A1
A3
A5
A7
GND
+5V
GND
+12V
GND
-12V
GND
+5V
GND
B0
B2
B4
B6
GND
Description
Ground
Digital A 1
Digital A 3
Digital A 5
Digital A 7
Ground
+5 VDC
Ground
+12 VDC
Ground
-12 VDC
Ground
+5 VDC
Ground
Digital B 0
Digital B 2
Digital B 4
Digital B 6
Ground
Dir
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
A0
A2
A4
A6
AIref
A2D1
A2D2
A2D3
A2D4
D2A1
D2A2
D2A3
D2A4
AOref
B1
B3
B5
B7
Digital A 0
Digital A 2
Digital A 4
Digital A 6
Analog In Reference
Analog In 1
Analog In 2
Analog In 3
Analog In 4
Analog Out 1
Analog Out 2
Analog Out 3
Analog Out 4
Analog Out Reference
Digital B 1
Digital B 3
Digital B 5
Digital B 7
MSX Expansion
49 47 45
5 3 1
+---------//-----+
| H H H //H H H |
| ======//====== |
| H H H// H H H |
+-----//---------+
50 48 46 6 4 2
Name
Dir
/CS1
/CS2
/CS12
/SLTSL
n/c
/RFSH
/WAIT
/INT
/M1
/BUSDIR
/IORQ
/MREQ
/WR
/RD
/RESET
n/c
A0
A1
A2
Description
Memory Read in addresses 4000-7FFF
Memory Read in addresses 8000-BFFF
Memory Read in addresses 4000-BFFF
Low when Slot 2 (cartridge slot) is selected
Not connected.
Refresh signal from CPU
OC, Tells CPU to wait. Refresh signal is not maintained
OC, Requests a interrupt to CPU (call to addr 38h)
CPU fetches first part of instruction from memory.
NC, was used to control the data direction.
I/O request signal. (Address=Port)
Memory request signal. (Address=Address)
Write signal (strobe)
Read signal (strobe)
Reset
Not connected.
Address 0
Address 1
Address 2
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
D0
D1
D2
D3
D4
D5
D6
D7
GND
CLOCK
GND
SW1
+5V
SW2
+5V
+12V
SOUNDIN
-12V
Address 3
Address 4
Address 5
Address 6
Address 7
Address 8
Address 9
Address 10
Address 11
Address 12
Address 13
Address 14
Address 15
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Ground
CPU clock, 3.579 MHz
Ground
NC, Insert/remove detection for protection
+5 VDC (300mA max /slot)
NC, Insert/remove detection for protection
+5 VDC (300mA max /slot)
+12 VDC (50mA max /slot)
Sound input (-5dBm)
-12 VDC (50mA max /slot)
PC-Engine Cartridge
Available on the PC Engine.
Name
?
?
A18?
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
GND
D3
D4
D5
D6
D7
/CE
Description
Address 18
Address 16
Address 15
Address 12
Address 7
Address 6
Address 5
Address 4
Address 3
Address 2
Address 1
Address 0
Data 0
Data 1
Data 2
Ground
Data 3
Data 4
Data 5
Data 6
Data 7
Chip Select
25
26
27
28
29
30
31
32
33
34
35
36
37
38
A10
/OE
A11
A9
A8
A13
A14
A17
A19?
R/W
?
?
?
+5V
Address 10
Output Enable
Address 11
Address 9
Address 8
Address 13
Address 14
Address 17
Address 19
Read/Write
+5 VDC
Pin 1 is the short pin on the left (if the card is to inserted forwards)
Pin 38 is the long pin on the right.
Contributor: Joakim gren
Source:
Video Games FAQ (Part 3) - Pinout by David Shadoff
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-08
Name
SD7
SD0
SD6
SD1
SD5
SD2
SD4
SD3
GND
SCK
SVB
SS3
SCVV
AC
SOME
SMR
Description
Data Bit 7
Data Bit 0
Data Bit 6
Data Bit 1
Data Bit 5
Data Bit 2
Data Bit 4
Data Bit 3
0 Volts
Undefined Control Line
External Power Input / Battery Output Voltage - 0.6 Volt
Slot Select 3
+5 Volts
External On/Clear
Undefined Control Line
Undefined Control Line
SNES Cartridge
Available on the Nintendo SNES.
+-------------------------------//----------------------------+
| 32 33 34 35 | 36 37 38 39 40 //53 55 56 57 58 | 59 60 61 62 |
| 01 02 03 04 | 05 06 07 08 09// 22 24 25 26 27 | 28 29 30 31 |
+----------------------------//-------------------------------+
Name
GND
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
/IRQ
D0
D1
D2
Description
Ground
Address 11
Address 10
Address 9
Address 8
Address 7
Address 6
Address 5
Address 4
Address 3
Address 2
Address 1
Address 0
Interrupt
Data 0
Data 1
Data 2
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
D3
/READ
CIC
CIC
/RAM ENABLE
VCC
Data 3
Read
?
?
RAM Enable
+5 VDC
GND
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
/ROM ENABLE
D4
D5
D6
D7
/WRITE
CIC
CIC
n/c
VCC
Ground
Address 12
Address 13
Address 14
Address 15
Address 16
Address 17
Address 18
Address 19
Address 20
Address 21
Address 22
Address 23
ROM Enable
Data 4
Data 5
Data 6
Data 7
Write
?
?
Not connected
+5 VDC
60
61
62
Contributor: Joakim gren
Source:
Video Games FAQ (Part 3) - Pinout by Thomas Rolfes
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-08
SUN SROMBO
Available on SUN SPARCengine motherboards
Seems to be for SUN internal factory tests/programming
Name
ADR19
VCC
ADR16
ADR18
ADR15
ADR17
ADR12
ADR14
ADR7
ADR13
ADR6
ADR8
ADR5
ADR9
ADR4
ADR11
ADR3
RD_L
ADR2
ADR10
ADR1
ROMBO_CS_L
ADR0
DAT7
25
26
27
28
29
30
31
32
33
34
DAT0
DAT6
DAT1
DAT5
DAT2
DAT4
GND
DAT3
NC
WR_L
SUN SROMBOlite
Available on SUN SPARCengine motherboards
Seems to be for SUN internal factory tests/programming
28 PIN IDC MALE at the motherboard
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Name
+5V
GND
EB_RD_L
EB_WR_L
EB_SCC_CS_L
EB_LATCH
EB_RDY_L
EB_DAT<0>
EB_DAT<1>
EB_DAT<2>
EB_DAT<3>
BRST_L
EB_DAT<4>
EB_DAT<5>
EB_DAT<6>
EB_DAT<7>
ROMBO_CS_L
EB_ADR<0>
EB_ADR<1>
EB_ADR<2>
EB_ADR<3>
SYNC_SER_IRQ_L
EB_ADR<4>
EB_ADR<5>
EB_ADR<6>
EB_ADR<7>
+5V
GND
Name
Dir
Description
+5v
Power, 300mA
/CNTRL2
Game adapter control signal
+12v
Power, 100mA
-12v
Power, 50mA
/CNTRL1
Game adapter control signal
/WAIT
Z80 WAIT
/RST
Z80 RST
CPU CLK
Buffered 3.58MHz system clock
A15
Buffered Address bus
A14
"
A13
"
A12
"
A11
"
A10
"
A9
"
A8
"
A7
"
A6
"
A5
"
A4
"
A3
"
A2
"
A1
"
A0
"
/RFSH
RAM expansion refresh
/EXCSR
Video-CPU write select
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
/M1
/EXCSW
/WR
/MREQ
/IORQ
/RD
D0
D1
D2
D3
D4
D5
D6
D7
CSOUND
/INT
/RAMDIS
/ROMDIS
/BK32
/BK31
/BK22
/BK21
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Z80 M1
CPU-Video write select
Z80 WR
Z80 MREQ
Z80 IORQ
Z80 RD
Buffered Data Bus
"
"
"
"
"
"
"
Audio input signal
Z80 INT
Disable user RAM
Disable basic ROM
Enable bank 32 Memory (8000-ffff)
Enable bank 31 Memory (0000-7FFF)
Enable bank 22 Memory (8000-FFFF)
Enable bank 21 Memory (0000-7FFF)
System Ground
System Ground
Name
+5v
+5v
A7
A12
A6
A13
A5
A8
A4
A9
A3
A11
A10
A2
A0
A1
D0
D7
D1
D6
D2
D5
D3
D4
CCS3
CCS4
27
28
29
30
CCS1
CCS2
GND
GND
TG-16 Cartridge
Available on the TG-16.
Name
?
?
A18?
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
GND
D4
D3
D2
D1
D0
/CE
Description
Address 18
Address 16
Address 15
Address 12
Address 7
Address 6
Address 5
Address 4
Address 3
Address 2
Address 1
Address 0
Data 7
Data 6
Data 5
Ground
Data 4
Data 3
Data 2
Data 1
Data 0
Chip Select
25
26
27
28
29
30
31
32
33
34
35
36
37
38
A10
/OE
A11
A9
A8
A13
A14
A17
A19?
R/W
?
?
?
+5V
Address 10
Output Enable
Address 11
Address 9
Address 8
Address 13
Address 14
Address 17
Address 19
Read/Write
+5 VDC
Pin 1 is the short pin on the left (if the card is to inserted forwards)
Pin 38 is the long pin on the right.
Contributor: Joakim gren
Source:
Video Games FAQ (Part 3) - Pinout by David Shadoff
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-08
Name
+8V
+8V
GND
READYA
GND
RESET*
GND
SCLK
LCP*
AUDIO
RDBENA*
PCBEN
HOLD*
IAQHA
SENILA*
SENILB*
INTA*
LOAD*
D7
GND
D5
D6
D3
D4
D1
D2
GND
Dir
nc
nc
H
H
nc
H
H
nc
Description
+5V 3-T regulator voltage supply (about +8V)
+5V 3-T regulator voltage supply (about +8V)
Ground
System ready (10K pull-up to +5V)
Ground
System reset (active low)
Ground
System clock (not connected)
CPU indicator 1=TI99 0=2nd generation (not connected)
Input audio (=AUDIOIN)
Active low: enable flex cable data bus drivers (1K pull-up)
PCB enable for burn-in (always High)
Active low CPU hold request (always High)
IAQ [or] HOLDA (logical or)
Interrupt level A sense enable (always High)
Interrupt level B sense enable (always High)
Active low interrupt level A (=EXTINT*)
Unmaskable interrupt (not connected)
Data bit 7 (LSB)
Ground
Data bit 5
Data bit 6
Data bit 3
Data bit 4
Data bit 1
Data bit 2
Ground
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
D0
A14
A15
A12
A13
A10
A11
A8
A9
A6
A7
A4
A5
A2
A3
A0
A1
AMB
H
AMA
H
GND
AMC
H
GND
CLKOUT*
CRUCLK*
DBIN
GND
WE*
CRUIN
MEMEN*
-12V
-12V
+12V
+12V
Name
RESET
GND
D7
CRUCLK*
D6
CRUIN
D5
A15
D4
A13
D3
A12
D2
A11
D1
A10
D0
A9
VCC
A8
GS*
A7
A14
A3
DBIN
A6
Dir
IN
IN/OUT
OUT
IN/OUT
IN
IN/OUT
OUT
IN/OUT
OUT
IN/OUT
OUT
IN/OUT
OUT
IN/OUT
OUT
IN/OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
Description
Resets the system (active high)
Signal groud
Data bus, bit 7 (least significant)
Inversion of TMS9900 CRUCLOCK pin
CRU input to TMS9900
Address bus, bit 15 / also CRU output bit
27
28
29
30
31
32
33
34
35
36
GRC
A5
VDD
A4
GR
WE*
VSS
ROMG*
GND
GND
OUT
OUT
OUT
IN
OUT
OUT
-
Name
VCC
SBE
RESET*
EXTINT*
A5
A10
A4
A11
DBIN
A3
A12
READY
LOAD*
A8
A13
A14
A7
A9
A15
A2
GND
CRUCLK*
GND
PHI3*
GND
WE*
Dir
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
Description
+5 Volts power supply
Low if addr in >9000-94xx (sound port)
System reset (active low)
External interrupt (active low)
Address bus, bit 5
Active high = read memory
Active high = memory is ready
Unmaskable interrupt (=> BLWP @>FFFC)
Address bus, lsb. Also CRU output bit.
Ground
Inversion of TMS9900 CRUCLOCK pin
Ground
Inversion of phase 3 clock
Ground
Write Enable (derived from TMS9900 WE* pin)
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
GND
MBE*
A6
A1
A0
MEMEN*
CRUIN
D7
D4
D6
D0
D5
D2
D1
IAQ
D3
VDD
AUDIOIN
OUT
OUT
OUT
OUT
OUT
IN
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN
IN/OUT
IN
Ground
Active low if addr in >4000-5FFF (card ROMs)
Address bus, bit 0 (most significant)
Memory access enable (active low)
CRU input bit to TMS9900
Data bus, bit 7 (least significant)
Data bus, bit 0 (most significant)
Interrupt acknowledged by TMS9900
-5 Volts power supply
To sound generator AUDIO IN pin
Name
GND
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9
CA10
CA11
CA12
CA13
I/O 2
I/O 3
S02
/NMI
/RESET
Description
Ground
Address 0
Address 1
Address 2
Address 3
Address 4
Address 5
Address 6
Address 7
Address 8
Address 9
Address 10
Address 11
Address 12
Address 13
Decoded I/O block 2, starting at $9130
Decoded I/O block 3, starting at $9140
Phase 2 System Clock
Non maskable Interrupt
6502 Reset
Y
Z
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
n/c
GND
GND
CD0
CD1
CD2
CD3
CD4
CD5
CD6
CD7
/BLK 1
/BLK 2
/BLK 3
/BLK 5
RAM 1
RAM 2
RAM 3
V R/W
C R/W
/IRQ
n/c
+5V
GND
Not connected
Ground
Ground
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
BLK 1 (Memory location $2000 - $3fff)
BLK 2 (Memory location $4000 - $5fff)
BLK 3 (Memory location $6000 - $7fff)
BLK 5 (Memory location $a000 - $bfff)
RAM 1 (Memory location $0400 - $07ff)
RAM 2 (Memory location $0800 - $0bff)
RAM 3 (Memory location $0c00 - $0fff)
Read/Write from Vic chip (1=R, 0=W)
Read/Write from CPU (1=R, 0=W)
6502 Interrupt Request
Not connected
+5 VDC
Ground
Alcatel HC600/800/1000
1
I
3
I
5
I
7
I
9
I
11 13 15
I I I
O 17
I
2
I
4
I
6
I
8
I I I I
10 12 14 16
Description
Vbat_ext
EMMI_PAE
Mic
EMMI_OPE
GND
EXT_EMET
SCL_E
EXT_RECDIT
SDA_E
GND
GND
DC_IN (charge)
Speaker
MARCHE
DC_IN (charge)
GND
Antenna+internal switch (int/ext)
Ericsson 218/337/318/388
UNKNOWN CONNECTOR
Pin Dir
Description
1
Voice
2
+5V=External Power, 0V=Battery
3
Ext Speak control
4 Analog GND
5
Voice
6
+5V=POWER ON, 0V=POWER OFF
7
Charger control
8 Digital/DC GND
9
0V=normal,+5V=test, +12V=test+flash
10
Hook
11
TTL serial in
12
TTL serial out
13
0V for aprox 1 sec = POWER ON/OFF
14
DC Power supply
Direction is phone relative world.
Contributor: Joakim gren
Source:
Ericsson 218/318/337/388 pinout at Technick.net
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-08
Ericsson 628/788
UNKNOWN CONNECTOR
Pin
1
2
3
4
5
6
Description
Audio Out
Audio In
Accessory Sense. GND to enable External Mic and Speaker (Analog)
Audio Signal GND
Portable handsfree In.
Music Mute Out, High when phone is used.
In Flash Memory Voltage and Service Voltage,
7
In 0V=normal,+5V=test, +12V=test+flash
8 Logic Out, Status On. Sources over 100mA
9 Data Out from Mobile Station. Debug messages appear here at 112KBaud when in debug mode.
10 Digital Ground and DC return
11 Data in
12 DC in for battery charging, DC out for accessory power
Contributor: Joakim gren
Source:
Ericsson 628/788 pinout at Technick.net
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-08
Ericsson 688/888
UNKNOWN CONNECTOR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
Description
+ external power supply (7.2Volt - 600mA)
RS232 input (TTL)
GND (digital)
RS232 output (TTL)
+5V output
Test. Switch phone off and provide +5V and switch back on. (set comms at 9600, n,8,1)
Mute
Internal/external mic and ear (0=External - open=Internal)
GND (analogic)
? Related to Mic/Speak
BF in
BF out
Motorola 6200/7500/8200/8400/8700
ANT- (O) | | | | | | | | | |
10 9 8 7 6 5 4 3 2 1
Top of phone (screen)
Pin
1
2
3
4
5
6
7
8
9
10
Signal Description
Audio Ground
Ext b+
T Data
C Data
R Data
Logic Ground
Audio Out - on/off
Audio In
Manual Test
Battery Feedback
NEC P3
+----------------------+
|
1 2 3 4 5 6 |
|
o o o o o o |
| O
|
|
o o o o o o |
|
7 8 9 10 11 12 |
+----------------------+
Pin
1
2
3
4
5
6
7
8
9
10
11
12
Description
Audio out (EAR)
Audio out (EAR/SPEAKER)
Audio out (SPEAKER)
SDATA (Serial Data)
No Connect
VCC (+8V)
No Connect
Audio in (MIC)
GND
BUSY
SCLK (Serial Clock)
GND
Nokia 1610
Name
GND
V_OUT
XMIC
NC
NC
MBUS
NC
SGND
XEAR
Hook
NC
V_IN
Description
Charger/System Ground
Accessory Output Supply. (3.4V...10V - 50mA)
External Microphone Input and Accessory Identification
Not Connected
Not Connected
Serial Control Bus
Not Connected
Signal Ground
External Speaker and Mute Control
Hook Signal
Not Connected
Charging Supply Voltage (Max 16V)
Nokia 2110
+-----------------------------------------+
|
16 15 14 13 12 11 10 9
|
| ANT o o o o o o o o
Charge |
| (O)
[ ] (o)
|
|
o o o o o o o o
|
|
8 7 6 5 4 3 2 1
|
+-----------------------------------------+
Pin
Name
1 GND
2
MIC/JCONN
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AGND
TDA
M2BUS
HOOK/RXD2
PHFS/TXD2
VCHAR
GND
EAR/HFPWR
DSYNC
RDA
BENA
VF
DCLK
VCHAR
Description
Digital ground
External audio input from accessories or handsfree microphone. Multiplexed with
junction box connection control signal
Analogue ground for accessories
Transmitted DBUS data to the accessories
Serial Bidirectional data and control between the handportable and accessories
Hook indication. HP has a 100KE pull-up resistor
Handsfree device power on/off, data to flash programming device
Battery charging voltage
Digital ground
External Audio output to accessories or handsfree speaker
DBUS data bit sync clock
DBUS recieved data from the accessories
Power supply to headset adapter
Programming voltage for FLASH
DBUS data clock
Battery charging voltage
Nokia 31xx/81xx
Name
GND
V_OUT
XMIC
EXT_RF
TX
MBUS
BENA
SGND
XEAR
Hook
RX
V_IN
Description
Charger/System Ground
Accessory Output Supply. (3.4V...10V - 50mA)
External Microphone Input and Accessory Identification
External RF Control Input
FBUS Transmit
Serial Control Bus
Not Connected
Signal Ground
External Speaker and Mute Control
Hook Signal
FBUS Receive
Charging Supply Voltage (Max 16V)
U high
Description
1.4 V Compact Handsfree Unit Connected
2.05 Headset Adapter Connected
2.56 V Infra Red Link Conneceted
Nokia 5110/6110
(at the cellular phone)
NOKIA SPECIAL at the cellular phone.
Pin
1
2
3
4
5
6
7
8
9
Description
VIN CHARGER INPUT VOLTAGE 8.4V 0.8A
CHRG CTRL CHARGER CONTROL PWM 32Khz
XMIC MIC INPUT 60mV - 1V
SGND SIGNAL GROUND
XEAR EAR OUTPUT 80mV - 1V
MBUS 9600 B/S
FBUS_RX 9.6 - 230.4 KB/S
FBUS_TX 9.6 - 230.4 KB/S
L_GND CHARGER / LOGIC GND
Panasonic G500
UNKNOWN CONNECTOR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
GND
TX_Audio
AGND
HF_ON (L=ON)
AOP_Sense
Serial_Up
Serial_Down
External_Power
Ground
RX_Audio
Radio_Mute
HF_Sense
Reserved
Ignition
Logic_Power
PAON
Dir
---->
---->
<-<--->
<--
Description
Ground
?
Audio_Ground
L=H/F ON
Data Adaptor Select
UART up (9600,33.8kbps)
UART down
POWER FOR CHARGING
<---> L=MUTE
<-- L=H/F MODE
L=FLASH WRITE ENABLE
<-- H=ON
--> H=HANDSET ON
--> Power Amplifier Control Signal
Phillips Fizz/Spark
UNKNOWN CONNECTOR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
GROUND
GROUND
HANDS FREE ON/OFF
MUTE
TX
RX
RTS
REPROGRAMMING
ON HOOK CHARGER (APPROX 13V? TO 14V)
AUX MIC
AUX SPEAKER
GROUND
+VCC for Car Charger
+VCC for Car Charger
Siemens C25/S25
Top
+-------------------------------------+
Left | [] [] [] [] [] [] [] [] [] [] [] [] | Right
| 1 2 3 4 5 6 7 8 9 10 11 12 |
+-------------------------------------+
Pin
1
2
3
4
5
6
7
8
9
10
11
12
Name
Dir
Description
GND
SELF-SERVICE
LOAD
BATTERY
DATA OUT
DATA IN
Z_CLK
Z_DATA
MICG
MIC
AUD
AUDG
in/out
in
out
out
in
in
out
-
Ground
Recognition/control battery charger
Charging voltage
Battery (S25 only)
Data sent (S25 only)
Data received (S25 only)
Recognition/control accessories
Recognition/control accessories
Ground for microphone
Microphone input
Loudspeaker
Ground for external speaker
Description
Power (+ 9V)
Battery charge
Handsfree sos
Handsfree extern (10K resistor to +9 to enable handsfree functions)
TXE
RXE
Ignition (10K resistor to +9 to illuminate the display continiously)
Antenna extern (10K resistor to ground to enable external microphone and antenna)
Audio 1
Audio 2 (loudspeaker amplifier output)
Microphone (use electrect microfoon and 46 db preamp.)
Audio ground (do not connect to 13 and 14 )
Ground (supply)
Ground (supply)
Normal
VSS
VSS
DQ0
DQ32
DQ1
DQ33
DQ2
DQ34
DQ3
DQ35
VCC
VCC
DQ4
DQ36
DQ5
DQ37
DQ6
DQ38
DQ7
DQ39
VSS
VSS
/CAS0
/CAS4
ECC
VSS
VSS
DQ0
DQ32
DQ1
DQ33
DQ2
DQ34
DQ3
DQ35
VCC
VCC
DQ4
DQ36
DQ5
DQ37
DQ6
DQ38
DQ7
DQ39
VSS
VSS
/CAS0
/CAS4
Description
Ground
Ground
Data 0
Data 32
Data 1
Data 33
Data 2
Data 34
Data 3
Data 35
+5 VDC
+5 VDC
Data 4
Data 36
Data 5
Data 37
Data 6
Data 38
Data 7
Data 39
Ground
Ground
Column Address Strobe 0
Column Address Strobe 4
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
/CAS1
/CAS5
VCC
VCC
A0
A3
A1
A4
A2
A5
VSS
VSS
DQ8
DQ40
DQ9
DQ41
DQ10
DQ42
DQ11
DQ43
VCC
VCC
DQ12
DQ44
DQ13
DQ45
DQ14
DQ46
DQ15
DQ47
VSS
VSS
n/c
n/c
n/c
n/c
DU
DU
/CAS1
/CAS5
VCC
VCC
A0
A3
A1
A4
A2
A5
VSS
VSS
DQ8
DQ40
DQ9
DQ41
DQ10
DQ42
DQ11
DQ43
VCC
VCC
DQ12
DQ44
DQ13
DQ45
DQ14
DQ46
DQ15
DQ47
VSS
VSS
CB0
CB4
CB1
CB5
DU
DU
Don't use
Don't use
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
VCC
VCC
DU
DU
/WE
n/c
/RAS0
n/c
/RAS1
n/c
/OE
n/c
VSS
VSS
n/c
n/c
n/c
n/c
VCC
VCC
DQ16
DQ48
DQ17
DQ49
DQ18
DQ50
DQ19
DQ51
VSS
VSS
DQ20
DQ52
DQ21
DQ53
DQ22
DQ54
DQ23
DQ55
VCC
VCC
DU
DU
/WE
n/c
/RAS0
n/c
/RAS1
n/c
/OE
n/c
VSS
VSS
CB2
CB6
CB3
CB7
VCC
VCC
DQ16
DQ48
DQ17
DQ49
DQ18
DQ50
DQ19
DQ51
VSS
VSS
DQ20
DQ52
DQ21
DQ53
DQ22
DQ54
DQ23
DQ55
+5 VDC
+5 VDC
Don't use
Don't use
Read/Write
Not connected
Row Address Strobe 0
Not connected
Row Address Strobe 1
Not connected
Not connected
Ground
Ground
+5 VDC
+5 VDC
Data 16
Data 48
Data 17
Data 49
Data 18
Data 50
Data 19
Data 51
Ground
Ground
Data 20
Data 52
Data 21
Data 53
Data 22
Data 54
Data 23
Data 55
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
VCC
VCC
A6
A7
A8
A11
VSS
VSS
A9
A12
A10
A13
VCC
VCC
/CAS2
/CAS6
/CAS3
/CAS7
VSS
/VSS
DQ24
DQ56
DQ25
DQ57
DQ26
DQ58
DQ27
DQ59
VCC
VCC
DQ28
DQ60
DQ29
DQ61
DQ30
DQ62
DQ31
DQ63
VCC
VCC
A6
A7
A8
A11
VSS
VSS
A9
A12
A10
A13
VCC
VCC
/CAS2
/CAS6
/CAS3
/CAS7
VSS
/VSS
DQ24
DQ56
DQ25
DQ57
DQ26
DQ58
DQ27
DQ59
VCC
VCC
DQ28
DQ60
DQ29
DQ61
DQ30
DQ62
DQ31
DQ63
+5 VDC
+5 VDC
Address 6
Address 7
Address 8
Address 11
Ground
Ground
Address 9
Address 12
Address 10
Address 13
+5 VDC
+5 VDC
Column Address Strobe 2
Column Address Strobe 6
Column Address Strobe 3
Column Address Strobe 7
Ground
Ground
Data 24
Data 56
Data 25
Data 57
Data 26
Data 58
Data 27
Data 59
+5 VDC
+5 VDC
Data 28
Data 60
Data 29
Data 61
Data 30
Data 62
Data 31
Data 63
139
140
141
142
143
144
VSS
VSS
SDA
SCL
VCC
VCC
VSS
VSS
SDA
SCL
VCC
VCC
Ground
Ground
+5 VDC
+5 VDC
Front, Left
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Non-Parity?
VSS
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VCC
DQ14
DQ15
Parity?
VSS
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VCC
DQ14
DQ15
72 ECC?
VSS
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VCC
DQ14
DQ15
80 ECC?
VSS
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VCC
DQ14
DQ15
Description
Ground
Data 0
Data 1
Data 2
Data 3
+5 VDC or +3.3 VDC
Data 4
Data 5
Data 6
Data 7
Data 8
Ground
Data 9
Data 10
Data 11
Data 12
Data 13
+5 VDC or +3.3 VDC
Data 14
Data 15
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
n/c
n/c
VSS
n/c
n/c
VCC
/WE0
/CAS0
/CAS1
/RAS0
/OE0
VSS
A0
A2
A4
A6
A8
A10
A12
VCC
VCC
DU
CB0
CB1
VSS
n/c
n/c
VCC
/WE0
/CAS0
/CAS1
/RAS0
/OE0
VSS
A0
A2
A4
A6
A8
A10
A12
VCC
VCC
DU
CB0
CB1
VSS
n/c
n/c
VCC
/WE0
/CAS0
/CAS1
/RAS0
/OE0
VSS
A0
A2
A4
A6
A8
A10
A12
VCC
VCC
DU
CB0
CB1
VSS
CB8
CB9
VCC
/WE0
/CAS0
/CAS1
/RAS0
/OE0
VSS
A0
A2
A4
A6
A8
A10
A12
VCC
VCC
DU
72 ECC?
VSS
/OE2
/RAS2
/CAS2
/CAS3
/WE2
VCC
n/c
n/c
CB2
CB3
VSS
80 ECC?
VSS
/OE2
/RAS2
/CAS2
/CAS3
/WE2
VCC
CB10
CB11
CB2
CB3
VSS
Front, Right
Pin
43
44
45
46
47
48
49
50
51
52
53
54
Non-Parity?
VSS
/OE2
/RAS2
/CAS2
/CAS3
/WE2
VCC
n/c
n/c
n/c
n/c
VSS
Parity?
VSS
/OE2
/RAS2
/CAS2
/CAS3
/WE2
VCC
n/c
n/c
CB2
CB3
VSS
Description
Ground
Row Address Strobe 2
Column Address Strobe 2
Column Address Strobe 3
Read/Write Input
+5 VDC or +3.3 VDC
Parity/Check Bit Input/Output 10
Parity/Check Bit Input/Output 11
Parity/Check Bit Input/Output 2
Parity/Check Bit Input/Output 3
Ground
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
DQ16
DQ17
DQ18
DQ19
VCC
DQ20
n/c
DU
n/c
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VCC
DQ28
DQ29
DQ30
DQ31
VSS
n/c
n/c
n/c
SDA
SCL
VCC
DQ16
DQ17
DQ18
DQ19
VCC
DQ20
n/c
DU
n/c
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VCC
DQ28
DQ29
DQ30
DQ31
VSS
n/c
n/c
n/c
SDA
SCL
VCC
DQ16
DQ17
DQ18
DQ19
VCC
DQ20
n/c
DU
n/c
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VCC
DQ28
DQ29
DQ30
DQ31
VSS
n/c
n/c
n/c
SDA
SCL
VCC
DQ16
DQ17
DQ18
DQ19
VCC
DQ20
n/c
DU
n/c
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VCC
DQ28
DQ29
DQ30
DQ31
VSS
n/c
n/c
n/c
SDA
SCL
VCC
72 ECC?
VSS
DQ32
DQ33
DQ34
80 ECC?
VSS
DQ32
DQ33
DQ34
Data 16
Data 17
Data 18
Data 19
+5 VDC or +3.3 VDC
Data 20
Not connected
Don't Use
Not connected
Ground
Data 21
Data 22
Data 23
Ground
Data 24
Data 25
Data 26
Data 27
+5 VDC or +3.3 VDC
Data 28
Data 29
Data 30
Data 31
Ground
Not connected
Not connected
Not connected
Serial Data
Serial Clock
+5 VDC or +3.3 VDC
Back, Left
Pin
85
86
87
88
Non-Parity?
VSS
DQ32
DQ33
DQ34
Parity?
VSS
DQ32
DQ33
DQ34
Description
Ground
Data 32
Data 33
Data 34
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
DQ35
VCC
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VCC
DQ46
DQ47
n/c
n/c
VSS
n/c
n/c
VCC
DU
/CAS4
/CAS5
/RAS1
DU
VSS
A1
A3
A5
A7
A9
A11
A13
VCC
DU
DU
DQ35
VCC
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VCC
DQ46
DQ47
CB4
CB5
VSS
n/c
n/c
VCC
DU
/CAS4
/CAS5
/RAS1
DU
VSS
A1
A3
A5
A7
A9
A11
A13
VCC
DU
DU
DQ35
VCC
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VCC
DQ46
DQ47
CB4
CB5
VSS
n/c
n/c
VCC
DU
/CAS4
/CAS5
/RAS1
DU
VSS
A1
A3
A5
A7
A9
A11
A13
VCC
DU
DU
DQ35
VCC
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VCC
DQ46
DQ47
CB4
CB5
VSS
CB12
CB13
VCC
DU
/CAS4
/CAS5
/RAS1
DU
VSS
A1
A3
A5
A7
A9
A11
A13
VCC
DU
DU
Data 35
+5 VDC or +3.3 VDC
Data 36
Data 37
Data 38
Data 39
Data 40
Ground
Data 41
Data 42
Data 43
Data 44
Data 45
+5 VDC or +3.3 VDC
Data 46
Data 47
Parity/Check Bit Input/Output 4
Parity/Check Bit Input/Output 5
Ground
Parity/Check Bit Input/Output 12
Parity/Check Bit Input/Output 13
+5 VDC or +3.3 VDC
Don't Use
Column Address Strobe 4
Column Address Strobe 5
Row Address Strobe 1
Don't Use
Ground
Address 1
Address 3
Address 5
Address 7
Address 9
Address 11
Address 13
+5 VDC or +3.3 VDC
Don't Use
Don't Use
Back, Right
Pin
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
Non-Parity?
VSS
DU
/RAS3
/CAS6
/CAS7
DU
VCC
n/c
n/c
n/c
n/c
VSS
DQ48
DQ49
DQ50
DQ51
VCC
DQ52
n/c
DU
n/c
VSS
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VCC
DQ60
DQ61
DQ62
DQ63
Parity?
VSS
DU
/RAS3
/CAS6
/CAS7
DU
VCC
n/c
n/c
CB6
CB7
VSS
DQ48
DQ49
DQ50
DQ51
VCC
DQ52
n/c
DU
n/c
VSS
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VCC
DQ60
DQ61
DQ62
DQ63
72 ECC?
VSS
DU
/RAS3
/CAS6
/CAS7
DU
VCC
n/c
n/c
CB6
CB7
VSS
DQ48
DQ49
DQ50
DQ51
VCC
DQ52
n/c
DU
n/c
VSS
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VCC
DQ60
DQ61
DQ62
DQ63
80 ECC?
VSS
DU
/RAS3
/CAS6
/CAS7
DU
VCC
CB14
CB15
CB6
CB7
VSS
DQ48
DQ49
DQ50
DQ51
VCC
DQ52
n/c
DU
n/c
VSS
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VCC
DQ60
DQ61
DQ62
DQ63
Description
Ground
Don't Use
Column Address Strobe 3
Column Address Strobe 6
Column Address Strobe 7
Don't Use
+5 VDC or +3.3 VDC
Parity/Check Bit Input/Output 14
Parity/Check Bit Input/Output 15
Parity/Check Bit Input/Output 6
Parity/Check Bit Input/Output 7
Ground
Data 48
Data 49
Data 50
Data 51
+5 VDC or +3.3 VDC
Data 52
Not connected
Don't Use
Not connected
Ground
Data 53
Data 54
Data 55
Ground
Data 56
Data 57
Data 58
Data 59
+5 VDC or +3.3 VDC
Data 60
Data 61
Data 62
Data 63
162
163
164
165
166
167
168
VSS
CK3
n/c
SA0
SA1
SA2
VCC
VSS
CK3
n/c
SA0
SA1
SA2
VCC
VSS
CK3
n/c
SA0
SA1
SA2
VCC
VSS
CK3
n/c
SA0
SA1
SA2
VCC
Ground
Not connected
Serial Address 0
Serial Address 1
Serial Address 2
+5 VDC or +3.3 VDC
Front, Left
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Non-Parity
VSS
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VDD
DQ14
DQ15
72 ECC?
VSS
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VDD
DQ14
DQ15
80 ECC?
VSS
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VDD
DQ14
DQ15
Description
Ground
Data 0
Data 1
Data 2
Data 3
+5 VDC or +3.3 VDC
Data 4
Data 5
Data 6
Data 7
Data 8
Ground
Data 9
Data 10
Data 11
Data 12
Data 13
+5 VDC or +3.3 VDC
Data 14
Data 15
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
n/c
n/c
VSS
n/c
n/c
VDD
/WE
DQMB0
DQMB1
/S0
DU
VSS
A0
A2
A4
A6
A8
A10/AP
BA1
VDD
VDD
CK0
CB0
CB1
VSS
n/c
n/c
VDD
/WE
DQMB0
DQMB1
/S0
DU
VSS
A0
A2
A4
A6
A8
A10/AP
BA1
VDD
VDD
CK0
CB0
CB1
VSS
CB8
CB9
VDD
/WE
DQMB0
DQMB1
/S0
DU
VSS
A0
A2
A4
A6
A8
A10/AP
BA1
VDD
VDD
CK0
80 ECC?
VSS
DU
/S2
DQMB2
DQMB3
DU
VDD
CB10
CB11
CB2
CB3
VSS
Description
Front, Right
Pin
43
44
45
46
47
48
49
50
51
52
53
54
Non-Parity
VSS
DU
/S2
DQMB2
DQMB3
DU
VDD
n/c
n/c
n/c
n/c
VSS
72 ECC?
VSS
DU
/S2
DQMB2
DQMB3
DU
VDD
n/c
n/c
CB2
CB3
VSS
Ground
Don't Use
Chip Select 2
Byte Mask signal 2
Byte Mask signal 3
Don't Use
+5 VDC or +3.3 VDC
Parity/Check Bit Input/Output 10
Parity/Check Bit Input/Output 11
Parity/Check Bit Input/Output 2
Parity/Check Bit Input/Output 3
Ground
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
DQ16
DQ17
DQ18
DQ19
VDD
DQ20
n/c
Vref,NC
CKE1
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
VSS
CK2
n/c
n/c
SDA
SCL
VDD
DQ16
DQ17
DQ18
DQ19
VDD
DQ20
n/c
Vref,NC
CKE1
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
VSS
CK2
n/c
n/c
SDA
SCL
VDD
DQ16
DQ17
DQ18
DQ19
VDD
DQ20
n/c
Vref,NC
CKE1
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
VSS
CK2
n/c
n/c
SDA
SCL
VDD
Data 16
Data 17
Data 18
Data 19
+5 VDC or +3.3 VDC
Data 20
Not connected
Clock Enable Signal 1
Ground
Data 21
Data 22
Data 23
Ground
Data 24
Data 25
Data 26
Data 27
+5 VDC or +3.3 VDC
Data 28
Data 29
Data 30
Data 31
Ground
Clock signal 2
Not connected
Not connected
Serial Data
Serial Clock
+5 VDC or +3.3 VDC
Back, Left
Pin
85
86
87
88
Non-Parity
VSS
DQ32
DQ33
DQ34
72 ECC?
VSS
DQ32
DQ33
DQ34
80 ECC?
VSS
DQ32
DQ33
DQ34
Description
Ground
Data 32
Data 33
Data 34
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
DQ35
VDD
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VDD
DQ46
DQ47
n/c
n/c
VSS
n/c
n/c
VDD
/CAS
DQMB4
DQMB5
/S1
/RAS
VSS
A1
A3
A5
A7
A9
BA0
A11
VDD
CK1
A12
DQ35
VDD
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VDD
DQ46
DQ47
CB4
CB5
VSS
n/c
n/c
VDD
/CAS
DQMB4
DQMB5
/S1
/RAS
VSS
A1
A3
A5
A7
A9
BA0
A11
VDD
CK1
A12
DQ35
VDD
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VDD
DQ46
DQ47
CB4
CB5
VSS
CB12
CB13
VDD
/CAS
DQMB4
DQMB5
/S1
/RAS
VSS
A1
A3
A5
A7
A9
BA0
A11
VDD
CK1
A12
Data 35
+5 VDC or +3.3 VDC
Data 36
Data 37
Data 38
Data 39
Data 40
Ground
Data 41
Data 42
Data 43
Data 44
Data 45
+5 VDC or +3.3 VDC
Data 46
Data 47
Parity/Check Bit Input/Output 4
Parity/Check Bit Input/Output 5
Ground
Parity/Check Bit Input/Output 12
Parity/Check Bit Input/Output 13
+5 VDC or +3.3 VDC
Column Address Strobe
Byte Mask signal 4
Byte Mask signal 5
Chip Select 1
Row Address Strobe
Ground
Address 1
Address 3
Address 5
Address 7
Address 9
Bank Address 0
Address 11
+5 VDC or +3.3 VDC
Clock signal 1
Address 12
Back, Right
Pin
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
Non-Parity
VSS
CKE0
/S3
DQMB6
DQMB7
A13
VDD
n/c
n/c
n/c
n/c
VSS
DQ48
DQ49
DQ50
DQ51
VDD
DQ52
n/c
Vref,NC
n/c
VSS
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VDD
DQ60
DQ61
DQ62
DQ63
72 ECC?
VSS
CKE0
/S3
DQMB6
DQMB7
A13
VDD
n/c
n/c
CB6
CB7
VSS
DQ48
DQ49
DQ50
DQ51
VDD
DQ52
n/c
Vref,NC
n/c
VSS
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VDD
DQ60
DQ61
DQ62
DQ63
80 ECC?
VSS
CKE0
/S3
DQMB6
DQMB7
A13
VDD
CB14
CB15
CB6
CB7
VSS
DQ48
DQ49
DQ50
DQ51
VDD
DQ52
n/c
Vref,NC
n/c
VSS
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VDD
DQ60
DQ61
DQ62
DQ63
Description
Ground
Clock Enable Signal 0
Chip Select 3
Byte Mask signal 6
Byte Mask signal 7
Address 13
+5 VDC or +3.3 VDC
Parity/Check Bit Input/Output 14
Parity/Check Bit Input/Output 15
Parity/Check Bit Input/Output 6
Parity/Check Bit Input/Output 7
Ground
Data 48
Data 49
Data 50
Data 51
+5 VDC or +3.3 VDC
Data 52
Not connected
Not connected
Ground
Data 53
Data 54
Data 55
Ground
Data 56
Data 57
Data 58
Data 59
+5 VDC or +3.3 VDC
Data 60
Data 61
Data 62
Data 63
162
163
164
165
166
167
168
VSS
CK3
n/c
SA0
SA1
SA2
VDD
VSS
CK3
n/c
SA0
SA1
SA2
VDD
VSS
CK3
n/c
SA0
SA1
SA2
VDD
Ground
Clock signal 3
Not connected
Serial address 0
Serial address 1
Serial address 2
+5 VDC or +3.3 VDC
30 pin SIMM
SIMM=Single Inline Memory Module.
Name
VCC
/CAS
DQ0
A0
A1
DQ1
A2
A3
GND
DQ2
A4
A5
DQ3
A6
A7
DQ4
A8
A9
A10
DQ5
/WE
GND
DQ6
Description
+5 VDC
Column Address Strobe
Data 0
Address 0
Address 1
Data 1
Address 2
Address 3
Ground
Data 2
Address 4
Address 5
Data 3
Address 6
Address 7
Data 4
Address 8
Address 9
Address 10
Data 5
Write Enable
Ground
Data 6
24
25
26
27
28
29
30
A11
DQ7
QP
/RAS
/CASP
DP
VCC
Address 11
Data 7
Data Parity Out
Row Address Strobe
Something Parity ????
Data Parity In
+5 VDC
ECC
VSS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VCC
PD5
A0
A1
A2
A3
A4
A5
A6
n/c
DQ8
DQ9
Optimized
VSS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VCC
PD5
A0
A1
A2
A3
A4
A5
A6
n/c
DQ8
DQ9
Description
Ground
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
+5 VDC
Presence Detect 5
Address 0
Address 1
Address 2
Address 3
Address 4
Address 5
Address 6
Not connected
Data 8
Data 9
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
A7
DQ16
VCC
A8
A9
n/c
/RAS1
DQ17
DQ18
DQ19
DQ20
VSS
/CAS0
A10
A11
/CAS1
/RAS0
/RAS1
DQ21
/WE
/ECC
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
VCC
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
A7
DQ16
VCC
A8
A9
n/c
/RAS1
DQ17
DQ18
DQ19
DQ20
VSS
/CAS0
A10
A11
/CAS1
/RAS0
/RAS1
DQ21
/WE
/ECC
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
VCC
Data 10
Data 11
Data 12
Data 13
Data 14
Data 15
Address 7
Data 16
+5 VDC
Address 8
Address 9
Not connected
Row Address Strobe 1
Data 17
Data 18
Data 19
Data 20
Ground
Column Address Strobe 0
Address 10
Address 11
Column Address Strobe 1
Row Address Strobe 0
Row Address Strobe 1
Data 21
Read/Write
Data 22
Data 23
Data 24
Data 25
Data 26
Data 27
Data 28
Data 29
Data 30
Data 31
+5 VDC
60
61
62
63
64
65
66
67
68
69
70
71
72
DQ32
DQ33
DQ34
DQ35
n/c
n/c
n/c
PD1
PD2
PD3
PD4
n/c
VSS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
PD1
PD2
PD3
PD4
DQ39
VSS
Data 32
Data 33
Data 34
Data 35
Data 36
Data 37
Data 38
Presence Detect 1
Presence Detect 2
Presence Detect 3
Presence Detect 4
Data 39
Ground
72 pin SIMM
SIMM=Single Inline Memory Module
Non-Parity
VSS
DQ0
DQ16
DQ1
DQ17
DQ2
DQ18
DQ3
DQ19
VCC
n/c
A0
A1
A2
A3
A4
A5
A6
A10
DQ4
DQ20
DQ5
Parity
VSS
DQ0
DQ16
DQ1
DQ17
DQ2
DQ18
DQ3
DQ19
VCC
n/c
A0
A1
A2
A3
A4
A5
A6
A10
DQ4
DQ20
DQ5
Description
Ground
Data 0
Data 16
Data 1
Data 17
Data 2
Data 18
Data 3
Data 19
+5 VDC
Not connected
Address 0
Address 1
Address 2
Address 3
Address 4
Address 5
Address 6
Address 10
Data 4
Data 20
Data 5
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
DQ21
DQ6
DQ22
DQ7
DQ23
A7
A11
VCC
A8
A9
/RAS3
/RAS2
n/c
n/c
n/c
n/c
VSS
/CAS0
/CAS2
/CAS3
/CAS1
/RAS0
/RAS1
n/c
/WE
n/c
DQ8
DQ24
DQ9
DQ25
DQ10
DQ26
DQ11
DQ27
DQ12
DQ28
VCC
DQ29
DQ21
DQ6
DQ22
DQ7
DQ23
A7
A11
VCC
A8
A9
/RAS3
/RAS2
PQ3
PQ1
PQ2
PQ4
VSS
/CAS0
/CAS2
/CAS3
/CAS1
/RAS0
/RAS1
n/c
/WE
n/c
DQ8
DQ24
DQ9
DQ25
DQ10
DQ26
DQ11
DQ27
DQ12
DQ28
VCC
DQ29
Data 21
Data 6
Data 22
Data 7
Data 23
Address 7
Address 11
+5 VDC
Address 8
Address 9
Row Address Strobe 3
Row Address Strobe 2
Parity bit 3 (for the 3rd byte, bits 16-23)
Parity bit 1 (for the 1st byte, bits 0-7)
Parity bit 2 (for the 2nd byte, bits 8-15)
Parity bit 4 (for the 4th byte, bits 24-31)
Ground
Column Address Strobe 0
Column Address Strobe 2
Column Address Strobe 3
Column Address Strobe 1
Row Address Strobe 0
Row Address Strobe 1
Not connected
Read/Write
Not connected
Data 8
Data 24
Data 9
Data 25
Data 10
Data 26
Data 11
Data 27
Data 12
Data 28
+5 VDC
Data 29
61
62
63
64
65
66
67
68
69
70
71
72
DQ13
DQ30
DQ14
DQ31
DQ16
n/c
PD1
PD2
PD3
PD4
n/c
VSS
DQ13
DQ30
DQ14
DQ31
DQ16
n/c
PD1
PD2
PD3
PD4
n/c
VSS
Data 13
Data 30
Data 14
Data 31
Data 16
Not connected
Presence Detect 1
Presence Detect 2
Presence Detect 3
Presence Detect 4
Not connected
Ground
Size:
PD2
GND
GND
NC
NC
PD1
GND
NC
GND
NC
Size
4 or 64 MB
2 or 32 MB
1 or 16 MB
8 MB
Accesstime:
PD4
GND
GND
NC
NC
PD3
GND
NC
GND
NC
Accesstime
50, 100 ns
80 ns
70 ns
60 ns
SmartCard AFNOR
-------------+------------|
8
|
4
|
|
|
|
+-------\
|
/-------+
|
7
+----+----+
3
|
|
|
|
|
+--------|
|--------+
|
6
|
|
2
|
|
+
+----+
|
+-------/
|
\-------+
|
5
|
1
|
|
|
|
-------------+-------------
Name
VCC
R/W
CLOCK
RESET
GND
VPP
I/O
FUSE
Description
+5 VDC
Read/Write
Clock
Reset
Ground
+21 VDC
In/Out
Fuse
SmartCard ISO
-------------+------------|
1
|
5
|
|
|
|
+-------\
|
/-------+
|
2
+----+
+
6
|
|
|
|
|
+--------|
|--------+
|
3
|
|
7
|
|
+----+----+
|
+-------/
|
\-------+
|
4
|
8
|
|
|
|
-------------+-------------
Name
VCC
R/W
CLOCK
RESET
GND
VPP
I/O
FUSE
Description
+5 VDC
Read/Write
Clock
Reset
Ground
+21 VDC
In/Out
Fuse
Name
VCC
RESET
CLOCK
n/c
GND
n/c
I/O
n/c
Description
+5 VDC
Reset
Clock
Not connected
Ground
Not connected
In/Out
Not connected
Name
VCC
RESET
CLOCK
n/c
GND
n/c
I/O
n/c
Description
+5 VDC
Reset
Clock
Not connected
Ground
Not connected
In/Out
Not connected
72 pin SO DIMM
SO DIMM=Small Outline Dual Inline Memory Module
Non-Parity
VSS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VCC
PD1
A0
A1
A2
A3
A4
A5
A6
A10
n/c
DQ9
DQ10
DQ11
DQ12
Parity
VSS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VCC
PD1
A0
A1
A2
A3
A4
A5
A6
A10
PQ8
DQ9
DQ10
DQ11
DQ12
Description
Ground
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
+5 VDC
Presence Detect 1
Address 0
Address 1
Address 2
Address 3
Address 4
Address 5
Address 6
Address 10
Data 8 (Parity 1)
Data 9
Data 10
Data 11
Data 12
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
DQ13
DQ14
DQ15
A7
A11
VCC
A8
A9
/RAS3
/RAS2
DQ16
n/c
DQ18
DQ19
VSS
/CAS0
/CAS2
/CAS3
/CAS1
/RAS0
/RAS1
A12
/WE
A13
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
n/c
DQ27
DQ28
DQ29
DQ31
DQ30
VCC
DQ32
DQ13
DQ14
DQ15
A7
A11
VCC
A8
A9
RAS3
RAS2
DQ16
PQ17
DQ18
DQ19
VSS
CAS0
CAS2
CAS3
CAS1
RAS0
RAS1
A12
WE
A13
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
PQ26
DQ27
DQ28
DQ29
DQ31
DQ30
VCC
DQ32
Data 13
Data 14
Data 15
Address 7
Address 11
+5 VDC
Address 8
Address 9
Row Address Strobe 3
Row Address Strobe 2
Data 16
Data 17 (Parity 2)
Data 18
Data 19
Ground
Column Address Strobe 0
Column Address Strobe 2
Column Address Strobe 3
Column Address Strobe 1
Row Address Strobe 0
Row Address Strobe 1
Address 12
Read/Write
Address 13
Data 20
Data 21
Data 22
Data 23
Data 24
Data 25
Data 26 (Parity 3)
Data 27
Data 28
Data 29
Data 31
Data 30
+5 VDC
Data 32
63
64
65
66
67
68
69
70
71
72
DQ33
DQ34
n/c
PD2
PD3
PD4
PD5
PD6
PD7
VSS
DQ33
DQ34
PQ35
PD2
PD3
PD4
PD5
PD6
PD7
VSS
Data 33
Data 34
Data 35 (Parity 4)
Presence Detect 2
Presence Detect 3
Presence Detect 4
Presence Detect 1
Presence Detect 6
Presence Detect 7
Ground
Name
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A1
A2
A3
A4
A5
Description
Data Bus 0
Data Bus 1
Data Bus 2
Data Bus 3
Data Bus 4
Data Bus 5
Data Bus 6
Data Bus 7
Data Bus 8
Data Bus 9
Data Bus 10
Data Bus 11
Data Bus 12
Data Bus 13
Data Bus 14
Data Bus 15
Address Bus 1
Address Bus 2
Address Bus 3
Address Bus 4
Address Bus 5
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
R/W
/CSMCOD
/CSMCEN
VCC
GND
A18
A19
Address Bus 6
Address Bus 7
Address Bus 8
Address Bus 9
Address Bus 10
Address Bus 11
Address Bus 12
Address Bus 13
Address Bus 14
Address Bus 15
Address Bus 16
Address Bus 17
Read/Write (High=Read)
Chip Select Odd Bytes
Chip Select Even Bytes
+5 Volts DC
Ground
Address Bus 18 (Short J16 to connect A18 to processor bus)
Address Bus 19 (Short J17 to connect A19 to processor bus)
CompactFlash
Developed by SanDisk.
Is compatible with PC-Card ATA with a simple passive adapter.
See PC-Card ATA for more information.
Name
GND
D3
D4
D5
D6
D7
/CE1
A10
/OE
A9
A8
A7
VCC
A6
A5
A4
A3
Description
Ground
Data 3
Data 4
Data 5
Data 6
Data 7
Card Enable 1
Address 10
Output Enable
Address 9
Address 8
Address 7
+5V
Address 6
Address 5
Address 4
Address 3
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
A2
A1
A0
D0
D1
D2
/WP:/IOIS16
/CD2
/CD1
D0
D0
D0
D0
D0
/CE2
/VS1
/IORD
/IOWR
/WE
/READY:/RDY:/IREQ
VCC
CSEL
/VS2
RESET
/WAIT
/INPACK
/REG
/BVD2:SPKR
/BVD1:STSCHG
D8
D9
D10
GND
Address 2
Address 1
Address 0
Data 0
Data 1
Data 2
Write Protect : IOIS16
Card Detect 2
Card Detect 1
Data 0
Data 0
Data 0
Data 0
Data 0
Card Enable 2
Refresh
I/O Read
I/O Write
Write Enable
Ready : Busy : IREQ
+5V
RFU
Reset
Wait
Register Select
Battery Voltage Detect 2 : SPKR
Battery Voltage Detect 1 : STSCHG
Data 8
Data 9
Data 10
Ground
PC Card ATA
This specification makes it possible to share ATA & PC Card with the same connectors.
Namel
Ground
DD3
DD4
DD5
DD6
DD7
/CS0
INTRQ
VCC
x
x
PC-Card equiv
Ground
D3
D4
D5
D6
D7
/CE1
A10
/OE
x 1) A9
i
A8
i
x
x
/WE
/READY:IREQ
VCC
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
DA2
DA1
DA0
DD0
DD1
DD2
/IOCS16
Ground
Ground
/CD1
DD11
DD12
DD13
DD14
DD15
/CS1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
/DIOR
/DIOW
x
x
i
i
i
i
i
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x 1)
i
x
x
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
/WP:IOIS16
Ground
Ground
/CD1
D11
D12
D13
D14
D15
/CE2
/VS1
/IORD
/IOWR
VCC
VCC
M/SCSEL
x
x
/RESET
x 2)
x 2)
i
/VS2
x
RESET
59
60
61
62
63
64
65
66
67
68
IORDY
DMARQ
/DMACK
/DASP
/PDIAG
DD8
DD9
DD10
/CD2
Ground
o
o
o
x
x
x
x
x
x
x
x 3)
x 3)
o
x
x
x
x
x
x
x
/WAIT
/INPACK
/REG
/BVD2:SPKR
/BVD1:STSCHG
D8
D9
D10
/CD2
Ground
x = Required.
i = Ignored by host in ATA mode.
o = Optional.
nothing = Not connected.
1) Device shall support only one /CS1 signal pin.
2) Device shall support either /M/S or CSEL but not both.
3) Device shall hold this signal negated if it does not support this function.
Contributor: Joakim gren
Source:
ATA-2 specifications
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
Name
+5 V
GND
D0
D2
D4
D6
GND
D8
D10
D12
D14
GND
+5 V
GND
D16
D18
D20
D22
GND
D24
D26
D28
D30
GND
+5 V
GND
T0
T2
T4
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
T6
GND
T8
T10
T12
T14
GND
+5 V
GND
CLK
GND
/TOEN
/TWEN
/ADV
A12
CSIZ(1)
A14
A16
A18
A20
GND
A22
A24
A26
A28
GND
+5 V
GND
D32
D34
D36
D38
GND
D40
D42
D44
D46
GND
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
+5 V
GND
D48
D50
D52
D54
GND
D56
D58
D60
D62
GND
+5 V
+3.3 V
GND
D1
D3
D5
D7
GND
D9
D11
D13
D15
GND
+3.3 V
GND
D17
D19
D21
D23
GND
D25
D27
D29
D31
GND
+3.3 V
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
GND
T1
T3
T5
T7
GND
T9
T11
T13
T15
GND
+3.3 V
GND
CPRES
A11
/DOEN
/DWEN
/ADSC
/CSIZ(2)
GND
A13
A15
A17
A19
GND
A21
A23
A25
A27
GND
+3.3 V
D33
D35
D35
D37
D39
GND
D41
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
D43
D45
D47
GND
+3.3 V
GND
D49
D51
D53
D55
GND
D57
D59
D61
D63
GND
+3.3 V
Name
D0
D1
D2
D3
D4
D5
D6
D7
/CS
IRQ
GND
/RST
GND
ACK
GND
A1
GND
R/W
REQ
Description
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Chip Select
Interrupt Request
Ground
Reset
Ground
Acknowledge
Ground
?
Ground
Read/Write
Data Request
Description
Common/Negative
External inverter shutdown, positive side
line fail, normaly open contact
return/external inverter shutdown negative side
line fail, normaly closed contact
low battery, positive side (2 minute warning)
Name
Dir
Description
This pin is shorted to PIN 5 (ground) if the mains power supply fails
Battery Mode
out
or is out of tolerance. (NORMALLY OPEN)
Ground
Ground terminal and common root of contacts at PIN 1, 8 and 9
If a positive signal level (+5V to +12V DC) is applied, the UPS
UPS shut-down
IN
system switches off (PIN 5 is ground)
This pin is shorted to PIN 5 (ground) if the batteries have been
Battery Capacity Low OUT discharged to such an extent that the remaining stored energy time is
less than 2 minutes. (NORMALLY OPEN)
The connection between this pin and PIN 5 (ground) is disconnected if
Battery Mode
OUT the main power supply fails oe is out of tolerance. (NORMALLY
CLOSED)
Name
FN Pwr
DI-A
DI-B
VCC
CI-A
CI-B
+5V
+5V
DO-A
DO-B
VCC
NC
NC
FN Pwr
Protective Gnd
Description
Power (+12V @ 2.1W or +5V @ 1.9W)
Data In circuit A
Data In circuit B
Voltage Common
Control In circuit A
Control In circuit B
+5 volts (from host)
Secondary +5 volts (from host)
Data Out circuit A
Data Out circuit B
Secondary Voltage Common
Reserved
Reserved
Secondary +12V @ 2.1W or +5V @ 1.9W
Protective Ground
Available on Macintosh Quadra computers, Apple Ethernet NB Card, and LaserWriter IIg printers?
Contributor: Joakim gren
Source:
Apple Tech Info Library 8863 at Apple TIL homepage
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
AUI
Is the directions right???
Description
control in circuit shield
control in circuit A
data out circuit A
data in circuit shield
data in circuit A
voltage common
?
control out circuit shield
control in circuit B
data out circuit B
data out circuit shield
data in circuit B
voltage plus
voltage shield
?
Name Dir
Description
V
+5 Vdc/ 3.3 Vdc
MDIO
MII Data Input/Output
MDC
MII Data Clock
RxD
Rx Data
RxD
Rx Data
RxD
Rx Data
RxD
Rx Data
Rx_DV
Rx Data Valid
Rx_CLK
Rx Clock
Rx_ER
Rx Error
Tx_ER
Tx Error
Tx_CLK
Tx Clock
Tx_EN
Tx Enable
TxD
Tx Data
TxD
Tx Data
TxD
Tx Data
TxD
Tx Data
COL
Collision
CRS
Carrier Sense
V
+5 Vdc/ +3.3 Vdc
V
+5 Vdc/ +3.3 Vdc
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
V
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
+5 Vdc/ +3.3 Vdc
SUN AUI
26 PIN HI-DENSITY D-SUB FEMALE at the motherboard.
26 PIN HI-DENSITY D-SUB MALE at the cable.
Available on the SUN SPARCengine 5 motherboard
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Name
Transmit Receive +
Collision AUI Power
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
Transmit +
Receive Collision +
Ground
N/C
N/C
N/C
N/C
N/C
Ground
Ground
N/C
Ground
Source:
SUN SPARCengine 5 manual at SUN manuals site
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
Ethernet 10/100Base-T
Same connector and pinout for both 10Base-T and 100Base-TX.
Name
TX+
TXRX+
n/c
n/c
RXn/c
n/c
Description
Transmit Data+
Transmit DataReceive Data+
Not connected
Not connected
Receive DataNot connected
Not connected
Ethernet 1000Base-T
1000 Base-T uses all pairs for bidirectional traffic in the RJ45 connector. Cables used should be of
Category 5e(nhanced), even though Category 5 cables usually works too.
Name
BI_DA+
BI_DABI_DB+
BI_DC+
BI_DCBI_DBBI_DD+
BI_DD-
Description
Bi-directional pair A +
Bi-directional pair A Bi-directional pair B +
Bi-directional pair C +
Bi-directional pair C Bi-directional pair B Bi-directional pair D +
Bi-directional pair D -
Ethernet 100Base-T4
100Base-T4 uses all four pairs. 100Base-TX only uses two pairs.
Name
TX_D1+
TX_D1RX_D2+
BI_D3+
BI_D3RX_D2BI_D4+
BI_D4-
Description
Tranceive Data+
Tranceive DataReceive Data+
Bi-directional Data+
Bi-directional DataReceive DataBi-directional Data+
Bi-directional Data-
Note: TX & RX are swapped on Hub's. Don't know about Bi-directional data.
Contributor: Joakim gren, Kim Scholte
Source:
?
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
Network Information
Networking standards
10Base-T (Standard Ethernet)
Speed: 10 Mbit/s
Connectors: RJ45
Cables: Twisted Pair (category 3)
Wiring scheme: EIA/TIA 568B
Maximum cable length: 100 m
Star Topology
Speed: 10 Mbit/s
Connectors: BNC
Speed: 10 Mbit/s
Connectors: N-Type
Cables: RG8
Wiring scheme: EIA/TIA 568B
Maximum cable length: 500 m
Maximum devices per cable segment: 100
Minimum distance between devices: 2.5 m
Bus Topology
Terminators in each end: 50 ohm
TokenRing
Speed: 4 or 16 Mbit/s
Connectors: RJ45 or IBM Data Connector
Cables: Twisted Pair (category 3)
Maximum ring length: 168m at 16Mbit/s, 360 m at 4Mbit/s
Maximum cable length: Depends on ring length and network layout
Maximum devices per network: 72 (UTP) or 250-260 (Type1)
Token based ring Topology (physical star, logical ring)
Cabeling
Twisted Pair
Category type
Category 3
Category 4
Category 5
Category 5 Enhanced
Bandwidth
16 MHz
20 MHz
125 MHz
125 MHz
Typical speed
16 Mbit/s
20 Mbit/s
100 Mbit/s
100 Mbit/s (1000Mbit/s with 1000BaseT)
ECP Parallel
ECP = Extended Capabilities Port
Name
Dir
Description
nStrobe
Strobe
data0
Address, Data or RLE Data Bit 0
data1
Address, Data or RLE Data Bit 1
data2
Address, Data or RLE Data Bit 2
data3
Address, Data or RLE Data Bit 3
data4
Address, Data or RLE Data Bit 4
data5
Address, Data or RLE Data Bit 5
data6
Address, Data or RLE Data Bit 6
data7
Address, Data or RLE Data Bit 7
/nAck
Acknowledge
Busy
Busy
PError
Paper End
Select
Select
/nAutoFd
Autofeed
/nFault
Error
/nInit
Initialize
/nSelectIn
Select In
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
25 GND
Signal Ground
Signal Descriptions:
nStrobe
This signal is registers data or address into the slave on the assering edge during .
data 0-7
Contains address, data or RLE data. Can be used in both directions.
nAck
Valid data driven by the peripheral when asserted. This signal handshakes with nAutoFd in reverse.
Busy
This signal deasserts to indicate that the peripheral can accept data. In forward direction this handshakes
with nStrobe. In the reverse direction this signal indicates that the data is RLE compressed by being low.
PError
Used to acknowledge a change in the direction of transfer. High=Forward.
Select
Printer is online.
nAutoFd
Requests a byte of data from the peripheral when asserted, handshaking with nAck in the reverse
direction. In the forward direction this signal indicates whether the data lines contain ECP address or
data.
nFault
Generates an error interrupt when asserted.
nInit
Sets the transfer direction. High=Reverse, Low=Forward.
nSelectIn
Low in ECP mode.
Contributor: Joakim gren, Rob Gill
Source:
Microsoft MSDN Library: Extended Capabilities Port Specs
Info: Microsoft MSDN Library
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
IEEE1284-B
Name
Dir
Description
nStrobe
Strobe
data0
Address, Data or RLE Data Bit 0
data1
Address, Data or RLE Data Bit 1
data2
Address, Data or RLE Data Bit 2
data3
Address, Data or RLE Data Bit 3
data4
Address, Data or RLE Data Bit 4
data5
Address, Data or RLE Data Bit 5
data6
Address, Data or RLE Data Bit 6
data7
Address, Data or RLE Data Bit 7
/nAck
Acknowledge
Busy
Busy
PError
Paper End
Select
Select
/nAutoFd
Autofeed
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
26
27
28
29
30
31
32
33
34
35
36
GND
GND
GND
GND
GND
/nInit
/nFault
GND
GND
GND
/nSelectIn
Signal Ground
Signal Ground
Signal Ground
Signal Ground
Signal Ground
Initialize
Error
Signal Ground
Signal Ground
Signal Ground
Select In
IEEE1284-C
36 PIN HI-DENSITY CENTRONICS???
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Name
Dir
Description
Busy
Busy
Select
Select
/nAck
Acknowledge
/nFault
Error
PError
Paper End
data0
Address, Data or RLE Data Bit 0
data1
Address, Data or RLE Data Bit 1
data2
Address, Data or RLE Data Bit 2
data3
Address, Data or RLE Data Bit 3
data4
Address, Data or RLE Data Bit 4
data5
Address, Data or RLE Data Bit 5
data6
Address, Data or RLE Data Bit 6
data7
Address, Data or RLE Data Bit 7
/nInit
Initialize
nStrobe
Strobe
/nSelectIn
Select In
/nAutoFd
Autofeed
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
31
32
33
34
35
36
GND
GND
GND
GND
GND
GND
Signal Ground
Signal Ground
Signal Ground
Signal Ground
Signal Ground
Signal Ground
MSX Parallel
Name
/STB
PDB0
PDB1
PDB2
PDB3
PDB4
PDB5
PDB6
PDB7
n/c
BUSY
n/c
n/c
GND
Dir
Description
Strobe
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Printer is busy
-
Signal Ground
Name
Dir
Description
/STROBE
Strobe
D0
Data Bit 0
D1
Data Bit 1
D2
Data Bit 2
D3
Data Bit 3
D4
Data Bit 4
D5
Data Bit 5
D6
Data Bit 6
D7
Data Bit 7
/ACK
Acknowledge
BUSY
Busy
POUT
Paper Out
SEL
Select (Shared with RS232 RING-indicator)
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
+5V
+5 Volts DC (10 mA max)
n/c
Not connected.
/RESET
Reset
Parallel (Amiga)
Name
Dir
Description
/STROBE
Strobe
D0
Data Bit 0
D1
Data Bit 1
D2
Data Bit 2
D3
Data Bit 3
D4
Data Bit 4
D5
Data Bit 5
D6
Data Bit 6
D7
Data Bit 7
/ACK
Acknowledge
BUSY
Busy
POUT
Paper Out
SEL
Select (Shared with RS232 RING-indicator)
+5V PULLUP
+5 Volts DC (10 mA max)
n/c
Not connected.
/RESET
Reset
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
Name
Dir Description
/STROBE
Strobe
D0
Data Bit 0
D1
Data Bit 1
D2
Data Bit 2
D3
Data Bit 3
D4
Data Bit 4
D5
Data Bit 5
D6
Data Bit 6
D7
Data Bit 7
/ACK
Acknowledge
BUSY
Busy
PE
Paper End
SELIN
Select In
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
RESETGND
Reset Ground
26 /RESET
Reset
Parallel (PC)
Name
Dir Description
/STROBE
Strobe
D0
Data Bit 0
D1
Data Bit 1
D2
Data Bit 2
D3
Data Bit 3
D4
Data Bit 4
D5
Data Bit 5
D6
Data Bit 6
D7
Data Bit 7
/ACK
Acknowledge
BUSY
Busy
PE
Paper End
SEL
Select
/AUTOFD
Autofeed
/ERROR
Error
/INIT
Initialize
/SELIN
Select In
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
Parallel (SUN)
Available on SUN SPARCengine motherboards
26 PIN HI-DENSITY D-SUB CONNECTOR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Name
Dir Description
/STROBE
Strobe
D0
Data Bit 0
D1
Data Bit 1
D2
Data Bit 2
D3
Data Bit 3
D4
Data Bit 4
D5
Data Bit 5
D6
Data Bit 6
D7
Data Bit 7
/ACK
Acknowledge
BUSY
Busy
PE
Paper End
SEL
Select
/AUTOFD
Autofeed
/ERROR
Error
/RESET
Reset
/SELIN
Select In
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
GND
Signal Ground
Source:
SUN SPARCengine 5 manual at SUN manuals site
SUN SPARCengine Ultra 20 OEM Manual
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
Name
/STROBE
D0
D1
D2
D3
D4
D5
D6
GND
n/c
BUSY
n/c
n/c
GND
n/c
n/c
n/c
GND
n/c
GND
GND
GND
GND
GND
GND
GND
GND
Description
Strobe
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Ground
Not connected
Busy
Not connected
Not connected
Ground
Not connected
Not connected
Not connected
Ground
Not connected
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
27
28
29
30
31
32
33
34
35
n/c
GND
n/c
n/c
n/c
n/c
GND
n/c
n/c
Not connected
Ground
Not connected
Not connected
Not connected
Not connected
Ground
Not connected
Not connected
Centronics
Name
Dir
Description
/STROBE
Strobe
D0
Data Bit 0
D1
Data Bit 1
D2
Data Bit 2
D3
Data Bit 3
D4
Data Bit 4
D5
Data Bit 5
D6
Data Bit 6
D7
Data Bit 7
/ACK
Acknowledge
BUSY
Busy
POUT
Paper Out
SEL
Select
/AUTOFEED
Autofeed
n/c
Not used
0V
Logic Ground
CHASSIS GND
Shield Ground
+5 V PULLUP
+5 V DC (50 mA max)
GND
Signal Ground (Strobe Ground)
GND
Signal Ground (Data 0 Ground)
GND
Signal Ground (Data 1 Ground)
GND
Signal Ground (Data 2 Ground)
GND
Signal Ground (Data 3 Ground)
GND
Signal Ground (Data 4 Ground)
GND
Signal Ground (Data 5 Ground)
26
27
28
29
30
31
32
33
34
35
36
GND
GND
GND
GND
/GNDRESET
/RESET
/FAULT
0V
n/c
+5 V
/SLCT IN
(at ???)
(at ???)
50 PIN D-SUB MALE at ???.
50 PIN D-SUB FEMALE at ???.
Pin
22
21
23
38
19
20
1
41
34
43
36
28
29
50
49
46
12
27
25
24
Return Dir
Description
6
Ready
5
On Line
7
Demand
37
Data Strobe
3
Data 1
4
Data 2
2
Data 3
40
Data 4
18
Data 5
42
Data 6
35
Data 7
44
Data 8
13
Parity
32
Ident 0
16
Ident 1
47
Interface Verify
39
+5 VDC (Test)
11
Parity Error
9
Bottom of Form
8
Top of Form
Active State
High
High
High
High
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
Low
High
High
High
High
30
31
26
48
47
14
15
10
17
33
Paper Instruction
Buffer Clear
Paper Moving
Paper Moving
Not VFU
High
High
High
High
High
(at ???)
(at ???)
50 PIN M/50 MALE at ???.
50 PIN M/50 FEMALE at ???.
Pin
CC
Y
E
j
B
F
L
R
V
Z
n
Return Dir
Description
EE
Ready
AA
On Line
C
Demand
m
Data Strobe
D
Data 1
J
Data 2
N
Data 3
T
Data 4
X
Data 5
b
Data 6
k
Data 7
Active State
High
High
High
High
n/a
n/a
n/a
n/a
n/a
n/a
n/a
u
z
d
a
v
HH
r
M
S
p
A
W
FF
e
w
BB
f
c
x
K
t
P
U
s
H
Y
DD
h
Data 8
Parity
Ident 0
Ident 1
Interface Verify
+5 VDC (Test)
Parity Error
Bottom of Form
Top of Form
Paper Instruction
Buffer Clear
Paper Moving
Paper Moving
Not VFU
n/a
n/a
n/a
n/a
Low
High
High
High
High
High
High
High
High
High
DEC Printer
(at ???)
(at ???)
37 PIN D-SUB FEMALE at ???.
37 PIN D-SUB MALE at ???.
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Name
DAT<3>
DAT<6>
DAT<7>
Strobe
On Line
Connection
DAVFU
Demand
DAT<1>
Dir
Description
Data Bit 3
Not available
Not available
Not available
Data Bit 6
Data Bit 7
Not available
Data Bit 1
Not available
Not available
Not available
Strobe
Not available
Connection
Not available
Not available
DAVFU
Data Bit 0
Not available
Data Bit 2
Not available
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
DAT<2>
DAT<4>
DAT<5>
DAT<0>
Ground
Ground DAT<0>
Ground DAT<1>
Ground DAT<2>
Ground DAT<3>
Ground DAT<4>
Ground DAT<5>
Ground DAT<6>
Ground DAT<7>
Data Bit 2
Data Bit 4
Data Bit 5
Not available
Data Bit 2
Ground
Ground Data Bit 0
Ground Data Bit 1
Ground Data Bit 2
Ground Data Bit 3
Ground Data Bit 4
Ground Data Bit 5
Ground Data Bit 6
Ground Data Bit 7
Not available
Not available
Name
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
SERIAL CONTROL DATA
(Reserved)
SERIAL CONTROL CLOCK
(Reserved)
(Reserved)
CLOCK GROUND
CLOCK
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
+12
+5
-12
(Reserved)
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
(Reserved)
DATA(7) GROUND
DATA(7)
DATA(6) GROUND
DATA(6)
DATA(3)
DATA(3) GROUND
DATA(4)
DATA(4) GROUND
DATA(5)
DATA(5) GROUND
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
DATA(0)
DATA(0) GROUND
DATA(1)
DATA(1) GROUND
DATA(2)
DATA(2) GROUND
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
IEEE488
Name
DIO1
DIO2
DIO3
DIO4
EOI
DAV
NRFD
NDAC
IFC
SRQ
ATN
DIO5
DIO6
DIO7
DIO8
REN
Description
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
End Or Indentity
Data Valid
Not Ready For Data
No Data Accepted
Interface Clear
Service Request
Attention
Shield
Data Bit 5
Data Bit 6
Data Bit 7
Data Bit 8
Remote Enabled
Ground DAV
Ground NRFD
Ground NDAC
Ground IFC
Ground SRQ
Ground ATN
Logical Ground
Source
Talker
Talker
Talker
Talker
Talker/Controller
Controller
Listener
Listener
Controller
Talker
Controller
Talker
Talker
Talker
Talker
Controller
-
Data Lines:
Name
Description
DIO1 to DIO8 Data Input Output
Handshake Lines:
Name
Description
DAV Data Valid
NRFD Not Ready For Data
NDAC Not Data Accepted
Description
Attention
Interface Clear
Remote Enable
Service Request
End or Identify
3.5" Power
Used for floppies.
Name according to the ATX standard: Floppy Drive Connector.
Name
+5V
GND
GND
+12V
Color
Red
Black
Black
Yellow
Description
+5 VDC
+5 V Ground
+12 V Ground (Same as +5 V Ground)
+12 VDC
5.25" Power
Used for harddisks & 5.25" peripherals.
Name according to the ATX standard: Peripheral Connector.
Name
+12V
GND
GND
+5V
Color
Yellow
Black
Black
Red
Description
+12 VDC
+12 V Ground (Same as +5 V Ground)
+5 V Ground
+5 VDC
AT Backup Battery
Name
BATT+
key
GND
GND
Description
Battery+
Key
Ground
Ground
AT LED/Keylock
Name
LED
GND
GND
KS
GND
Description
LED Power
Ground
Ground
Key Switch
Ground
Name
GND
+12V
GND
Motherboard IrDA
For motherboards with a IrDA compliant Infrared Module connector.
1 2 3 4 5
. . . . .
5 PIN IDC MALE at the motherboard.
Pin
1
2
3
4
5
Name
+5v
n/c
IRRX
GND
IRTX
Description
Power
Not connected
IR Module data received
System GND
IR Module data transmit
Motherboard Power
(at the Computer)
P8
Pin
1
2
3
4
5
6
Name
PG
+5V
+12V
-12V
GND
GND
Color
Orange
Red
Yellow
Blue
Black
Black
Description
Power Good, +5 VDC when all voltages has stabilized.
+5 VDC (or n/c)
+12 VDC
-12 VDC
Ground
Ground
P9
Pin
1
2
3
4
5
6
Name
GND
GND
-5V
+5V
+5V
+5V
Color
Black
Black
White or Yellow
Red
Red
Red
Description
Ground
Ground
-5 VDC
+5 VDC
+5 VDC
+5 VDC
PC Speaker
Name
-SP
key
GND
+SP5V
Description
-Speaker
Key
Ground
+Speaker +5 VDC
Turbo LED
Name
+5V
/HS
+5V
Description
+5 VDC
HighSpeed
+5 VDC
Name
+5V
+5V
+5V
+5V
GND1
GND2
GND3
GND4
+12V
KEY
-12V
+5V USER
-5V
TICK
You will be able to tell the orientation with the help of pin 10, it is missing.
Note: TICK is NOT found on PC power supplies
Contributor: Joakim gren
Source:
Amiga Power Supply pinouts at National Amiga
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-08
Name
+VID
+5V
+5V
+5V
GND
GND
GND
GND
GND
-5V
+5V USER
TICK
-12V/-12V USER
+12V/+12V USER
Name
TICK
-12V
-5V
GND
GND
GND
GND
GND
+5V
+5V
+5V
+5V
FAIL
+12V
+12V
+5V USER
GND
GND
GND
GND
+5V
+5V
+5V
+5V
Source:
Amiga Power Supply pinouts at National Amiga
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-08
Name
+5V
Shield Ground
+12V
Signal Ground
-12V
(at ???)
6 PIN MOLEX 90331-0010 at ???
Pin
1
2
3
4
5
6
Name
COM
COM
COM
3.3V
3.3V
5V
Color
Black
Black
Black
Orange
Orange
Red
Description
Ground
Ground
Ground
+3.3 VDC
+3.3 VDC
+5 VDC
Name
FanM
FanC
3.3V Sense
1394R
1394V
Reserved
Color
White
White/Blue
White/Brown
White/Black
White/Red
n/a
Description
Fan Monitor
Fan Control
3.3V Sense Line
IEEE-1394 Ground
IEEE-1394 Voltage?
Name
3.3V
3.3V
COM
5V
COM
5V
COM
PWR_OK
5VSB
12V
3.3V
-12V
COM
/PS_ON
COM
COM
COM
-5V
5V
5V
Color
Orange
Orange
Black
Red
Black
Red
Black
Gray
Purple
Yellow
Orange
Blue
Black
Green
Black
Black
Black
White
Red
Red
Description
+3.3 VDC
+3.3 VDC
Ground
+5 VDC
Ground
+5 VDC
Ground
Power Ok (+5V & +3.3V is ok)
+5 VDC Standby Voltage (max 10mA)
+12 VDC
+3.3 VDC
-12 VDC
Ground
Power Supply On (active low)
Ground
Ground
Ground
-5 VDC
+5 VDC
+5 VDC
18 AWG is recommended for all wires except pin 11, which should be 22 AWG
Name
Reserved
Fan On/Off
Reserved
Reserved
Reserved
Reserved
Color Description
n/a
White/Blue Fan Control
n/a
n/a
n/a
n/a
Name
3.3V
3.3V
COM
5V
COM
5V
COM
PWR_OK
5VSB
12V
3.3V
-12V
COM
/PS_ON
COM
COM
COM
res
5V
5V
Color
Orange
Orange
Black
Red
Black
Red
Black
Gray
Purple
Yellow
Orange
Blue
Black
Green
Black
Black
Black
Red
Red
Description
+3.3 VDC
+3.3 VDC
Ground
+5 VDC
Ground
+5 VDC
Ground
Power Ok (+5V & +3.3V is ok)
+5 VDC Standby Voltage (max 10mA)
+12 VDC
+3.3 VDC
-12 VDC
Ground
Power Supply On (active low)
Ground
Ground
Ground
Reserved
+5 VDC
+5 VDC
18 AWG is recommended for all wires except pin 11, which should be 22 AWG
For 300W configurations 16 AWG is recommended.
Contributor: Joakim gren
Source:
?
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-08
Name
12Vdig
12Vdig
12Vdig
12Vdigsen
com
com
com
12Vdigsenrtn
Color
Description
White +12 VDC (Digital)
White +12 VDC (Digital)
White +12 VDC (Digital)
Sense +12 VDC (Digital) (Optional?)
Black Ground
Black Ground
Black Ground
Ground Sense +12 VDC (Digital) (Optional?)
AWG
18
18
18
18
18
18
Name
12Vcpu#
12Vcpu#
12Vcpu#
com
com
com
Color
White
White
White
Black
Black
Black
Description
+12 VDC (CPU)
+12 VDC (CPU)
+12 VDC (CPU)
Ground
Ground
Ground
AWG
18
18
18
18
18
18
Name
5Vsense
3.3Vsense
res
com
com
12Vio
-12V
I2C clk
FanC
PS-OK
res
5Vsensertn
3.3Vsensertn
res
com
12Vio
12Vio
sleep
I2C data
FanM
PS-on
res
Color
Description
Red
Sense +5 VDC
Orange Sense +3.3 VDC
reserved
Black Ground
Black Ground
Yellow +12 VDC (I/O)
Blue -12 VDC
I2C Clock (optional?)
Purple Fan Control
Grey PoweSupply Ok
reserved
Black Ground Sense +5 VDC
Black Ground Sense +3.3 VDC
reserved
Black Ground
Yellow +12 VDC (I/O)
Yellow +12 VDC (I/O)
White Sleep
I2C Data (Optional?)
Brown Fan Monitor
Green PowerSupply On
reserved
AWG
22
22
18
18
18
18
?
22
22
22
22
18
18
18
18
?
22
22
Name
3.3V
3.3V
3.3V
3.3V
3.3V
com
com
com
com
com
5V
5V
3.3V
3.3V
3.3V
3.3V
3.3Vaux
com
com
com
com
5Vsb
5V
5V
Color
Orange
Orange
Orange
Orange
Orange
Black
Black
Black
Black
Black
Red
Red
Orange
Orange
Orange
Orange
Brown
Black
Black
Black
Black
Purple
Red
Red
Description
+3.3 VDC
+3.3 VDC
+3.3 VDC
+3.3 VDC
+3.3 VDC
Ground
Ground
Ground
Ground
Ground
+5 VDC
+5 VDC
+3.3 VDC
+3.3 VDC
+3.3 VDC
+3.3 VDC
+3.3 VDC Auxilary
Ground
Ground
Ground
Ground
+5 VDC Standby
+5 VDC
+5 VDC
AWG
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
20
18
18
18
18
20
18
18
Name
+12 volts
+ 5 volts
+ 5 volts
/VSYNC
/HSYNC
VIDOUT
Sound
-12 volts
PWM (Brightness control signal)
Ground
Ground
Ground
Ground
Ground
Name
Shield Ground
Shield Ground
Shield Ground
Not connected
+5v In
9Vac in
9Vac in
SUN Power
18 PIN MOLEX 39-29-9182 CONNECTOR at the motherboard
Available on the SUN SPARCengine 5 motherboard
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Description
+12
-12
+5
+5
+5
+5
+5
+5
Power off
Ground
Ground
Ground
Ground
Ground
Ground
AC Outlet
Fan
Power on
Name
+3.3V
GND
+3.3V
GND
+3.3V
GND
+3.3V
GND
PWR_SENSE_3.3V
GND
PWR_SENSE_GND
+12V
+5V
GND
+5V
GND
+5V
GND
+5V
GND
PWR_SENSE_5V
GND
PWR_SENSE_GND
-12V
Name
n/c
DSR
GND
n/c
RxD
DTR
DCD
GND
TxD
Description
Not connected
Data Set Ready
Ground
Not connected
Receive Data
Data Terminal Ready
Output from modem
Ground
Transmit Data
Name
LINET/R
DAA GND
DAA GND
DAA GND
/RA DVR
DAA ID IN
/RING3 DET
/RBDVR
DAA CNTL
+5 V MODEM
Description
Line/talk receive
Modem DAA ground
Modem DAA ground
Modem DAA ground
Modem relay A driver
ID input
Ring detect signal
Modem relay B driver
Modem DAA control
+5 V power
When the PowerBook Duo computer is housed in the Duo Dock, you cannot access the integral modem
via the RJ-11 connector on the PowerBook Duo's rear panel. A modem adapter card provides the
connection. It plugs into the side of the Duo Dock's main logic board, using a 10-pin header connector.
The card supplies the RJ-11 hook up, which is accessed on the rear panel of the Duo Dock. The adapter
card interfaces with the modem card in the PowerBook Duo computer via its 10-pin connector, printed
circuit traces, and the 152-pin expansion connector.
Contributor: Joakim gren
Source:
Apple Tech Info Library 12929: Duo Dock/Duo Dock II, External Pinouts at Apple TIL homepage
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2000-07-09
Name Dir
Description
GND
Ground
SD
Send Data
RD
Receive Data
RTS
Request To Send
GND
Ground
FAULTFalse when deselected
DTR
Data Terminal Ready
Name Dir
Description
GND
Ground
n/c
Not connected
GND
Ground
TXD+
Transmit Data +
TXDTransmit Data n/c
Not connected
RXCLK
TRxC of Zilog 8530
RXD+
Receive Data +
RXDReceive Data -
Name Dir
Description
GND
Ground
TXDTransmit Data
RXDReceive Data
RTS
Request To Send
CTS
Clear To Send
DSR
Data Set Ready
GND
Ground
DCD
Data Carrier Detect
DTRData Terminal Ready
RING
?
Name
GND
TxD
RxD
RTS
CTS
DSR
GND
DCD
n/c
n/c
n/c
n/c
n/c
n/c
TxC
n/c
RxC
n/c
n/c
n/c
n/c
n/c
n/c
TEXT
n/c
Description
Ground
Transmit Data line
Receive Data line
Request To Send
Clear To Send
Data Set Ready
Ground
Data Carrier Detect
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Connected to TRxCA
Not connected
Connected to RTxCA
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Connected to TRxCA
Not connected
Name
GND
TxDRxDn/c
n/c
HSK/DSR
GND
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
RxD+
TxD+/DTR
n/c
n/c
n/c
n/c
n/c
Description
Ground
Transmit Data line
Receive Data line
Not connected
Not connected
TRxCB or CTSB
Ground
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Receive Data line
Connected to DTRB
Not connected
Not connected
Not connected
Not connected
Not connected
AppleLine RS232
Name
Dir
SNG
TXD
RCD
RTS
CTS
DSR
GND
DCD
n/c
n/c
n/c
CH
n/c
n/c
n/c
n/c
n/c
n/c
n/c
DTR Terminal Ready Signal, Out
n/c
CE
n/c
n/c
n/c
Description
Shield ground
Tx Transmit Data, Out
Rx Receive Data, In
Request to Send, Out
Clear to Send, In
Data Set Ready, In
Ground
Data Carrier Detect, In
No connection
No connection
No connection
Data signal rate selector, In
No connection
No connection
No connection
No connection
No connection
No connection
No connection
No connection
Ring indicator, In
No connection
No connection
No connection
Name
/SRQIN
GND
ATN
CLK
DATA
/RESET
Description
Serial SRQIN
Ground
Serial ATN In/Out
Serial CLK In/Out
Serial DATA In/Out
Reset
Name
RTS
DTR
TXD
n/c
n/c
RXD
DSR
CTS
Description
Dir
Request To Send
Data Terminal Ready
Tranceive Data
Not connected
Not connected
Receive Data
Data Set Ready
Clear To Send
Name
Description
NC
/BUSY Enabled when the printer is busy
GND
DATA RS-232 level data
Name
RTS
RXD
TXD
DTR
GND
Description
Dir
Request To Send
Receive Data
Transmit Data
Data Terminal Ready
Ground
Note: Since the multimeter is a DCE the pin naming can seem strange.
Contributor: Joakim gren, Anselm Belz
Source:
?
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-08
DCE
DCE is acronym for Data Communication Equipment.
Examples of DCE is modems.
Wiring
Wiring a cable for DTE to DCE communication is easy. All wires goes straight from pin x to pin x.
But wiring a cable for DTE to DTE (nullmodem) or DCE to DCE requires that some wires are crossed. A
signal should be wired from pin x to the opposite signal at the other end. With opposite signals means for
example Transmit & Receive.
Contributors: Joakim gren, Richard L. Lane, Rob Gill
Source:
?
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-08
Audio/Video
Home Audio/Video
Amiga to SCART
C128/C64C to SCART (S-Video)
NeoGeo to SCART
Video to TV SCART
Video
9 to 15 pin VGA
Amiga to C1084 Monitor
C128/C64C to CBM 1902A Monitor
Loopback plugs
Parallel
Parallel Port Loopback (CheckIt)
Parallel Port Loopback (Norton)
Serial
Serial Port Loopback (25 CheckIt)
Serial Port Loopback (25 Norton)
Serial Port Loopback (9 CheckIt)
Serial Port Loopback (9 Norton)
Misc
MIDI
MIDI
Serial
Mac to HP48
Misc Unsupported Cables
Networks
AUI
AAUI to AUI
Ethernet AUI to AUI
Ethernet
Ethernet 10/100/1000Base-T and 100Base-T4 Crossover
Ethernet 10/100/1000Base-T Straight Thru
Parallel
64NET
C64 Centronics Printer
GEOCable
LapLink/InterLink Parallel
ParNet Parallel
ParaLoad
Printer
Serial
Information
Defintion: DTE & DCE
Modem (Straight)
Mac to C64 Nullmodem
Macintosh Modem (With DTR)
file:///C|/tmp/tech/HwB/cable/index.html (2 of 4) [6/15/2001 12:01:29 AM]
Nullmodem (Crossed)
Mac to C64 Nullmodem
Nullmodem (25-25)
Nullmodem (9-25)
Nullmodem (9-9)
Cisco Console (25)
Cisco Console (9)
Conrad Electronics MM3610D (25)
Conrad Electronics MM3610D (9)
RocketPort Serial (25)
Serial Printer (25-25)
Serial Printer (9-25)
Storage
Floppy
Floppy
X1541
Harddrive
ESDI
ST506/412
IDE/ATA
IDE
Paravision SX1 to IDE
SCSI
SCSI Cable (Amiga/Mac)
SCSI Cable (D-Sub to Hi D-Sub)
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
Short tutorial
Heading
First at each page there a short heading describing the cable.
Pin table
The pin table is perhaps the information you are looking for. Should be simple to read. Contains mostly
the following three columns; Name, Pin 1, Pin 2. Sometimes when not the same pin is connected to each
side there is another column describing the name at connector 2.
Strobe
Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7
...
25-DSub
1
2
3
4
5
6
7
8
9
...
36-Cen
1
2
3
4
5
6
7
8
9
...
Amiga to SCART
RGB Red In
RGB Green In
RGB Blue In
Video In
Video GND
Blanking GND
Blanking (Connect via a 150 Ohm resistor)
Audio/RGB switch (Connect via a 1 kOhm resistor)
Phono Right
Phono Right GND
2
4
Audio IN Right
GND
Phono Left
Phono Left GND
6
4
Audio IN Left
GND
Analog Red
Analog Green
Analog Blue
Composite Sync
Video GND
GND
+12V
+12V
Amiga
3
4
5
10
17
19
22
22
TV
20
15
4+17
2+6
LUM
CHROMA
GND
AUDIO
NeoGeo to SCART
(To the Computer)
TV
6+2
18
20
16
11
15
7
Audio In Left+Right
Blanking Signal Ground
Composite Video In
Blanking Signal
RGB Green In
RGB Red In
RGB Blue In
Video to TV SCART
TV
1
2
3
6
4
VCR
2
1
6
3
4
Audio Right In
Audio Right Out
Audio Left In
Audio Left Out
Audio Ground
Red
Red Ground
Green
Green Ground
Blue
Blue Ground
15
13
11
9
7
5
15
13
11
9
7
5
Red
Red Ground
Green
Green Ground
Blue
Blue Ground
Status / 16:9
Reserved
Reserved
Fast Blanking Ground
Fast Blanking
Video Out Ground
Video In Ground
Video Out
Video In
Ground
8
10
12
14
16
17
18
19
20
21
8
10
12
14
16
18
17
20
19
21
Status / 16:9
Reserved
Reserved
Fast Blanking Ground
Fast Blanking
Video In Ground
Video Out Ground
Video In
Video Out
Ground
9 to 15 pin VGA
15-Pin
1
2
3
13
14
6
7
8
10 + 11
C1084
4
1
5
2
3
R
G
B
HSYNC
GND
C1902A
6
4
3
2
LUM
CHROMA
GND
AUDIO
(To Computer).
25 PIN D-SUB MALE to Computer.
Name
Busy
Acknowledge
Paper end
Select
Data Bit 0
Pin
11
10
12
13
2
Pin
17
16
14
1
15
Name
Select Input
Initialize
Auto Feed
Strobe
Error
(To Computer).
25 PIN D-SUB MALE to Computer.
Name
Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Pin
2
3
4
5
6
Pin
15
13
12
10
11
Name
Error
Select
Paper Out
Acknowledge
Busy
(To Computer).
25 PIN D-SUB FEMALE to Computer.
Name
Jumpering 1
Jumpering 2
Jumpering 3
Pin
2
4
6
(To Computer).
25 PIN D-SUB FEMALE to Computer.
Name
Jumpering 1
Jumpering 2
Jumpering 3
Pin
2
4
6
(To Computer).
9 PIN D-SUB FEMALE to Computer.
Name
CD
CD
RXD
DTR
RTS
Pin
1
1
2
4
7
Pin
6
9
3
6
8
Name
DSR
RI
TXD
DSR
CTS
(To Computer).
9 PIN D-SUB FEMALE to Computer.
Name
Jumpering 1
Jumpering 2
Jumpering 3
Pin
2
7
1
MIDI
(to the 1st peripheral)
2nd
2
4
5
Note: Although that pin 2 only is connected at MIDI Out it's simpler to connect it to both ends.
Contributor: Joakim gren
Source:
?
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
Mac to HP48
(at the Computer)
HP48
3
5
4+8
SHIELD SHIELD
RxD
TxD
GND
Shield
23 Pin
16
16
9
8
9
6
11
12
23
Comment
AAUI to AUI
Is the directions right???
AAUI
5
9
shell
2
4
shell
6
10
shell
3
1
shell
AUI
2
3
4
5
6
8
9
10
11
12
13
14
AUI1
3
5
10
12
AUI2
5
3
12
10
Name
RxD A
TxD A
RxD B
TxD B
Pin
Vc
6
Collision Detect B 9
Contributor: Ren Guzmn
Source:
Usenet posting by Andrew J V Yeomans
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-08
NIC1
1
2
3
4
5
6
7
8
Color
White/Orange
Orange
White/Green
Blue
White/Blue
Green
White/Brown
Brown
NIC2
3
6
1
7
8
2
4
5
Name
RX+ (BI_DB+)
RX- (BI_DB-)
TX+ (BI_DA+)
- (BI_DD+)
- (BI_DD-)
TX- (BI_DA-)
- (BI_DC+)
- (BI_DC-)
That means that the white/orange cable connected to NIC 1 pin 1 should go to NIC 2 pin 3 and NIC 1 pin
2 to NIC 2 pin 6 etc.
Note 1: It's important that each pair is kept as a pair. TX+ & TX- must be in the pair, and RX+ & RXmust together in another pair. (Just as the table above shows).
Note 2: While 10Base-T and 100Base-TX only uses 2 pairs, please connect all four since 100Base-T4
and 1000Base-T needs them and save yourself some future debugging :)
Note 3: The colors originate from the numbering and name on NIC1.
Contributors: Joakim gren, Niklas Edmundsson, Jim C?, Jason D. Pero, Oscar Fernandez Sierra, Cayce Balara, Jeffrey
R. Broido, Patrick Smart, Jeffrey R. Broido, Kim Scholte
Source:
IEEE Std 802.3, 2000 Edition
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
(To hub).
RJ45 MALE CONNECTOR to network interface card).
RJ45 MALE CONNECTOR to hub).
Name
TX+
TXRX+
RX-
Pin
1
2
3
4
5
6
7
Cable Color
White/Orange
Orange
White/Green
Blue
White/Blue
Green
White/Brown
Pin
1
2
3
4
5
6
7
Name
TX+
TXRX+
RX-
Brown
Note: It's important that each pair is kept as a pair. TX+ & TX- must be in the pair, and RX+ & RXmust together in another pair. (Just as the table above shows).
Just for your information, this is how the pairs are named:
Pair
1
2
3
4
Pins
4&5
1&2
3&6
7&8
Common color
Blue
Orange
Green
Brown
The + side of each pair is called the "tip" and the - side is called the "ring", a reference to old telephone
connectors.
Contributor: Joakim gren, Oscar Fernandez Sierra, Jeffrey R. Broido
Source:
?
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
64NET
(To C64).
(To PC).
DZM 12 DREH to the C64 UserPort.
25 PIN D-SUB MALE to the PC
GND
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
C64 Dir PC
A
25 GND
C
10 /ACK
D
11 BUSY
E
12 PE
F
5 D3
H
6 D4
J
7 D5
K
8 D6
L
9 D7
GEOCable
Printer
33
11
2
3
4
5
6
7
8
9
1
16
Ground
Busy
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
Strobe
Ground
LapLink/InterLink Parallel
Will work with:
LapLink from Travelling Software
MS-DOS v6.0 InterLink from Microsoft
Windows 95 Direct Cable connection from Microsoft
Norton Commander v4.0 & v5.0 from Symantec
Pin
2
3
4
5
6
10
11
12
13
15
16
17
25
Pin
15
13
12
10
11
5
6
4
3
2
16
17
25
Name
Error
Select
Paper Out
Acknowledge
Busy
Data Bit 3
Data Bit 4
Data Bit 2
Data Bit 1
Data Bit 0
Reset
Select
Signal Ground
?
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
ParNet Parallel
Pin
Pin
Name
2
2
Data Bit 0
3
3
Data Bit 1
4
4
Data Bit 2
5
5
Data Bit 3
6
6
Data Bit 4
7
7
Data Bit 5
8
8
Data Bit 6
9
9
Data Bit 7
10+13 10+13 Acknowledge + Select
11
11
Busy
12
12
Paper Out
17-25 17-25 Signal Ground
ParaLoad
(To C64).
(To Amiga).
DZM 12 DREH at the C64 UserPort.
25 PIN D-SUB MALE at the Amiga
C64
Ground A
FLAG2 B
PB0
C
PB1
D
PB2
E
PB3
F
PB4
H
PB5
J
PB6
K
PB7
L
PA2
M
Amiga
17-25
1
2
3
4
5
6
7
8
9
11
Ground
Strobe
D0
D1
D2
D3
D4
D5
D6
D7
Busy
Printer
25-DSub
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
36-Cen
1
2
3
4
5
6
7
8
9
10
11
12
13
14
32
31
36
33
19,20
21,22
23,24
Signal Ground
Signal Ground
Signal Ground
Signal Ground
Shield
22
23
24
25
Shield
25,26
27
28,29
30,16
Shield+17
RTS+DTR
CTS
TxD
RxD
GND
DCD
RTS
CTS
TxD
RxD
GND
DSR+DTR
Modem (25-25)
This cable should be used for DTE to DCE (for instance computer to modem) connections with hardware
handshaking.
(To Computer).
(To Modem).
25 PIN D-SUB FEMALE to the Computer
25 PIN D-SUB MALE to the Modem
Female
Shield Ground
1
Transmit Data
2
Receive Data
3
Request to Send
4
Clear to Send
5
Data Set Ready
6
System Ground
7
Carrier Detect
8
Data Terminal Ready 20
Ring Indicator
22
Male Dir
1
2
3
4
5
6
7
8
20
22
Modem (9-15)
This cable should be used to connect an internal 14.4kbps Speedster modem to a computer.
(To Computer).
15 pin Dir
11
13
12
10
1+8+15
3
4
5
6
Modem (9-25)
This cable should be used for DTE to DCE (for instance computer to modem) connections with hardware
handshaking.
(To Computer).
(To Modem).
9 PIN D-SUB FEMALE to the Computer
25 PIN D-SUB MALE to the Modem
Female Male Dir
Shield
1
Transmit Data
3
2
Receive Data
2
3
Request to Send
7
4
Clear to Send
8
5
Data Set Ready
6
6
System Ground
5
7
Carrier Detect
1
8
Data Terminal Ready 4
20
Ring Indicator
9
22
Contributor: Joakim gren, Sren Graversen
Source:
?
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-08
Nullmodem (25-25)
Use this cable between two DTE devices (for instance two computers).
D-Sub 2
2
3
6+8
7
20
5
4
Transmit Data
Receive Data
Data Set Ready + Carrier Detect
System Ground
Data Terminal Ready
Clear to Send
Request to Send
Note: DSR & CD are jumpered to fool the programs to think that they are online.
Contributor: Joakim gren, Drew Sullivan, Niklas Edmundsson, Don Rifkin, Richard Marker
Source:
?
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-08
Nullmodem (9-25)
Use this cable between two DTE devices (for instance two computers).
D-Sub 25
2
3
6+8
7
20
5
4
Transmit Data
Receive Data
Data Set Ready + Carrier Detect
System Ground
Data Terminal Ready
Clear to Send
Request to Send
Note: DSR & CD are jumpered to fool the programs to think that they are online.
Contributor: Joakim gren, Drew Sullivan, Niklas Edmundsson, Don Rifkin
Source:
?
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-08
Nullmodem (9-9)
Use this cable between two DTE devices (for instance two computers).
D-Sub 2
3
2
6+1
5
4
8
7
Transmit Data
Receive Data
Data Set Ready + Carrier Detect
System Ground
Data Terminal Ready
Clear to Send
Request to Send
Note: DSR & CD are jumpered to fool the programs to think that they are online.
Contributor: Joakim gren, Drew Sullivan, Niklas Edmundsson, Don Rifkin
Source:
?
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-08
(To Computer).
(To Modem).
25 PIN D-SUB FEMALE to the Computer
25 PIN D-SUB MALE to the Modem
Shield Ground
Transmit Data
Receive Data
System Ground
Female
1
2
3
7
Jumper these:
Request to Send
Clear to Send
4
5
Male Dir
1
2
3
7
4
5
6
8
20
?
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-08
(To Computer).
(To Modem).
9 PIN D-SUB FEMALE to the Computer
25 PIN D-SUB MALE to the Modem
Shield Ground
Transmit Data
Receive Data
System Ground
Jumper these:
Request to Send
Clear to Send
7
8
4
5
6
8
20
?
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-08
(To Computer).
Male Dir
6
3
8
1
2
7
(To Computer).
Male Dir
3
6
7
2
8
1
(To PC).
(To multimeter).
25 PIN D-SUB FEMALE to PC.
5 PIN UNKNOWN CONNECTOR to the multimeter
PC
Request To Send
4
Receive Data
3
Transmit Data
2
Data Terminal Ready 20
Ground
7
Conrad Dir
1
2
3
4
5
(To PC).
(To multimeter).
9 PIN D-SUB FEMALE to PC.
5 PIN UNKNOWN CONNECTOR to the multimeter
PC
Request To Send
7
Receive Data
2
Transmit Data
3
Data Terminal Ready 4
Ground
5
Conrad Dir
1
2
3
4
5
RJ45
1
2
3
3
6
6
7
8
D-Sub Dir
4
20
7
2
3
8
6
5
(To Computer).
(To Printer).
25 PIN D-SUB FEMALE to Computer.
25 PIN D-SUB FEMALE to Printer.
D-Sub 1
Receive Data
2
Transmit Data
3
Clear To Send + Data Set Ready
5+6
Carrier Detect + Data Terminal Ready 8 + 20
Ground
7
D-Sub 2
3
Transmit Data
2
Receive Data
20
Data Terminal Ready
7
Ground
(To Computer).
(To Printer).
9 PIN D-SUB FEMALE to Computer.
25 PIN D-SUB FEMALE to Printer.
D-Sub 1
Receive Data
3
Transmit Data
2
Clear To Send + Data Set Ready
8+6
Carrier Detect + Data Terminal Ready 1 + 4
Ground
5
D-Sub 2
3
Transmit Data
2
Receive Data
20
Data Terminal Ready
7
Ground
Floppy
The original floppy cable required that each drive was jumpered to the right ID. But IBM come up with
an idea to avoid jumpering the floppies.
If wire 10-16 are twisted before the last connector the jumpering is avoided. Each drive should be
jumpered to act as Drive 2. If only one drive is used then leave the middle connector free.
The IDC could also be an edge connector on some old drives.
Controller
Drive 2
Twist
Drive 1
+--+
+--+
+--+
|::|===================| |============| | <-Pin 1
|::|===================| |=====\/=====| |
|::|===================| |=====/\=====| |
|::|===================| |============| |
|::|===================| |============| |
|::|===================| |============| |
|::|===================| |============| |
+--+
+--+
+--+
Controller
1-9
10
11
12
Drive 1
1-9
16
15
14
Drive 2
1-9
10
11
12
Wire 13
Wire 14
Wire 15
Wire 16
Wire 17-34
13
14
15
16
17-34
13
12
11
10
17-34
13
14
15
16
17-34
X1541
Used to transfer data from a Commodore 1541/1581 diskdrive to a PC. The X1541 software is written by
Leopoldo Ghielmetti.
Diskdrive
2
3
4
5
6
GND
ATN
CLOCK
DATA
RESET
ESDI
The ESDI interface requires two cables, one for control and one for data. The control cable is shared
between the two drives. But each drive has each own data cable. By twisting some wires on the control
cable it won't be necessary to set the ID for each drive, since the twist will do the job. Wires 25 to 29
should be twisted between drive 1 & drive 2.
Controller
Drive 2
Twist
Drive 1
+--+
+--+
+--+
|::|===================| |============| | <-Pin 1
|::|===================| |============| |
|::|===================| |============| |
|::|===================| |============| |
|::|===================| |=====\/=====| |
|::|===================| |=====/\=====| |
|::|===================| |============| |
+--+
+--+
+--+
Control cable
Wire 26
Wire 27
Wire 28
Wire 29
Wire 30-34
26
27
28
29
30-34
28
27
26
25
30-34
26
27
28
29
30-34
Data cable
ST506/412
The ST506/412 interface requires two cables, one for control and one for data. The control cable is
shared between the two drives. But each drive has each own data cable. By twisting some wires on the
control cable it won't be necessary to set the ID for each drive, since the twist will do the job. Wires 25 to
29 should be twisted between drive 1 & drive 2.
Controller
Drive 2
Twist
Drive 1
+--+
+--+
+--+
|::|===================| |============| | <-Pin 1
|::|===================| |============| |
|::|===================| |============| |
|::|===================| |============| |
|::|===================| |=====\/=====| |
|::|===================| |=====/\=====| |
|::|===================| |============| |
+--+
+--+
+--+
Control cable
Wire 26
Wire 27
Wire 28
Wire 29
Wire 30-34
26
27
28
29
30-34
28
27
26
25
30-34
26
27
28
29
30-34
Data cable
IDE
The IDE interface requires only one cable. All pins straight from 1 to 1, 2 to 2 and so on. The drives can
be connected in any order. Only remember that one should be jumpered as Master and the other as Slave.
If only one drive is used, jumper it as Single (if such a mode exists, or most common Master else).
Controller
Drive 1 or 2
Drive 1 or 2
+--+
+--+
+--+
|::|===================|::|============|::| <-Pin 1
|::|===================|::|============|::|
|::|===================|::|============|::|
|::|===================|::|============|::|
|::|===================|::|============|::|
|::|===================|::|============|::|
|::|===================|::|============|::|
+--+
+--+
+--+
D-Sub
1
2
3
4
5
6
7
8
9
10
11+12
13+14
15+16
17
18
19
20
21
22
IDC
1
17
13
9
5
2
4
8
12
16
19
22
24
26
n/c
n/c
30
21
22
Data bit 5
Data bit 7
Ground
Data bit 9
Data bit 11
Data bit 13
Data bit 15
I/O Write
I/O Read
Interrupt Request
Address bit 2
Address bit 1
Address bit 0
Chip Select 1
Chip Select 0
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
23
24
40
26
27
28
29
23
25
31
36
33
35
38
37
Note: Pin 18+19 (+5V) can be used to power the harddisk. But most harddisks require both +5V and
+12V.
Contributor: Joakim gren
Source:
?
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
IDC
48
42
50
40
38
36
2
8
12
14
16
46
32
44
18
4
6
10
26
Note: All the other pins (7+9+14+16+18+24) at the DSub should be connected to the all odd pins
except 25 at the IDC connector.
file:///C|/tmp/tech/HwB/cable/storage/scsiamigamac.html (1 of 2) [6/15/2001 12:01:48 AM]
Hi DSub
49
46
50
45
44
43
26
29
31
32
33
48
41
47
34
27
28
30
38
Note: All the other pins (7+9+14+16+18+24) at the DSub should be connected to pins 1-25 at the
Hi-density D-Sub connector.
file:///C|/tmp/tech/HwB/cable/storage/scsidsubtohidsub.html (1 of 2) [6/15/2001 12:01:48 AM]
Name Dir
Description
CLK ?
Clock
GND
Ground
TXD+
Transmit data +
TXDTransmit data - (0V for RS-232, Reader enable for 20mA)
GND
Ground
n/c
Not connected (no pin)
RXDReceive data RXD+
Receive data +
GND
Ground
+12V
+12 VDC
24
25 2
n/c
RI
Not connected
Ring Indicator
DEC MMJ
MMJ=Modified Modular Jack
Invented by Digital Equipment Corporation (DEC) (now: Compaq)
Name
DTR
TXD+
TXDRXD+
RXDDSR
Description
Data Terminal Ready
Transmit Data +
Transmit Data Receive Data +
Receive Data Data Set Ready
EIA-449 (RS-449)
Common names: EIA-449, RS-449, ISO 4902
Primary channel
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
SG
RC
n/a
SD+
ST+
RD+
RS+
RT+
CS+
IS
DM+
TR+
RR+
SS
SQ
NS
TT+
SB
SC
102
102b
n/a
103
114
104
105
115
106
n/a
107
108.2
109
116
110
n/a
113
117
102a
Signal Ground
Receive Common
unused
Send Data (B)
Send Timing (B)
Receive Data (B)
Request To Send (B)
Receive Timing (B)
Clear To Send (B)
Terminal In Service
Data Mode (B)
Terminal Ready (B)
Receiver Ready (B)
Select Standby
Signal Quality
New Signal
Terminal Timing (B)
Standby Indicator
Send Common
Ground
Ground
Data
Timing
Data
Control
Timing
Control
Control
Control
Control
Control
Control
Control
Control
Timing
Control
Ground
Description
AA
Shield Ground
AB
Signal Ground
BA
BB
CA
Transmitted Data
Received Data
Request To Send
CB
Clear To Send
CC
DCE Ready
CD
DTE Ready
CE
Ring Indicator
Function
Also known as protective ground. This is the chassis
ground connection between DTE and DCE.
The reference ground between a DTE and a DCE. Has the
value 0 Vdc.
Data send by the DTE.
Data received by the DTE.
Originated by the DTE to initiate transmission by the DCE.
Send by the DCE as a reply on the RTS after a delay in ms,
which gives the DCEs enough time to energize their circuits
and synchronize on basic modulation patterns.
Known as DSR. Originated by the DCE indicating that it is
basically operating (power on, and in functional mode).
Known as DTR. Originated by the DTE to instruct the DCE
to setup a connection. Actually it means that the DTE is up
and running and ready to communicate.
A signal from the DCE to the DTE that there is an
incomming call (telephone is ringing). Only used on
switched circuit connections.
CF
CH/CI
DA
DB
DD
IS
NS
RC
LL
RL
SB
SC
SF
SS
TM
Name RS232
n/a
SSR SRR
SSD SSD
SRD SRD
SG
SG
RC
RC
SRS SRS
SCS SCS
SC
SC
V.24 Dir
Description
101
Shield
122
Secondary Receiver Ready
118
Secondary Send Data
119
Secondary Receive Data
102
Signal Ground
102b
Receive Common
120
Secondary Request To Send
121
Secondary Clear To Send
102a
Send Common
EIA530 (RS530)
Name Dir
TxD
RxD
RTS
CTS
DSR
SGND
DCD
LL
DTR
Description
Shield
Transmitted Data
Received Data
Request To Send
Clear To Send
Data Set Ready
Signal Ground
Data Carrier Detect
Rtrn Receive Sig. Elmnt Timing
Rtrn DCD
Rtrn Transmit Sig. Elmnt Timing
Rtrn Transmit Sig. Elmnt Timing
Rtrn CTS
Rtrn TxD
Transmit Signal Element Timing
Rtrn RxD
Receive Signal Element Timing
Local Loopback
Rtrn RTS
Data Terminal Ready
21 RL
22
23
24
25
Remote Loopback
Rtrn DSR
Rtrn DTR
Transmit Signal Element timing
Test Mode
RL
CC
CD
DA
TM
7
6
20
11
HP 4S Scanner
Name Dir
Description
CD
Carrier Detect
RXD
Receive Data
TXD
Transmit Data
GND
System Ground
CTS
Clear to Send
DSR
Data Set Ready
RI
Ring Indicator
RTS
Request to Send
DTR
Data Terminal Ready
HP48/HP95
+---------+
| . . . . |
\---------/
1 2 3 4
Pin
1
2
3
4
Name
TXD
RXD
GND
Dir
OUT
IN
-
Description
Transmit Data
Receive Data
Ground
ITU-TSS V.35
Common names: ITU-TSS (CCITT) V.35
(at ???)
(at ???)
34 PIN M/34 MALE at ???.
34 PIN M/34 FEMALE at ???.
Pin
A
B
C
D
E
F
H
J
K
L
M
N
P
R
Name Dir
RTS
CTS
DSR
DCD
DTR
LL
TxDRxD-
Description
Chassis Ground
Signal Ground
Request To Send
Clear To Send
Data Set Ready
Data Carrier Detect
Data Terminal Ready
Local Loopback
Local Test
unused
unused
unused
Send Data A
Receive Data A
S
TxD+
T
RxD+
U
V
W
X
Y
Z
AA
BB
CC
DD
EE
FF
HH
JJ
KK
LL
MM
NN
Send Data B
Receive Data B
Terminal Timing A
Receive Timing A
Terminal Timing B
Receive Timing B
Send Timing A
unused
Send Timing B
unused
unused
unused
unused
unused
unused
unused
unused
unused
unused
unused
ITU-TSS X.21
Common names: ITU-TSS (CCITT) X.21, ISO 4903
Name Dir
Description
n/a
Shield
T (A)
Transmit (A)
C (A)
Control (A)
R (A)
Receive (A)
I (A)
Indication (A)
S (A)
Signal Timing (A)
B (A)
Byte Timing (A)
G
Ground
T (B)
Transmit (B)
C (B)
Control (B)
R (B)
Receive (B)
I (B)
Indication (B)
S (B)
Signal Timing (B)
B (B)
Byte Timing (B)
unused
Type
Ground
Data
Control
Data
Control
Timing
Timing
Ground
Data
Control
Data
Control
Timing
Timing
Source:
X.21 Page at Connectivity Knowledge Platform (Made IT)
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
HwB: Lowrance AirMap 100, GlobalMap 100, GlobalNav 12, GlobalNav 200, GlobalNav 212 Connector (Offline)
Name
VCC
RX
GND
TX
-
Description
Power
RS-232 (receive serial)
Ground
NMEA/Pseudo RS-232 (transmit serial)
DO NOT USE (recharging purposes)
DO NOT USE (recharging purposes)
HwB: Lowrance AirMap, AirMap 300, GlobalMap 12, GlobalMap Sport Connector (Offline)
Name
GND
VCC
TX
RX
-
Description
Ground
Power
NMEA/Pseudo RS-232 (transmit serial)
RS-232 (receive serial)
DO NOT USE
DO NOT USE
Name
VCC
RX
GND
TX
Description
Power
RS-232 (receive serial)
Ground
NMEA/Pseudo RS-232 (transmit serial)
MIDI In
MIDI=Musical Instrument Digital Interface.
Name
n/c
n/c
n/c
CSRC
CSINK
Description
Not connected
Not connected
Not connected
Current Source
Current Sink
MIDI Out
MIDI=Musical Instrument Digital Interface.
Name
n/c
GND
n/c
CSINK
CSRC
Description
Not connected
Ground
Not connected
Current Sink
Current Source
Macintosh RS-422
It's possible to connect RS-232 peripheral to the RS-422 port available on Macintosh computers. Use
RXD- as RXD, TXD- as TXD, Ground RXD+, Leave TXD+ unconnected, GPi as CD.
Name
Dir
Description
HSKo
Output Handshake
HSKi/CLK
Input Handshake or External Clock
TXDTransmit Data (-)
GND
Ground
RXDReceive Data (-)
TXD+
Transmit Data (+)
GPi
General Purpose Input
RXD+
Receive Data (+)
Macintosh Serial
Available on Macintosh Mac 512KE and earlier.
+5V
3
4
5
6
GND
Tx+
Tx+12V
DSR/HSK
8
9
Rx+
Rx-
Dir
Description
Ground
+5 VDC. Don't use this one, it may be converted into output handshake in later
equipment.
Ground
Transmit Data, positive going component
Transmit Data, negative going component
+12 VDC
Handshake input. Signal name depends on mode: Used for Flow Control or
Clock In.
Receive Data, positive going component
Receive Data, negative going component
Minuteman UPS
Is the directions right???
Description
Unused
Battery power
Unused
Common (same as 7)
Low battery
RS-232 level shutdown
Common (same as 4)
Ground level shutdown (A500 and above, reserved on <A500)
Reserved
RS-232D
Name Dir
Description
DSR/RI
Data Set Ready / Ring Indicator
CD
Carrier Detect
DTR
Data Terminal Ready
GND
System Ground
RXD
Receive Data
TXD
Transmit Data
CTS
Clear to Send
RTS
Request to Send
RS232
Common names: EIA-232D (RS232-D), ITU-TSS (CCITT) V.24/V.28, ISO 2110
Name
GND
TXD
RXD
RTS
CTS
DSR
GND
CD
STF
S.CD
S.CTS
S.TXD
TCK
S.RXD
RCK
LL
S.RTS
DTR
RS232
n/a
BA
BB
CA
CB
CC
AB
CF
SCF
SCB
SBA
DB
SBB
DD
LL
SCA
CD
V.24 Dir
Description
101
Shield Ground
103
Transmit Data
104
Receive Data
105
Request to Send
106
Clear to Send
107
Data Set Ready
102
System Ground
109
Carrier Detect
RESERVED
RESERVED
126
Select Transmit Channel
122
Secondary Carrier Detect
121
Secondary Clear to Send
118
Secondary Transmit Data
114
Transmission Signal Element Timing
119
Secondary Receive Data
115
Receiver Signal Element Timing
141
Local Loop Control
120
Secondary Request to Send
108.2
Data Terminal Ready
21
22
23
24
25
RL
RI
DSR
XCK
TI
RL
CE
CH
DA
TM
140
125
111
113
142
RS366
Function
Description
Circuit EIA
unused
Digit Present
Call Request
CRQ
PND
unused
unused
unused
unused
10
unused
11
unused
12
unused
DSC
NB1-NB8
18
unused
19
unused
20
unused
21
unused
22
13
23
unused
24
unused
25
unused
DLO
RS422 37pin
Name Dir
Description
GND
Shield Ground
SRI
Signal Rate Indicator
n/c
Spare
SD
Send Data
ST
Send Timing
RD
Receive Data
RTS
Request To Send
RR
Receiver Ready
CTS
Clear To Send
LL
Local Loopback
DM
Data Modem
TR
Terminal Ready
RR
Receiver Ready
RL
Remote Loopback
IC
Incoming Call
SF/SR
Select Frequency/Select Rate
TT
Terminal Timing
TM
Test Mode
GND
Ground
RC
Receive Twister-Pair Common
GND
Spare Twister-Pair Return
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
/SD
GND
GND
/RS
/RT
/CS
IS
/DM
/TR
/RR
SS
SQ
NS
/TT
SB
SC
RS422 9pin
Name
RTS+
RTSTXD+
TXDCTS+
CTSRXD+
RXD-
Description
Shield
Request To Send +
Request To Send Transmit Data +
Transmit Data Clear To Send +
Clear To Send Received Data +
Received Data -
RocketPort Serialport
Available at RocketPort serialport expansion cards.
Name
RTS
DTR
GND
TXD
RXD
DCD
DSR
CTS
Description
Dir
Request To Send
Data Terminal Ready
Ground
Tranceive Data
Receive Data
Data Carrier Detect
Data Set Ready
Clear To Send
Name
TXD
RXD
RTS
CTS
DSR
GND
CD
DTR
CD
CTS
TXD
TC
RXD
RC
TC
RTS
DTR
TCO
TCO
Port Dir
Description
A
Transmit Data
A
Receive Data
A
Request to Send
A
Clear to Send
A
Data Set Ready
System Ground
A
Carrier Detect
B
Data Terminal Ready
B
Carrier Detect
B
Clear to Send
B
Transmit Data
A
Transmit Clock from DCE, usually not used
B
Receive Data
A
Receive Clock from DCE, usually not used
B
Transmit Clock from DCE, usually not used
B
Request to Send
A
Data Terminal Ready
A
Transmit Clock from DTE, usually not used.
B
Transmit Clock from DTE, usually not used.
Source:
SUN Field Engineer Handbook, VolumeII, 12/15/93
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
Serial (15)
Seems to be available at a 14.4kbps modem called Speedster.
2
4
6
10 12 14
- [][][][][][][][][][][][][][][] 1
3
5
7 8 9 11 13 15
Name
GROUND
SUSP#
COMBDSR#
COMBRTS#
COMBCTS#
COMBRI#
n/c
GROUND
+5VIN
COMBDTR#
COMBDCD#
COMBTXD
COMBRXD
SPKDATA
GROUND
RS232 Dir
Description
GND
Ground
?
DSR
Data Set Ready
RTS
Request to Send
CTS
Clear to Send
RI
Ring Indicator
?
GND
Ground
+5V DC In
DTR
Data Terminal Ready
CD
Carrier Detect
TXD
Transmit Data
RXD
Receive Data
?
GND
Ground
Name
SHIELD
TXD
RXD
RTS
CTS
DSR
GND
CD
n/c
n/c
n/c
n/c
n/c
-5V
AUDO
AUDI
EB
/INT2
n/c
DTR
+5V
n/c
+12V
/C2
/RESET
Dir
Description
Shield Ground
Transmit Data
Receive Data
Request to Send
Clear to Send
Data Set Ready
System Ground
Carrier Detect
?
-
Serial (Amiga)
Name
SHIELD
TXD
RXD
RTS
CTS
DSR
GND
CD
+12V
-12V
AUDO
n/c
n/c
n/c
n/c
n/c
n/c
AUDI
n/c
DTR
n/c
Dir
Description
Shield Ground
Transmit Data
Receive Data
Request to Send
Clear to Send
Data Set Ready
System Ground
Carrier Detect
+12 Volts DC (20 mA max)
-12 Volts DC (20 mA max)
Amiga Audio Out (Left)
Speed Indicate
22
23
24
25
RI
n/c
n/c
n/c
Ring Indicator
-
Serial (MSX)
Name Dir
Description
PG
Protective Ground
TXD
Transmit Data
RXD
Receive Data
RTS
Request to Send
CTS
Clear to Send
DSR
Data Set Ready
GND Signal Ground
DCD
Carrier Detect
DTR
Data Terminal Ready
Name
SHIELD
TXD
RXD
RTS
CTS
DSR
GND
CD
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
DTR
n/c
RI
n/c
n/c
n/c
Dir
-
Description
Shield Ground
Transmit Data
Receive Data
Request to Send
Clear to Send
Data Set Ready
System Ground
Carrier Detect
Serial (PC 9)
Also known as EIA/TIA 574
Name
CD
RXD
TXD
DTR
GND
DSR
RTS
CTS
RI
RS232
CF
BB
BA
CD
AB
CC
CA
CB
CE
V.24 Dir
Description
109
Carrier Detect
104
Receive Data
103
Transmit Data
108.2
Data Terminal Ready
102
System Ground
107
Data Set Ready
105
Request to Send
106
Clear to Send
125
Ring Indicator
Serial (Printer)
Name
SHIELD
TXD
RXD
n/c
n/c
DSR
GND
DCD
n/c
n/c
?
n/c
n/c
n/c
n/c
n/c
TTY-TXD
n/c
n/c
DTR
n/c
n/c
?
?
TTY-RXD
Dir
Description
Shield Ground
Transmit Data
Receive Data
Not connected
Not connected
Data Set Ready
System Ground
Data Carrier Detect
Not connected
Not connected
Reverse Channel
Not connected
Not connected
Not connected
Not connected
Not connected
TTY Receive Data
Not connected
Not connected
Data Terminal Ready
Not connected
Not connected
TTY Receive Data Return
TTY Transmit Data Return
TTY Receive Data
Name Dir
Description
DTR
Data Terminal Ready
CTS
Clear to Send
TXD
Transmit Data
GND
System Ground
RXD
Receive Data
RTS
Request to Send
CD
Carrier Detect
GND
System Ground
Serial (SUN)
Available on SUN computers since the SUN3 series (1988) to the current UltraSparc systems
(RS423/RS232)
Name
n/c
TXD
RXD
RTS
CTS
DSR
GND
DCD
n/c
n/c
n/c
n/c
n/c
n/c
TRxC
n/c
RTxC
n/c
n/c
DTR
n/c
n/c
n/c
Dir
Description
Transmit Data
Receive Data
Request to Send
Clear to Send
Data Set Ready
System Ground
Data Carrier Detect
Transmit Clock
Receive Clock
Data Terminal Ready
-
24 TxC
25 n/c
Transmit Clock
-
Name
REMOTE SWITCH
GND
REMOTE SWITCH
DATA IN
DATA OUT
C16/C116/+4 Cassette
Available on the Commodore C16, C116 and +4 computers.
C64 Cassette
Cassette TI-99/4a
Name
Cass 1 motor control
Dito
Output to tape 2
Audio gate
Output to tape 2
Cass 2 motor control
Dito
Input from tape 1 or 2
Dito
Dir
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
Comment
CRU bit 22
neg
CRU bit 25
CRU bit 24
neg
CRU bit 23
neg
CRU bit 27
neg
CoCo Cassette
Available on the Tandy/Radio Shack Color Computer (CoCo).
Description
Motor Relay
Ground
Motor Relay
Signal Input
Signal Output
MSX Cassette
(at the computer)
Name
Dir
Description
GND
Ground
GND
Ground
GND
Ground
CMTOUT
Sound Output
CMTIN
Sound Input
REM+
Remote control (from relay)
REMRemote control (from relay)
GND
Ground
Name
12v
CASR
CASW
AUDIO
GND
ME
READY
Description
Power 100mA
Cassette data read
Cassette data write
Cassette audio
System ground
System Ready
Mitsumi CD-ROM
(at the controller & CD-ROM)
Name
A0
GND
A1
GND
n/c
GND
n/c
GND
n/c
GND
n/c
GND
INT
GND
REQ
GND
ACK
GND
RE
GND
WE
GND
Description
Address Bit 0
Ground
Address Bit 1
Ground
Not connected
Ground
Not connected
Ground
Not connected
Ground
Not connected
Ground
Interrupt
Ground
Data request For DMA
Ground
Data Acknowledge For DMA
Ground
Read Enable
Ground
Write Enable
Ground
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
EN
GND
DB0
GND
DB1
GND
DB2
GND
DB3
GND
DB4
GND
DB5
GND
DB6
GND
DB7
GND
Bus Enable
Ground
Data Bit 0
Ground
Data Bit 1
Ground
Data Bit 2
Ground
Data Bit 3
Ground
Data Bit 4
Ground
Data Bit 5
Ground
Data Bit 6
Ground
Data Bit 7
Ground
Panasonic CD-ROM
(at the controller & CD-ROM)
Name
GND
RESET
GND
GND
GND
MODE0
GND
MODE1
GND
WRITE
GND
READ
GND
ST0
GND
n/c
GND
n/c
GND
ST1
GND
EN
Description
Ground
CD-Reset
Ground
Ground
Ground
Operation Mode Bit 0
Ground
Operation Mode Bit 1
Ground
CD-Write
Ground
CD-Read
Ground
CD-Status Bit 0
Ground
No Connection
Ground
No Connection
Ground
CD-Status Bit 1
Ground
CD-Data Enable
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
GND
ST2
GND
S/DE
GND
ST3
GND
GND
D7
D6
GND
D5
D4
D3
GND
D2
D1
D0
Ground
CD-Status Bit 2
Ground
CD-Status/Data Enable
Ground
CD-Status Bit 3
ground
ground
CD-Data 7
CD-Data 6
ground
CD-Data 5
CD-Data 4
CD-Data 3
ground
CD-Data 2
CD-Data 1
CD-Data 0
Sony CD-ROM
(at the controller & CD-ROM)
Name
RESET
GND
DB7
GND
DB6
GND
DB5
GND
DB4
GND
DB3
GND
DB2
GND
DB1
GND
DB0
GND
WE
GND
RE
GND
Description
Reset
Ground
Data Bit 7
Ground
Data Bit 6
Ground
Data Bit 5
Ground
Data Bit 4
Ground
Data Bit 3
Ground
Data Bit 2
Ground
Data Bit 1
Ground
Data Bit 0
Ground
Write Enable
Ground
Read Enable
Ground
23
24
25
26
27
28
29
30
31
32
33
34
ACK
GND
REQ
GND
INT
GND
A1
GND
A0
GND
EN
GND
Name
/REDWC
n/c
n/c
n/c
/FD2S
/DCG
/SIDE
/DLOCK
/HLD
/INDEX
/READY
n/c
/SEL1
/SEL2
/SEL3
/SEL4
/DIR
/STEP
/WDAT
/WGAT
/TR00
/WPROT
/RDATA
n/c
n/c
Dir
-
Description
Reduced Write Current
Reserved
Reserved
Reserved
Disk is two sided
Disk has been changed/door open
Side select
Door lock
Head load
Index Pulse
Ready
Not connected
Select Drive 1
Select Drive 2
Select Drive 3
Select Drive 4
Direction
Step
Write data
Write gate
Track 00 (Zero)
Write protect
Read data
Not connected
Not connected
Name
/RDY
/DKRD
GND
GND
GND
GND
GND
/MTRXD
/SEL2
/DRES
/CHNG
+5V
/SIDE
/WPRO
/TKO
/DKWE
/DKWD
/STEP
DIR
/SEL3
/SEL1
/INDEX
+12V
Dir
OC
OC
OC
OC
OC
OC
OC
OC
OC
OC
Description
Disk Ready
Disk Read Data
Ground
Ground
Ground
Ground
Ground
Disk Motor Control
Select Drive 2
Disk Reset
Disk Removed From Drive-Latched Low
+5 Volts DC (250 mA max)
Select Disk Side (0=Upper, 1=Lower)
Disk is Write Protected
Drive Head position over Track 0
Disk Write Enable
Disk Write Data
Step the Head-Pulse, First low, then high
Select Head Direction (0=Inner, 1=Outer)
Select Drive 3
Select Drive 1
Disk Index Pulse
+12 Volts DC (160 mA max, 540 mA surge
Source:
Amiga 4000 User's Guide from Commodore
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
Name
READY
GND
SIDE 1 SELECT
GND
READ DATA
GND
WRITE PROTECT
GND
TRACK 0
GND
WRITE GATE
GND
WRITE DATA
GND
STEP
GND
DIRECTION SELECT
GND
MOTOR ON
GND
n/c
GND
DRIVE SELECT 1
GND
n/c
GND
INDEX
28
29
30
31
32
33
34
GND
n/c
GND
n/c
GND
n/c
GND
Name
n/c
n/c
n/c
NINDEX
n/c
NDSEL1
n/c
NMOTOR
NDSEL
NSTEP
NWDATA
NWGATE
NTK00
NWRPT
NRDDTA
NSIDE1
NREADY
n/c
Dir
?
?
?
?
Description
Not connected
Not connected
Not connected
Not connected
Not connected
Step head
Write Data
Write Gate
Track 00
Write Protect
Read Data
?
?
Not connected
Name
Ground
Ground
Ground
Ground
-12V
+5V
+12V
+12V
?
PWM
PH0
PH1
PH2
PH3
WrReqHdSel
Enbl2Rd
Wr
Description
-12 VDC
+5 VDC
+12 VDC
+12 VDC
?
Regulates speed of the drive
Control line to send commands to the drive
Control line to send commands to the drive
Control line to send commands to the drive
Control line to send commands to the drive
Turns on the ability to write data to the drive
Control line to send commands to the drive
Enables the Rd line (else Rd is tri-stated)
Data actually read from the drive
Data actually written to the drive
Name
GND
PH0
GND
PH1
GND
PH2
GND
PH3
+5V
/WRREQ
+5V
SEL
+12V
/ENBL
+12V
RD
+12V
WR
+12V
n.c.
Description
Ground
Phase 0: state control line
Ground
Phase 1: state control line
Ground
Phase 2: state control line
Ground
Phase 3: register write strobe
+5 volts
Write data request
+5 volts
Head select
+12 volts
Drive enable
+12 volts
Read data
+12 volts
Write data
+12 volts
Not connected
Name
RD
SIDE0
GND
INDEX
SEL0
SEL1
GND
MOTOR
DIR
STEP
WD
WG
TRK00
WP
Description
Read Data
Side 0 Select
Ground
Index
Drive 0 Select
Drive 1 Select
Ground
Motor On
Direction In
Step
Write Data
Write Gate
Track 00
Write Protect
Internal Diskdrive
(at the computer & diskdrives)
34 PIN IDC MALE at the computer & diskdrives.
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
Name
Dir
Description
/REDWC
Density Select
n/c
Reserved
n/c
Reserved
/INDEX
Index
/MOTEA
Motor Enable A
/DRVSB
Drive Sel B
/DRVSA
Drive Sel A
/MOTEB
Motor Enable B
/DIR
Direction
/STEP
Step
/WDATE
Write Data
/WGATE
Floppy Write Enable
/TRK00
Track 0
/WPT
Write Protect
/RDATA
Read Data
/SIDE1
Head Select
/DSKCHG
Disk Change
Name
CGND
CGND
CGND
CGND
-12V
+5V
+12V
+12V
n/c
PWM
CA0
CA1
CA2
LSTRB
/WrReq
HdSel
/Enbl2
Rd
Wr
Dir
?
?
?
?
?
?
?
?
Description
Chassis ground
Chassis ground
Chassis ground
Chassis ground
-12 VDC
+5 VDC
+12 VDC
+12 VDC
Not connected
Regulates speed of the drive
Control line to send commands to the drive
Control line to send commands to the drive
Control line to send commands to the drive
Control line to send commands to the drive
Turns on the ability to write data to the drive
Control line to send commands to the drive
Enables the Rd line (else Rd is tri-stated)
Data actually read from the drive
Data actually written to the drive
Name
+12V
+5V
+5V
/INDEX
/DSEL1
DIR
/STEP
WRITEDATA
/WRITEGATE
/TRACK00
/WRITEPROTECT
READDATA
/SIDESELECT
+12V
+12V
+5V
/DSEL1
/MOTOR
READY
GND
GND
GND
GND
GND
GND
Dir
Description
+12 VDC
+5 VDC
+5 VDC
Sector hole passed sensor.
Drive Select 1
Direction (0=In, 1=Dir)
Moves head 1 step in DIR direction.
Write Data
Write Gate
Head is over Track 00 (outermost track)
Write protected disk (0=Write protected)
Data read from diskette.
Side Select (0=Side 1, 1=Side 0)
+12 VDC
+12 VDC
+5 VDC
Select Drive 0
Motor On
Ready
Ground
Ground
Ground
Ground
Ground
Ground
Name
GND
FD_DENSEL
GND
33_W_to_VCC
GND
FD_DRATE0_MSEN0
N/C
FD_INDEX_L
GND
MTR0_L
GND
FD_DRV1_SEL_L
N/C
FD_DRV0_SEL_L
GND
FD_MTR1_L
MSEN1
FD_DIR_L
GND
FD_STEP_L
GND
FD_WR_DAT_L
GND
FD_WR_GATE_L
GND
FD_TRK0_L
27
28
29
30
31
32
33
34
MSEN0
FD_WR_PROT_L
GND
FD_RD_DAT_L
GND
FD_HD_SEL_L
GND
FD_DSK_CHNG_L
ESDI
ESDI=Enhanced Small Device Interface.
Developed by Maxtor in the early 1980's as an upgrade and improvement to the ST506 design.
Control connector
Pin Name
Description
2
Head Sel 3
4
Head Sel 2
6
Write Gate
8
Config/Stat Data
10
Transfer Acknowledge
12
Attention
14
Head Sel 0
file:///C|/tmp/tech/HwB/connector/storage/esdi.html (1 of 3) [6/15/2001 12:02:13 AM]
16
18
20
22
24
26
28
30
32
34
Sect/Add MK Found
Head Sel 1
Index
Ready
Transfer Request
Drive Sel 1
Drive Sel 2
Drive Sel 3
Read Gate
Command Data
Data connector
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
GND
GND
GND
GND
GND
GND
Description
Drive Selected
Sect/Add MK Found
Seek Complete
Address Mark Enable
(reserved, for step mode)
Ground
Write Clock+
Write ClockCartridge Changed
Read Ref Clock+
Read Ref ClockGround
NRZ Write Data+
NRZ Write DataGround
Ground
NRZ Read Data+
NRZ Read DataGround
Ground
?
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
ST506/412
Developed by Seagate.
Also known as MFM or RLL since these are the encoding methods used to store data. Seagate originally
developed it to support their ST506 (5 MB) and ST412 (10 MB) drives.
The first drives used an encoding method called MFM (Modified Frequency Modulation). Later a new
encoding method was developed, RLL (Run Length Limited). RLL had the advantage that it was
possible to store 50% more with it. But it required better drives. This is almost never an problem. Often
called 2,7 RLL because the recording scheme involves patterns with no more than 7 successive zeros and
no less than two.
Control connector
Pin Name Description
2
Head Sel 8
4
Head Sel 4
file:///C|/tmp/tech/HwB/connector/storage/st506.html (1 of 3) [6/15/2001 12:02:13 AM]
6
8
10
12
14
16 RES
18
20
22
24
26
28
30
32
34
Write Gate
Seek Complete
Track 0
Write Fault
Head Sel 1
(reserved)
Head Sel 2
Index
Ready
Step
Drive Sel 1
Drive Sel 2
Drive Sel 3
Drive Sel 4
Direction In
Data connector
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Name Description
Drive Selected
GND Ground
RES (reserved)
GND Ground
RES (reserved)
GND Ground
RES (reserved)
GND Ground
RES (reserved)
RES (reserved)
GND Ground
GND Ground
Write Data+
Write DataGND Ground
GND Ground
Read Data+
Read Data-
19 GND Ground
20 GND Ground
Contributor: Joakim gren
Source:
?
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
Name Dir
Description
+5VL
+5 VDC (Logic)
+5VM
+5 VDC (Motor)
GND
Ground
/TYPE
Type (0=ATA)
ATA Internal
ATA=AT bus Attachment..
Developed by Western Digital, Conner & Seagate ?.
Name
/RESET
GND
DD7
DD8
DD6
DD9
DD5
DD10
DD4
DD11
DD3
DD12
DD2
DD13
DD1
DD14
DD0
DD15
GND
Dir
Description
Reset
Ground
Data 7
Data 8
Data 6
Data 9
Data 5
Data 10
Data 4
Data 11
Data 3
Data 12
Data 2
Data 13
Data 1
Data 14
Data 0
Data 15
Ground
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
KEY
DMARQ
GND
/DIOW
GND
/DIOR
GND
IORDY
SPSYNC:CSEL
/DMACK
GND
INTRQ
/IOCS16
DA1
PDIAG
DA0
DA2
/IDE_CS0
/IDE_CS1
/ACTIVE
GND
?
?
?
?
IDE Internal
IDE=Integrated Drive Electronics.
Developed by Compaq and Western Digital.
Newer version of IDE goes under the name ATA=AT bus Attachment.
Name
/RESET
GND
DD7
DD8
DD6
DD9
DD5
DD10
DD4
DD11
DD3
DD12
DD2
DD13
DD1
DD14
DD0
DD15
GND
Dir
Description
Reset
Ground
Data 7
Data 8
Data 6
Data 9
Data 5
Data 10
Data 4
Data 11
Data 3
Data 12
Data 2
Data 13
Data 1
Data 14
Data 0
Data 15
Ground
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
KEY
n/c
GND
/IOW
GND
/IOR
GND
IO_CH_RDY
ALE
n/c
GND
IRQR
/IOCS16
DA1
n/c
DA0
DA2
/IDE_CS0
/IDE_CS1
/ACTIVE
GND
?
-
Key
Not connected
Ground
Write Strobe
Ground
Read Strobe
Ground
Address Latch Enable
Not connected
Ground
Interrupt Request
IO ChipSelect 16
Address 1
Not connected
Address 0
Address 2
(1F0-1F7)
(3F6-3F7)
Led driver
Ground
Name
/IDE-RESET
D0
D2
D4
D6
GND
D8
D10
D12
D14
GND
GND
GND
GND
GND
GND
GND
+5V
+5V
GND
D1
D3
D5
D7
Description
Drive Reset
Data bit 0
Data bit 2
Data bit 4
Data bit 6
Ground
Data bit 8
Data bit 10
Data bit 12
Data bit 14
Ground
Ground
Ground
Ground
Ground
Ground
Ground
5V Power
5V Power
Ground
Data bit 1
Data bit 3
Data bit 5
Data bit 7
25
26
27
28
29
30
31
32
33
34
35
36
37
GND
D9
D11
D13
D15
/IOW
/IOR
IDE-IRQ
IDE-A2
IDE-A1
IDE-A0
/BICS1
/BICS0
Ground
Data bit 9
Data bit 11
Data bit 13
Data bit 15
I/O Write
I/O Read
Interrupt Request
Address bit 2
Address bit 1
Address bit 0
Chip Select 1
Chip Select 0
SCSI Information
Background
It all started back in 1979 when the diskdrive manufacturer come with the bright idea to make a new
transfer protocol. The protocol was named Shugart Associates Systems Interface, SASI. This protocol
wasn't an ANSI standard, so NCR join Shugart and the ANSI committee X3T9.2 was formed. The new
name for the protocol was, Small Computer Systems Interface, SCSI.
Common Command Set, CCS, was added in 1985. ANSI finished the SCSI standard in 1986. SCSI-II
devices was released in 1988 and was an official standard in 1994. SCSI-III is currently not yet official.
Usage
SCSI is used to connect peripherals to an computer. It allows you to connect harddisks, tape devices,
CD-ROMs, CD-R units, DVD, scanners, printers and many other devices. SCSI is in opposite to
IDE/ATA very flexible. Today SCSI is most often used servers and other computers which require very
good performance. IDE/ATA is more popular due to the fact that IDE/ATA devices tend to be cheaper.
Definitions
SCSI
Short for Small Computer Systems Interface. The original SCSI protocol. ANSI standard X3.131-1996.
Busspeed 5 MHz. Datawidth 8 bits.
SCSI-II
SCSI-II adds support for CD-ROM's, scanners and tapedrives.
Fast SCSI-II
Uses the busspeed of 10MHz instead of the original 5MHz.
Wide SCSI-II
Uses 16 bits instead of the original 8 bits.
Ultra SCSI-III
Uses the busspeed of 20MHz.
Contributors: Joakim gren
Source:
From the head of Joakim gren
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
Name Dir
Description
n/c
Reserved for SCSI disk mode.
/DB0
Bit 0 of SCSI data bus
GND
Ground
/DB1
Bit 1 of SCSI data bus
TPWR
Termination power
/DB2
Bit 2 of SCSI data bus
/DB3
Bit 3 of SCSI data bus
GND
Ground
/ACKS
Handshake signal. When low acknowledges a request for data transfer
GND
Ground
/DB4
Bit 4 of SCSI data bus
GND
Ground
GND
Ground
/DB5
Bit 5 of SCSI data bus
GND
Ground
/DB6
Bit 6 of SCSI data bus
GND
Ground
/DB7
Bit 7 of SCSI data bus
/DBP
SCSI data bus parity bit
GND
Ground
/REQ
Request for a data transfer
GND
Ground
/BSY
When active (low) indicates that the SCSI data bus is busy
GND
Ground
/ATN
When active (low) indicates an attention condition
When active (low) indicates that data is on the SCSI bus. When high, indicates that
/C/D
control signals are on the bus
/RST
SCSI bus reset
/MSG
Indicates the message phase
/SEL
SCSI select
30 /I/O
Name
Dir
Description
GND
Ground
GND
Ground
GND
Ground
GND
Ground
GND
Ground
GND
Ground
GND
Ground
GND
Ground
GND
Ground
GND
Ground
GND
Ground
GND
Ground
GND
Ground
GND
Ground
GND
Ground
GND
Ground
GND
Ground
GND
Ground
TERMPWR
Termination Power
/DB0
Data Bus 0
/DB1
Data Bus 1
/DB2
Data Bus 2
/DB3
Data Bus 3
/DB4
Data Bus 4
25
26
27
28
29
30
31
32
33
34
35
36
37
/DB5
/DB6
/DB7
/DBP
/ATN
/BSY
/ACK
/RST
/MSG
/SEL
/C/D
/REQ
/I/O
Data Bus 5
Data Bus 6
Data Bus 7
Data Bus Parity
Attention
Busy
Acknowledge
Reset
Message
Select
Control/Data
Request
Input/Output
Name
GND
+DB0
+DB1
+DB2
+DB3
+DB4
+DB5
+DB6
+DB7
+DBP
DIFFSENS
res
TERMPWR
res
+ATN
GND
+BSY
+ACK
+RST
+MSG
Dir
?
-
Description
Ground
+Data Bus 0
+Data Bus 1
+Data Bus 2
+Data Bus 3
+Data Bus 4
+Data Bus 5
+Data Bus 6
+Data Bus 7
+Data Bus Parity (odd Parity)
???
Reserved
Termination Power
Reserved
+Attention
Ground
+Bus is busy
+Acknowledge
+Reset
+Message
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
+SEL
+C/D
+REQ
+I/O
GND
GND
-DB0
-DB1
-DB2
-DB3
-DB4
-DB5
-DB6
-DB7
-DBP
GND
res
TERMPWR
res
-ATN
GND
-BSY
-ACK
-RST
-MSG
-SEL
-C/D
-REQ
-I/O
GND
+Select
+Control or Data
+Request
+In/Out
Ground
Ground
-Data Bus 0
-Data Bus 1
-Data Bus 2
-Data Bus 3
-Data Bus 4
-Data Bus 5
-Data Bus 6
-Data Bus Parity7
-Data Bus Parity (odd Parity)
Ground
Reserved
Termination Power
Reserved
-Attention
Ground
-Bus is busy
-Acknowledge
-Reset
-Message
-Select
-Control or Data
-Request
-In/Out
Ground
Name Dir
Description
GND
Ground
DB0
Data Bus 0
DB1
Data Bus 1
DB2
Data Bus 2
DB3
Data Bus 3
DB4
Data Bus 4
DB5
Data Bus 5
DB6
Data Bus 6
DB7
Data Bus 7
PARITY
Data Parity (odd Parity)
GND
Ground
GND
Ground
GND
Ground
TMPWR
Termination Power
GND
Ground
GND
Ground
/ATN
Attention
n/c
Not connected
/BSY
Busy
44
45
46
47
48
49
50
/ACK
/RST
/MSG
/SEL
/C/D
/REQ
/I/O
Acknowledge
Reset
Message
Select
Control/Data
Request
Input/Output
Name Dir
Description
GND
Ground
DB1
Data Bus 1
DB3
Data Bus 3
DB5
Data Bus 5
DB7
Data Bus 7
GND
Ground
/SEL
Select
GND
Ground
TMPWR
Termination Power
/RST
Reset
C/D
Control/Data
I/O
Input/Output
GND
Ground
DB0
Data Bus 0
DB2
Data Bus 2
DB4
Data Bus 4
DB6
Data Bus 6
PARITY
Data Parity
GND
Ground
/ATN
Attention
21
22
23
24
25
/MSG
/ACK
BSY
/REQ
GND
Message
Acknowledge
Busy
Request
Ground
Name Dir
Description
/REQ
Request
/MSG
Message
I/O
Input/Output
/RST
Reset
/ACK
Acknowledge
BSY
Busy
GND
Ground
DB0
Data Bus 0
GND
Ground
DB3
Data Bus 3
DB5
Data Bus 5
DB6
Data Bus 6
DB7
Data Bus 7
GND
Ground
C/D
Control/Data
GND
Ground
/ATN
Attention
GND
Ground
/SEL
Select
PARITY
Data Parity
DB1
Data Bus 1
22
23
24
25
DB2
DB4
GND
TMPWR
Data Bus 2
Data Bus 4
Ground
Termination Power
(at ???)
60 PIN BURNDY (C-60) at ???
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Name
GND
DB0
GND
DB1
GND
DB2
GND
DB3
GND
DB4
GND
DB5
GND
DB6
GND
DB7
GND
DPB
GND
GND
GND
GND
GND
GND
Dir
Description
Ground
Data Bus 0
Ground
Data Bus 1
Ground
Data Bus 2
Ground
Data Bus 3
Ground
Data Bus 4
Ground
Data Bus 5
Ground
Data Bus 6
Ground
Data Bus 7
Ground
Data Parity (odd Parity)
Ground
Ground
Ground
Ground
Ground
Ground
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
n/c
TERMPWR
GND
GND
GND
GND
GND
/ATN
GND
GND
GND
/BSY
GND
/ACK
GND
/RST
GND
/MSG
GND
/SEL
GND
/C/D
GND
/REQ
GND
/I/O
GND
res
res
res
res
res
res
res
res
res
Not connected
Termination Power
Ground
Ground
Ground
Ground
Ground
Attention
Ground
Ground
Ground
Busy
Ground
Acknowledge
Ground
Reset
Ground
Message
Ground
Select
Ground
Control/Data
Ground
Request
Ground
Input/Output
Ground
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Name
+5V
+5V
RET
RET
GND
DB0
GND
DB1
GND
DB2
GND
DB3
GND
DB4
GND
DB5
GND
DB6
GND
DB7
Dir
Description
+5 VDC
+5 VDC
Return (Ground?)
Return (Ground?)
Ground
Data Bus 0
Ground
Data Bus 1
Ground
Data Bus 2
Ground
Data Bus 3
Ground
Data Bus 4
Ground
Data Bus 5
Ground
Data Bus 6
Ground
Data Bus 7
1
18
24
26
32
36
24
38
40
42
24
44
50
46
24
48
1
1
1
1
GND
PARITY
GND
TMPWR
/ATN
/BSY
GND
/ACK
/RST
/MSG
GND
/SEL
/I/O
/C/D
GND
/REQ
RET
RET
+5V
+5V
Ground
Data Parity (odd Parity)
Ground
Termination Power
Attention
Busy
Ground
Acknowledge
Reset
Message
Ground
Select
Input/Output
Control/Data
Ground
Request
Return (Ground?)
Return (Ground?)
+5 VDC
+5 VDC
Name
Dir
GND
GND
+DB0
-DB0
+DB1
-DB1
+DB2
-DB2
+DB3
-DB3
+DB4
-DB4
+DB5
-DB5
+DB6
-DB6
+DB7
-DB7
+DBP
-DBP
DIFFSENS ?
GND
Description
Ground
Ground
+Data Bus 0
-Data Bus 0
+Data Bus 1
-Data Bus 1
+Data Bus 2
-Data Bus 2
+Data Bus 3
-Data Bus 3
+Data Bus 4
-Data Bus 4
+Data Bus 5
-Data Bus 5
+Data Bus 6
-Data Bus 6
+Data Bus 7
-Data Bus Parity7
+Data Bus Parity (odd Parity)
-Data Bus Parity (odd Parity)
???
Ground
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
res
res
TERMPWR
TERMPWR
res
res
+ATN
-ATN
GND
GND
+BSY
-BSY
+ACK
-ACK
+RST
-RST
+MSG
-MSG
+SEL
-SEL
+C/D
-C/D
+REQ
-REQ
+I/O
-I/O
GND
GND
Reserved
Reserved
Termination Power
Termination Power
Reserved
Reserved
+Attention
-Attention
Ground
Ground
+Bus is busy
-Bus is busy
+Acknowledge
-Acknowledge
+Reset
-Reset
+Message
-Message
+Select
-Select
+Control or Data
-Control or Data
+Request
-Request
+In/Out
-In/Out
Ground
Ground
Name Dir
Description
DB0
Data Bus 0
DB1
Data Bus 1
DB2
Data Bus 2
DB3
Data Bus 3
DB4
Data Bus 4
DB5
Data Bus 5
DB6
Data Bus 6
DB7
Data Bus 7
PARITY
Data Parity (odd Parity)
GND
Ground
GND
Ground
GND
Ground
TMPWR
Termination Power
GND
Ground
GND
Ground
/ATN
Attention
GND
Ground
/BSY
Busy
/ACK
Acknowledge
40
42
44
46
48
50
/RST
/MSG
/SEL
/C/D
/REQ
/I/O
Reset
Message
Select
Control/Data
Request
Input/Output
Name
GND
+DB0
+DB1
+DB2
+DB3
+DB4
+DB5
+DB6
+DB7
+DBP
DIFFSENS
res
TERMPWR
res
+ATN
GND
+BSY
+ACK
+RST
+MSG
+SEL
Dir
?
-
Description
Ground
+Data Bus 0
+Data Bus 1
+Data Bus 2
+Data Bus 3
+Data Bus 4
+Data Bus 5
+Data Bus 6
+Data Bus 7
+Data Bus Parity (odd Parity)
???
Reserved
Termination Power
Reserved
+Attention
Ground
+Bus is busy
+Acknowledge
+Reset
+Message
+Select
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
+C/D
+REQ
+I/O
GND
GND
-DB0
-DB1
-DB2
-DB3
-DB4
-DB5
-DB6
-DB7
-DBP
GND
res
TERMPWR
res
-ATN
GND
-BSY
-ACK
-RST
-MSG
-SEL
-C/D
-REQ
-I/O
GND
+Control or Data
+Request
+In/Out
Ground
Ground
-Data Bus 0
-Data Bus 1
-Data Bus 2
-Data Bus 3
-Data Bus 4
-Data Bus 5
-Data Bus 6
-Data Bus Parity7
-Data Bus Parity (odd Parity)
Ground
Reserved
Termination Power
Reserved
-Attention
Ground
-Bus is busy
-Acknowledge
-Reset
-Message
-Select
-Control or Data
-Request
-In/Out
Ground
Name Dir
Description
GND
Ground
DB0
Data Bus 0
DB1
Data Bus 1
DB2
Data Bus 2
DB3
Data Bus 3
DB4
Data Bus 4
DB5
Data Bus 5
DB6
Data Bus 6
DB7
Data Bus 7
PARITY
Data Parity (odd Parity)
GND
Ground
GND
Ground
GND
Ground
TMPWR
Termination Power
GND
Ground
GND
Ground
/ATN
Attention
n/c
Not connected
/BSY
Busy
/ACK
Acknowledge
/RST
Reset
46
47
48
49
50
/MSG
/SEL
/C/D
/REQ
/I/O
Message
Select
Control/Data
Request
Input/Output
Name
Dir
Description
+DB12
Data Bus 12
+DB13
Data Bus 13
+DB14
Data Bus 14
+DB15
Data Bus 15
+DPB1
Data Parity (odd Parity)
GND
Ground
+DB0
Data Bus 0
+DB1
Data Bus 1
+DB2
Data Bus 2
+DB3
Data Bus 3
+DB4
Data Bus 4
+DB5
Data Bus 5
+DB6
Data Bus 6
+DB7
Data Bus 7
+DPB
Data Parity (odd Parity)
DIFFSENSE ?
Diff Sense?
TERMPWR
Termination Power
TERMPWR
Termination Power
res
reserved
+ATN
Attention
GND
Ground
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
+BSY
+ACK
+RST
+MSG
+SEL
+C/D
+REQ
+I/O
GND
+DB8
+DB9
+DB10
+DB11
-DB12
-DB13
-DB14
-DB15
-DPB1
GND
-DB0
-DB1
-DB2
-DB3
-DB4
-DB5
-DB6
-DB7
-DPB
GND
TERMPWR
TERMPWR
res
-ATN
GND
-BSY
-ACK
-RST
-MSG
Busy
Acknowledge
Reset
Message
Select
Control/Data
Request
Input/Output
Ground
Data Bus 8
Data Bus 9
Data Bus 10
Data Bus 11
Data Bus 12
Data Bus 13
Data Bus 14
Data Bus 15
Data Parity (odd Parity)
Ground
Data Bus 0
Data Bus 1
Data Bus 2
Data Bus 3
Data Bus 4
Data Bus 5
Data Bus 6
Data Bus 7
Data Parity (odd Parity)
Ground
Termination Power
Termination Power
reserved
Attention
Ground
Busy
Acknowledge
Reset
Message
60
61
62
63
64
65
66
67
68
-SEL
-C/D
-REQ
-I/O
GND
-DB8
-DB9
-DB10
-DB11
Select
Control/Data
Request
Input/Output
Ground
Data Bus 8
Data Bus 9
Data Bus 10
Data Bus 11
Name
12V
12V
12V
12V
3.3V
3.3V
-DB(11)
-DB(10)
-DB(9)
-DB(8)
-I/O
-REQ
-C/D
-SEL
-MSG
-RST
-ACK
-BSY
-ATN
-P_CRCA
-DB(7)
-DB(6)
-DB(5)
-DB(4)
-DB(3)
-DB(2)
-DB(1)
-DB(0)
Dir
Description
+12 VDC
+12 VDC
+12 VDC
+12 VDC
+3.3 VDC
+3.3 VDC
Data Bus 11
Data Bus 10
Data Bus 9
Data Bus 8
Input/Output
Request
Control/Data
Select
Message
Reset
Acknowledge
Busy
Attention
?
Data Bus 7
Data Bus 6
Data Bus 5
Data Bus 4
Data Bus 3
Data Bus 2
Data Bus 1
Data Bus 0
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
-DB(P1)
-DB(15)
-DB(14)
-DB(13)
-DB(12)
5V
5V
5V CHARGE
SPINDLE SYNC
RMT_START
SCSI ID (0)
SCSI ID (2)
12V GROUND
12V GROUND
12V GROUND
MATED 1
3.3V CHARGE
DIFFSNS
+DB(11)
+DB(10)
+DB(9)
+DB(8)
+I/O
+REQ
+C/D
+SEL
+MSG
+RST
+ACK
+BSY
+ATN
+P_CRCA
+DB(7)
+DB(6)
+DB(5)
+DB(4)
+DB(3)
+DB(2)
?
?
Data Bus 15
Data Bus 14
Data Bus 13
Data Bus 12
Ground (Signal)
Ground (Signal)
Ground (Signal)
Spindle Sync
Remote Start
SCSI ID Bit 0
SCSI ID Bit 2
+12 VDC Ground
+12 VDC Ground
+12 VDC Ground
?
+3.3 VDC Charge
Differential Sense
Data Bus 11
Data Bus 10
Data Bus 9
Data Bus 8
Input/Output
Request
Control/Data
Select
Message
Reset
Acknowledge
Busy
Attention
?
Data Bus 7
Data Bus 6
Data Bus 5
Data Bus 4
Data Bus 3
Data Bus 2
67
68
69
70
71
72
73
74
75
76
77
78
79
80
+DB(1)
+DB(0)
+DB(P1)
+DB(15)
+DB(14)
+DB(13)
+DB(12)
MATED 2
5V GROUND
5V GROUND
ACTIVE LED OUT
DLYD_START
SCSI ID (1)
SCSI ID (3)
Data Bus 1
Data Bus 0
?
Data Bus 15
Data Bus 14
Data Bus 13
Data Bus 12
?
+5 VDC Ground
+5 VDC Ground
?
?
SCSI ID Bit 1
SCSI ID Bit 3
Name
12V
12V
12V
12V
3.3V
3.3V
-DB(11)
-DB(10)
-DB(9)
-DB(8)
-I/O
-REQ
-C/D
-SEL
-MSG
-RST
-ACK
-BSY
-ATN
-P_CRCA
-DB(7)
-DB(6)
-DB(5)
-DB(4)
-DB(3)
-DB(2)
-DB(1)
-DB(0)
Dir
Description
+12 VDC
+12 VDC
+12 VDC
+12 VDC
+3.3 VDC
+3.3 VDC
Data Bus 11
Data Bus 10
Data Bus 9
Data Bus 8
Input/Output
Request
Control/Data
Select
Message
Reset
Acknowledge
Busy
Attention
?
Data Bus 7
Data Bus 6
Data Bus 5
Data Bus 4
Data Bus 3
Data Bus 2
Data Bus 1
Data Bus 0
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
-DB(P1)
-DB(15)
-DB(14)
-DB(13)
-DB(12)
5V
5V
5V CHARGE
SPINDLE SYNC
RMT_START
SCSI ID (0)
SCSI ID (2)
12V GROUND
12V GROUND
12V GROUND
MATED 1
3.3V CHARGE
GROUND
SIGNAL RETURN
SIGNAL RETURN
SIGNAL RETURN
SIGNAL RETURN
SIGNAL RETURN
SIGNAL RETURN
SIGNAL RETURN
SIGNAL RETURN
SIGNAL RETURN
SIGNAL RETURN
SIGNAL RETURN
SIGNAL RETURN
SIGNAL RETURN
SIGNAL RETURN
SIGNAL RETURN
SIGNAL RETURN
SIGNAL RETURN
SIGNAL RETURN
SIGNAL RETURN
SIGNAL RETURN
?
?
Data Bus 15
Data Bus 14
Data Bus 13
Data Bus 12
Ground (Signal)
Ground (Signal)
Ground (Signal)
Spindle Sync
Remote Start
SCSI ID Bit 0
SCSI ID Bit 2
+12 VDC Ground
+12 VDC Ground
+12 VDC Ground
?
+3.3 VDC Charge
Ground
Ground (Signal)
Ground (Signal)
Ground (Signal)
Ground (Signal)
Ground (Signal)
Ground (Signal)
Ground (Signal)
Ground (Signal)
Ground (Signal)
Ground (Signal)
Ground (Signal)
Ground (Signal)
Ground (Signal)
Ground (Signal)
Ground (Signal)
Ground (Signal)
Ground (Signal)
Ground (Signal)
Ground (Signal)
Ground (Signal)
67
68
69
70
71
72
73
74
75
76
77
78
79
80
SIGNAL RETURN
SIGNAL RETURN
SIGNAL RETURN
SIGNAL RETURN
SIGNAL RETURN
SIGNAL RETURN
SIGNAL RETURN
MATED 2
?
5V GROUND
5V GROUND
ACTIVE LED OUT ?
DLYD_START
?
SCSI ID (1)
SCSI ID (3)
Ground (Signal)
Ground (Signal)
Ground (Signal)
Ground (Signal)
Ground (Signal)
Ground (Signal)
Ground (Signal)
+5 VDC Ground
+5 VDC Ground
SCSI ID Bit 1
SCSI ID Bit 3
Name
Dir
Description
GND
Ground
TERMPWR
Termination Power
TERMPWR
Termination Power
res
reserved
GND
Ground
DB12
Data Bus 12
DB13
Data Bus 13
DB14
Data Bus 14
DB15
Data Bus 15
DPB1
Data Parity (odd Parity)
DB0
Data Bus 0
DB1
Data Bus 1
DB2
Data Bus 2
DB3
Data Bus 3
DB4
Data Bus 4
DB5
Data Bus 5
DB6
Data Bus 6
DB7
Data Bus 7
DPB
Data Parity (odd Parity)
GND
Ground
GND
Ground
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
TERMPWR
TERMPWR
res
GND
/ATN
GND
/BSY
/ACK
/RST
/MSG
/SEL
/C/D
/REQ
/I/O
DB8
DB9
DB10
DB11
Termination Power
Termination Power
reserved
Ground
Attention
Ground
Busy
Acknowledge
Reset
Message
Select
Control/Data
Request
Input/Output
Data Bus 8
Data Bus 9
Data Bus 10
Data Bus 11
Adaptec RAIDport
60 PIN UNKNOWN CONNECTOR
Pin
Pin
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
Description
Signal
n/c
n/c
Ground
n/c
REQ[A]#
RSVD
REQ[B]#
REQ[C]#
LED[A]#
n/c
n/c
RSVD
CLK40
Ground
MRW
MD[0]
MD[2]
MD[4]
Ground
MD[6]
MA[14]
MA[12]
MA[10]
MA[8]
PRSNT1
MA[6]
MA[4]
Ground
MA[2]
B30
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
MA[0]
n/c
n/c
n/c
n/c
ACK[A]#
RSVD
ACK[B]#
ACK[C]#
IDDAT
n/c
n/c
SY_RST#
ROMCS[A]#
RAMCS#
Ground
MDP
MD[1]
RAMPS#
MD[3]
MD[5]
MA[13]
MD[7]
MA[11]
MA[9]
MA[7]
Ground
MA[5]
MA[3]
SEECS[A]
MA[1]
IEEE488
12 PIN UNKNOWN CONNECTOR at the Computer
1 2 3 4 5 6
= = = = = =
###### ###########
(At the computer)
= = = = = =
A B C D E F
Pin
A or 1
B or 2
C or 3
D or 4
E or 5
F or 6
Description
GND
+5v
Motor (computer controlled +6v for datasette motor)
Read line from casette
Write line cassette
Cassette Switch Sense (monitors cassette play/ff/rew buttons)
Digital Joystick 1
Pin
1
2
3
4
5
6
7
8
9
Digital Joystick 2
Pin
1
2
3
4
5
6
7
8
9
n/c
FIRE2
FIRE1
GND
n/c
-
Not connected
Fire button 2
Fire button 1
Ground
Not connected
Name
GAMESW1
+5V
GND
n/a
Description
Switch input 1 (sometimes called paddle button 1).
+5 VDC (max 100mA)
System ground.
Not used
Paddle 0 hand controller input. Must be connected to a 150K ohm variable resistor
PDL0
connected to +5V.
n/c
Not connected
GAMESW0 Switch input 0 (sometimes called paddle button 0).
Paddle 1 hand controller input; must be connected to a 150K ohm variable resistor
PDL1
connected to +5V.
n/a
Not used
Sticks
Pin
1
2
3
4
5
6
7
8
9
Description
Up
Down
Left
Right
NC
Fire
NC
Ground
NC
Paddles
Pin
1
2
3
4
5
6
7
8
9
Description
NC
NC
2P Fire
1P Fire
NC
NC
+5v (pot common)
Ground
2P Paddle
Description
Up thru
Down thru
Left thru
Right thru
Front trigger
Fire thru
+5v (triggers)
Ground
Top trigger
1
2
3
4
5
6
7
8
9
*
0
#
+5v pulls pins 5 & 9
through 4.7k resistors
Color
WHT
BLU
GRN
BRN
n/c
ORG
n/c
BLK
n/c
Dir
Description
Up
Down
Left
Right
Not connected
Button
Not connected
Ground(-)
Not connected
Description
Keypad -- right column
Keypad -- middle column
Keypad -- left column
Start, Pause, and Reset common
Keypad -- third row and Reset
Keypad -- second row and Pause
Keypad -- top row and Start
Keypad -- bottom row
Pot common
Horizontal pot (POT0, 2, 4, 6)
Vertical pot (POT1, 3, 5, 7)
5 volts DC
Bottom side buttons (TRIG0, 1, 2, 3)
Top side buttons
0 volts -- ground
Color Dir
Description
WHT
Up
BLU
Down
GRN
Left
BRN
Right
RED
Button (R)ight (-)
ORG ?
Both buttons (+)
n/c
Not connected
BLK
Ground(-)
YLW
Button (L)eft (-)
Name
Description
UP0
Up 0
DOWN0
Down 0
LEFT0
Left 0
RIGHT0
Right 0
PAD0Y
Paddle 0 Y
FIRE0/LIGHT GUN Fire 0/Lightgun
VCC
+5 VDC
n/c
Not connected
GND
Ground
FIRE2
Fire 2
UP2
Up 2
DOWN2
Down 2
LEFT2
Left 2
RIGHT2
Right 2
PAD0X
Paddle 0 X
Name
Description
UP0
Up 0
DOWN0
Down 0
LEFT0
Left 0
RIGHT0
Right 0
PAD0Y
Paddle 0 Y
FIRE0/LIGHT GUN Fire 0/Lightgun
VCC
+5 VDC
n/c
Not connected
GND
Ground
FIRE2
Fire 2
UP2
Up 2
DOWN2
Down 2
LEFT2
Left 2
RIGHT2
Right 2
PAD0X
Paddle 0 X
Atari Mouse/Joy
Mouse
C16/C116/+4 Joystick
Available on the Commodore C16, C116 and +4 computers.
Joystick 1
Pin
1
2
3
4
5
6
7
8
Name
Dir
Comment
JOYA0
JOYA1
JOYA2
JOYA3
+5VDC
BUTTON A
?
GND
COMMON A ? ?
Is connected to DATA2 thru a buffer.
Joystick 2
Pin
1
2
3
4
5
6
7
8
Name
Dir
Comment
JOYB0
JOYB1
JOYB2
JOYB3
+5VDC
BUTTON B
?
GND
COMMON B ? ?
Is connected to DATA1 thru a buffer.
Control Port 1
Pin
1
2
3
4
5
6
7
8
9
Name
Dir Comment
JOYA0
JOYA1
JOYA2
JOYA4
POT AY
BUTTON A/LP
+5V
50 mA max
GND
POT AX
Control Port 2
Pin
1
2
3
4
5
Name
JOYB0
JOYB1
JOYB2
JOYB4
POT BY
Dir
Comment
6
7
8
9
BUTTON B
+5V
GND
POT BX
50 mA max
MSX Joystick
Name
Dir
Description
/FORWARD
Forward
/BACK
Backward
/LEFT
Left
/RIGHT
Right
+5V
+5 VDC (50mA max)
/TRG1
Trigger A / Output 1
/TRG2
Trigger A / Output 1
OUTPUT
Output 3
GND
Signal Ground
NeoGeo Joystick
Available on the NeoGeo videogame.
Name
GND
n/c
SELECT
BUTTOND
BUTTONB
RIGHT
DOWN
n/c
BUTTOND
n/c
START
BUTTONC
BUTTONA
LEFT
UP
Dir
-
Description
Ground
Not connected
Select Button
"D" Button
"B" Button
Right
Down
Not connected
"D" Button, again?
Not connected
Start Button
"C" Button
"A" Button
Left
Up
Description
+5v
Data Clock
Data Latch
Serial Data
N/C
N/C
Ground
Wire Color
White
Yellow
Orange
Red
Brown
PC Gameport
PC Gameport+MIDI
Some soundcards have some MIDI signals included in their Gameport. Ground and VCC has been used
for this.
Name
Dir Description
+5V
+5 VDC
/B1
Button 1
X1
Joystick 1 - X
GND
Ground
GND
Ground
Y1
Joystick 1 - Y
/B2
Button 2
+5V
+5 VDC
+5V
+5 VDC
/B4
Button 4
X2
Joystick 2 - X
MIDITXD
MIDI Transmit
Y2
Joystick 2 - Y
/B3
Button 3
MIDIRXD
MIDI Receive
Source:
?
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
Name (Select=GND)
Up
Down
Gnd / Left
Gnd / Right
+5VDC
Button A
Select
Ground
Start
Name (Select=+5V)
Up
Down
+5VDC
Button B
Select
Ground
Button C
The chip inside the controller is a 74HC157. This is a high-speed cmos quad 2-line to 1-line multiplexer.
The console can with help of the Select-pin choose from two functions on each input.
Contributor: Joakim gren, Neal Patrick Howland
Source:
SEGA Genesis A/V pinout at GamesX
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2000-07-09
Name
DATA
CMD
N/C (9 V unused)
GND
VCC
ATT
CLK
N/C
ACK
Description
Data
Command
Not connected
Ground
Vcc
ATT select
Clock
Not connected
Acknowledge
Signals description:
DATA
Signal from Controller to PSX. This signal is an 8 bit serial transmission synchronous to the falling edge
of clock (That is both the incoming and outgoing signals change on a high to low transition of clock. All
the reading of signals is done on the leading edge to allow settling time.)
COMMAND
Signal from PSX to Controller. This signal is the counter part of DATA. It is again an 8 bit serial
transmission on the falling edge of clock.
VCC
VCC can vary from 5V down to 3V and the official SONY Controllers will still operate. The controllers
outlined here really want 5V. The main board in the PSX also has a surface mount 750mA fuse that will
blow if you try to draw to much current through the plug (750mA is for both left, right and memory
cards).
file:///C|/tmp/tech/HwB/connector/userinput/psxjoy.html (1 of 2) [6/15/2001 12:02:37 AM]
ATT
ATT is used to get the attention of the controller. This signal will go low for the duration of a
transmission. I have also seen this pin called Select, DTR and Command.
CLOCK
Signal from PSX to Controller. Used to keep units in sync.
ACK
Acknowledge signal from Controller to PSX. This signal should go low for at least one clock period after
each 8 bits are sent and ATT is still held low. If the ACK signal does not go low within about 60 us the
PSX will then start interogating other devices.
Contributor: Joakim gren
Source:
Sony Playstation Controller Information
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-08
Dir
OUT
IN
IN
IN
OUT
IN
IN
Name
N.C.
Test joystick 2
UP
Fire button pressed
Left
N.C.
Test joystick
Down
Right
Vectrex Controller
9 PIN UNKNOWN CONNECTOR
Pin
1
2
3
4
5
6
7
8
9
Description
Button 1
Button 2
Button 3
Button 4
Horizontal Pot
Vertical Pot
+5V
GND
-5V
The joystick potentiometers work by voltage division between -5V and +5V. Actually, it uses a couple of
resistors on each side to make it more like -3.4V to 3.4V.
Vertical Pin 6:
Voltage
-3.4 V
0V
+3.4 V
Direction
Down
Center
Up
Horizontal Pin 5:
Voltage
-3.4 V
0V
+3.4 V
Direction
Left
Center
Right
Name
DATA
CLOCK
GND
GND
+12V
n/c
n/c
n/c
n/c
Description
Data
Clock
Ground
Ground
+12 VDC
Not connected
Not connected
Not connected
Not connected
Keyboard (5 Amiga)
(at the computer)
5 PIN DIN 180 (DIN41524) FEMALE (A1000/A2000/A3000) at the computer.
Pin
1
2
3
4
5
A1000
+5 Volts
CLOCK
DATA
GND
n/c
A2000/A3000
KCLK
KDAT
n/c
GND
+5 Volts
Keyboard (5 PC)
(at the computer)
5 PIN DIN 180 (DIN41524) FEMALE at the computer.
Pin
1
2
3
4
5
Name
CLOCK
DATA
n/c
GND
VCC
Description
Technical
Clock
CLK/CTS, Open-collector
Data
RxD/TxD/RTS, Open-collector
Not connected Reset on some very old keyboards.
Ground
+5 VDC
Keyboard (6 Amiga)
(at the computer)
6 PIN MINI-DIN FEMALE (PS/2 STYLE) (A4000/CDTV) at the computer.
Pin
1
2
3
4
5
6
Name Dir
Description
/DATA
Data
n/c
Not connected
GND
Ground
+5V
+5 Volts DC (100 mA max)
CLOCK
Clock
n/c
Not connected
Keyboard (6 PC)
(at the computer)
6 PIN MINI-DIN FEMALE (PS/2 STYLE) at the computer.
Pin
1
2
3
4
5
6
Name Dir
Description
DATA
Key Data
n/c
Not connected
GND
Ground
VCC
Power , +5 VDC
CLK
Clock
n/c
Not connected
Name Dir
Description
/DATA
Data
/TxD
Transmit Data (0-5V and reversed)
GND
Ground
+5V
+5 Volts DC (100 mA max)
CLOCK
Clock
/RxD
Receive Data (0-5V and reversed)
Keyboard (XT)
(at the computer)
5 PIN DIN 180 (DIN41524) FEMALE at the computer.
Pin
1
2
3
4
5
Name
CLK
DATA
/RESET
GND
VCC
Description
Technical
Clock
CLK/CTS, Open-collector
Data
RxD, Open-collector
Reset
Ground
+5 VDC
Macintosh Keyboard
Available on Macintosh Mac Plus and earlier.
SUN Keyboard/Mouse
Available on SUN3's and older
Name
Dir
Description
Keyboard In
Keyboard In
GND
Ground
Keyboard Out
Keyboard Out
GND
Ground
Mouse In
Mouse In
GND
Ground
Mouse Out
Mouse Out (!)
GND
Ground
GND
Ground
VCC
Power , +5 VDC
VCC
Power , +5 VDC
VCC
Power , +5 VDC
VCC
Power , +5 VDC
VCC
Power , +5 VDC
VCC
Power , +5 VDC
Name
Dir
Description
1
2
3
4
5
6
GND
GND
VCC
Mouse In
Keyboard Out
Keyboard In
Power On
VCC
Ground
Ground
Power , +5 VDC
Mouse In
Keyboard Out
Keyboard In
Power On (Configurable as Mouse Out on 3/80, 4300, 4400 and 600MP
CPUs!)
Power, +5 VDC
TI-99/4A Keyboard
UNKNOWN connector (inside the console) Red wire is #15
Pin
5
4
1
2
7
3
10
11
12 13
=
.
space L
enter O
9
fctn 2
shift S
ctrl W
X
14
,
K
I
8
3
D
E
C
15
M
J
U
7
4
F
R
V
9
N
H
Y
6
5
G
T
B
8 6
/
;
P
0
1 lock
A
Q
Z
Note:
Pressing a key closes the contact between corresponding row + column. Since there are no diodes to
prevent current going backwards, pressing 3 keys at a time often results in appearance of a "phantom"
key at the 4th corner of the square formed by these keys (e.g 8+7+3=phantom 4: current goes
pin15-7-8-3-pin7 as if 4 were pressed).
Contributor: Joakim gren
Source:
?
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2000-07-09
Amiga Mouse/Joy
Mouse/Trackball
V-pulse
H-pulse
VQ-pulse
HQ-pulse
BUTTON 3(M)
BUTTON 1(L)
+5V
GND
BUTTON 2(R)
Lightpen
n/c
n/c
n/c
n/c
Penpress
/Beamtrigger
+5V
GND
BUTTON 2
Digital Joystick
/FORWARD
/BACK
/LEFT
/RIGHT
n/c
/BUTTON 1
+5V
GND
BUTTON 2
Paddle
Dir Comment
BUTTON 3
n/c
BUTTON 1
BUTTON 2
PotX
n/c
+5V
50 mA max
GND
PotY
Name
Ground
+5V
GND
X2
X1
?
SWY2
Y1
Description
+5 VDC
Ground
Horizontal movement line (connected to VIA PB4 line)
Horizontal movement line (connected to SCC DCDA- line)
?
Mouse button line (connected to VIA PB3)
Vertical movement line (connected to VIA PB5 line)
Vertical movement line (connected to SCC DCDB- line)
Macintosh Mouse
Available on Macintosh Mac Plus and earlier.
Name Dir
Description
CGND
Chassis ground
+5V
+5 VDC
CGND
Chassis ground
X2
Horizontal movement line (connected to VIA PB4 line)
X1
Horizontal movement line (connected to SCC DCDA-line)
n/c
Not connected
SWMouse button line (connected to VIA PB3)
Y2
Vertical movement line (connected to VIA PB5 line)
Y1
Vertical movement line (connected to SCC DCDB-line)
Mouse (PS/2)
(at the computer)
6 PIN MINI-DIN FEMALE (PS/2 STYLE) at the computer.
Pin
1
2
3
4
5
6
Name Dir
Description
DATA
Key Data
n/c
Not connected
GND
Ground
VCC
Power , +5 VDC
CLK
Clock
n/c
Not connected
Name
+5V
-5V
n/c
n/c
MTXD
n/c
n/c
n/c
GND
Dir
Description
+5 VDC
-5 VDC
Not connected
Not connected
Data
Not connected
Not connected
Not connected
Ground
Name
Data
Power On
+5V
GND
Description
Data, grounded by an open collector or pulled to +5 V through 470
Power on, fed by +5 V through 100 k; connect to pin 4 to turn on the system
+5 V at 500 mA maximum drain; protected by a 1.25-A circuit breaker
Ground return
What does the information that is listed for each adapter mean? See the tutorial.
Audio/Video
Video
Macintosh Video to VGA
Parallel
Parallel
A1000 to Amiga Parallel
Centronics to LapLink
Serial
Mouse
PS/2 to Serial Mouse
Serial to PS/2 Mouse
Serial
9 to 25 Serial
Nullmodem
Serial to PS/2 Mouse
Mice/Keyboards/Joysticks
Joystick
Amiga 4 Joysticks
PC 2 Joysticks
Keyboard
DIN to Mini-DIN Keyboard
Mini-DIN to DIN Keyboard
PS/2 Keyboard (Gateway) Y
PS/2 Keyboard (IBM Thinkpad) Y
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
Short tutorial
Heading
First at each page there a short heading describing the adapter.
Pin table
The pin table is perhaps the information you are looking for. It should be quite simple to read. Contains
mostly the following three columns; Name, Pin 1, Pin 2. Sometimes when not the same pin is connected
to each side there is another column describing the name at connector 2.
9-Pin
Carrier Detect
1
Receive Data
2
Transmit Data
3
Data Terminal Ready 4
System Ground
5
Data Set Ready
6
Request to Send
7
Clear to Send
8
Ring Indicator
9
25-Pin
8
3
2
20
7
6
4
5
22
Mac
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VGA Dir
6
1
13
4
2
7
11
n/c
3
12
10
14
8
n/c
n/c
Amiga
23
24
25
14
15
16
Centronics to LapLink
This adapter will allow you to use a normal printercable (Centronics) as a LapLink/InterLink cable.
36-Cen
2
3
4
5
6
10
11
12
13
32
16
17
19-30+33
25-DSub
15
13
12
10
11
5
6
4
3
2
16
17
18-25
Name
Error
Select
Paper Out
Acknowledge
Busy
Data Bit 3
Data Bit 4
Data Bit 2
Data Bit 1
Data Bit 0
Reset
Select
Signal Ground
Mini-DIN
3
2
6
4
D-SUB
5
2
3
7
GND
RxD
TxD
RTS
D-SUB
4+7+9
1
3+5
6
DTR+RTS+RI
CD
TXD+GND
DSR
9 to 25 Serial
This adapter will enable you to connect a 25 pin serialcable to a 9 pin connector at the computer.
25-Pin
8
3
2
20
7
6
4
5
22
Nullmodem
This adapter will enable you to use a normal serialcable as a nullmodem.
Male
1
3
2
5
4
20
6
7
Shield Ground
Receive Data
Transmit Data
Clear to Send
Request to Send
Data Terminal Ready
Data Set Ready
Ground
Amiga 4 Joysticks
This adapter will make it possible to connect 2 extra joysticks to the Amiga. This requires that the game
is aware of this Multi-Joystick Extender in order to use it. The adapter is connected to the parallelport of
the Amiga.
Parport
2
3
4
5
6
7
8
9
11
13
18
19
Joy 1 Joy 2
1
2
3
4
1
2
3
4
6
6
8
8
Source:
Tomi Engdahl's Joystick page
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
PC 2 Joysticks
This adapter will make it possible to connect 1 extra joystick to the PC. The gameport contains pins for
two joysticks but you will need this adapter to be able to connect two joysticks to one connector.
PC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Joy 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Joy 2
-
4
5
1
2
3
6
7
+5 VDC
15 15
Note: Since pin 12 is often used for MIDI-signals on gameport equipped soundcards it's better to use the
ground from pin 4 & 5, pin 15 is also used for MIDI-signals...
Contributor: Joakim gren
Source:
Tomi Engdahl's Joystick page
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
Mini-DIN
Shield
5
1
3
4
DIN
Shield
2
4
5
1
Keyboard
2
3
4
6
-
Mouse
2
3
4
6
Keyboard
2
3
4
6
-
Mouse
1,2
3
4
5
6
Filter
Active Filter: Bessel 12dB Highpass
Active Filter: Bessel 12dB Lowpass
Active Filter: Bessel 18dB Highpass
Active Filter: Bessel 18dB Lowpass
Active Filter: Bessel 24dB Highpass
Active Filter: Bessel 24dB Lowpass
Active Filter: Butterworth 12dB Highpass
Active Filter: Butterworth 12dB Lowpass
Active Filter: Butterworth 18dB Highpass
Active Filter: Butterworth 18dB Lowpass
Active Filter: Butterworth 24dB Highpass
Active Filter: Butterworth 24dB Lowpass
Active Filter: Butterworth 6dB Highpass
Active Filter: Butterworth 6dB Lowpass
Active Filter: Linkwitz 24dB Highpass
Active Filter: Linkwitz 24dB Lowpass
Misc
Operation Amplifier: Addition
Operation Amplifier: Inverting Amplifier
Operation Amplifier: Non-inverting Amplifier
Serial
C64 to RS232 Interface
CD32 Keyboard to Serial Interface 1
CD32 Keyboard to Serial Interface 2
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
Short tutorial
Heading
First at each page there a short heading describing what the connector is.
Pin table
The pin table is perhaps the information you are looking for. Should be simple to read. Contains mostly
the following three columns; Pin, Name & Description.
Pin
1
2
3
4
5
Name
CLOCK
GND
DATA
VCC
n/c
Description
Key Clock
GND
Key Data
+5 VDC
Not connected
C=4.7n-10nF
Ra=1.1017/(2*pi*Fc*C)
Rb=1.4688/(2*pi*Fc*C)
Units: Rx [Ohm], C [F], Fc [Hz]
Contributor: Joakim gren
Source:
?
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
R=4.7k-10 kOhm
Ca=0.9076/(2*pi*Fc*R)
Cb=0.6809/(2*pi*Fc*R)
Units: R [Ohm], Cx [F], Fc [Hz]
Contributor: Joakim gren
Source:
?
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
C=4.7n-10nF
Ra=1.0474/(2*pi*Fc*C)
Rb=2.0008/(2*pi*Fc*C)
Rc=1.3228/(2*pi*Fc*C)
Units: Rx [Ohm], C [F], Fc [Hz]
Contributor: Joakim gren
Source:
?
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
R=4.7k-10 kOhm
Ca=0.9548/(2*pi*Fc*R)
Cb=0.4998/(2*pi*Fc*R)
Cc=0.7560/(2*pi*Fc*R)
Units: R [Ohm], Cx [F], Fc [Hz]
Contributor: Joakim gren
Source:
?
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
C=4.7n-10nF
Ra=1.3701/(2*pi*Fc*C)
Rb=1.4929/(2*pi*Fc*C)
Rc=0.9952/(2*pi*Fc*C)
Rd=2.5830/(2*pi*Fc*C)
Units: Rx [Ohm], C [F], Fc [Hz]
Contributor: Joakim gren
Source:
?
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
R=4.7k-10 kOhm
Ca=0.7298/(2*pi*Fc*R)
Cb=0.6699/(2*pi*Fc*R)
Cc=1.0046/(2*pi*Fc*R)
Cd=0.3872/(2*pi*Fc*R)
Units: R [Ohm], Cx [F], Fc [Hz]
Contributor: Joakim gren
Source:
?
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
C=4.7n-10nF
Ra=0.7071/(2*pi*Fc*C)
Rb=1.414/(2*pi*Fc*C)
Units: Rx [Ohm], C [F], Fc [Hz]
Contributor: Joakim gren
Source:
?
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
R=4.7k-10 kOhm
Ca=1.414/(2*pi*Fc*R)
Cb=0.7071/(2*pi*Fc*R)
Units: R [Ohm], Cx [F], Fc [Hz]
Contributor: Joakim gren
Source:
?
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
C=4.7n-10nF
Ra=0.500/(2*pi*Fc*C)
Rb=2.000/(2*pi*Fc*C)
Rc=1.000/(2*pi*Fc*C)
Units: Rx [Ohm], C [F], Fc [Hz]
Contributor: Joakim gren
Source:
?
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
R=4.7k-10 kOhm
Ca=2.000/(2*pi*Fc*R)
Cb=0.500/(2*pi*Fc*R)
Cc=1.000/(2*pi*Fc*R)
Units: R [Ohm], Cx [F], Fc [Hz]
Contributor: Joakim gren
Source:
?
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
C=4.7n-10nF
Ra=0.9239/(2*pi*Fc*C)
Rb=1.0824/(2*pi*Fc*C)
Rc=0.3827/(2*pi*Fc*C)
Rd=2.6130/(2*pi*Fc*C)
Units: Rx [Ohm], C [F], Fc [Hz]
Contributor: Joakim gren
Source:
?
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
R=4.7k-10 kOhm
Ca=1.0824/(2*pi*Fc*R)
Cb=0.9239/(2*pi*Fc*R)
Cc=2.6130/(2*pi*Fc*R)
Cd=0.3827/(2*pi*Fc*R)
Units: R [Ohm], Cx [F], Fc [Hz]
Contributor: Joakim gren
Source:
?
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
C=4.7n-10nF
R=1.000/(2*pi*Fc*C)
Units: R [Ohm], C [F], Fc [Hz]
Contributor: Joakim gren
Source:
?
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
R=4.7k-10 kOhm
C=1.000/(2*pi*Fc*R)
Units: R [Ohm], C [F], Fc [Hz]
Contributor: Joakim gren
Source:
?
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
C=4.7n-10nF
Ra=Rc=1/(2*sqr(2)*pi*Fc*C)
Rb=Rd=2Ra
Units: Rx [Ohm], C [F], Fc [Hz]
Contributor: Joakim gren
Source:
?
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
R=4.7k-10 kOhm
Ca=Cc=2*Cb
Cb=Cd=1/(2*sqr(2)*pi*Fc*R)
Units: R [Ohm], Cx [F], Fc [Hz]
Contributor: Joakim gren
Source:
?
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
VOUT= -(V1/R1+V2/R2)*RO
This circuit is used to add several signals to one. By setting all resistors to the same value, R1=R2=RO,
you get the following formula:
VOUT= -(V1+V2)
You can theoretically add how many signals you like. Here's an example with three in-signals:
VOUT= -(V1/R1+V2/R2+V3/R3)*RO
Contributor: Joakim gren
Source:
?
VOUT= -(R2/R1)*VIN
The signal is inverted with this design (notice the minus sign in the formula). But it's very easy to change
the gain with the help of R2.
Contributor: Joakim gren
Source:
?
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
VOUT= (1+R1/R2)*VIN
One positive effect with this design is that the signal isn't inverted. But you can't have less gain than 1
times the in-signal.
Contributor: Joakim gren
Source:
?
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
C64 RS232
_________
PA2
PB1
PB6
FLAG2
PB0
VCC
GND
|
|
M-----------11-|
|-14------------------D-----------10-|
|--7------------------K-----------12-| MAX 232 |-13------------------B---X--------9-|
|--8------------------C---|
|
|--3--|+-|
2-----------16-|
|--1-----|
N------X----15-|
|
X--|+-2-|
|--5--|+-|
X--+|-6-|_________|--4-----|
|
|----------------------------------------
TXD
RTS
CTS
RXD
(2)
(4)
(5)
(3)
DB25-connector
GND (7)
+5V
GND
TxD
RxD
-------------Pin16
-------------Pin15--------------------------GND
------------>Pin10 (---|>*-) Pin7-------->RxD
<------------Pin9
(--*<|--) Pin8<--------Txd
C1
+--)|----Pin1
+----DSR
|
+
(*) |
+--------Pin3
+----DCD
C2
|
+--)|----Pin4
+----DTR
|
+
+--------Pin5
+----RTS
C3
(*) |
GND--|(----Pin6
+----CTS
+
(Polung!)
C4
GND--)|----Pin16
+
C5
+--|(----Pin16
| +
(Polung!)
+--------Pin2
Pin7
Pin3
Pin2
Pin6
Pin8
Pin20
Pin4
Pin5
(**)
shielding-----------------------------------------| |-shielding
connect the shielding of all cables to each other - but only
connect it to only ONE interface port connector (i used the
keyboard plug).
For the condensers C1..C5 you must get 1 uF electrolyt-condesers.
If your signal-converter is kind of the xxx232A (A-type) you must
easy to solder
cheap
fits within a SUB-D 25 plug
does not consume CD32 +5V power ;-)
cons: 'dirty' solution; i.e. circuitry makes use of the 1488/89 tolerances
you may only connect Amiga-computers to your cd32 when using THIS
[1] circuitry - since they all use the 1488/89 chip set.
PCs 'may' work, too. But interface board must contain 1488/89 chip
set.
I do believe that this will work on all Amigas -I tested it at least
on 3 different Amiga-models, however, there is still no guarantee
that this will work on yours.
However, I use both interface-types since about 6 months.
been no problem yet.
There has
s> Also, has anyone made their own connector to the expansion port to
s> pull off the RGB signals? I'd appreciate hearing of your experience.
Yea, does work fine. In use for about 6 months; and still no probs, too.
For details refer to the cd32-faq.
file:///C|/tmp/tech/HwB/circuit/serial/CD32KeyboardToSerial2.html (2 of 5) [6/15/2001 12:02:56 AM]
I am not quite sure about the cd32-pin numbers, just take a look in the
faq.
bis den bald
Klaus
[---------------------------------------------------------------------------]
Date: Fri, 21 Oct 1994 14:55:00 +0100
From: Klaus_Hegemann@punk.fido.de (Klaus Hegemann)
Subject: Re: [2]Using Auxiliary Port as Serial Port
Message-ID: <b1a112f9%fidonet@p29.f113.n2452.z2.fidonet.org>
References: <b1990b05%fidonet@p29.f113.n2452.z2.fidonet.org>
Newsgroups: comp.sys.amiga.cd32
X-Comment-To: sburton@dres.dnd.ca (All)
Organization: Fido.DE domain gateway (IN e.V.)
Lines: 117
X-Gateway: FIDOGATE 3.8.0
X-FTN-Tearline: CrossPoint v3.02
X-FTN-Origin: Josef Matula for President (2:2452/113.29)
X-FTN-Domain: Z242@fidode
X-FTN-Seen-By: 1000/1 150 600 601 2000/1 2452/113 3000/1 4900/99 6000/0
X-FTN-Path: 1000/600 1
Hi!
'updated info:'
Amiga 500,2000,1200,...
level: RS232
-12V..+12V
|\ |
TxD o-------| >|---.
Pin2
|/ |
|
D1
|
1N4001
.-.
| |
| |
IC1 7400
R1 | |
........
(*) `-' 1: _
:
|
___| \ :3
*--*___| O-------->o
|
: |_/ :
.-. 2:
:
| |
:
:
| |
:
:
R2 | |
:
:
(*) `-'
:
:
|
:
:
|
:
:
file:///C|/tmp/tech/HwB/circuit/serial/CD32KeyboardToSerial2.html (3 of 5) [6/15/2001 12:02:56 AM]
Amiga CD32
level: /TTL
0V..+5V
/RxD Pin6
|
===
GND ///
:
:
:
:
:
_ :4
6: / |____
RxD o<-------------------O |____*----o /TxD Pin2
Pin3
: \_|
:
:5
:.......
GND o---------------*-----------------o GND Pin3
Pin7
|
| ........
| 7:
:IC1
*--:GND
:
| 9:
:
*--: \
:
|10: |not :
*--: |used:
|12: |
:
*--: |
:
|13: |
:14
`--: / +5V:-.
:......: |
|
|
+5V o---------------------------'
Pin4
shield o=======================! [n.c.] o shield
Pin1
The RS232-TxD-signal carries +12V or -12V level. As the first step
in conversion the diode D1 blocks if the signal drops to -12V.
In this case the voltage divider (R1,R2) is only connected with
GND potential. So the gate input carries GND level, too.
When the RS232-TxD-signal changes to +12V the diode will pass it
through and the voltage divider now provides a +5V-level signal to
the gate input.
The backward conversion consists of simple negation of the cd32's
/TxD signal. In fact there is no level conversion.
While the conversion for the received signal does
work proper with any RS232 opponent, the sended
signal furthermore carries TTL-level.
The opponent hardware tries to regain the TTL-level signal from
its 'RS232' input. The conversion unit handles the provided
pseudo RS232-type signals correct (as we want ist to be:-).
(*) voltage divider R1-R2:
U
U
R1+R2
R1+R2
= 12V
R1+R2
= 5V
R2
-----U
R2
----R2
U
I
= 5 mA
R1+R2
R1+R2
==> R1+R2 = -----I
R1+R2
= 2400 Ohm
(R1+R2) * U
R2
= 5V ==> R2 = ------------R2
U
R1+R2
R1=1500 Ohm
R2=1000 Ohm ==> I=4.8 mA ==> U(R2)=4.8 V
..
will be OK
Information
ASCII Table
AWG Table
SI Prefixes Table
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
ASCII Table
Dec
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Hex
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
Char
NUL
SOH
STX
ETX
EOT
ENQ
ACK
BEL
BS
TAB
LF
VT
FF
CR
SO
SI
DLE
DC1
DC2
DC3
DC4
NAK
SYN
ETB
CAN
EM
SUB
ESC
FS
GS
RS
Description
Dec
(null)
32
(start of heading)
33
(start of text)
34
(end of text)
35
(end of transmission)
36
(enquiry)
37
(acknowledge)
38
(bell)
39
(backspace)
40
(horizontal tab)
41
(NL line feed, new line) 42
(vertical tab)
43
(NP form feed, new page) 44
(carriage return)
45
(shift out)
46
(shift in)
47
(data link escape)
48
(device control 1)
49
(device control 2)
50
(device control 3)
51
(device control 4)
52
(negative acknowledge) 53
(synchronous idle)
54
(end of trans. block)
55
(cancel)
56
(end of medium)
57
(substitute)
58
(escape)
59
(file separator)
60
(group separator)
61
(record separator)
62
Hex
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
Char Dec
64
!
65
"
66
#
67
$
68
%
69
&
70
'
71
(
72
)
73
*
74
+
75
,
76
77
.
78
/
79
0
80
1
81
2
82
3
83
4
84
5
85
6
86
7
87
8
88
9
89
:
90
;
91
<
92
=
93
>
94
Hex
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
Char
@
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
T
U
V
W
X
Y
Z
[
\
]
^
Dec
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
Hex
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
Char
`
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
q
r
s
t
u
v
w
x
y
z
{
|
}
~
31 1F
US
(unit separator)
63 3F
95 5F
127 7F
DEL
Format control
BS
Backspace. Indicates movement of the printing mechanism or display cursor backwards in one position.
HT
Horizontal Tabulation. Indicates movement of the printing mechanism or display cursor forward to the
next preassigned 'tab' or stopping position.
LF
Line Feed. Indicates movement of the printing mechanism or display cursor to the start of the next line
(ie one line down).
VT
Vertical Tabulation. Indicates movement of the printing mechanism or display cursor to the next of a
series of preassigned printing lines.
FF
Form Feed. Indicates movement of the printing mechanism or display cursor to the starting position of
the next page, form, or screen.
CR
Carriage Return. Indicates movement of the printing mechanism or display cursor to the starting position
(left) of the current line.
Transmission control
SOH
Start of Heading. Used to indicate the start of a heading which may contain address or routing
information.
STX
Start of Text. used to indicate the start of the text and so also indicates the end of the heading.
ETX
End of Text. Used to terminate the text which was started with STX. End of Transmission indicates the
end of a transmission which may have included one or more 'texts' with their headings.
ENQ
Enquiry. A request for a response from a remote station. It may be used as a "who are you?" request for a
station to identify itself.
ACK
Acknowledge. A character transmitted by a receiving device as an affirmation response to a sender. It is
used as a positive response to polling messages.
NAK
Negative Acknowledgement. A character transmitted by a receiving device as a negative response to a
sender. It is used as a negative response to polling messages.
SYN
Synchronous/Idle. Used by a synchronous transmission system to achieve synchronisation. When no data
is being sent a synchronous transmission system may send SYN characters continuously.
ETB
End of Transmission Block. Indicates the end of a block of data for communication purposes. It is used
for blocking data where the block structure is not necessarily related to the processing format.
Information separator
FS
File Separator.
GS
Group Separator.
RS
Record Separtator.
US
Unit Separator.
Information separators to be used in an optional manner except that their heirarchy shall be FS (the most
inclusive) to US (the least inclusive).
Miscellaneous
NUL
Null. No character. Used for filling in time or filling space on tape when there is no data.
BEL
Bell. Used when there is need to call human attention. It may control alarm or attention devices.
SO
Shift Out. Indicates that the code combinations which follow shall be interpreted as _outside_ the
standard character set until an SI character is reached.
SI
Shift In. Indicates that the code combinations which follow shall be interpreted according to the standard
character set.
DLE
Data Link Escape. A character which shall change the meaning of one or more contiguously following
characters. It can provide supplementary controls or permits the sending of data characters having any bit
combination.
CAN
Cancel. Indicates that the data which preceeds it in a message or block should be disregarded (usually
because an error has been detected).
EM
End of Medium. Indicates the physical end of a card, tape or other medium, or the end of the required or
used portion of the medium.
SUB
Substitute. Substituted for a character that is found to be erroneous or invalid.
ESC
Escape. A character intended to provide code extension in that it gives a specified number of
contiguously following characters an alternate meaning.
SP
Space. A nonprinting character used to separate words, or to move the printing mechanism or display
cursor forward by one position.
DEL
Delete. Used to obliterate unwanted characters (for example, on paper tape by punching a hole in
_every_ bit position).
Contributor: Joakim gren
Source:
ASCII table at The Pin-Out directory
Data & Computer Communications from Stallings
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
AWG Table
AWG=American Wire Gauge standard
Gauge
AWG
46
44
42
41
40
39
38
37
36
35
34
33
32
30
29
27
26
25
24
22
20
Diam
mm
0,04
0,05
0,06
0,07
0,08
0,09
0,10
0,11
0,12
0,13
0,14
0,15
0,16
0,17
0,18
0,19
0,20
0,25
0,30
0,35
0,40
0,45
0,50
0,55
0,60
0,65
0,70
0,75
0,80
Area
mm2
0,0013
0,0020
0,0028
0,0039
0,0050
0,0064
0,0078
0,0095
0,011
0,013
0,015
0,018
0,020
0,023
0,026
0,028
0,031
0,049
0,071
0,096
0,13
0,16
0,20
0,24
0,28
0,33
0,39
0,44
0,50
R
ohm/km
13700
8750
6070
4460
3420
2700
2190
1810
1520
1300
1120
970
844
757
676
605
547
351
243
178
137
108
87,5
72,3
60,7
51,7
44,6
38,9
34,1
I at 3A/mm2
mA
3,8
6
9
12
15
19
24
28
33
40
45
54
60
68
75
85
93
147
212
288
378
477
588
715
850
1,0 A
1,16 A
1,32 A
1,51 A
19
18
16
14
13
12
0,85
0,90
0,95
1,00
1,10
1,20
1,30
1,40
1,50
1,60
1,70
1,80
1,90
2,00
0,57
0,64
0,71
0,78
0,95
1,1
1,3
1,5
1,8
2,0
2,3
2,6
2,8
3,1
30,2
26,9
24,3
21,9
18,1
15,2
13,0
11,2
9,70
8,54
7,57
6,76
6,05
5,47
1,70 A
1,91 A
2,12 A
2,36 A
2,85 A
3,38 A
3,97 A
4,60 A
5,30 A
6,0 A
6,7 A
7,6 A
8,5 A
9,4 A
SI Prefixes Table
Example: 1 TW=1000 GW (W=Watt)
Symbol
Z
E
P
T
G
M
k
h
da
d
c
m
u
n
p
f
a
z
y
Prefix
Zetta
Exa
peta
tera
giga
Mega
kilo
hecto
deca
deci
centi
milli
micro
nano
pico
femto
atto
zepto
yokto
Factor
1021
1018
1015
1012
109
106
103
102
101
10-1
10-2
10-3
10-6
10-9
10-12
10-15
10-18
10-21
10-24
Prefix
peta
tera
giga
Mega
kilo
Factor
250
240
230
220
210
Factor
1125899906842624
1099511627776
1073741824
1048576
1024
Source:
Farnell Components Catalogue
Copyright The Hardware Book Team 1996-2001.
May be copied and redistributed, partially or in whole, as apropriate.
Document last modified: 2001-06-07
Here are some links to good sites of technical information on the Internet.
I have a lot of pages I will add as soon as I get the time for it. They are currently in my bookmarks file.
Remember that I usually add links to pages covering a specific topic at bottom of the best suited HwB
page.
Misc:
Name
Author
TheRef
F. Robert Falbo
Blue Planet
The Tech Page
Corporation
Norm's Industrial Electronics
Norman Dyrvik
Circuit Cookbook
Dan Charrois
Electrical Engineering Circuits Archive Jerry Russell
sandpile.org: 80x86
Christian Ludloff
Many
Stefan Wieman
Tomi Engdahl
PC Mechanic
David Risley
Richard Steven
Walz
Jaap van Ganswijk
Lawrence Wright
Comment
Pin-Outs.com
Name
Author
Comment
alt.comp.hardware.homebuilt FAQ
Mark Sokos
FAQs:
If you have any more good links of interest, please send us an e-mail.
Feel free to add a link to Hardware Book at Your page. You can use this banner if you would like to:
Please help us make this reference guide larger. We guess there is much more to add. Don't hesitate to
send some strange pinout, circuit or cable.
If you have a strange serial-port on your dish-washer, SEND it to us :-)
If it does not have one you could send me a circuit on how to add a serial-port to it. :-)
We have already heard from two people that has a serial port on their dish-washers :)
Tomas gren
Editor of HwB.
Niklas Edmundsson
Editor of HwB.
Magnus Jonsson
Editor of HwB.
Could it be even better? Perhaps if You help us. Please send any material you have that might be of
interest for this project. Send it to us.
We would especially like to thank the following people:
Academic Computer Club For hosting the current Hardware Book Main Site
Karl Asha
Rob Gill
Petr Krc
Marco Budde