`timescale 1ns/1ps

module FullAdder(SumOut,CarryOut,In1,In2,CarryIn);
output SumOut;
output CarryOut;
input In1,In2;
input CarryIn;
SumOut = In1^In2^CarryIn;
CarryOut= In1&In2|((In1^In2)&CarryIn);
endmodule
module multiplexer(Out,InA,InB,Select);'
output Out;
input InA,InB,Select;
if(Select==0)
begin
Out=InA;
end
else
begin
Out=InB;
end
endmodule
module 8bitAdder(Sum_8,In1_8,In2_8,CarryIn_8,CarryOut_8);
output[7:0] Sum_8;
output CarryOut_8;
input[7:0] In1_8,In2_8;
input CarryIn_8;
FullAdder
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adder1(Sum_8[0],Carry1,In1_8[0],In2_8[0],CarryIn);
adder2(Sum_8[1],Carry2,In1_8[1],In2_8[1],Carry1);
adder3(Sum_8[2],Carry3,In1_8[2],In2_8[2],Carry2);
adder4(Sum_8[3],Carry4,In1_8[3],In2_8[3],Carry3);
adder5(Sum_8[4],Carry5,In1_8[4],In2_8[4],Carry4);
adder6(Sum_8[5],Carry6,In1_8[5],In2_8[5],Carry5);
adder7(Sum_8[6],Carry7,In1_8[6],In2_8[6],Carry6);
adder8(Sum_8[7],CarryOut_8,In1_8[7],In2_8[7],Carry7);

endmodule

module CarrySelectAdder(sum,cout,op1,op2,reset,clock);
output[63:0] sum;
output cout;

input[63:0] op1,op2;
input reset,clock;
reg[63:0] op1_reg,op2_reg,sum_reg,sum;
reg Carry_In;
always@(posedge reset) begin
op1_reg<=63'b0;
op2_reg<=63'b0;
sum<=63'b0;
Carry_In<=0;
reg[14:0] Carry_Out;
end
always@(posedge clock) begin
op1_reg<=op1;
op2_rge<=op2;
sum=sum_reg;
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adder1(sum_reg[7:0],op1[7:0],op2[7:0],Carry_In,Carry_Out[0]);
adder2(sum_reg[15:8],op1[15:8],op2[15:8],0,Carry-Out[1]);
adder3(sum_reg[23:16],op1[23:16],op2[23:16],0,Carry-Out[2]);
adder4(sum_reg[31:24],op1[31:24],op2[31:24],0,Carry-Out[3]);
adder2(sum_reg[15:8],op1[15:8],op2[15:8],0,Carry-Out[1]);
adder2(sum_reg[15:8],op1[15:8],op2[15:8],0,Carry-Out[1]);
adder2(sum_reg[15:8],op1[15:8],op2[15:8],0,Carry-Out[1]);
adder2(sum_reg[15:8],op1[15:8],op2[15:8],0,Carry-Out[1]);