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  • Top Pins

    Uploaded by

    Manoj Kumar
    13 views5 pages
    kkkk

    Original Title

    top_pins

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    kkkk

    Copyright:

    © All Rights Reserved
    Download as TXT, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    13 views5 pages

    Top Pins

    Uploaded by

    Manoj Kumar
    kkkk

    Copyright:

    © All Rights Reserved
    Download as TXT, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 5

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    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN

    R3 [get_ports FPGA_CLKP]
    P3 [get_ports FPGA_CLKN]
    U4 [get_ports CPU_RESET]
    M20 [get_ports HDR_1]
    L20 [get_ports HDR_2]
    L24 [get_ports HDR_3]
    L25 [get_ports HDR_4]
    M24 [get_ports HDR_5]
    M25 [get_ports HDR_6]
    L22 [get_ports HDR_7]
    L23 [get_ports HDR_8]
    M21 [get_ports HDR_9]
    M22 [get_ports HDR_10]
    P21 [get_ports HDR_11]
    N23 [get_ports HDR_12]
    N24 [get_ports HDR_13]
    P19 [get_ports HDR_14]
    N19 [get_ports HDR_15]
    P23 [get_ports HDR_16]
    P16 [get_ports HDR_28]
    N16 [get_ports HDR_29]
    N17 [get_ports HDR_30]
    R16 [get_ports HDR_31]
    K26 [get_ports HDR_32]
    AE25 [get_ports {ADC1P_D[0]}]
    AE26 [get_ports {ADC1N_D[0]}]
    AC22 [get_ports {ADC1P_D[1]}]
    AC23 [get_ports {ADC1N_D[1]}]
    AF24 [get_ports {ADC1P_D[2]}]
    AF25 [get_ports {ADC1N_D[2]}]
    AD25 [get_ports {ADC1P_D[3]}]
    AD26 [get_ports {ADC1N_D[3]}]
    AE23 [get_ports {ADC1P_D[4]}]
    AF23 [get_ports {ADC1N_D[4]}]
    AD23 [get_ports {ADC1P_D[5]}]
    AD24 [get_ports {ADC1N_D[5]}]
    AD21 [get_ports {ADC1P_D[6]}]
    AE21 [get_ports {ADC1N_D[6]}]
    AF19 [get_ports {ADC1P_D[7]}]
    AF20 [get_ports {ADC1N_D[7]}]
    AE22 [get_ports {ADC1P_D[8]}]
    AF22 [get_ports {ADC1N_D[8]}]
    AD20 [get_ports {ADC1P_D[9]}]
    AE20 [get_ports {ADC1N_D[9]}]
    AB21 [get_ports {ADC1P_D[10]}]
    AC21 [get_ports {ADC1N_D[10]}]
    AA20 [get_ports {ADC1P_D[11]}]
    AB20 [get_ports {ADC1N_D[11]}]
    AA19 [get_ports ADC1_DCOP]
    AB19 [get_ports ADC1_DCON]
    AC18 [get_ports ADC1_OTRP]
    AD18 [get_ports ADC1_OTRN]
    AE17 [get_ports ADC1_CSB]
    AF17 [get_ports ADC1_SDIO]
    AA17 [get_ports ADC1_SCLK]
    AB17 [get_ports ADC1_PWDN]
    AC17 [get_ports ADC1_RESET]
    U25 [get_ports {ADC2P_D[0]}]
    U26 [get_ports {ADC2N_D[0]}]
    V26 [get_ports {ADC2P_D[1]}]

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    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN

    W26 [get_ports {ADC2N_D[1]}]


    AB26 [get_ports {ADC2P_D[2]}]
    AC26 [get_ports {ADC2N_D[2]}]
    W25 [get_ports {ADC2P_D[3]}]
    Y26 [get_ports {ADC2N_D[3]}]
    Y25 [get_ports {ADC2P_D[4]}]
    AA25 [get_ports {ADC2N_D[4]}]
    V24 [get_ports {ADC2P_D[5]}]
    W24 [get_ports {ADC2N_D[5]}]
    AA24 [get_ports {ADC2P_D[6]}]
    AB25 [get_ports {ADC2N_D[6]}]
    AA22 [get_ports {ADC2P_D[7]}]
    AA23 [get_ports {ADC2N_D[7]}]
    AB24 [get_ports {ADC2P_D[8]}]
    AC24 [get_ports {ADC2N_D[8]}]
    V23 [get_ports {ADC2P_D[9]}]
    W23 [get_ports {ADC2N_D[9]}]
    Y22 [get_ports {ADC2P_D[10]}]
    Y23 [get_ports {ADC2N_D[10]}]
    U22 [get_ports {ADC2P_D[11]}]
    V22 [get_ports {ADC2N_D[11]}]
    U21 [get_ports ADC2_DCOP]
    V21 [get_ports ADC2_DCON]
    T20 [get_ports ADC2_OTRP]
    U20 [get_ports ADC2_OTRN]
    V19 [get_ports ADC2_CSB]
    W19 [get_ports ADC2_SDIO]
    V18 [get_ports ADC2_SCLK]
    W18 [get_ports ADC2_PWDN]
    T14 [get_ports ADC2_RESET]
    K21 [get_ports {DACP_D[0]}]
    J21 [get_ports {DACN_D[0]}]
    H21 [get_ports {DACP_D[1]}]
    H22 [get_ports {DACN_D[1]}]
    J23 [get_ports {DACP_D[2]}]
    H23 [get_ports {DACN_D[2]}]
    G22 [get_ports {DACP_D[3]}]
    F22 [get_ports {DACN_D[3]}]
    J24 [get_ports {DACP_D[4]}]
    H24 [get_ports {DACN_D[4]}]
    F23 [get_ports {DACP_D[5]}]
    E23 [get_ports {DACN_D[5]}]
    K22 [get_ports {DACP_D[6]}]
    K23 [get_ports {DACN_D[6]}]
    G24 [get_ports {DACP_D[7]}]
    F24 [get_ports {DACN_D[7]}]
    E25 [get_ports {DACP_D[8]}]
    D25 [get_ports {DACN_D[8]}]
    E26 [get_ports {DACP_D[9]}]
    D26 [get_ports {DACN_D[9]}]
    H26 [get_ports {DACP_D[10]}]
    G26 [get_ports {DACN_D[10]}]
    G25 [get_ports {DACP_D[11]}]
    F25 [get_ports {DACN_D[11]}]
    M19 [get_ports PLL_LOL]
    T19 [get_ports UART_SIN]
    U19 [get_ports UART_SOUT]
    N18 [get_ports IIC_SCL_MAIN]
    K25 [get_ports IIC_SDA_MAIN]
    R20 [get_ports GPIO_LED_5]

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    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN

    P24 [get_ports GPIO_LED_4]


    R26 [get_ports GPIO_LED_3]
    T25 [get_ports GPIO_LED_2]
    T24 [get_ports GPIO_LED_1]
    M26 [get_ports GPIO_LED_0]
    J25 [get_ports SM_FAN_TACH]
    P4 [get_ports DDR3_CKE0]
    N4 [get_ports DDR3_CKE1]
    R1 [get_ports DDR3_WE_B]
    P1 [get_ports DDR3_RAS_B]
    T4 [get_ports DDR3_CAS_B]
    T3 [get_ports DDR3_S0_B]
    T2 [get_ports DDR3_S1_B]
    R2 [get_ports DDR3_ODT0]
    U2 [get_ports DDR3_ODT1]
    N8 [get_ports DDR3_RESET_B]
    U1 [get_ports DDR3_TEMP_EVENT]
    M2 [get_ports DDR3_CLK0_P]
    L2 [get_ports DDR3_CLK0_N]
    N3 [get_ports DDR3_CLK1_P]
    N2 [get_ports DDR3_CLK1_N]
    H7 [get_ports {DDR3_DQSP[7]}]
    G7 [get_ports {DDR3_DQSN[7]}]
    J4 [get_ports {DDR3_DQSP[6]}]
    H4 [get_ports {DDR3_DQSN[6]}]
    B5 [get_ports {DDR3_DQSP[5]}]
    A5 [get_ports {DDR3_DQSN[5]}]
    C1 [get_ports {DDR3_DQSP[4]}]
    B1 [get_ports {DDR3_DQSN[4]}]
    V3 [get_ports {DDR3_DQSP[3]}]
    V2 [get_ports {DDR3_DQSN[3]}]
    AD1 [get_ports {DDR3_DQSP[2]}]
    AE1 [get_ports {DDR3_DQSN[2]}]
    AD5 [get_ports {DDR3_DQSP[1]}]
    AE5 [get_ports {DDR3_DQSN[1]}]
    V8 [get_ports {DDR3_DQSP[0]}]
    W8 [get_ports {DDR3_DQSN[0]}]
    H9 [get_ports {DDR3_DM[7]}]
    G5 [get_ports {DDR3_DM[6]}]
    F3 [get_ports {DDR3_DM[5]}]
    G1 [get_ports {DDR3_DM[4]}]
    U7 [get_ports {DDR3_DM[3]}]
    AA3 [get_ports {DDR3_DM[2]}]
    AC4 [get_ports {DDR3_DM[1]}]
    AC6 [get_ports {DDR3_DM[0]}]
    E6 [get_ports {DDR3_D[63]}]
    D6 [get_ports {DDR3_D[62]}]
    H8 [get_ports {DDR3_D[61]}]
    G8 [get_ports {DDR3_D[60]}]
    F8 [get_ports {DDR3_D[59]}]
    F7 [get_ports {DDR3_D[58]}]
    H6 [get_ports {DDR3_D[57]}]
    G6 [get_ports {DDR3_D[56]}]
    J6 [get_ports {DDR3_D[55]}]
    J5 [get_ports {DDR3_D[54]}]
    L8 [get_ports {DDR3_D[53]}]
    K8 [get_ports {DDR3_D[52]}]
    K7 [get_ports {DDR3_D[51]}]
    K6 [get_ports {DDR3_D[50]}]
    G4 [get_ports {DDR3_D[49]}]

    set_property
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    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN

    F4 [get_ports {DDR3_D[48]}]
    E5 [get_ports {DDR3_D[47]}]
    D5 [get_ports {DDR3_D[46]}]
    D4 [get_ports {DDR3_D[45]}]
    C4 [get_ports {DDR3_D[44]}]
    B4 [get_ports {DDR3_D[43]}]
    A4 [get_ports {DDR3_D[42]}]
    D3 [get_ports {DDR3_D[41]}]
    C3 [get_ports {DDR3_D[40]}]
    C2 [get_ports {DDR3_D[39]}]
    A3 [get_ports {DDR3_D[38]}]
    A2 [get_ports {DDR3_D[37]}]
    F2 [get_ports {DDR3_D[36]}]
    E2 [get_ports {DDR3_D[35]}]
    E1 [get_ports {DDR3_D[34]}]
    D1 [get_ports {DDR3_D[33]}]
    G2 [get_ports {DDR3_D[32]}]
    V1 [get_ports {DDR3_D[31]}]
    W1 [get_ports {DDR3_D[30]}]
    W5 [get_ports {DDR3_D[29]}]
    W4 [get_ports {DDR3_D[28]}]
    V6 [get_ports {DDR3_D[27]}]
    W6 [get_ports {DDR3_D[26]}]
    W3 [get_ports {DDR3_D[25]}]
    Y3 [get_ports {DDR3_D[24]}]
    AB1 [get_ports {DDR3_D[23]}]
    AC1 [get_ports {DDR3_D[22]}]
    Y2 [get_ports {DDR3_D[21]}]
    Y1 [get_ports {DDR3_D[20]}]
    AE2 [get_ports {DDR3_D[19]}]
    AF2 [get_ports {DDR3_D[18]}]
    AB2 [get_ports {DDR3_D[17]}]
    AC2 [get_ports {DDR3_D[16]}]
    AA4 [get_ports {DDR3_D[15]}]
    AB4 [get_ports {DDR3_D[14]}]
    AC3 [get_ports {DDR3_D[13]}]
    AD3 [get_ports {DDR3_D[12]}]
    AE3 [get_ports {DDR3_D[11]}]
    AF3 [get_ports {DDR3_D[10]}]
    AF5 [get_ports {DDR3_D[9]}]
    AF4 [get_ports {DDR3_D[8]}]
    Y7 [get_ports {DDR3_D[7]}]
    Y6 [get_ports {DDR3_D[6]}]
    Y5 [get_ports {DDR3_D[5]}]
    AA5 [get_ports {DDR3_D[4]}]
    AB5 [get_ports {DDR3_D[3]}]
    Y8 [get_ports {DDR3_D[2]}]
    AA8 [get_ports {DDR3_D[1]}]
    AB6 [get_ports {DDR3_D[0]}]
    K2 [get_ports {DDR3_A[15]}]
    L3 [get_ports {DDR3_A[14]}]
    N6 [get_ports {DDR3_A[13]}]
    L7 [get_ports {DDR3_A[12]}]
    L5 [get_ports {DDR3_A[11]}]
    N7 [get_ports {DDR3_A[10]}]
    K3 [get_ports {DDR3_A[9]}]
    H1 [get_ports {DDR3_A[8]}]
    M6 [get_ports {DDR3_A[7]}]
    K1 [get_ports {DDR3_A[6]}]
    M7 [get_ports {DDR3_A[5]}]

    set_property
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    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN
    PACKAGE_PIN

    K5
    L4
    J1
    J3
    M4
    H2
    M1
    N1

    [get_ports
    [get_ports
    [get_ports
    [get_ports
    [get_ports
    [get_ports
    [get_ports
    [get_ports

    {DDR3_A[4]}]
    {DDR3_A[3]}]
    {DDR3_A[2]}]
    {DDR3_A[1]}]
    {DDR3_A[0]}]
    {DDR3_BA[2]}]
    {DDR3_BA[1]}]
    {DDR3_BA[0]}]

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