BO CO

BI TP CHUYN (KTT)
ti: Thit k b truyn nhn UART
GVHD: Hunh Vit Thng
SVTH: L c Nhn

Lp: 11DT3

Vn Minh

Lp: 11DT2

H Vit Thnh

Lp: 11DT3

Nhm: 7

1. Kin thc c bn v UART:

- UART (Universal Asynchronous Receiver Transmitter) gi l b thu pht d
liu khng ng b ni tip. UART c s dng ph bin giao tip gia cc thit
b khc nhau.
- UART c nhim v chuyn i 1 byte (8 bit) d liu t song song sang ni tip
v thm vo cc bit start, stop to thnh khung truyn truyn i.
- B pht UART c iu khin vic truyn ti d liu bng mt xung clock gi
l tc baud.

Hnh 1: Khung truyn UART

-

D liu c gi i khng ng b xung clock nn gia b truyn v b nhn

cn c mt s thng nht vi nhau. V vy, khi b truyn truyn mt khung d liu
(frame), b nhn s ly mu cc tn hiu v sau tp hp v khi phc li tn hiu
gc.
- C ch ny c minh ha hnh 2, mt bit thng tin c chia thnh 16 im
ly mu. V xc sut li v tr mu u v mu cui l cao nht cn xc sut li v
tr gia l thp nht nn ta chn im ly mu gia.

Hnh 2: C ch ly mu nhn d liu

 T nhng kin thc trn v yu cu ca bi, ta thit k mt b va truyn

va nhn UART, hin th ngay ra gi tr va truyn i.

2. Thit k:
2.1. S khi ca thit k:

Hnh 3: S khi ca thit k

-

Trong :

Khi iu khin CONTROL: tip nhn tn hiu iu khin tx_in to

tn hiu cho php khi truyn UART hot ng. ng thi nhn cc gi tr d liu t
rev_data hin th ra led n.

Khi to tc truyn BAUD_RATE: da vo tn s clock ca h

thng, khi ny s tnh ton v to xung nhp truyn d liu khi truyn v ly mu d
liu khi nhn.

Khi truyn ni tip UART_TRANSMITTER: nhn d liu t ng vo

data_in v pht i da trn tc baud c tnh ton trong khi BAUD_RATE.

Khi nhn ni tip UART_RECEIVER: pht hin, ly mu v lu tr d

liu nhn ni tip t chn uart_rx vi tc baud c tnh ton khi
BAUD_RATE.

2.2. My trng thi hu hn:

-

My trng thi hu hn ca b truyn:

reset=0 or uart_en=0

Idle
Idle
tx_enable=1

tx_count=1001
and tx_clken

Load_tx
s

Shift_data

Hnh 4: My trng thi hu hn ca b truyn

-

Trong :
reset: tn hiu reset h thng.
uart_en: tn hiu cho php h thng lm vic.
tx_enable: tn hiu cho php b truyn lm vic.
tx_count: tn hiu m s bit c truyn i.
tx_clken: xung cho php dch tng bit d liu khi b truyn hot ng.

Trng thi hin ti M t

iu kin

Trng thi k tip

Idle

Trng thi ban u khi b tx_enable

truyn khng hot ng

Load_txs

Load_txs

Trng thi np d liu

vo thanh ghi dch truyn

Shift_data

Shift_data

Trng thi truyn tng bit tx_count=1001 Idle

v tx_clken
1

d liu

My trng thi hu hn ca b nhn:

reset=0 or uart_en=0
Idle
uart_rx_sync=0

rx_count=1010
uart_rx_sync=1
and samp_count=0111

Check_start_
Receive_dat
bit
a
uart_rx_sync=0 and samp_count=0111
Hnh 5: My trng thi hu hn ca b nhn
-

Trong :
Reset: tn hiu reset h thng.
Uart_en: tn hiu cho php h thng lm vic.
Uart_rx_sync: tn hiu ly mu c c.
Samp_count: tn hiu m s ln ly mu trong tng xung vo.
Rx_count: tn hiu m xung vo.

Trng thi hin ti

M t

iu kin

Trng thi k tip

Idle

Trng thi ban u khi

b nhn khng hot

uart_rx_sync=0

Check_start_bit

ng
Check_start_bit

Trng thi ly mu v
kim tra bit start

samp_count=0111
v uart_rx_sync=1
samp_count=0111

Idle
Receive_data

v uart_rx_sync=0
Receive_data

Trng thi ly mu cc
bit d liu trn ng
nhn

rx_count=1010

Idle

3. Chng trnh chnh:

3.1. Code VHDL:
-

Khi BAUD_RATE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.
--library UNISIM;

--use UNISIM.VComponents.all;

entity baud_rate is
port (
clk : in std_logic;

-- clock dong bo he thong

reset : in std_logic; -- reset he thong. Tich cuc muc thap

uart_en : in std_logic;
Tich cuc muc cao

-- cho phep he thong lam viec.

tx_clken : out std_logic;

du lieu khi bo truyen hoat dong

-- xung cho phep dich tung bit

rx_clken : out std_logic

tri lay mau du lieu o bo nhan

-- xung cho phep xac dinh vi

);
end baud_rate;

architecture Behavioral of baud_rate is

signal tx_count: std_logic_vector(13 downto 0);
signal rx_count: std_logic_vector(9 downto 0);
signal tx_clken_temp: std_logic;
signal rx_clken_temp: std_logic;
constant temp: integer:=324;
MHz

-- 9600=fo/((324+1)*16 - 1), fo=50

begin
process(clk)
-- tao xung dich du lieu o bo phat
begin
if rising_edge(clk) then
if ((reset='0') or (tx_clken_temp='1') or (uart_en='0'))
then

tx_count <= (others => '0');

else
tx_count <= (tx_count + 1);
end if;
end if;
end process;

process (tx_count, tx_clken_temp)

begin
if (tx_count = (((temp + 1)*16) - 1)) then
tx_clken_temp <= '1';
else
tx_clken_temp <= '0';
end if;
tx_clken <= tx_clken_temp;
end process;

process(clk)
-- tao xung lay mau du lieu o bo nhan
begin
if rising_edge(clk) then
if ((reset='0') or (rx_clken_temp='1') or (uart_en='0'))
then
rx_count <= (others => '0');
else
rx_count <= (rx_count + 1);
end if;

end if;
end process;

process (rx_count, rx_clken_temp)

begin
if (rx_count = temp) then
rx_clken_temp <= '1';
else
rx_clken_temp <= '0';
end if;
rx_clken <= rx_clken_temp;
end process;
end Behavioral;

Khi CONTROL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.
--library UNISIM;

--use UNISIM.VComponents.all;

entity control is
port(
clk : in std_logic;

-- clock dong bo he thong

reset : in std_logic; -- reset he thong. Tich cuc muc thap

uart_en : in std_logic;
Tich cuc muc cao

-- cho phep he thong lam viec.

tx_in : in std_logic; -- cho phep ghi du lieu tu data_in

vao bo truyen. Tich cuc muc cao
nhan duoc

rev_data : in std_logic_vector(7 downto 0); -- du lieu

led_0 : out std_logic_vector(3 downto 0);

nhan duoc xuat ra led don

-- gia tri

led_1 : out std_logic_vector(3 downto 0);

nhan duoc xuat ra led don

-- gia tri

dong

tx_en : out std_logic -- tin hieu cho phep bo truyen hoat

);

end control;

architecture Behavioral of control is

-- khai bao cac tin hieu
signal data_led_0: std_logic_vector(3 downto 0);
signal data_led_1: std_logic_vector(3 downto 0);
signal tx_in_sync: std_logic;
begin
process (rev_data)
-- gan gia tri cho led don
begin

data_led_0 <= rev_data(3 downto 0);

data_led_1 <= rev_data(7 downto 4);
end process;
led_0 <= data_led_0;
led_1 <= data_led_1;
process (clk, reset, uart_en, tx_in, tx_in_sync)
-- tao tin hieu cho phep truyen
begin
if rising_edge(clk) then
if (reset='0') then
tx_in_sync <= '0';
else
tx_in_sync <= tx_in;
end if;
end if;

tx_en <= (not tx_in_sync) and tx_in and uart_en;

end process;
end Behavioral;

Khi UART_TRANSMITTER

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity uart_transmitter is
port (
clk : in std_logic;

-- clock dong bo he thong

reset : in std_logic; -- reset he thong. Tich cuc muc thap

uart_en : in std_logic;
Tich cuc muc cao

-- cho phep he thong lam viec.

data_in : in std_logic_vector(7 downto 0); -- 8 bit du

lieu ngo vao
tx_enable : in std_logic;

-- tin hieu cho phep bo truyen

hoat dong
tx_clken : in std_logic;
du lieu khi bo truyen hoat dong
uart_tx : out std_logic

-- xung cho phep dich tung bit

-- duong truyen du lieu dong

bo
);
end uart_transmitter;

architecture Behavioral of uart_transmitter is

signal state: std_logic_vector(1 downto 0);
constant idle: std_logic_vector(1 downto 0):= "00";

constant load_txs: std_logic_vector(1 downto 0):= "01";

constant shift_data: std_logic_vector(1 downto 0):= "10";
signal tsr: std_logic_vector(9 downto 0);
signal tx_count: std_logic_vector(3 downto 0);
begin
-- may trang thai huu han
process(clk)
begin
if rising_edge(clk) then
if ((reset='0') or (uart_en='0')) then
state <= idle;
else
case state is
when idle =>
if (tx_enable='1') then state <=

load_txs;

end if;
when load_txs =>
state <= shift_data;
when shift_data =>
if ((tx_count="1001") and (tx_clken='1'))
then -- dem den 10 vi khung truyen co 10 bit du lieu
state <= idle;
end if;
when others =>
state <= idle;
end case;
end if;
1

end if;
end process;
-- dau ra may trang thai huu han
process(clk)
begin
if rising_edge(clk) then
if ((reset='0') or (uart_en='0')) then
tsr <= "0000000000";
uart_tx <= '1';
tx_count <= "0000";
else
case state is
when idle =>
tsr <= "0000000000";
uart_tx <= '1';
tx_count <= "0000";
when load_txs =>
tsr <= ('1' & data_in & '0');
bit 0 la bit start, bit 1 la bit stop vao khung truyen

-- gan

when shift_data =>

if (tx_clken = '1') then
uart_tx <= tsr(0);

-- gan du lieu

vao duong truyen

tsr <= ('1' & tsr(9 downto 1));

--

dich du lieu
tx_count <= tx_count + 1;

-- bo

dem truyen
end if;
when others =>

tsr <= "0000000000";

uart_tx <= '1';
tx_count <= "0000";
end case;
end if;
end if;
end process;
end Behavioral;

Khi UART_RECEIVER

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity uart_receiver is
port (
clk : in std_logic;

-- clock dong bo he thong

reset : in std_logic; -- reset he thong. Tich cuc muc thap

uart_en : in std_logic;
Tich cuc muc cao

-- cho phep he thong lam viec.

rx_clken : in std_logic;
tri lay mau du lieu o bo nhan

-- xung cho phep xac dinh vi

uart_rx : in std_logic;
nhan duoc

-- duong nhan du lieu dong bo

rev_data : out std_logic_vector(7 downto 0) -- du lieu

);

end uart_receiver;

architecture Behavioral of uart_receiver is

signal rx_count: std_logic_vector(3 downto 0); -- tin hieu dem
xung vao
signal samp_count: std_logic_vector(3 downto 0);
dem so lan de lay mau trong tung xung vao
signal uart_rx_sync: std_logic;

-- tin hieu

-- tin hieu lay mau doc duoc

signal rsr: std_logic_vector(7 downto 0);

signal state: std_logic_vector(1 downto 0);
constant idle: std_logic_vector(1 downto 0):= "00";
constant check_start_bit: std_logic_vector(1 downto 0):= "01";
constant receive_data: std_logic_vector(1 downto 0):= "10";
begin
process(clk)
begin
if rising_edge(clk) then
if ((reset='0') or (uart_en='0')) then
uart_rx_sync <= '1';
else

uart_rx_sync <= uart_rx;

end if;
end if;
end process;
-- may trang thai huu han
process(clk)
begin
if rising_edge(clk) then
if ((reset='0') or (uart_en='0')) then
state <= idle;
else
case state is
when idle =>
if (uart_rx_sync = '0') then
state <= check_start_bit;
end if;
when check_start_bit =>
if (samp_count = "0111") then

-- lay

mau o gia tri thu 8

if (uart_rx_sync = '0') then
state <= receive_data;
else
state <= idle;
end if;
end if;
when receive_data =>
if (rx_count="1010") then
xung thu 10 vi khung truyen co 10 bit

-- dem den

state <= idle;

end if;
when others =>
state <= idle;
end case;
end if;
end if;
end process;
-- dau ra may trang thai huu han
process(clk)
begin
if rising_edge(clk) then
if ((reset='0') or (uart_en='0')) then
rsr <=

"11111111";

rx_count <= "0000";

samp_count <= "0000";
else
case state is
when idle =>
rx_count <= "0000";
samp_count <= "0000";
when check_start_bit =>
if (rx_clken='1') then
samp_count <= samp_count + 1;

--

bo dem lay mau

end if;
when receive_data =>

if (rx_clken='1') then
samp_count <= samp_count + 1;
if (samp_count="0111") then
rx_count <= rx_count + 1;
if(rx_count<"1001") then
-chi dem den xung thu 9, loai bo bit start va stop ra du lieu nhan
duoc
rsr <= (uart_rx_sync &
rsr(7 downto 1));

-- dich du lieu
end if;
end if;
end if;
when others =>
rx_count <= "0000";
samp_count <= "0000";

end case;
end if;
end if;
end process;
rev_data <= rsr;
end Behavioral;

3.2. Code testbench:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--USE ieee.numeric_std.ALL;

ENTITY test_uart IS
END test_uart;

ARCHITECTURE behavior OF test_uart IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT full_uart
PORT(
clk : IN

std_logic;

reset : IN

std_logic;

-- clock dong bo he thong

-- reset he thong. Tich cuc muc thap

uart_en : IN
Tich cuc muc cao

std_logic;

data_in : IN
lieu ngo vao

std_logic_vector(7 downto 0);

tx_in : IN std_logic;
vao bo truyen. Tich cuc muc cao
uart_rx : IN

-- cho phep he thong lam viec.

-- 8 bit du

-- cho phep ghi du lieu tu data_in

std_logic;

-- duong nhan du lieu dong bo

led_0 : OUT std_logic_vector(3 downto 0);

nhan duoc xuat ra led don

-- gia tri

led_1 : OUT std_logic_vector(3 downto 0);

nhan duoc xuat ra led don

-- gia tri

uart_tx : OUT

std_logic

-- duong truyen du lieu dong

bo
);
END COMPONENT;

--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal uart_en : std_logic := '0';
signal data_in : std_logic_vector(7 downto 0) := (others => '0');
signal tx_in : std_logic := '0';
signal uart_rx : std_logic := '0';

--Outputs
signal led_0 : std_logic_vector(3 downto 0);
signal led_1 : std_logic_vector(3 downto 0);
signal uart_tx : std_logic;

-- Clock period definitions

-- chu ky = 20 ns, f = 50 MHz
-- baud_rate = 9600 => t_data = 104200 ns
constant clk_period : time := 20 ns;
constant t_data: time := 104200 ns;
BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: full_uart PORT MAP (
clk => clk,
reset => reset,
uart_en => uart_en,

data_in => data_in,

tx_in => tx_in,
uart_rx => uart_rx,
led_0 => led_0,
led_1 => led_1,
uart_tx => uart_tx
);

data_in <= "00010010";

clock: process
-- tao xung tan so 50 MHz
begin
clk <= '1';
wait for 10 ns;
clk <= '0';
wait for 10 ns;
end process;

-- Stimulus process
stim_proc1: process
begin
reset <= '0';
wait for 20 ps;
-- tao du lieu vao
tx_in <= '1';

-- cho phep bo truyen hoat dong

wait for 20 ps;

reset <= '1';
uart_en <= '1';
wait for t_data;
-- dich du lieu
for i in 0 to 7 loop
uart_rx <= data_in(i);
wait for t_data;
end loop;
-- phat hien bit stop
uart_rx <= '1';
wait for t_data;
wait;
end process;
END;

3.3. Kt qu m phng:

Hnh 6: thi im uart_tx nhn gi tr bit start v ghi vo trong bit MSB ca led_1

Hnh 7: thi im uart_tx nhn gi tr bit LSB ca data_in v tip tc ghi vo led_1

Hnh 8: thi im uart_tx nhn gi tr bit th 2 ca data_in v ghi vo led_1

Hnh 9: qu trnh truyn nhn kt thc, 4 bit cao ca data_in c ghi vo

led_1 v 4 bit thp ca data_in c ghi vo led_0

3.4. Kt qu tng hp phn cng:

Hnh 10: Kt qu tng hp phn cng

4. Nhn xt, kt lun:
- Kt qu m phng cho thy khi UART c thit k hot ng ng vi
yu cu c t ra.
- So vi truyn nhn song song th truyn nhn ni tip c tc chm hn
nhng hn ch c li.
- Bi tp ny gip ta nm vng hn cc kin thc lp trnh phn cng VHDL,
vit testbench v s dng cng c m phng.