5 4 3 2 1

VCC
K1
5
3 VCC

1
J1 4

C
1 1
2 R2
D 2 VCC 1kx8 D

1
CON2 RELAY SPDT

2
3
4
5
6
7
8
9
2N3906 2

1
4
5
9
U1 U2

20
Q1

NC
NC
NC
NC
3
12 12

VCC
P1.0/AIN0 a a
P1.1/AIN1 13 11 b
11 P3.7 P1.2 14 16 c
15 7 f g b
P1.3 d
P1.4 16 2 e
17 13 e c
P1.5 f d
P1.6 18 8 g

com1

com2

com3

com4
P1.7 19 15 pt.
Y1 5 XTAL1
4 XTAL2

10

14
3

6
12MHz 7-segment
C C

C1 C2
30pF 30pF

1 RST/VPP

P3.0/RXD 2
VCC 3
P3.1/TXD
P3.2/INTO 6
P3.3/INT1 7

+ C3 S1
10uF 8
P3.4/T0
S5 9
P3.5/T1
S2
B B
RESET
R1
10k AT89C2051

A A

Title
Clock Controller V2.0

Size Document Number Rev

A <Doc> <RevCode>

Date: Friday, July 21, 2006 Sheet 1 of 1

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