----------------------------------------- Sign Extender Module : IITB-RISC

-- Author : Titto Thomas

-- Date : 8/3/2014
---------------------------------------library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SE is
generic (
initial
final
);
port (
data_in
data_out
);
end SE;

: integer;
: integer

-- number of input std_logics

-- number of output std_logics

: in std_logic_vector(initial-1 downto 0); -- data input

: out std_logic_vector(final-1 downto 0) -- data output

architecture SignExtend of SE is
begin
data_out <= std_logic_vector(resize(signed(data_in), final));
e the vector and pass it out
end architecture SignExtend;

-- resiz