-- Code your design here

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity parte_3 is
port(
input :in std_logic_vector (7 downto 0);
inmux,aload,reset,clock : in std_logic;
IRLoad, JNZMuz, PCLoad: in std_logic;
IR_out: out std_logic_vector(2 downto 0);
aneq0,output :out std_logic_vector(7 downto 0)
);
end entity;
architecture funcionamiento of parte_3 is
--espacio para designar seales
signal mux2out
: std_logic_vector(7 downto 0);
signal mux1out, incout
: std_logic_vector(3 downto 0);
signal decout
: std_logic_vector(7 downto 0);
signal a_in, a_out
: std_logic_vector(7 downto 0);
signal intruccion, ir_reg
: std_logic_vector(7 downto 0);
begin
--multiplexor2
mux2out <= input when inmux = '1' else
decout;
a_in <= mux2out;
--registro
process(clk, reset)
begin
if (reset = '1') then
a_out <= (others => '0');
elsif rising_edge(clk) then
if (aload = '1') then
a_out <= a_in;
end if;
end if:
end process;
--8_bit decrecent
decout <=a_out -"00000001";
--seales de salida
aneq0 <= a_out(7) or a_out(6) or a_out(5) or a_out(4) or a_out(3) or a_out(2) or a_out(1) or
a_out(0);
output <= a_out;

--IR 8bits
process(clk, reset)
begin
if (reset = '1') then
ir_reg <= (others => '0');
elsif rising_edge(clk) then
if (IRLoad = '1') then
ir_reg <= instruccion;
end if;
end if:
end process;
IR_out <= ir_reg(7 downto 5);
--multiplexor1
mux1out <= ir_reg(3 downto 0) when JNZMux = '1' else
incout;

--4bit increment
incout <= pc_reg + "0001";
--4bit PC
process(clk, reset)
begin
if(reset = '1') then
pc_reg <= (others => '0');
elsif (rising_edge(clk)) then
if(PCLoad = '1') then
pc_reg <= mux1out;
end if;
end if;
end process;

--ROM address
process(clk)
begin
if rising_edge(clk) then
case pc_reg is
when "0000" => instruccion <= "01100000";
when "0001" => instruccion <= "10000000";
when "0010" => instruccion <= "10100000";
when "0011" => instruccion <= "11000001";
when "0100" => instruccion <= "11111111";
when "0101" => instruccion <= "11111111";
when "0110" => instruccion <= "11111111";
when "0111" => instruccion <= "11111111";

when "1000" => instruccion <= "11111111";

when "1001" => instruccion <= "11111111";
when "1010" => instruccion <= "11111111";
when "1011" => instruccion <= "11111111";
when "1100" => instruccion <= "11111111";
when "1101" => instruccion <= "11111111";
when "1110" => instruccion <= "11111111";
when "1111" => instruccion <= "11111111";
when others => instruccion <= "--------";
end case;
end if;
end process;