Wong & Lok: Theory of Digital Communications

3. Synchronization

Chapter 3
Synchronization
Information about the communication channel, such as the channel phase response, is necessary for
the construction of the various receivers discussed in Chapter 2. In many practical situations, this
information is not known a priori and the relevant channel parameters have to be estimated from
the received signal. The three main channel parameters required by most receivers are the carrier
frequency, the carrier phase1 , and the symbol timing of the received signal. The carrier frequency of
the received signal may be different from that of the nominal value of the transmitter carrier frequency.
This discrepancy can be the results of the deviation of the transmitter oscillator from the nominal
frequency and, more importantly, the Doppler effect when the transmitter is in motion relative to the
receiver. In reality, it takes a finite amount of time for the information-bearing electromagnetic wave
to travel from the transmitter to the receiver. This transmission delay introduces a mismatch between
the symbol timing at the transmitter and that at the receiver. Recall that we need to sample the output
of the matched filter at an exact time2 to optimize the error performance. We need to know the symbol
timing at the receiver (or equivalently, the transmission delay) in order to eliminate the performance
degradation due to the timing mismatch. The carrier phase of the received signal is the sum of three
major components, namely, the random phase of the transmitter oscillator, the channel phase response,
and the phase due to the transmission delay. In order to model all the three channel defects, we need to
augment the simple non-dispersive channel model we employ in the previous chapters. The received
1
2

Carrier phase information is not needed if noncoherent demodulation is employed

Equivalently, we need to know the exact integration interval for the correlator implementation.

3.1

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3. Synchronization

signal in the augmented model3 is given by

r(t) = Av (t  ) cos[2 (fc + fd )(t  ) + ] + n(t);

where

(3.1)

v (t) is the baseband signal and the new parameter fd and  are employed to model the de-

viation of the received carrier frequency from the nominal carrier frequency and the transmission
delay, respectively. Very often, we can combine the phase terms in (3.1) to a single phase term

=

2(f + f ) modeling the received carrier phase.

c

The process of estimating these parameter is called synchronization. As an brief introduction to the
subject, we focus on the estimation of the carrier phase and the transmission delay while neglecting the
carrier frequency mismatch (to be justify in a short while). The process of estimating the carrier phase
is known as carrier phase synchronization, which, we will show, can be accomplished by a phaselocked loop (PLL) circuit. The process of estimating the transmission delay is known as symbol timing
synchronization, which, we will show, can be accomplished by a delay-locked loop (DLL) circuit. It
turns out that the same PLL circuit used for carrier synchronization can also be employed to track the
carrier frequency mismatch when it is significant.

3.1 Effect of Synchronization Errors

First, we investigate the effect of errors in the estimation of the three parameters on the performance of
a typical communication system. For simplicity, let us consider a BPSK system in which the received
signal is given by

r(t)

= Ap (t
= Ap (t
T

 ) cos[2 (fc + fd )(t  ) + ] + n(t)

 ) cos[2 (fc + fd )t + ] + n(t);

(3.2)

(t) is an AWGN process with noise spectral density N =2. By some synchronization process,
we obtain estimates f^ , ^, and ^ of the parameters f ,  , and , respectively. Therefore, we form the
where n

correlator demodulator based on these estimated parameters as shown in Figure 3.1. It is straightfor3

Here, we assume that only the in-phase channel is used for simplicity. If the quadrature channel is also employed, we

can either add the corresponding term to (3.1) or use the complex baseband representation.

3.2

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3. Synchronization
T +^

+Ap
T (t- ) cos [2 (fc+fd)t + ]
+ n(t)

dt

?
>
<

cos [2 (fc+fd)t + ]
^

Figure 3.1: Correlator receiver for BPSK with estimated parameters

ward to show that when j

^j  T , the average bit error probability of error (assuming the bit values

0 and 1 are sent with equal probabilities) given by

Pb = Q 
where

=
We note that  

Z T +min(;^)

2E

N0

cos[2(f

max(;
^)

f^d )t + ( ^)]dt:

(3.3)

(3.4)

1 with equality only if f^ = f , ^ =  , and ^ =  (modulo 2). Hence, errors in the

d

estimation of any of the parameters will cause the error probability go higher than the optimal value

Q(

2E =N ).
b

From the result above, we see that if jfd

estimation error in fd , then

where

f^d j  1=T , i.e., the data rate is much higher than the

j
 j cos(
);
 1
T
!

(3.5)

 =  ^ and
 =  ^. Therefore, errors in estimating both the transmission delay and

the carrier phase cause significant bit error performance degradation.

3.2 Carrier Phase Synchronization

For simplicity, we assume that fd

= 0 and  = 0 and focus on the estimation of the carrier phase .

We start by developing the maximum likelihood estimator of  under the non-dispersive channel model
and the assumption that the transmitted signal is known to the receiver (i.e., the transmitted signal is
not data-modulated). Then we discuss several common phase-locked mechanisms which are practical
approximations to the ML phase estimator under different situations.

3.3

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3. Synchronization

3.2.1 Maximum likelihood carrier phase estimation

Under the assumption that fd

= 0 and  = 0, the channel model in (3.1) reduces to

r(t) = Av (t) cos(2fct + ) + n(t);

(3.6)

(t) is AWGN with spectral density N =2 and v(t) is the known transmitted signal. Our goal is
to obtain an estimator ^ of the carrier phase  based on the maximum likelihood principle used in the
where n

previous chapter. This means that we need to specify and evaluate the likelihood function. To do so,
we employ the vector space representation in Session 2.5.1. First, we note that the signal space in this
case is two dimensional and is spanned by

p
2 v(t) cos(2f t)
 (t) =
c
kpvk

(3.7)

= kv2k v(t) sin(2f t)

We can complete the basis by adding the orthonormal signals f g1
2 (t)

(3.8)

n n=3

. Based on an argument similar

to those in Sections 2.5.3 and 2.5.4, we can show that the first two elements of the vector representing

r(t),
r1
r2

=
=

1
r(t)1 (t)dt
1
1
r(t)2 (t)dt
1

(3.9)
(3.10)

form a sufficient statistic for the estimation of the phase . From (3.6), we see that

r1

r2

Akvp
k cos 

2 +n
Akv k sin 
p
2 +n

(3.11)

(3.12)

where n1 and n2 are iid zero-mean Gaussian random variable with variance N0 = . Hence, the likelihood function is given by

1 exp (r
f (r ; r j) =
N
"

Akv k cos =

As before, the ML estimator of

p
2) + (r + Akvk sin = 2)

N0

(3.13)

 is the one that maximizes the likelihood function or, equivalently,

the log-likelihood function, i.e.,

^M L = arg max

f (r1 ; r2 j) = arg max
ln f (r1; r2j):


3.4

(3.14)

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3. Synchronization

dt
X
r(t)

v(t) cos ( 2

arctan(Y/X)

fc t )

ML

Y
dt

- v(t) sin ( 2 fc t )
Figure 3.2: ML phase estimation circuit
This reduces to

^M L

= arg max(r cos  r sin )

r
= tan
r
1
r(t)v (t) sin(2f t)dt
1
= tan
1
r(t)v (t) cos(2f t)dt
1


6
16
4

1
Z

3
7
7
5

(3.15)

Thus, the ML phase estimator can be implemented by the circuit shown in Figure 3.2. An additional
(more popular) way to implement the ML phase estimator can be obtained by differentiating the metric

r1 cos 

r2 sin  with respect to  and setting the derivative to zero. By doing so, we can show that

the ML estimator has to satify

Z

1
r(t)v (t) sin(2fct + ^)M L )dt = 0:
1

(3.16)

We can construct the feedback loop structure as shown in Figure 3.3 to solve for (3.16) above. Phase
estimation circuits based on the structure in Figure 3.3 are generally known as phase-locked loops.

3.5

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3. Synchronization

r(t)

dt

^
- v(t) sin ( 2 fc t + )

^
If > 0, increase
^
If < 0, decrease

Figure 3.3: ML phase estimation loop

3.2.2 Phase-locked loops

The ML phase estimation circuit based on the feedback loop structure in Figure 3.3 has several advantages over the non-feedback structure in Figure 3.2. First, due to its feedback structure, the phaselocked loop (PLL) structure can track variations in the channel phase. We will see later that this is true
(with a slight modification to the loop) even when the received signal is data-modulated. Hence, the
PLL can be employed to track the channel phase response throughout the whole duration of communication, while the non-feedback ML phase estimation circuit in Figure 3.2 can only operate during the
initial training phase. Second, in practice the phase-control device in Figure 3.3 is implemented by a
voltage-controlled oscillator (VCO). With the VCO, the PLL also can be employed to track the carrier
frequency of the received signal.
Phase-locked loop for unmodulated carrier
A typical practical implementation of the PLL structure in 3.3 is shown in Figure 3.4. For simplicity,
we assume that v

(t) is a constant signal, which approximates the case where a training signal with a

very long duration is employed to perform the phase synchronization, and that the AWGN is absent.
The received signal

r(t) contains only the carrier. With this assumption, the operation of the PLL
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3. Synchronization

phase detector
e(t)
r(t)

LPF

loop
filter

e(t)

VCO

x(t)
Figure 3.4: Practical phase-locked loop
circuit can be described as follows:





The carrier to be locked is

r(t) = A cos(2fc t + ):

(3.17)

The reference signal is

x(t) =

2 sin(2f t +  (t)):
c

(3.18)

In the simplest case, the phase detector is just a multiplier followed by a low-passed filter (to
remove the double frequency term). Therefore the output of the phase detector is the error signal

e(t) = Kp A sin( r (t));

(3.19)

where Kp is the constant gain of the filter over its passband.

The loop filter is employed to limit the variance of the noise in the error signal. Hence its bandwidth determines the performance of the PLL when noise is present. The smaller the bandwidth
of the loop filter, the smaller is the variance of the noise in the error signal. On the other hand,
the tracking ability of the PLL is also determined by the loop filter bandwidth. A larger bandwidth enables the PLL to track rapidly changing channel phase. Therefore, the bandwidth of
loop filter is chosen as a compromise between robustness toward noise and tracking ability. For
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3. Synchronization

simplicity, we assume that it provides a constant gain Kl when noise in absent. Therefore,

e0 (t) = Kl e(t) = Kl Kp A sin( r (t)):

(3.20)

The VCO adjusts the frequency (and, hence, phase) of its output according to the relations

d
r (t) = Kv e0 (t)
dt

(3.21)

where Kv is a constant gain.

From above,

d
 (t) = K sin( r (t));
(3.22)
dt r
where the overall gain K = Kv Kl Kp A. Suppose that r (t) is close to . Then, approximately,
d
 (t) = K ( r (t)):
dt r

(3.23)

The solution of this simple differential equation is given by

r (t) = 

(

r (0))e

Kt

(3.24)

(t) tends to . Notice that the overall gain controls the speed of convergence. In case that
the initial phase reference  (t) is not close to . The situation is depicted in Figure 3.5, which shows
that  (t) will drift to the vicinity of  + 2k for some integer k . Then locking begins.
Clearly, r

For practical communication systems, such as BPSK systems, the carrier phase cannot be tracked
with such the simple approach above. It is because the data, which can possibly change in every
symbol interval (typically a very short time), affect the phase of the carrier. However, if extra power is
spent to send an unmodulated carrier together with the data signal, i.e., the transmitted signal is of the
form

m(t) cos(2fc t) +

2P cos(2f t)
c

(3.25)

(t) is the information signal and P is the power of the unmodulated carrier, then a BPF with

where m

a very narrow pass-band around the carrier frequency fc can be used to filter off the data signal, and
the phase of carrier can be tracked with the PLL in Figure 3.4.

3.8

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3. Synchronization

1.5

e(t)

0.5

0.5

1.5

2
8

Figure 3.5: Drift of the phase reference to a stable equilibrium

Phase-locked loops for modulated carrier
Instead of using extra power to send an unmodulated carrier, carrier phase of modulated signal can
also be tracked in the following way if the modulation method is BPSK. The received signal is

r(t) = A[

bn pT (t nT )] cos(2fct + );

(3.26)

neglecting the noise. The effect of the data signal can be removed by squaring. We get, after squaring,

r ( t) =

A2

(3.27)
2 [1 + cos(22f t + 2)]:
Passing the result through a BPF tuned at 2f , we get an unmodulated carrier whose phase, 2, can be
2

tracked with the PLL in Figure 3.4. Using this approach, we obtained the squaring loop in Figure 3.6.

2, there is a phase ambiguity of  in our estimate of

, i.e., we do not know the actual carrier phase is  or  +  . To overcome this problem, the data must
Notice that since we are only able to determine

be differentially encoded at the transmitter and differentially decoded at the receiver.

A similar approach to carrier phase recovery for BPSK is the Costas loop in Figure 3.7. The idea
3.9

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r(t)

3. Synchronization

BPF

Loop
Filter

LPF

VCO

Figure 3.6: Squaring loop

r(t)

LPF

VCO

/2 shifter

LPF
Figure 3.7: Costas loop

3.10

Loop
Filter

e(t)

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3. Synchronization

A m ( t ) cos ( 2 fc t + )

Loop
Filter

LPF

m(t)
VCO

Figure 3.8: Phase-locked loop with clean data

is quite similar to the squaring loop. The data signal is again removed by the multiplication before the
loop filter. The input to the loop filter is given by

1
2

e(t) = Kl2 A2 sin 2( r (t)):

Hence, again, we are tracking

(3.28)

2, and a phase ambiguity of  remains just as in the squaring loop.

Differential encoding and decoding are again needed. Actually, with suitable choices of filters, it can
be shown that the squaring loop and the Costas loop are equivalent.
Both the squaring loop and the Costas loop remove the data in the received signal by multiplying
the noisy received data by itself. However, if we assume that we know the original data, we can remove
the data in received signal with the known clean data as shown in Figure 3.8. Of course, in general,
the receiver does not know the transmitted data. However, a slight modification of this approach can
be used under the following conditions:
1. A training sequence is available, i.e., before the actual transmission of data, the transmitter sends
a standard sequence of symbols that are known a prior by both the transmitter and the receiver.
2. The signal-to-noise ratio Eb =N0 is high.
If a long enough training sequence is available, the receiver can lock onto the carrier during the training
period. After the training period, the receiver has a good estimate of the carrier phase. If Eb =N0 is
high, the probability of error is very small. Hence, the decisions made by the receiver are most likely to
be correct. These correctly decided symbols are fed back to the PLL to continue to track the carrier
phase. This PLL based approach is called the decision-directed PLL, which is shown in Figure 3.9.
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3. Synchronization

A m ( t ) cos ( 2 fc t + )

?
>
<

dt

cos ( 2 fc t + )

/2 shifter

VCO

Filter

Delay

Figure 3.9: Decision-directed PLL receiver

Under high SNR, decision directed loops work better than non-decision directed loops because clean
data are used instead of noisy data. If clean data is available, it can be shown that the decision-directed
PLL is actually performing for the ML phase estimation for the case of a modulated carrier.

3.3 Symbol Timing Synchronization

For simplicity, we assume that

fd

= 0 and we have achieved carrier phase synchronization, i.e., we

know the value of  and focus on the estimation of the symbol timing  . The simplified model for the
received signal is

r(t) = Av (t  ) cos(2fc t + ) + n(t):

(3.29)

3.3.1 ML symbol timing estimation with training signal

First, we assume that the baseband signal

v (t) is known, i.e., a training signal is sent to allow the

receiver to perform symbol timing synchronization. Based on this assumption, we work out the ML
estimator for  . Again, we start from a basis fi

(t)g1

i=1

for the space of all finite-energy signals and

represent the signals in (3.29) by vectors:

r = s( ) + n;
3.12

(3.30)

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3. Synchronization

( ), and n are

where the ith elements of r, s

=
s ( ) =
n =
ri

1
r(t)i (t)dt
1
1
Av (t  ) cos(2fc t + )i (t)dt
1
1
n(t)i (t)dt:
1

(3.31)
(3.32)
(3.33)

r can be a sufficient statistic for the estimation of  in

general. Therefore, we need to employ the whole vector r instead. However, in order to keep our the
development simple (not strictly rigorous though), we start by the truncated observation vector rK and
then let K increase to infinity. For a fixed (and finite) K , the likelihood function is given by
Unlike the previous cases, no truncation of

f (rK j ) =

K
Y
k =1

1 exp
pN
0

1 (r

N0

sk ( )) :
2

(3.34)

As in the previous cases, it is easy to see that the ML estimator is given by

^M L = arg max



K h
X

2r s ( )

s2k ( ) :
i

k k

k =1

(3.35)

Now, letting K approaches infinity, we have

^M L

= arg max


Xh

2r s ( )
k k

k =1

s2k ( )

= arg max 2A 1 r(t)v(t  ) cos(2f t + )dt

1
= arg max 1 r(t)v(t  ) cos(2f t + )dt:


A2

1 2
v (t
1

 ) cos2 (2fct + )dt

(3.36)

A necessary condition that the ML estimator has to satisfy in general is


d Z1
r(t)v (t  ) cos(2fct + )dt =^ = 0:
ML
d 1

(3.37)

For the special case where the training signal is a (known) sequence of BPSK pulses, i.e.,

v (t) =

bi pT (t iT );

(3.38)

dr~
(^ + iT ) = 0;
d M L

(3.39)

the necessary condition in (3.37) becomes

X

bi

3.13

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3. Synchronization

bi

r(t)

pT (t)

d
dt

^
iT+

cos (2 f ct + )
VCC

Figure 3.10: Delay-locked loop using a BPSK training signal

where

r~( ) = [r(t) cos(2fc t + )  pT ]( ):

(3.40)

As in the case of carrier phase estimation, we can employ a feedback structure, known as delay-locked
loop (DLL), to solve for

M L as shown in Figure 3.10. The estimate of  is varied by the voltage-

controlled clock (VCC) in the DLL. When the SNR is high, after the initial training period, we can
replace the known symbols by the decisions made by the demodulator. In this way, we can keep the
DLL running for the whole duration of transmission. The DLL so obtained is called a decision-directed
DLL.

3.3.2 Non-decision-directed ML symbol timing estimation

When the SNR is low, the decision-directed DLL becomes ineffective. We need an estimator which
does not need the data symbol information to estimate the symbol timing. To simply our discussion
here, we assume that a finite but large number of bits are transmitted using the BSPK format defined
in (3.38). Let b be the vector which contains all the transmitted BPSK symbols bi and the dimension
of b be I . Then for each bit pattern b, we can construct an equation describing the received signal in
the vector notation based on the basis in the previous section:

r = s(; b) + n:

3.14

(3.41)

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3. Synchronization

rK and then let K approach infinity. Since our goal

is to avoid using the symbol information, we model the symbol vector b as a random vector with

Again, we work on the truncated observation

equal-probable bit patterns. With this assumption, the likelihood function is obtained by averaging the

(r j; b) over all possible bit patterns:

1 f (r j; b)
f (r j ) =
2 b
1 exp 1 (r s (; b))
pN
= 21
N

conditional density function f

K
X Y

k =1

Taking logarithm, letting K go to infinity, and removing the irrelevant term

^M L

"

#)

)

N0

#)
2

(
Y

0 k =1

"

(3.42)

1=pN , we get

1
= arg max ln 21 exp N1 (r s (; b))
b
1
= arg max ln 2 exp 2NA b r~( + iT )
b
= arg max ln cosh 2NA r~( + iT )
= arg max lncosh 2A r~( + iT ) ;
(

(3.43)

~( ) is given by (3.40). Since this estimator is supposed to work in situations that the SNR is
low, we can use the approximation lncosh x  x , for small x, to simplify the non-decision-directed
where r

1
2

ML estimator in (3.43) to

^M L  arg max



r~2 ( + iT )

(3.44)

Again, by differentiating the metric and setting the derivative to zero, we obtain a necessary condition
the ML estimator must satisfy
X

dr~2
(^ + iT ) = 0;
d M L

(3.45)

and can be implemented by the DLL structure shown in Figure 3.11. We can further approximate the

~ ( ) by

derivative of r 2

dr~2
r~2 ( + ) r~2 (
(
) 
d
2

(3.46)

where is a small time derivation. The resulting DLL, shown in Figure 3.12, based on this approximation is known as the early-late gate DLL.

3.15

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r(t)

pT (t)

( )

3. Synchronization

dt

^
iT+

cos (2 f ct + )

VCC

Figure 3.11: Non-decision-directed delay-locked loop

( )

^
iT+ -

delay

pT (t)

r(t)

VCC

+
cos (2 f ct + )

advance

^
iT+ +

( )

Figure 3.12: Early-late gate delay-locked loop

3.16