ANALYTICAL MODELING OF FIN ANGLE VARIATION IN FDSOI FINFET TECHNOLOGY

Name: Geethu Maria Abraham Reg No: 98915051 Guide: Mr. Ayoob Khan T.E
College Of Engineering Chengannur, January 2016
ABSTRACT: The introduction of FinFET architecture was expected to support better integration beyond 22nm technology . To support integration as the fin is being tapered

quantum mechanical effects with unbalanced bonds along the fin come into scene and these parameters contribute to electrical parameter mismatches in the device. This
project tries to include this mechanism to improve the quantitative understanding of mismatch in FinFETs. An analytical model can substantiate these angle variation for a
better matched device.

AIM & OBJECTIVE

RESULTS

AIM : To study the effect of fin tapering on electrical

parameters of FinFET.
OBJECTIVE: To analytically represent the threshold
voltage in terms of fin angle.

Transfer
characteristics
of an FDSOI
FinFET

INFERENCES
PARAMETER

DEPENDANCE

Threshold Voltage
VT

Decreases with surface

charge density.
Decreases with oxide
thickness.

DESIGN FLOW
VT versus charge
density plot
Simulating
trapezoidal
FinFETs with
charge strips

Obtaining
threshold voltage
(VT) from
structures

Calculating VT
and VT with
reference to
rectangular
FDSOI FinFET

Modelling of
VT in terms
of fin angle

VT versus Fin angle

plot

GANTT CHART

Rectangular FDSOI FinFET

Trapezoidal FDSOI FinFET

SOFTWARE REQUIRED
TCAD DEVICE SIMULATOR SILVACO

Magnitude increases with

fin angle
Magnitude increases with
oxide thickness

FUTURE WORK

[1]

DEVICE STRUCTURES

Shift in Threshold
Voltage
VT

To derive an equation for VT based on the

simulation results obtained, so that it can
substantiate the mismatch observed in FDSOI
FinFETs.

REFERENCES
[1] Samarth Agarwal, Terence B. Hook et al., Transistor
Matching and Fin Angle Variation in FinFET Technology IEEE
transactions on electron devices, vol. 62, no. 4, April 2015
[2] Y. X. Liu et al., On the gate-stack origin threshold voltage
variability
. in scaled FinFETs and multi-FinFETs, in Proc. Symp.
VLSIT, Jun. 2010, pp. 101102.
[3] J. Mazurier et al., On the variability in planar FDSOI
technology: From MOSFETs to RAM cells, IEEE Trans. Electron
Devices, vol. 58, no. 8, pp. 23262336, Aug. 2011.
[4] C.-H. Lin et al., Channel doping impact on FinFETs for 22
nm and beyond, in Proc. Symp. VLSIT, Jun. 2012, pp. 1516.
[5] Yuan Taur and Takh Ning Fundamentals of Modern VLSI
Devices