RISC

ARCHITECTURE

by:
PRATEEK RAJ GAUTAM
M.TECH ECE HBTI
SR.NO:725/09
What is CISC?
 CISC : Complex Instruction Set Computer
& are chips that are easy to program and
which make efficient use of memory.
Why to use CISC
 Earliest machines were programmed in
assembly language and memory was slow and
expensive.
 CISC reduce load from the programmer side
 Each instruction executes multiple low level
operations
 Intel 80x86 and Motorola 68,000 are based on
CISC
 Intel pentium is hybrids, which runs CISC
instructions on fast RISC core
Issues with CISC
 2-operand format.
 where instructions have a source and a destination.
 Register to register, register to memory, and memory to register
 Multiple addressing modes for memory.
 Variable length instructions.
 length varies according to addressing mode.
 Instructions which require multiple clock cycles
to execute.
 Small number of general purpose registers.
 So we need instructions which can operate on memory
Issues with CISC
 Very large no of instructions.
 Hard to remember.
 Only 20% are used in 80% of program.
 Implementing code is difficult
 (which increase design time)
 Size of package increase
 (which requires more Silicon & increase cost).
Search for RISC
 Longer programs & use of Compilers.
 The majority of CISC instructions were
rarely used.
 Some complex instructions were slower
than a group of simple instructions
performing an equivalent task
 Too many instructions for designers to optimize each
one
What is RISC?
 Reduced Instruction Set Computer.

 This utilizes a small, highly-optimized set of

instructions.
Characteristic features of RISC
 One cycle execution time:
 RISC processors have a CPI (clock per instruction) of one cycle.
 Uses a load-store architecture
 Pipelining:
 A technique that allows simultaneous execution of parts or
stages of instructions.
 Large number of general purpose registers:
 Reduce interactions with memory
Load/Store Architecture
 Individual instructions to store/load data
and to perform operations
 All operations are performed on operands
in registers
 Main memory is used only to load/store
instructions
Programming issues
CX=AX+BX
 CISC:
 ADD AX,BX
 MOV BX,CX

*BX is overwritten
*Delay in MOV

 RISC:
 ADD AX,BX,CX
MIPS: An example of RISC
Microprocessor without Interlocked Pipelining Stage

 Smaller and simpler instruction set

 111 instructions
 One cycle execution time
 Pipelining
 32 registers
 32 bits for each register
MIPS Instruction Set
 25 branch/jump instructions
 21 arithmetic instructions
 15 load instructions
 12 comparison instructions
 10 store instructions
 8 logic instructions
 8 bit manipulation instructions
 8 move instructions
 4 miscellaneous instructions
MISC/RISC Pipeline Stages
 Fetch instruction
 Decode instruction
 Execute instruction
 Access operand
 Write result

 Note: Slight variations depending on processor

Without Pipelining

Clock Cycle 1 2 3 4 5 6 7 8 9 10

Instr 1

Instr 2
With Pipelining

Clock Cycle 1 2 3 4 5 6 7 8 9

Instr 1
Instr 2
Instr 3
Instr 4
Instr 5
RISC Disadvantages
 Size of program is long.
 Burden on the software programmer.
 Now, CISC microprocessors are becoming
fast and cheap so it is not justified to
burden programmer.
Why CISC Persists
 Most Intel and AMD chips are CISC x86
 Most PC applications are written for x86
 Intel spent more money on research to
improving the performance of their chips
References:

[1] A.K.Ray & K.M.Bhurcjandi, Advanced Microprocessors and Peripherals,

Second Edition. New Delhi, Tata McGraw Hill Publishing Company Limited,
2008, 585

[2] Lloyd Borrett, RISC versus CISC, Australian Personal Computer, [online],
available: http://www.borrett.id.au/computing/art-1991-06-02.htm, april 2010

[3] Richard Murray, RISC vs CISC, [online], available: http://

www.heyrick.co.uk/assembler/riscvcisc.html, april 2010

[4]BARRY B. BREY, The Intel Microprocessors. Singapore: Pearson Education:

Sixth Edition,2006

Thank you