SS QQ PERG R ORC e sas oo I WS S : WN Cea RON *)ae EEE DEPARTMENT OF ELECTRICAL AND ELECTRONI \T OF CS ENGI q BANGLADESH UNIVERSITY OF ENGINNERING AND TECHNOLOGY LEVEL 4 TERM -2 EEE 457 VLSITI April 2012 Semester R236 COURSE OUTLINE INSTRUCTOR: A.B. Harun-ur Rashid, Room ECE 223 Reference Books: 1. Circuits, Interconnections and Packaging for V: Wesley Publishing Company CMOS VLSI design by Neil H. E. Weste, David Harris & Ayan Banerjee, Pearson Education, 3° Edition, Digital Integrated circuits: A Design Perspective by Jan M. Rabaey. Prentice Hall of India Pvt. Ltd. 2001 4. CMOS Cireuit Design, Layout and Simulation. R. Jacob Baker, Harry H. Li, David E Boyce, Wiley -IEEE publication, 2" Edition 2008 Design of Analog CMOS Integrated Circuits by Behizad Razavi, Tata MoGraw- Hill Publishing Company Limited 6. CMOS Analog Circuit Design (2"* Edition) by Philip E. Allen and Douglas R. Holberg, Oxford University Press 2002 7. Fundamentals of Digital Logic with Verilog Design — Stephen Brown and Zvonko Vranesic, Tata McGraw-Hill Publishing Company Ltd, Tata-McGraw- Hill Edition 2002. 8. Advanced Digtial Design with the Verilog HDL, Michael D. Ciletti, Prentice Hall of India Private Limited, 2005 by H.B, Bakoglu, Addision- Lecture Plan: 1" week adres, Scaling of MOS transistors and Secondary effects on device. Interconnect sealing and parasitic RC effects. Lumped and distributed RC Delay modeling. Driving large capacitive load (cascaded driver) and long interconnect lines (repeaters). (Bakog!u) 2"! week: is CMOS process Enhancements: Multiple threshold voltages and Oxide thickr dielectric and Metal gate transistors, Low-k dielectric and Cu-interconnests- flow of an advanced CMOS process. SOI devices, Multiple gate transis and High Mobility transistors. Design Margin, design corners. (Slides) . High- K Process inFETs) a = electrical ¢! del: High Speed uit design. Elmore delay model. Logical effort, electrical effort and delay in logic gates. (Weste) Class Test 14" week: Cross talk and its effects in dela i igning circui = : ry and noise. Desi circuits for performance. Circuit families. (Weste}+(Rabaey) - 5" week: Architecture for high speed design : Adder enhancement techniques and their implementations. Multiplication enhancement techniques: Modified Booth algorithm, Wallace tree multiplication. (Weste) 6" week: Digital Design: Sequential circuit design. Sequencing methods, Maximum delay constrains and minimum delay constrains. Clock skew. Circuit design of latches and flip- flops. Clock Generation and Synchronization. High-speed clock distribution. (Weste) Class Test 2 7 — 8" week Analog Design: Passive circuit elements: Resistors, capacitors and inductors, MOSFET modeling and short channel effects, Mismatch and Offset cancellations of analog electronic circuits. (Baker)+(Rajavi) Stability and frequency compensation; Multi-pole system, Phase Margin, Frequency compensation. CMOS operational amplifier design, Compensation of Op Amps, Design of two stage Op Amps. Compensation of Two Stage Op Amps. (Allen) +(Rajavi) General CMOS layout guidelines of MOS transistors, resistor and capacitor, layout optimization and performance. Matching techniques in Layout. Layout data Interchange Formats: GDS2 Stream, CIF, LEF, DEF, SDF, ALF (Baker) +(Weste) 9" -10" week Design Methodology and Tools : Structured design Technique, cell based and full custom design. ASIC and full custom design flow, automated Layout generation. (Weste) Class test 3 Design of Finite State Machines using CAD tools: Verilog codes for Moore Type FSMs, Specification of Mealy FSMs using verilog. Exaples of Moore and Melay type FSM. (Brown) 11-12" week: “2 r Introduction to Verilog and SystemVerilog Synthesis of Combinational and Sequential Logic, Postsynthesis Design Validation: timing verification, Fault Simulation and testing. (Ciletti) Class test4 13" week: a High Speed and low power memory eireuit design. (Rabaey)- ee ve ME SPOS PPPS OOOO OOOO 6.6 yor"? 97- 05.12 Harun Rashid Room 223 hy Scaling _F MOS Tre @ current; Moores Laws: T ' | > Funchonality increase , cost daarease y Q Scaling : Parameters Sceling Fachr (S>2) L | Dimension (H, L, tex, X;) 5 Substrate Dering CNeub) $ + | Voltage (Yop » Vip > Yen) $ }Piiboy =50nm | @ Qurrent Pow Device » Ins: Tos = SP Se ys -y ANG = £ aye) fats % ie) G* - $ @ Gate Capacitance, Cai I& a Cox We] O)) Ge = tox 4 4 Seeking 3 tra ome @ Transistor on Resistance » Ry Ves ing: at Rie = aes | Sealing @ Intrinsic Gate Delay » ei [eae ee eal > Sealing: (a:b 2 4 @ Fossey dissipakion fer Gate.p: é Pol sealing +) b. 4 = dy Gat. @ Pocsor Delay Product rer ik 2 ; a [ext | scouting ay i ot a '® Power Dissipahon Pensity owes. DissigOoms eee my, =a] sana 0%Moore’s Law L Mor2 Meare L More than Moore =a 03.05.12 5G Pevice Sealin, 1995 = St Areas: ule @ be 2. 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CLF Aas In Con A QsnVe) q ) modu lafieay ParamekeCPOPOo OOS eve BDO ECE OS Pees oeoesend WY Body efeck 2 Me # Yin y LrCe-b iy voltage threshold voltage a Let Wb =1Ly Me = Lv Ye S Lt+-6y5 wa 8 = he {> Loco (Wige > Alobey Wive GND Tromsishy + Inter conneck (Multilevel) 40% Gon 30% FO%K eee rE) 2 mk) eet ry) a N= PO FH wires be = chip! size# Resistance, RE 2 RS ot 1 ee 7 WH % Capacitance, p "te £ Su i CF Seay th Cudire Cusine ¢ vtowitg ~ Str f ‘ Coomera tax) = 139A 430m) Process Stoing: egy, acess —>» 45 wm prockes) $5 220m but Glob asita IX lemath) THaAL | Sévme anera, ‘ ae CY Problem: In a 24m Peocess, Wn . ‘May tel a 1 2Mm a Face = 400A and Cing = 2 PEM Eon 5 9-35) PR Zend Caleulate Hu mtereonnéet length ab which interconnect tapacitance becomes comparable te gate capacitance Interconnul sabe©2060 b0ba8 POOKKSELODBRLOKLEOG [teeture=s] Microwind 2 oe Creating Resistance ia Microusing Ditpusion + NWeLe eelny N® Dittusion, pt sippusion | by) a tien ae tkO/y ee Silierde 3-1 a TING silfesde 50-200 2/8 silicide > When pt, Ww are mind ia) Sis duu Resistance ts decreased > There is another problem : For ieee ean. OCs Yeductd - So. Resistance | willl ve vedluced deperiding on the valut of bias Voltage so, R= Ff (VT) tsing ‘Polysiticon : Zhypes oF polysi eat “+ Silicided (3-10 2/q) pi unsiltided (55-400 aa) * does not dipend on Appuied voltageOF Gopacitance © MOS Gate Capacitance qh Bub gf eche) COR ae ara arta ap rier 4 leakage er ance I | 2 measureounk 4 Problem gray at & MIM Opacifor | ( Met — Thsulatey Meta) \ ~ 2F meted (ayer aa Hac oid. fred)! aptrer apa Te cree, cree eepacitence many umaat. TAH de diejethic const wir ¢ F AMMAIN, problem: sarah didtechie thitkniss sata fixed (4 dtm) $0, ‘Cap CURE anette sae — 4 Pptoblem Ganna ] Microwind WY only cape aT ON wom uefa anew say (metal 5 and metal 6) a Ara thickness Tey ET ar, Ma digleebere eonsh 3 change TH UTE COTE) high k Kee Wa) (2) PIP capacitor Poly - Insuledtor - Poly Prysticon2, O Page | powysilicen EI PolesZ Coes eeee 4-4-4344 2 « COOK Oe —t_¢-2-4 - SLo>e eve veo vBevOD TETTTCeerte PSSS5 59955 t FSSSTt TA Induchr : ee ee SES eR ier ce chs tastes arama, tr PAT Ataf vittal loyer aq natty mete eapec tence New mel argo ona aan lager fre LA ae yreted for fier short zara, OTE NAT mate fer Gro 200, 4 UT Asa meta az Trt by degeu lt YESiskanee we) GT AL muh coer Use 20% bul Far cud chi) Te) Ri, AQ sire resistance Avoid sate ar, EEG Ale aig ae crn hing + 2004m Cu 5 1% AORJem 2 A Re gh ao 4 2 le Ve Ry — Sheet Resistance 24 Ro D >, Anish om = AL * “Yay -9 ohm per square 7Q ahm p. u b Lech’ ¢ cla CER microwind LW aT fog oe3B (every trensistoy ard) IUSE Cuivre / ord ‘ay metal “32 Oa ae, — 1a level G tonsisker aren, areca Cros. OP cart | nebo Use TIT 2a WH ace cepacitanee aia, Fig Moduting of capacitonce: a fab pi? Parallel dapacitanm BVT. yess “pI fede giog Co peel tamed | x OE device GR tapactance @r ae WET Soph oa aT 20g Cesk Qe Grspea eylindvical Parollel ge ly _ Hint + Baie ae (1+ Tce Hin) |] J eee ‘2a in [ir 5% tm ]a 2 = °@ 2 2 Win v é on? Cet Hiaed § cat i, oo Wspd « oi i Fens » oP &,a00nt Wint = Wsp = pesign Rute Cx = Wire - Wire Capacitunee o> AT etseek anoeng Oy ling Use om Tm Interconnect Scaling Pororneter Ideal Sealing || Quasis iteas sealing 4 t Vel eal Binunsion 1 thickyt55 (Hint) Insult Ss +t thitkntss Cho) Local Interconnect s & Length 5 s Resistance. Ring Pint Vr int ‘eopacitince to Gar Car tint RE Const, RE perunit Length 14. 05.\2 } Const 2 seating"iq Heal seating: R=gi sy c= Se yz Foe Inteveormect esivg scaling a1 zara TEP seating 43 chip Gnbkeaan aq hip anieRea at Sy Cost minimized otaar. EB Resistance Brae (a) Souy Heed yo Wing Hin p Rint} s ? = sg) URS a i 5 % Sy Capacitance e Cov wy; % aR = int liog = £ tex z ’ + Gre) = = 4 = 3 rissa FARE Const Per unit Leng! groper = $e = chip dimension RE const Per unit length = 52° = Eo cat Globo Interconneck Re delay - Bie One| sé L L a4) 5%% ' TH Bwasi- Teal Scaling: mihi ay Ring Fy Sie oe . vl : Ww q Rint |, > iee peneeeeteee nrc rss COPPER es sea ee. SOSCSHSSOOPO OOP OOOO UE ODO OHHH CELE OLLELE OD VHSTt ay she RC coms} per untt length Abie eK = t R¢ const per unit length = oi 2 Globe Latercemnet! Re ditay) 00 ¢. Je # ideally delay should be low s>4 so, after sealing ip delay ts deevected » then it)# Jo0diq Material chan Resh ( Ab saa ae Résistance deectiue I CMA eppect pourdus /organie leew ke aateay Fig Modeling of Lnterconnect a, Helou lou =!'V cna, but achally Resiilarnce Lumped aT distributed . Deloy ia eiretut Fox delay Joy Rise hore [7OWVave 4 to% —9ox Fall Hee * . bub caper et tance araar: material use ora peeeeeeaeaeewaeaeeeeeeeeeererrereTotal Delays Stor circiy Ft FOr, colony Sum weet M3af wR ye DUN AMT, +0 et eley ty = tat ttt, PAtisoO oF Detey Distributed | Lumped tl »> POO OOOO vedo dd eddie ddccioobe bout SHOCK VLOoOY Fl mods R ™2 madel: T2 model oo oesCaF O34 om) Using El-more delay Mrddel tind Bey delay PRSSPeteeeeeerereeeeeaeeeeeeeeeererecer * FOF Rey Co 084 Rink Wink Hon Re ee.Ferre peg eg f POCOCLHVVV BEDOK HES MEOOOOY eer et Mi Cy Method 3 Eoening Trtevanneet Deloy Mi Civeuth Technique; x Ri "eave! On avore =4 10 squares Use of Repeater interconnee? Size Tated RG = 10x 103100 No of repeater |'k Find Teox Using Ek-mere allay model = te [Ox ReGnp FOF Rye +04 Rink % « * O07 Ringo] % = OF ReCrr + OF Rak 4 O.ghiiRs ab + OF Riu alee) Imprsventent 4. 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Censk R som componunts to futbtye techni Ty Solutions fo Shallocy gunchon Resistance Problem: Extensi or Implants Elevated Dut Ce / Dro Sitlicidet fens ansistor seculing Te Smee cen 3 | Secle TA Scaling of Device Tolaha eriout problens® jy # Locos bared sol, TH OVE he to bid bec ench Tate on # To Solve dhs Problem). 2 #2 eeeee.fT 3 2 2 2 2 2 ° ° 2 2 . . ° 2 2 2 2 * s 2 s 2 2 2 a 2 > 2 2 a a a a 2? a a a a a Aa @ x \ oeee Qa Physicod Limits note #% Poly ferx gose ara o 1D Sealing $i Mosrax: T Poly dopa ara) p, > Lb met Gt rat uct Aacut (idvppuds etal HUF Papel scresr mabe Aare (dip PUI | aera airy 1? 2 metal sar on P i Tor 27 a TEN ditpusion area ae a, nach Resistcnee a - band Y FA New Struchires and Materiods fer Neno-seate Noes o- r BuLK —> SOL —>) dq (double Gatez Ty Carbon Nono-tube rele Het nect pric rv connect 23105.12 qpdkooo oP: or hérinal reuif Elements i, Circusp Elemerd Fe > Lowy ass Nos 7 YQ Transistor - ded High ve nimoss -hvt Ls pros J Neiwinay votteege av) Tig y tees Me Ls igh votage (25¥) —1 lienslow ye; Heat Speédi \ CON) OFEIG@ Hors PIES TUT p Curent eter High pavser High Ye = toe mu cover qa! ‘one! tow Cy Nominal / High vwoH chon 3. onomar > Multiple Oxide thicknut Mulfipla eshald voltage High Vy substrate comeenhuhon T Fig Dédign Morgio® Faby ot aay aasign 3 vari Same 2tdat SPP PPP OP CP me pee ner peace eee eee eee ee HEEO Inter chip Thter wapen Intex Lot mos \seleshon + md tat coq cotlechvely tts1g7ws requirement podgill ang «2 | Ge Difgerent Sources Of variation os 4. Supply voltoge = @) IR drop TS Si variahoo f TS dS) Enviconyvruntal » we Operating temperatire: — Environmental 3. Process variation tas tLataye) PEA 2 & Filwe tnrekng Ta © Doping cemeenhrahon 4 Deviee variahdr a). cilipbaee | ladon oe ) Oxide Jhickness . tx 2eoeev00 \) Normal Diskeibuim y + x 3 Pan make A so ae weep Ay OCS reey cate eabake seartaa chipgarer ae iT ttt PP SP EL Caan SoS Hod ox. ev. exHvH BLOOD >. eka Design Corner : Slow —> current g Fast ~—> curren z € NA6s # Py a) nta PATOL ER eri tre ieem aang a va) sinha pio tae dt hy ‘aw ON amare speed T#RA JDOPSSSHSSHSSHSSVTOLHOIIOIIF POH HHOECHOEHLOHOUOODODOOa» LLL a Peopagahon Pe Pale \ teas 2 teas trap» tear = LAG 1s \ Lechire-9 29.05 TY Problem: Skelth a LinpuF NAND gate With Tansistow width chosen’ te achieve coorjh case &j4octve rise and fall resistance equal to a unit jnvetter. Compute Pu “Hig and falling propagation delay of the WAND gate driving h idenbecu NAND gabe » Assume At, > 2p .2 i 1 PMOS ON. so, AGF Phos 99 FM orged 202 erate, server errr rere rr apt Fort BF ide)? eau = Yr pkios (qua CRom 2197 arge 2 of For 44 3 ‘ e z N 5 e 4 e e 1 ayrort L 4 1 yr os ; v 1 vrenk , 1 Ls = t e Rony 1 i | tL aq Ns , - ty « e . nver rer Aa Wes 12 planip 34 NMHC is Ta. tater Aqerivalers Capacitance SinO00 oooee8 Deiving Capacitance ~ Fhe HBC > Cin = AG t-t-t-4 on "YA Standard Layout practice TT +t + 2 2 2 2 3 ° . e 2 2 2 2 * ° 2 2 > 2 2 2 2 2 2 2 > 2 a a > > 2 > a \‘ \ L\ ch Worst ose Rising Prapa gotion delay vsing El-mole ‘ \ dete ynodel op 4RcC ith) PdrTy wonst case felling prop duay sing Ex-ma le rmodel : F Tap = Exze + eGe(stHy = Re + 4ne CLth) C= 2 Hum , R22BkKR-Am in a Fon-out Of 3 NANp. 10 nm Process © t 3 45 s trae = ARE Gt) = 4x 2-5x10 X 2x19 C 143) e = IBXGKIO-'> = gxio-" see © ¢ = Fo psec e tpg 2 RE [4 +4443] e = + | 7 Sxi0% x IF . | - - > = Frio . = FOr ae x s e | Leclure-io 30- 05.12 « PUR AND Gate having eyeclive vise and fal veslstamed assunn An® 2Mp f Wavtece . las 3 —> -> > > > J * 2 * ? > > > > , > > , Fig Peta, Model: Gasan Peloy Model: In genered) the propagation cleloy oF gate fan bé expressed as d= +P dm delay i i Po parasitic delay op = 9 ‘nhevenk to the gake 5 hen no bad j ree a F is attadud > logical, efort, on complexity $> Ctfort delay o singe oh gare Storr niet bags on h= fam ouhop electrical Sport the com plexity and fan au oF the gate. Foe inverter ; C2 Paresitic delay, P= 3R¢ =e f Sa Ths @ 4 018i OF tne URS a =4(is 7 1? eae et | Gin oF On inyvertemys that con deliver the Same OUP URC yre tb P= 6Re Apter normalizing Ke aed r Bt a diaoe? d= PFE = Pt gh = Sth 2inpub’ NAND! Gale: d= 2+ th _ peal a eee ete ba 6 ee ( Nor maliged: pela os he —> Py x 3 4 vertical feat) "Problem: Determing te delay oF a FO4 rnverter C Fanout of 4 inverter). | Assume He inverter is fabricated in & 100nm process, coith’ % = Ig ps. Solve: d=ptgh = 4+ 4:4 =5 _ dalouy = Sali = 79 Gs— Oe S be es ‘a 1f the gates are of cama bype ; hed) ) Nunumber of jnver bers d= 24 hl = 2a ¢ od ewe LY a 2NK2 an i eee A ea Ot 4 | NN 23g hh I ae Ape se FY delay in Multistage Logie Network | Ik lo ae -: #e aie i a F 20 bit re ey get Tote Daleuy for the mulhstege rekvorn, qa 5 Day Deter iy! pl P—> sum of oll the parcsitic delouyLechure-tf eevee 5g Oplimizing Pelay in Multi stage Network: : j f : oe =e Estimate trninimum rod Cet ag delay of the patherom A | 9 ) 1 ‘ Jo 8 A +0 B and choose 4 istor sige to g,=4 k= 45-3 F 5A trans F 122 Fi eae vi Athieve tis deloug. 100 nm process, A>Sonw Path: eleebticcil eHort. | Hs CourN(Pathy 45 Sin (Path) oe. # fede, logical effork = G = 4; Mt Ge stm. Sean ee too 333 “Ih = = Poth epork , F = GH ( v0 branching) = Gp ie Branching ) # Branching Eppect =o x9 = 2x 48 xg ww = '@ 22 )Ga = tag ae The delay is minimum | jreahin gach stage has equat etport. #% The best stage epport, fl S25 = 5 [ oe oath singe 7 oF toot } 4% Hvltistage delays | D = De+p 7 Pp Pouts fort detey 1 te # Finding ys ee~ a + > » > a 4 > + a > 9 > > , , . , , , J , , , ) , , , , ) , , , : Finding 2: 5 > #x 1 *” AZ isthe toad iq terms gp tniclatts 2inpub'NAND Gote pu 4c} ie Assume dnt We = @ 22’ Mn aztip Now. Flad NOR..NAND gate size whieh will optimiag Hu wie § fall Hime. For WAND tzingut) yw =4 1, Un 24 For AND @ ip) NG 9 ‘ a > = te =l0 | ’. # Pade bevy seit Pies: jot grrigFor 2input Now gate Matern aregese ede Ty Problem: A contro! vnit Generate a clock signal from a unit sized inverter. Thé signal must drive Unit sized loads in @ach bit slice Of a 64-bit date path. Design tthe buyer chain - FBn, 7 —> arara arty Sinverker Arat elock pulse distrhed zr AL wm oF aren a 5 + BoA i \ ; " Maverter a Are step wise aria buper chain Vayarg or e * - - * . « . ‘ ‘ ‘ ‘ ‘ te . ‘ ‘ ‘ | .Leeture-12 04.05.12 CY Designing circuit for perfor mance Speed Power Consumphon { Pe Tew P= $f, Von Lewy vg fp = Puby factor =) 0-04 for CM OF CMOS : = 05 ter NMOS o¢ ke ff — vp Pseudo NMOS J = 4 a : i] r rm ] | ] { aya a PSEUDO NM™6) ey ; PRT Sto cuvp Ay L and CMOY of Ne CMs cron performance fara arr 5 D rH SL amo a8 ary CORE eos '3 oye MO ans NNO a2 strcar connected. boad (aq wats sag vam NMOS 99 strrer connected TA Foy better perpormance : 4- Reduce G+ G) Interna Diffusion eopacifunce can be reduced by reducinyDaven. CQ) Ci) Intercon nect Capereitance poly Ls no cembeet Ave TEVeC For me Paes | =e Git), fen-our | i Pr tmerease Tavg , Inenecse wy, ETT Poss | ie vee => j Ven’ Coan nok be increased ) Dymanic ¢/ re, eck Von AT sar wie + Sp — best cmos B. VV : emos. dV = Vop > Rae charged + oV. Vpp at COE dynamic ckt | 2 TH 2a, 6. slope Engingering wR 29SIs GAT APA, oukH gee ey \ depend ara propagation delay 4a kp Sea HASTA AIT GH tp ae NET cise oa RTA Aig SMos Cipevit ¢ | GS Gey Beit Gay | & = O26 C+ G CaKRGHG.) ao 2 nt aanagagaagasgsSe Pe PRS ok Oy imple mantahonLecture-13 06-0612 TA Sonu Techniqut ia improving CMos pexpormance : + 2h Input Ovdesing Delay Eppect # Consider the ful Ung ocdpuk i. transihm. S - 3 eH - el q . Fea ; ‘ L . Ar Za : | “ vest : ' Fig (ay fig Co) ’ Ddeuy oF $igca < belay of 19 () Discharge, path “Mat 1 far sig tH) a Aisbharge pobh arts Eig @ Fig ag layout LA 6cPR PPO ere ee weeddddddedidti dl > Figo) @& ipkermdiate node discharge 22 ete are ara GB ANI ON wee; ory delay GT HAT GETIM disehetrging path Consider aww wa wyoutr mode) is phe, 27d) dnt then ~s CB Problem: s= Gba-y + & CO; +b; + C;-)) bi ia # Low ovtpuk A AY Masha oMsNG5 (AVMs discharge mw gry move Grovod ong D1 Gay My Mas FD SRRBTA COV (sOTH current ) Current NT Oat A @ stele size aa fer Eno: % AGNF progressive size aa TS wer Oe orebrciy Pall? SigsBy Assymetrics Gate: Sa ura A fate con corler | Huge power flees Wars cmos q just tensitanc payer sow, : wa, But gear aleoays on 21, so, power consumphon esi 7 , ] fee ON / “we =) 4% ckt 241 ourpub Con maT ger arena compliment: NAND > AND Q-x) Nor > OR XNoR — XOR at D tt OF 46 part. alfemahvely dae on-oFFE 27a mA Vop CAR? GND CHTreENk slow Ja arr Path ATENY «So Poluer consUMphm Be, = adv: he complituantary outpur. lobe Th Cascode Voltage Switch Logic; Y= ABtaR = AGB (97) * Yas ABTAR = 406 : 2 input xor/xworAdy. ee ee = “ . # Lr outpuk a1 fae stale power consumpHon aera . # crema ath output ee oral circuit use TATA Fic 3 . & Dynamic Crevit : NMOS. circuit ‘ Pseudo NMOS Civeurt t mos ; i (Wageoted ease ' eMos P-oFF | = ee ae | Prascharpe | Seteatf ole ie y -| v a } Logit. Rat works in 2 phases : 4 Pre-charge 2 Evaluation oF logic > fat um? a e a "H Zinput xor Gate: Hetak 2) asap ite Ss ae o> 1 ) t ae a rile Lk A | A _ . Lip r "es en . f 1 ( teCy Footed Dynamic OM O84 e-oFF yo ore Yea “= ah ea (is Logie Evaluation # Pre-charge ORBAA logic 21d Bro ar @A CIA PNET comsuMPHon’ sta. arr (wea Nmos ér Ff conhnve Tad~ >—S-——— eo # Vpn ana GND aX path crewter coat Sea (eR Mot amt veststancet ax Sere depend ama ovirub Re Gana camer efrfra OA ta Ate @ PMos atl dominating - # Q Naa o> i Te FAT PMO oFF Rar omr vMaTT X Grr 190 ati but ad discharging 94 OF np Hore oiteTe ood tyne ca Hep Y 9) tae! 2er0 zur aT bub FAITH PAN Mos 26m ofp BU AAA YEO continu, PA: 7% Input should b¢ smaonotonicatty ising (far dynamic ext) e9 Start Lows ——» Remain tow Stark los —> Rise high Stork High ——+ Remain high Sturt High —* Fall low (nor sowed) (lost example 4 22 tose zt: Se, prohlem2ee) outpur monotonically fouling aor aba oulpuk Wap ama dynamic cht a input ay ATG ati Ty DOMIN@ ¢cMos: (AND) Normed Inver hy Dynamic CMos + Stabe «7 eMos (averter Dung mic Dynamic = DOMINO ¢Mo¢Lecture-15 "06-12 Cirevit Families (Review) a SU ROR PRR SE OS. Chapter 10 Cestel) £Q Prevdo N-mMos Gates: SS SE Sr Ex: Pesign a k-input AND gate using « Pseodo-NMos - “Determine the delay poy o fanout| of H. | Problem: Power tm Sumphon OB are, Soive Rrerta dynamic Mos. | WH Dynamic Logic Ud : Footed / Ungootedrg Invertee NAND2 NoR2 oe | a Monotonicity as 4 ovtpuk ak requivemunk @ fulfil! @eaar a $e) dynamite ekt aa Gani othe .. PEA cok allowed NAT. Rr | Groenaly camera Aoy cascade THA Gay amit inverter vse outpub 4 Wy | DOMINO ¢kt Ma Domino gobss CMOS Ovtput — inve ring Diming Ovrpul = Ranaiiven ier ~~ .vewowwewneeeeeeakiaanni Y Domino OpH mization 2 Toot YY = SoDe +5\D, + 52D. +53 Dy » HDs F S505 +S De +57 Dy “8/4. Mya) Pema OR gate \opur Inver ting 34 1D, so) sey Fl wu NAND gate Rp a 345or FA Deal - Rail Domindi j, 9 ah wa Domina faux NAND. Nok +xoR msn =MIAT, Solve? Pval-Rail. Domino —s Nendaverhng Ducel- Rel —» Inverting » Now-| eae Ganyrar A Usmly ana Example : xoR/xnNoe pl Wt (AmoeR w E Problem: Evalucthim at ST dynamic sodes floahng 2a ea BRM = - . # Dynamic moh hold Oma, Oy “keeper transistor’ Use TIO Wh # keeper Hantibtor weak 2 May but AD eae 3 aT or we recharge- 7 TH) THD 12M Dominga Logie: — Moholoni city ~ Leokage { — charge an ant j a " Noise Me = dv a Pass ae Civeuily: | A=o. ems Pass Transistor |. haere Bp pa] Na valtage drop bv Cw a ie | z fea LEAP: signal normally gate 4 ort. 4% Comcepk A Gaters | Ria, Souree/ Drain a3 Fira, “ip pet F rm [lace Complementary Ress-transisler Logie N@W Slide Lee IF) | 7 Single Gi} Addition : | Help Adder | Full Adder A S= AOB S=AaD | r A a : Aeie | Cor = 408 4 Cour = MAD (AB, C) i. = Ht | a nm —o-A good Ate Cor = AB+BA eA GFE = 12 Jrensistows Ly >a 2 r & v ee AB+ CCAFB) => J transistors “= ABE BebCA | a wii wAvizert apy 2mae 24tp Sieiag Aa ary 51a Facra Case AD oaf mm 224. Laversion ne Berge ae th. Corry Skip Adder canny Sele Stud e Garry look-ahead adder| Th Corry Look Ahiad Atay Fg $-24 = ALR + G40.) On [Hist cin =0] C1 = Aye, t GiB) c. = AB + (AitBi) AaB. + Git Bi) (ac #80) Cin * Co GAO walk TY «, 2% 06.12 Stide ¢ Wlsiac aden. ppt Gt va thaa Cg = AzB. + G2+B2) = ArB2 + pita, (Art Bry + (A+B) EAatBL) ALB, + Gots.) (aitB,) (Arte ) Cia For Ripple Carry Adder : et 4 zs ty = [IeN-1) = sa ie ! For Cary Look Aneciel Adder: Gare bit aA OA) kt qaTeN MT C2 CAO COAL BWA ckt GR comphr XT MM) Then abit Ta Aur aah mo block aaren, +. €or 12 bit pee ge SE 2 = catty look ahad adder 7 a dato C0 (19g NDPA Diagram Notedion‘Tnfermedhiarte cell. B Aa tH : FG, \ nt ay ay te, ¥ G = 67-6 PRG, ae i= Fr ® G,., Beart Gm Nee Sum “tbr 01 modified Pre {ix nadderEl @enerat Form Binary Mvitiplicoon Pot Diagram Array Nulh plier Rectang utar ee Carry Save Mui tpticy eture-17 7 High Speed Multiplication Booth Algorithm SFCEXIooo1 = Ceiciodes 4 cet 99.99 8FES Cre ) Nvlt plier iy : tk-t +k * ° ' 1 5, t ; J 1 ¢ i oO oO -! Hees 12 htt ts gtth-2 5 #14. of 45,, 2 lono Hplicand Ui 27” ourio — MultipalEEE” (OR4 4256+ 128- 64432 -j¢-s-2 (350), ‘ 2990 ‘ . We cheek every two consecutive bils ot a tiene ‘ p a ain Operation ‘ ° In the middle oy string oO 9 (No operation : io begianing of string 1 4 subkroet 9 t ' Tt End of String 1 se Rae ; 7 3 to parti Tn Hue middie of String 1 © No operction Wa Modified. Booth. Algorithm (Radix-4) Radix 4 Booth Yeearding ap multiplier bit A= Hijo 15° (11 ©)t OOPS » Implied 2ero is taken 1 Original on the vight t q Sign extensim bit let negahve (1) megahve (0) posihve We consult Hu block below to decide ty encoding icant > ded bit Y= mwHiPlica Ente % = multetier Kain Xai iat Parka) Product |xG cm) 275A) am oO oO 0 0 oO 0 ae z ‘ ° ° t i y 4y 1 0 0 ° ' 0 tn 5 : a 1 me : ; a -2Y 0 ' ; ‘ 4 l ° : fi 1 -4Y ‘ J a) % Pra 4 \ -0 1et t t Y= ooo00 Ears t+ Y add 7 0000°0° 110 ¢ Beh leds Es cegaiee oo tht {for og rey pie #¥ = 000000110 Bis eal oes cacy ay os) 11 t Glare Ber aot o oY em R=Mlioc ret 1asd J = Resultin 2% comphand Hea vesult 2's complemunk Gill give = =Ciele1oes) > ~-(84)i9Ptr ha pan” = -2y OF Cte Bs @a),, TI ah * —<([ ee Fai | PP y= NG Xs + Me, QB MH; ie. Sie 4 ekt Want Gauge 2a be My Sts ay shNURVEVV BEBE EULER UCL UL ULE IOUS Cbibaearitep rire : or Deg By ential Circuit, Design TA La @ @Q : = igh Vpp-V 2 Dake is conne actly fodrain /sovree ( digg usloa) 3% Nojse et output can propagate 4o jnpur (to corrupt Hue tapub) A: Output flo ating> but & & ¢ HIl prese Moditicatiay feedback ~% prodlim ere 1G) propyer FIR | Modigi coki or tri-state Inverter - — — — = — — — —_ — et —* —€ — -* — —, — ot es es es es es on a - an aa 2s 4 B Clocked “eNos Crreust — — = Ss 2 fa Flip-Flop Pesiqn: = ] = yeD f oT, Q —hy5 aa Modtticatar Clotk Skew ra ng WITH Ar ckt @ —T0 avoid trea + tra ttserup + threco L > Peg — Ctr ttre. + Esuecs ) Guanes 4 5 Seqwencing averhead . « . ‘| Ey Minimum Delos Constraints « tea > bhoid ~ heeay + tsicees oh Tackling Clock Skecy Problem | | © Routing clock jn the oppasite divechin of aha t Pd nun + T tea Gy Witertanty mally Be Sahspied ] } “Pea, man Eee P Bedinggen ae poy [throughout ait Iecrease] @ Two phase nor Overlapy "9 ele @) we designed cletk distributor nehuork H - tree clock dishibuho | | Uk Clock Buygering T + Sele SiaSrererer eran GG Ga @ Oo OOS ee OSS ee ae TY Synchronizer| f } ha Simple Synethronizer: [2 PPROPAnennnaaeeneroneeagnnanY Communication PHP SSHSS HHH HH TH SSH SHH HS AHHH ad HHHHSHHHH HHH HHKHEEEEE Clock iS een Asgnehro nov. y Bek Aue AAVGLEDUESE ELE DEDEDE DOLL Eee Kee e eee eee t cella 5y Combinational Circuit Ty Sequential Circuit MY Synchronous Seyuenkal Circuit Design aU Analog Civcurt Ty Transistor as Analog Device Trans In Satvrohm: Th ack 6 Ii yOy CS stage with Resistive Load ae ay) 3 F Problem: Avy ance FHS stage with diode covmécted (oad 1x = Gon Feb) Ve + VE a. to Tx Foro} Foi Gon Ay = ~Jn, aa TIARHHHHHOHOHASEAKEHHRAEEHESEHRELEHEHEHEOHEEHEEEEEEEE ELSUSE o bo oe LLd bbe oeebeobboobebesseeeeLee Ib Ch Operational Amplitier Cop-Amp) Dp Amps are ampligier thak Have susgireny high portuard Goin sothat ehin a negarkive feedback 1s appiieds the clare loop transfer funchen | prath cally rodependenk oF the Goin of He op-Amp # Hi Xe 3 Xs— EG A < ; . A x +A F ect 4 APPA i of CMOS Op-Amps vy; J 7 * 3 High inpuk resistance 28 Mos at gate PUK) output resishance high Paw Lr buyer VISITA» Cher leading) S Pole 216 AI ANw systema Ge] Compensede TSI Ast Compensthon eirewt (Ta;i sia L <= Ty Tdecd Opamp Tdeally an opamp has fofinite UWferenhal Voltage goin, Inginite input veristance amd ero Obfpub _ ot = | = | resistance &- S Usuott = 43; pyr Usuolly voltage Jain = a avround 2000 1s = Cant Sop aenp “Tt p Lg J Haw. = 4 Ve Thin +e input pert ec , com be -} e Nutt poiar b F - bY UNWREPP EE Mettene acioss Hu port by e 9 ¢ < Camterd—throven tu port ; = J eo i ts ) e re isi 2 e e e e Py Negahve Fredback Amputier Vout Ty Non- Tdeal Characterishes of} Op-Amps W) Finite digperential input impedanes 2. Rides Cig doo} (2) Finthe output vesisttintes Re » |@) Input Offseb voltage Input 2 2vo AT OP 4 2240 Way, ay fet 20 enrz T/P ese ) MITLULTITITT TTT ETEK TEE,SoSH DER SSHO ES SSSHHKOKOKD DO VOODOO OOXSCOOOOOEHOHHEEEEEE Phe japul vettage Meeessary po make the DUE voltage Av(s) 2 Avo Beep as ——— Gay av: +» poles oF Hue 6p-Amps Open loop rranspem fenchondominant Of the op-omp Cpetohm determing ped # Slety vote sloco High fre sperode z TACO PAT AT, # cdipend 7a Capacitance It S14 Sleco yore = 9 {Mou dt Hy Settling How: Cinar value ow ararg witsr ouspur aseillate TA Fat ay Ad Ose 10, AF ay UKM CoH differ ama aT UII LSOPO KOM REREeEEE EEE HERERO OEEEEEEEEEEEROEEEERESE.Poddbboobbo vee bo bbobbboobbbovessadedus Lecture- 22 09.07 a "Ga Single stage Op.amp a Tbsq= I> Mala T Sg fon = Gain = gan (Eli, ) Lema: In & linear Céreuit, He voltage gain ts gqual bo — Gin Rout» here Gm denotes Hu Hansconduetance OF Fe Cincutt Whin He oUbpur 1S shorted to ground ard Rou is fe Dutpur vosistante of the tireuit whin He inbul poltage is Ste to eroel Jy Resi 2% Aa Gm Rout Im (Ye fy te= %, i Ae eo, > In order to achieve high topology Com be used at QT CTC aya OA} cascome ate Te Cascode TaGar code BEF STSEHSST HE SSE SSESSSeFEHEFHEHEHAEOSEEESEOEEE EEE HECEEEVEL EH -LLERD bob LEbbEb bb oS Obed ovcoubeo bo ouODOL 2 PMOS. Cascode cutrent sources 1+ C9mset Imes) % 2 Maximum Output voltage sewing Mop = C Van —Viw, ) —-CV¥ee3.— 2 Common Mode gain & CMRR Viem > Vast Qu ¥gs2 Res Vgs CL 29m Rss) V9s = Viem 1429,Rss 2 Y, ve fom Ys ~ View I+ 29m Res on RsSSS asa bss e ab bee abo e ssa e asda ceded bees ee adobe es y S 8 | «9 9 . 2 a ; Sage 8 < f50 eT Z ij : 35 5 \ Awl | » so £ a) £ 3 £ = I" > zt 1 = ¢ 3 ,)+ RRs Tot Res +29, TR Roz >>% Ro Bomnuen greales, then, Potala stance introdueod by Ms. Fe C%n a3) Hence ; eae ce Rey in colevlahng totat canbe neglected resistance Of Hy drain Node and grou V9s3° = Transistor My senses ks voltage OS Vos 4 dyin «current & produces tg 1 4 = (= Oi sg Tog Copel a3) At the Output -node current dyperance bekveen 14 &'2 passes through You = (Ch =) te, te trea, G2) la), tif Smytoy 2 ea 1+ gm Vo3= Men f tnt, 2ARss 14-4 ma %q 4 ee VE «Toe, 2Rss 149373 m3 %o3 >> 1) gm # Gear current reg. USe THA MI” O/po vesiskariee onan high. 0 isdn Cuarese oSopme Fst» CMRRT Ty Frequency Response ‘£ CT3 = Monde RITATAALLALEKREKEHHHHH EEL ELE LEE EEEEEEEHOEEHEEFEE GELLechure-24 ‘a Frequency Response % Single stage opamp d ipacitance at the surput 4 Cyay Playg * Coby t Ce =? “Miss! = R n looking s esistance seen looki 4 Gatemdiratn ea. 0 %3 ) m3 Now, V9s5es = fe ROS paredlet combinakan op 15%) hile SHED C0, Wq) = Re; LRG Ve a M Mars | pie RO yy) ae, i fs a | - S4sRe ds 7 2+ 5RGy oblemn *all poles & zeros OF Ags) 7 hs - ~~ Ton = rs Jaw Pita ee c, Nou 2 = Tas; : is An Co ° 2) y | 2 | 5 : 2 . re > , 7 , i 3 - : 719.09.12 a, Pair PM eae | Pros Pieroni Nour prte. E Wee on PIIVYGE Coote cesistance of M03) Yoel ty Input resistance _ 5 Outpub resistance ; Votage gain Imi Cre" %) = (Jnnjk Catevlate the Voltage Goin oF the Pros digg pair op -amy BEEP TMhabit uses Hu 0-¢.4m pus sec wi = =02V for oli transistors and \ erreererrerr er eaeeeenaeeeneee Van a Wapl = tcce Yam 2 meee SS OL 2 Vev Ip Vow By = Grn © WN, ) Ime C¥e! Gz) Vy y, ° i Vaz / Yay = Gin e2tog Gmc USF = Im, Gs) 3] | Yitt, ehe | (ee: \ Vas ) | Tbe. Tn) | y, waz x Gme (“Be a * P= Wing War | Von. ee, Vove cd a | hia oe Ip 7) Way FPS% Frequsncy Reponse oF +2 WO 0-36 §ta0¢ ©P-Anyp Trans: dpe pies? OulpUR Teristane. Gm * Gme q Node equcton at Gm) Vid $+ Mz + SUVin + SC Node equahar at N; Ga Viniot ei + SCa Wa. ty Sitaulve- Va) =8 4 + Nia Corer CG) Ve CR at SG MeO ie ne to tS Cte) fer @ GCimis SCy Lm From eqn(y Gm vid = VA PR + SCP EH he PRe oles Hteas Cea? GS 2) FINS RoRika Gm, LP SE. ay . tt RIT hae CAF CoC Ce) J RRe at posive real axis The amplizier har vo poles ak Gp 5) Gy The dtnominaty can cupreseed ‘as Dey = (4+ Assuming = 2 opr + Gop, Woe ! ‘ te - GR PaGpRe th Ce CGmaRi Re FR + Re) Des) Hence, ep, = I a Se" REL e Haut Gare) J+ RECCer @? ah i bigger pron Gps G I Se ene R Lute Ct is + Sims s Pd, papper Hon eae tiles Egyect as R Ge Ame Repj» Dp, = o] sobshtoti ; T sobshhe linge lie sp ey,» Oe = a LE AU) BIT 1 zh ir | + K ; = ACia es 1 pe a i CTO ‘ , * SS ly Loop Goun L Ges) (fo Ath B(jus) Tie Vorrehon of loop gain dhe gFeabileky or inst Ty PRE phase dangle of He loop gain is 1e0%) Cith frequency debernines of the system ® (cos 80° + f sin 180°) = -1xxX At tS Grey the (oop gain wit! be veal mith a nagative Sign | 1 feed bark is o4ve Pa TE Beit), is clees than Unity Phin Ap auth b engrendter than open loop gate . bulk stables £5 | UGje) ] e1 , Hun aillohen wel Fake plack ag contolled » oserlahon a Tp IL Ge) >t. chy fet vs AbVE™ stability Pte ngaeist, Pt| Vegr side ORCL -Ltjo) greater than unity and | Spe eee tol Be iy cen sy <> } Lyf St Lechure - 27 30.0 Te Stauitt y Fm Stability of amptiier and pole ieabion |POl@-oF- ampuz ef cs) (7188 \ + t .a& disturbance applied | response ot Hu a er 2 ) cox(Wat) H Te pole ts on” Lys amplifier ci be stable Potes of seedbutk amptifie poles OF yeedback amplisier org 2Urey oF [t+ Ac) acs)] Cased: ampligier with singts pole response. ae = Ap SF Up |Honee’ elosaallivep) trans - sunchon | Apts) = SABZQi+~ is ; | yerayy| # negative > Fain sre | Single pote amplitior i, Buy Case 2 Amputier (sino ~~ SS Avs) = as 2 (les Ls ets.) C Pe Closed loop poles ate obmived Geia f — pole 2h arerarhy unsral Gea axisy — | 1 OTHEA overlap Vava_ | \ Hh complex. plane ama Case 3: Amplifier cith 2 pole ZB pole + may, ostillate based pole Cgainy paihon on Hue UNcendifenally tal ftim > stable 3 Ne. le response tha) S Cll He) + Un tiparsa.p)=0 = — t+ Oh + BAGS 5 Cues “ho? 4 Gases c camp py ystem phy tableSta oy ek. 5 r n hh bility srord Gain Margin ane ty Bode iY lea POR add Bq /gaiy AM, PM brine rp, 1 Phase ty ralr rasing — yh) Teg ree Ce = Taio stige os, ad bere en Rey é f eed back With feedback eapaci tor (Coy = i - - a ee Cacia me & . RiCeGmeRe 9 & ame 3 + CAFC) Cet , Ort , ORt + ede) back Frew Comptnshon of stage op Amp ith fea bac for| POOR Pole: Dominant Lesh hands polani cotued Mites ” Bote GMd atcoptishes decinod Covmpen fCOn Millan, Fhredvem s —_ trem: = 2— impedance * 2, = % Koa gcun eens Sali Mrbloan® capaci tinge 7 IfGoin artenr fra itt i wart tara, stabitity MA Be | & |} & phase Shigt ada > MORE Te gqodive | | maqnituds oshrle | more naga ve ek 228 has Uodesicabte eyyeek of boosting He loop gain SHEE. to, become CausiA the loop Phase | > null” Dara Bay seed eapeer tor 43 ITC2p nee RH eene USe Day Lai | Shows tha, the gain bandwidth product of two Stage Amplifier orpenshiing.” capasitance appro mated as G B Goin = Gm Ri GmzRe ) Ri Gima Re Ce BW = Gent BA GR 94 RR Gz RCo ry ' \y a ¢Th Problem: Ry | | One RH aero, Prove that, 22.0 -Amp Madaicd COM Tleea Ts Ht 2e80 is ten Himes higher Ge. thon in see fe must Be achieve 60° phase margin, The s@tond po Ploced at least 22 times higher than G 8B Solte 9 The feqwiremunt tor 60° phase margin ig Dm = Pisye — Avg [A GA) Byw Analog, 5% ronal oye DEO igthadee kk ., Monday eT-4Fa Be design GF Op=Amp.: Synchronous Sequential @ Sequentad Cire thie # Ype OF circurt on He past behavior a yy” OF tr ta ashith “oud, Of He Circuit. UIE Os cet ae AE PUP deper * PrésenP input rd A clock ggnat 1 J sed, too, h t Fe cook! Hla ope wukion °K dhe eireuy). GyTypess 4. Moore Type Sequential Circuits + outpuF slepends on on Hu stoke of the eireurt By Malay Type Seq. Cirevike Te oulpuk inputs OF dep phe erccuits, Ae stoke and primary ww Design Problem of Seqvenhal system: Stepi: Draco fi stake diagram appre chee ay spoke. = Fur] Geop 2: Stect@ Table —> {pr Pace ake a aS a | } 1 step 5+ stake Pesignmene Fa in bint B convert. states 19 VG] Raow" | esr ends o boft,osideccution jo Stake Assig nmeat 1-$0me assignnuak may be better th other ONEbor Encoding : sfoules as Ag He vemalain' dent cave fhe eu! expressistia ( Slide) h req isters Connected With Nn- oetes ay SW ov Gperahoan ral “ 1 } if | Pell oT | ede | | wy ree tae 4 bit bus (R,ovr four) | » EB iisl > Piin e iy ov} poe ae | Pie F | ! | | i | “O07 o iz | , Cran) l | + ! a | | ( ivol Cit | “ats ] 7 art iJ= Oo —— ad ) ; } , f i - c h ht \ [ | | , - on | | e ; t WJ ‘ - i Wi fom f | f i | | D/ ih | F a i yf ) | ipl I ts C | | J ! | i | ’ } Se! | 5 ¥ \/ ; ; 7 } : ; ! ‘ | : j ] ; i : j } } 1 I i I rt f nent nd c } j eal ) WV prt i rh Ay hea} } ; , 1c \ | 7 F ; \* 1 ol ‘cag | | | / t yes } f | : | ) ‘ WLP 1) 4 (7 mee ; / f i. ‘ | ay : , Oy WRVICR OF JN purs 4 OUsPul : | a) i 4 ) , ‘ey / i | OP F Ba ! e ey | tid ne tebe DIAG ray : ( gO! @Gligg ~ F I | J Ces ’ d ; 7 z 4 pu 2 : 4 « sVéril0G—> Melay type ta A serial Adder Exam! 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