OXFORD See DIGITAL ELECTRONICS : — 1 a iene KHARATE |Principal Matoshri College of Engineering and Research Centre NashikOXFORD other countries Published in india by Oxtord University Pree YMCA Library Building, 1 Jai Singh Road, New Delhi 10001 Indi © Oxford University Press 2010 ‘The moral rights of the author have been asserted First Edition published in 2010 Seventh impression 2013 Allrights reserved. No par of this publication may be reproduce, sored a retrieval stem, or transmitted, in any form or by any means win Briorpermision in writing of Oxford University Pres, or as expreninng sg by law by licence or under terms agreed with the appropriate eprooen rights organization, Enquiries concerning reproduction outside the sore ne above shouldbe sent tothe Rights Department, Oxford University recs sears address above You must not circulate this work in any other form and you must impose this same condition on any acquirer ISBN-13: 978-0-19-806183-0 ISBN-10; 0-19-806183-8 ‘Typeset in Times Roman by Pee-Gee Graphics, New Delhi Printed in India by Raj Kamal Electric Press, Kundli, Haryana Mrs Bl To my beloved parents hagirathi and Mr Kashiram KharacPREFACE 1 techniques and syst tremendous power and wefulnes of ital ncante aan vrei of applications inte areas Findus mache" cOmPUETS een com andhousehod appliances, among others. The areas whete digital aera jcscanbe applied are increasing ata fast pace. Several cial pa te ,ement skills, entrepreneurial arcmnering ails, cost advantage, project manag crea and ong customer relationships have made Iniathe prefered destination sanaraming electronics industry. This has allowed the individuals involved in ‘ero showease thei alent and meet the curent demands of the consumers sas indates. Alles actorshaveresltedin the growing interest among students and faculty members of this subject. ‘Developments inthe integrated circuits (IC) technology have made it possible tofabricate complex digital circuits such as microprocessors, memories, complex programmable logic devices (CPLDs), and field programmable gate arrays (FPGAs). The emergence of various programmable logic devices has resulted in significant changes in the design methodologies of digital systems. Therefore, itis essential to have a strong foundation of the basic digital techniques for making, effective use of automation in digital design. About the Book ‘Thisbookissuitable foracourse in digital electronics and logicdesign in undergraduate ‘engineering disciplines such as electrical, electronics, instrumentation, telecommunication, computer science, and information technology. The last four ‘chapters of the book will also be useful for postgraduate engineering students pursuing ‘courses in electronics and computer science as alsoto postgraduate students of physics specializing in electronics. ‘The book presents the basic theory of switching circuits and their applications, ‘The availability of various digital functions in ICs has changed the teaching of digital electronics from the good old approach of using discrete devices to anew approach of using modern digital ICs. This book adopts the new approach. The {exthas been systematically organized and the presentation has been kept at a level appropriate for students with the basic knowledge of circuit theory and digital electronics. _ Since the study of Boolean algebra helps in analysing and synthesizing switching circuits, a complete chapter is dedicated to Boolean algebra. Separate chapters on ‘asynchronous and synchronous circuits and K-maps have also been included.ee hillutrations and solved examples Thetextis interspersed with ll vl fran Content and Structure ed into 1Ochapters. A brief descriptioy diode transistor logic (DTL), modified diode-transistor logic, transistor-transi ‘ ed logic, integrated injection logic (121) Nag eestor cl ctailed study of different aumber systems, thing Chapter 2 includes the detailed study of > i conversion, binary arithmetic codes, eor detecting codes, and error comecting cae Clap 3 udes Bocca lebra, DeMorga's theorems, simplification Bolen expression by algebraic method, Karmaugh map metho, and gn MeCluskey method. Chapter 4 ls with combinational logic design using MSI circus, which g impr fr the dein of digital systems considering the simplicity in des cost, space, power requirement, speed, and other factors ‘ater inte he basi builing blocks of sequemal ruts including ip. TePconversons application of flip-flops, shift registers and ther application, Us chapter also discusses the analysis and design of synchronous sequentel ciruit Chapter 6 iscuses the analysis and design of asynchronous sequential circuits Chapter 7 discusses various ways of representing the control sections and data ‘cations of hardware algorithms. The chapter includes the use of algorithmic state machine (ASM) charts, register ‘wansfer language (RTL), and covers the hardware ‘description language, VHDL, ae ‘Programmable logic arrays (PLA), programmable array logic a ). generic aray logic (GAL), ‘complex programmable logic device (CPLD), ariemable gate amays (FPGAs), Xilinx XC 9500 CPLD family, and 4 fic imegrted circuits (ASIC), ‘hapter 9 ex, é Pains the mos common A/D and D/A conversion techniques. Chapter 1 Hapler 10 presents the Sindy of memory organization. and operations, classification, : EEPROM, stink Wo memories—RAM, ROM, EPROM, vite astra g this project. First ivi aceite mary il wn ed ne rings oe Fu and Pujn-tom vom Lrcsved cx ascaragecst mt ODDS nega ce for this endeavour and no ‘Ther fovingandcring ait hasbeen the driving free forth ende tude to Dr (Mrs) words of gratitude are enough. Ialso express my deep sense of gratitude to Dr( Saree oe : Ss ment, and undying enthusiasm throughout this project. I wish to specially thank ¢ with my research thank Po D:D. Dighe and MrH.D, Deshpande who helped me with Spel ato my prasad ther fox hk wooo e c riends, relatives, and colleagues love and support. Thanks are also due to all my friends, ees for their suppor. Finally, I thank the editorial team at Oxford University Press, Delhi, for their cooperati Dr G. K. KharateCONTENTS Chapter 1: LOGIC FAMILIES 1 1.1 Introduction 1 1.2 Logic Families 2 1.3 TransistorasSwiteh 3 AA Characteristics of Digital ICs 4 | _1S Resistor-Transistor Logic (RTL) 8 ~ L6 Direct Coupled Transistor Logic (DCTL) 9 “1.7 Diode-Transistor Logic (DTL) 17 poeee ~1.8 Modified Diode-Transistor Logic 12 a ~1.9 Transistor-Transistor Logic (TTL) 13 1.10 TTL Parameters 23 kA vsleie ae 1.11 Commonly Used ICs of Standard TTL 26000 1.12 Improved TTL Series 27000 1.13 Comparison of TTL Families 290 1.14 Emitter Coupled Logic Lis28 Arithmetic Overflow 91 Flop 306 BP ais 5.8 Characteristics of Flip-Flop 3 ce 5.9 Flip-Flop Conversions 307 c : SRA LOGIC GAT 5.10 Applications of Flip-Flops 32 chapter: BOOLEAN ALGEBRA Al a ie SOE Ca aaa 5.11 Registersand Shift Registers 427 tof Shih egiter 24 12 Basen Alghen129 512 Aplin of Shi 5 5.15 SynchronousCounter 355 5 Standard Representation foe Logical Functions : priveril oped i 5.16 Flip-Hlop Excitation Table 335 chat 5:17 Synchronous Counter Design 358 27 Sri seed Ho 31 eae ira os teem 5.19 Clocked Sequential Circuit 369 so ou ee ee $5.20 Analysis of Clocked Sequential Cieuit 371 eee .21 Design of Clocked Sequential Circuit 375. 3.11 Five- and Six-variables K-map 87 : a a 5.22 Lockout Condition 398 3.12 Quine-MeCluskeyMethod 185 iS At Rea Chapter 4: COMBINATIONAL LOGIC CIRCUITS 198 Oe ee 4.1 Introduction 198 Chapter 6: ASYNCHRONOUS SEQUENTIAL CIRCUITS 431 42 Design Procedure for Combinational Logic Circuit 199 6.1 Introduction 437 6.2. Fundamental Mode Asynchronous Sequential Circuits 432 6.3 Pulse Mode Asynchronous Sequential Circuits 440 6.4 Incompletely Specified State Machines 447 6.5 Problems in Asynchronous Cireuits 449 6.6 Design of Hazard-free Switching Circuits 452 43 Adders 202 44 Subtractor 211 45 BCD Adder 219 4.6 BCD Subtractor 220 4.7 Arithmetic Logie Unit 226 4.8 Comparator 229 49 Parity Generator 233 4.10 Patty Checker 235 4.11 Parity Generator/Checker (74180) 239 4.12 Multiplexer 247 413 Demultiplerer 257 4.14 CodeConverters 264 4.15 PIN Diagrams of ICs 286 Chapter 5: SEQUENTIAL LOGIC CIRCUITS ‘5.1 Introduction 293 5.2 I-bitMemory Cell 294 53 Clocked$-R Flip-Flop 297Chapter 9; Chapter 10: Index 86 Complex Progr 8.7 Field Program . 1b 8.8 Application Specig, AMD AND D/A CONVERT, 9.1 Introduction sy 9.2 9.3. Basie Principte 9.4 DACand aDCIe, 9.5 ADCO809 (8.pit ADC) 6599 9-6 ADC-7109 (12-bit by 9.7 DAC 0808 (8. it Dac)” AO. on Locic Fami.ies SEMICONDUCTOR yy 10.1 Introduction 639’ MORY PEVICg, 10.2 Memory Organization 630 val Diagram of Meno, Chapter Out! vreceenmeeecrarre 5 of og arin Bah charac fran Charactoistes of dal Ios ‘+ ATL, DCTL, TTL, ECL loge famios i + OMOS NANO, NOR and invertor 10.6 Characteristics of Memory Devices + Comparison of TTL and CMOS 10.7 Classification of Semiconduety Mend ‘tert Cvs endcosin 10.8 Read and Write Memory 644 C + intoracng of TTL {7a oe tae 10.9 ReadOnly Memory 652 ies "Y 63] 1.1 INTRODUCTION ekcgencemed with te inercomec on among digi Components systemisthey a _ sent , “ smmable LogicDevices 557 46 Complex Pr 7 Field Programmable m Specific ‘Gate Ary Fmepatd Circuits (ASICS) 561 ss Appia |p ANDDIA. CONVERTERS 584 91 ten 3 32 osicPrinipleofDAC 58 33 Basi Principleof ADC 59% 4 DACand ADCICS 495 ADCOSI (8-bit ADC) Be ape-7109 12-bit binary ADC) 61! 9.7 DACOSOR bit DAC). 626 Chapter 08 630 caper: SEMICONDUCTOR MEMORY DEVIC Tout Iniroduction 630 10.2 Memory Organization 630 10.3 Functional Diageamof Memory 631 Jot Memory Operations 632 1015 Expanding Memory Size 635 1066 Charactersicsof Memory Devices O47 10.7 Classification of Semiconductor Memories 642 108 Readand Write Memory 644 10.9 ReadOnly Memory 652 Indes i Chapter | — Locic FAMILIES == Chapter Out!ine ‘= Types of logic families + Switching characteristics of + charactors of ait ICs ATL, OCTL, TTL, ECL logic families {+ CMOS NAND, NOR and inverter + Comparison of TTL and CMOS + Interfacing ot TTL to CMOS and CMOS to TTL * inieriacing of TTL to ECL and ECL to TTL + 74X% series data shot nsistor 1.1 INTRODUCTION Digital fogiisconcerned with the interconnection among digital components and ‘modules, The best known example of adigtal system s the general purpose digital computer. Most ofthe digital cireuits are constructed om a single chip, which are refered to as integrated circuits (IC). Integrated eieuits contain a large number ofimerconnectd digital circuits within a single smal package ‘inl scale integration SSI and medium scale integration (MSI devices provide electronic components ina eas varity of forms and each form is referred as a ‘Now-a-days digital integratedcircutsare most i systems ICs ae popular duo eircnomous advanagehaslitetelon. © * Smallinsize rea + Loweost oe Olan pied cone2 _ Distal econ i" + High noise 1 high ity = Hignseod ecudes testy of diferent og ss ude shot of commonly sed eres 7AXX families, interfacing of logic 1.2 LOGIC FAMILIES ‘The setofcompatibe ICs with he sume logic levels and same supply voltages have aa ete eee ee finctons known eso fail. Based Unipolar kg family Inno logical, unipolar devices arth key element. MOSFET (Metal vide Senicontctor eld Eet Transistor is unipolar device in which caren Tvs hecase of only one type of charge ci (hat, either elestons tots). Theexamples oF utpoa ane include PMOS, NMOS, and CMOS. Bipolar logic family Transistors nd diodes ae bipolar devices, in which the current flows because of Jeuhthe charge cares (lecton ado) Inipoa loi fanilies, tasistors an diodes re ased as key clements On the bss of operations of transistor in 1Cs, bipolar oie fun are arr classified as + Swurated bipolar logic families * Unsaturated bipolar logic families ‘ns bipotar ogc fails, transistors operate in saturation region The speed of stud bipolar ogc fails low, easns of which would beisessed inertcoming topics, Examples of strated bipolar ogc fares at * Resitorunsistorlogic * Direct coupe ranssor logic + Integrated injection loge + Dioweansisor logic + High-reshold ogc * Trunistor-ansistor logic 1 Schotthy transstor-transsto logic * miter coupled logic 1.3 TRANSISTOR AS SWITCH _ tana ogic families. It Tranitr isonet si ror sation region. The cto sane lich OFF and saturation refered a8 switch ON. sah waar, which x neta ncolcr neon aren forwaia Stnterjunton sa andvotage across emiter and collector terminals is Vea Teva "08 Vrain waristoran0.3 for german si Theat Viz~0. foralcortanstorand01Vforgemaniontani ae ey bec be taelorin sraon tha the base curent abou! eign tay he colstr erent Ata i > Te clo ucaiar working «Betis Ua sg ‘operates as aswitch. In Sotto eered tas switch inthe eva region, bth eit condition and only reverse erent The saturation region, borne Fig. 1.1 Transistor asa switch ‘When input Ve applied to the transistor is LOW (0 V), the emitter junetion is seers biased, thes curent Mowing through the base terminal andthe cure lowing trough the collectorierninalisreversesaturationeurrent, whichis By applying KVL to the output loop, es Veo =1eRe=Vaa=0 Vou = Vor = toe ay Tn the cut-off region, collector curent Fe Hai a2) Wen the transistor is operating in et : : refered to a8 HIGH (logic 1) off the output i equal to Vee and itis ‘When input Vj that is applied tothe emitter Janson s forwarded caren flowing trvghtnete ie ee i ta sc e-card there isa consi tuput voltage considerable voltage drop across thecollectorresision Ad Vou Veta ) ‘When the transistor is operating itisreferedio asLOW (logic), by the input voltage,Fig. 1.2 Response of transistor switch for square wave input entries ro OFF ON ste he char i state condition. Similarly when it switches from ON to time to each the OFF sate, the excess Turn-ON time Isto time req ges fom low thigh are stored must be removed which takes sometime wired to each the steady stat condition when the input ch tows tett aa) where vis delay time and is time Delay time sthetime equi oe the collec ofthe maximum value of the elector current Ort neither forthe coetor cure tris from 101090 percent ofthe maximum value of the collector current Ft isthe ine equio move the exes care sored near the Junction, when the inpt changes from high to low Yorcurento rise fromOto 1Opereent fone + (sy wheres fll time an is storage time, Storage tine {zie time requited o drop the collector current 1090 percent of regs value of the collector curtent when the npun ‘changes from high to low. Falltime mn ered rope colledorcurent fom S00 deren ‘of the maximum value of the collector curen, 14 CHARACTERISTICS OF DIGITAL Ics et i tin of lyr ple items neni einen "Snares meen ny etre NB epee ep be per aE - sal a * Powers og Faniie + Figure of meri + Fun-out + Fania * Current and voltage parameters + Noise Immunity * Power supply requirements * Operating temperature 1.4.1 Speed of Operation npceiaind apron of ig 1x hae ih 1 ied nt propanol tins Ista seraga the propepulon ay Hi iow sate GW high vat fou. + ton. (1.6) ightotow state, bere asthe ly ime measure, when ouputchanges fom igh ieee ees oe ae ae aa hse The pat nd ouput votage waveforms of age gate ae show Fi 1.3 Input and output votage waveforms of logic gate ret ay limes are measured between 50 percent voltage levels of ‘input and ‘output waveforms crnyeroreeation delay between input and output should be as ‘minimum as Pesibleso tha the operating speed of IC remains high, 1.4.2 Power Dissipation terms of mili Watt mW), 14.3 Figure of Meritital sectonis if sit sa roduc of propagation delay and poy Figure of mei it Joules (ns xmW = pl). POE sored ners of PICO poms Ssipaton ese Parameters rrentand Voltage _ srs defnetbenimum and maxiaum mit of cure Cuenta volar Cae ong nd opt oF gic fail td voltae fring res Tighe! iat age) ste minima inp volage conespondin log ste. 1 don eel pave) este maximum ipotvolage corresponding ty epic tte Ve ih evel cpu volage) iis the minimam ouput voltage corresponding to lope a. Voq(towlevloup votage) isthe maximum ouput voltage comesponding tp logic ste (igh evel ip caret) Ms the minimum input curtentcomresponding to tan denied at cere Xs sit set one trina Macoracontenduatnsset eee Pe Iota tides ars OSHC 1.4.5 Fan-Out Fact ci esg : fee few dive he maximum name of sr = ‘High fan. ‘utis advantageous, because itreduces the need of additional : rive more gates, Consider Fig. 1.4, os Ie Ae drpacat e Logic Families Fou. tox. a7 1.4.6 Fann 5: Fan-in is the number of inputs toa gate. Fora two-inputs gate, fan-in is two; an fora four-inputs gate, fan-in is four. 1.4.7 Noise Immunity Unwanted signals are known as noise, The stray electric and magnetic fields may induce some noise atan input of digital circuit. Because of noise, the input voltage ‘may drop below Vj ormay be aise above Vi, which resultsin undesired operations. ‘The circuit should have the ability to tolerate the noise signal. ‘The noise immunity of digital circuit is defined asthe ability of a digital circuit to tolerate the noise signa. A quantitative measure of noise immunity isknown as noise margin. Logic | state noise margin and Logie O state noise margin can be calculated as: (1.8) as) Vou~ Vin Logie | state noise margin A\ Logic 0 state noise margin AO = Vn, = Vou, 1isimportant that fr logic families, Vy,> Voy and Vi, > Voy as shown in Fig. 1.5. Yu % You in ar npr voltage level Fig. 1.5. Input and output voltage levels Tit gate has Vou = 24 V, Vou. = 04 V, Vi =2 V, and Vi, = 08 V. The tkeLogic Families sawch thatthe ovtput OF 8G; iS in Logie g | See ae cia ae oe i tum current lows etc amt | > When he transistor operates in saturation region, maximum current Paws etme Valent Vw (ig, throushresstor The output voltage Vy= Vena Vera 0-2 foraltcon 2Vq-04 perates cutoff, no current flows through resistor Rcand the output voltage Mei tes 0.8V. When the nose intr Vp =Voo= #5 Vr itis logic | level voltage. ‘ «When oth the inputs ae in logic 0, transistors T and T; operate in cut-off, yw level inpat ofthe 84 re ye. bet po te oe igptleveland the output will intl put willbe unpredcane output of Bey ‘Themaxinum 0 the sini reset hands Vwhchinasis and the output is +Vec, ie. +5 (logic 1). + When any one ofthe inputs is at logic I level, the corresponding transistor ‘operates in saturation, and the output is Vy = 0.2 V (logic 0) aye Va=24- Vat «When to th input a a Tope vel, both the transistors operate in Voaue #24 = Vo saturation and the output is V; = 0.2 V (logic 0). The operation of circuit is Somme in Table (0. ‘heminommbighlevelinpoto te gateis2V, When the noise signalis prea (AV, theinputof gate willbe less than 2V, which transis iggy Table 1.1) Operation of RTL NOR gate (Fig. 1.7) thn 24-2 JP iat state andthe ourpot wll Be unpredictable 5 Ve Vp [Transistor Ty [Transistor Fy 1.4.8 Power Supply Requirements a ee ery etic requires supply voltage to operate. The required su i ri ‘ollag and power bythe C shouldbe as less as possible. aly Logie 0 | Logie 1 Cutoff Saturation Logic 1 | Logic | Saturation Curott oie | topic | Saturation Saturation 1.4.9 Operating Temperature (n the basis of operating temperature range, the application of the ICs will be kidd. The operating temperature isthe range of temperature in which an IC functions propel, Its in order of 55°C to +125°C. The accepted temperature eee Comsicn SLRS Sean neon 70 fo comme annul pions, Selection ofpaicullopc family forapartculer application depends on th Latwlemehot be pean nn emanate Param, Interms of 0 and 1, the above table can be written as in Table 1.1(b).. RESISTOR-TRANSISTOR LOGIC (RTL) RTL consists of resistors and transistors, An RTL, transistors operat eee ‘ Be : SS ae Fig. 1.7 acts as a wo-inputs NOR strain reglonas pe the input volage applied. Figure 1.7 shows the enn a eters “ oma: a listed |. Low noise margin (Typically 0.1 V) 2. Fan-outis poor (Typically ) 3. Propagation delay ishigh: ‘4. High power dissipation (15 ] a ¥ Fig. 18 Twornputs DCTL NOR gate a career both te iapets me inlopicl, hecoesponding wansisor or tansisions ee ers Current hogging problem Figure 1.9 shows DCTL gate driving a three-inputs NOR gate, ki "519 OCT gate diving the theeinputs NOR gate | Initially the input of tan : loi 7, ots ncaa sg 28 and thei esa opie Veg ope cae This | the input of 7 chanpaataey erase } of teva gta ere | ‘Vand 0.78 V, respectively. When the voltage at the outpot of driving gate reaches O.BV, Ty goesin sat ‘The whole current flows through the base of 7% and the transist ‘Once Famages, 73 goes in saturation and will notallow other transistors toenter in saturation, The whole current flows through the base of Ts and it may damage. Similarly ll the transistors ofthe driven circuit are damaged. Itis known as the ‘current hogging problem. 1.7 DIODE-TRANSISTOR LOGIC (DTL) ThecircuitofaDTL consists of diodes and transistors. Figure 1.10shows the circuit ‘of a two-inputs diode-transistor logic NAND gate Fig. 1.10. Twouinputs DTL NAND gate Operation * When the transistor operates in saturation, the, the output voltage Vio)= Verar= « Q2¥.and wen topenes incu heoupuvalige Vena Voce 1S, Fonear ets inputs rein ogc 0, y= Vez =0.2.V, the input diodes are see. volage at point xs Va= Vo + Vp =02 + 0.7 =0.9V which at point naar n@ttvethetasistorin saturation because the voltage deseed 2107s Osea tansisor in saturation shouldbe Vasa Vna + Vin 08+-0.7+0.9=2.2V. The transi i oe “ansistoroperatesin cut-off andthe output voltageDigital : ne circuit is summa in of DT Je 124) Operon of Diodes rized in Table 1.2(a), L NAND gat (Fig. 1.10) bl x y sd based | Forward bi ad Tome evra | Reese bated | Cutt Lone || peered Pe vse biased | Forward biased | Cutoft | Logic + | | 1 | Logic 0 | Reverse ss tage e biased | Saturation | Logie » | Interns of 0 and |, Table 12a) can be written asin Table 1.2(b), {able 1.26) Operation of OTL NAND gate (Fig. 1.10) A B s | 0 0 7 | lPesgr 1 1 ° 1 eS Lo OO ‘Thecircuitshown in Fig |.10 acts as atwo-input NAND gate and Tablel.2(b) shows the truth table of NAND gate. Following are the advantages and disadvantages of DTL over RTL. Advantages 1. Fan-utis high 2. Power dissipation is 8-12 mW. 3. Noise immunity is good. Disadvantages 1, More elements are required, 2 Popsetion lay ismore(ypically30ns)andhence the speed of operation isles, 8 MODIFIED DIODE-TRANSISTOR LO‘ More fan-out gates are ‘safmetion ofsourcec ‘hecurent supply ofthe Preferred for most of the applications, Fan-out of the gate urent. The fan-out of alogic gate is increased by increasing # gate (souree current), When the base current of a transistor Logi Famties_ SS 1.11 Modified diode transistor logic 9 TRANSISTOR-TRANSISTOR LOGIC (ITL) Transistor-ransistorlogicis one of the popular saturated logic families, Transistor isthe basic element of this logic family, which operates either in cut-off or saturation region. The frst version of TTL is known as the standard TTL. Standard TTLs are available in various forms: 1. TTL with passive pull-up 2. ‘TTL with totem-pole output 3. TTL with open collector output 4, Tristate TTL, 1.9.1 TTL with Passive Pull-Up Figure 1.12 shows two-input TTLNAND gate with passive pull-up. Transistor, ‘has two emitter terminals. These terminals act as the inputs of the gate, thats, input ‘Aand input B. The input voltages are logic Oorlogic 1, where logic O corresponds to 0.2.V and logic 1 corresponds 1045 V. Veo=+5V tee Fig, 112 Twovinput TTL NAND gateAan. arein on 0, Y= Vera =0.2V, the ee Orne ico + When bot the inputs ( ions of transistor T) a oo 8 o junction is 4 Vgp 0.2407 =09 V. The minimum yon wanton 7 Fin= 10 hat T, and 7; start to conduct, is Vg, SE ra bebe of : isla i so. = 1 VT reed voles gre Va 4 nce Tp and Ta allabe atthe base of 7; and hen are in cutofy she volag avai Pee Lisle ae at varvakage sequal othe supply voltage Vec logic | level cup im gic Ista «ee ay one of the inputs isa logic 0 evel, the Corresponding emi When an oe ormardbiasedandthe voltage a the bas of Tis Vy, jen 107 =09¥. The minimum voltage required at the base of oa cot 7 eit wtoncie, Valen oy + Vat oy + 0.7 = 0.50.54 Brn FA the requted voltages preater than the vollage available ate pacofTandhence Ty and, are incu-off and the output voltage is quad reine sappy volage Voc outpatis in logic | tate + Whonallthe inputs rei ogi state, theemitter junctions of 7) are reverse biased andthe current supply by the sources sufficient operate Ty and, insaturaton andthe oupat isin logic stat ‘The operation ofthe circuit is summarized in Table 1.3(a). Table 1.1a). Operation of TTL NAND gate (Fig. 1.12) Tapas Transistor Ty Transistors | Output aoa Emitter Emitter | T;and T, junction A_| junction B Logic 0 | Togic 0 | Forward biased | Forward biased | Cut-off | Logie 1 Logic 0 | Logic 1 | Forward biased | Reverse biased | Cut-off | Logic 1 Logie | | Logie 0 | Reverse biased | Forward biased | Cut-off | Logie 1 [topic 1] Logic 1 | Reverse biased | Reverse biased | Saturation | Logic 0 | terms of Oand 1, Table 1.3(a) can be written as follows: Table 1300) Operation of TTL NAND gate (Fig. 1.12) Ya Ve % 0 ? ' ° i ip 1 is i Lt iio 0 Thecircuitshown in Fi is given in Table 1.3, Passive pullup ‘When both inputs are capacitorof ded gat change tologie ' |12actsasatwo-input NAND gate andits ruth table biased and 7, towards Voc: ese Tames _ AB Fig. 1.13 TTL with passive pull-up “The capacitor ofthe loaded gate is pulled towards Vec through the passive component Re, and hence the circuit is known as TTL with passive pull-up. In TTL with passive pull-up, the time constant is Re, x Co- The speed of the circuit can be improved by decreasing Ry, which decreases the time constant. By decreasing the value of R¢,, the power dissipation will go up due to the increased collector current of transistor 7. This problem of TTL with passive pull-up is ‘overcome in TTL with active pull-up. 1.9.2 TILwith Totem-Pole Output Figure 1.14 shows the circuit of a two-input TTL NAND gate with totem-pole ‘output, It is possible in TTL to improve the speed of operation by reducing the time constant without increasing power dissipation with the help of active pull- up. TTL with active pull-up is known as TTL with totem-pole output, Voo= 45a ———— is Vor m* Vi NS i cis greater han the voltage available ye gro? 5V. The required voltage is 21 ie availabe ay Yee (loge 1 level), output sink supply voltage Voc (lo r torreon becuent sappy he source Voc OU Reise tt ‘Tyand Ty sat t0 cond I state. Singg 0 to operate in saturation « When any one ofthe inpts is at logic O eve, the corresponding em juntion of, is forward biased andthe voltage atthe base of 74 et Vjp + Vgq=0.2+-0.7= 0.9V. The minimum voltage required at he so that and Ty start to conduct is Vatu in + Vat in + Oop ed vollgeis renter than the volageavaige and, tein et off andthe output vane of sngea7= tv. The re sete tue of, eat he isaqualto te suplyvliage Vee (ope level output inlay Since Tis ineut-of region, the current supply by the source Vee thrones = Simnde rexbeia go aoe detested nae hinedanbecueatupry bythe souls siento operas Tea insaturation and the output is logic O state Since T3 is in saturation region the voltage atthe collector of 7, is ow and T, operates in cut-off. The operation ofthe circuit is summarized in Table 1.4(a) Table 1.4) Operation of TTL NAND gate (Fig, 1.14) i Transitory [Pranttors] Transistor] apa | 4 ] B Emitter | Emiuer | T;andT,| 1, Junction A | junction B [Levco Lsico| Forward | Forward | Curoft sam fost] Roce | Sis ace toric of togic1 | Forma | cu vere | Cutott [Saturation {Logie a Pied fast a ox Lge 0 Rene | Foon | Cutot fsutuaion [Logi viased viasec : [tees fener Ase |e aa a Ll biased biased Se Interms of terms of and 1 Table (a) can be writen asin Table 1.4(b), Table 1b) Operation of TTL NAND gate (Fig. 1.14) Logic Famies _ 972 Active pullup When both the inputs are high, T3 oper nd T, operates in cut-off. The current provided by the load is sinke of the loaded gate is charged up 10 Versa logic 0, the corresponding goes into cut-off and, rates in saturation region, Vo bby Ts the capacitor ‘When one or more than one input changes to emitter junetion or junctions of 7 are forward biased. 7 {isin saturation and the diode D is forward biased. The eapacitor ofthe loaded gate starts charge towards Vcc through Ty and Dy as shown in Fig. 1.15 The capacitor of the loaded gate is pulled towards Voc through the active components [and D,. Hence the cireuitis known as TTL with active pull-up. In totem-pole output, Tact as an emitter follower. The outputimpedance of emitter follower is low. This means that the output voltage can change quickly from low state to high state. ‘When the output changes from high o low, Ts operates in saturation and the capacitor of the loaded gate discharges quickly through 7. Due to the current spike problem, wired-AND connection must not be used for totem-pole output circuits, as discussed in the next section. phcc = +SV, Voy = Vnesau + VoraLogie Families ee senceofa dod, the voltage required atthe base of 7, sy Intheabse that aan, conducts ota) ‘ 02405=07V 2 Teagan of 7 seater a he og rug and 7 rein saturation. To avoid ths situation, dag hence both T; and 7, ti D, #8 Used in ye Iermenfaie eons ind atc OT, ean toconduct, is ¥a,=Voo* Vo+ Vita cay aa ucla Fig. 1.17. Two:input modified TTL NAND Thevolagavalsble atthe base of 7; isesthan he Voltage required and ce J 7 isoperatng in cut-off. aan ae ‘The circuit ofa modified TTL. with aclamping diode at input is shown in Fig. 1.18. ghecn1V Sink current Uishecurensuplidby the load. Figure I. 16shows atwo-input modified: NAND gate driving a similar gate a When both the inputs ar in logic 1 state, 7; operates in saturation and Tag Cutoff. The output of the driver gate is logic 0 (Vo 0.2.V), the emitter junction of wansistor Tot the loaded gate becomes forward biased and the ‘current supply J = : ¢ z z z Fig. 1.18 Modified TTL with clamping diode at input Clamping diodes are commonly used in TTL to suppress the ringing caused because ofthe fast transition found in TTL. Atnormal input signal, the diodes are reverse biased forhighas wells low voltages, When transition occurs, the reactive component associated with the load causes ringing as shown in Fig, 1.19.a ee 20 Disita Electronics Les transistor may be damaged. The oes) connected the np orga, for negative spike and mits the voltage up to -0.7 V and protects ey eB anise 1.9.3 Wired-AND Connection Ar AND cometon has wo or mor thntivo gates connected pee, 4 wired-AND connection, the fami of the circuits increase er Using i>, 2 }—se 11>) T CP 5 4 Fig. 1.20. Wired-AND connection ‘Here the outputs of two NAND gates are connected together. =h¥, Y= 4B Hence ¥ = AB.@D Using De-Morgan’s theorem, Y= ABCD ‘ant Wied-AND connection i not possible in TTL with totem-pole output Thy fat diagram of wired-AND connection for TTL with totem-pole cup shown in Fig. 1.21 F121 Wited-AND connection for TTL with totem-pole ‘output aa the cutpt of gate is high and gate, is ow, then T, of gate; operates in Of gate; pense Ptses it saturation, 7; of gate, operates in saturation and Ty 2 Tsofgae ut load current and the current supplied by Voc of 2 fow though mst nt be ne eg? Tscanbe burnt out, Hence, wed: AND connection i i a Logic Famites (21 is overcome in TTL with open collector output. Figure ‘TTL NAND gate with open collector output 1.22 shows the cireuitofa emia Fig. 1.22 TTL NAND gate with open collector output The collector tenminal of 7; savailable outside the IC where the external resistor is to be connected. The circuit acts as a TTL with passive pull-up and hence the advantages of active pull-up cannot be achieved in the circuit but wired-AND connections possible. 1.9.5 Unconnected Inputs of TTL ‘The input circuit of a TTL is shown in Fig. 1.23. ‘When the inputisin logic state, theemitter junction is forward biased and the current flows through the junction. When the inputs se inlogic | state, theemitterjunctionisreversed a biased and the current cannot flow through the junction. If any one of the inputs of the ‘TTL gate is open, then the corresponding 2 “ Junction cannot be forward biased, and the currentcannot flow. The input acts exactly in thessame way, asin case when logic lis applied to that input. Therefore in TTL ICs, all ‘unconnected inputs are treated as logical 1s, Fig. 1.23 Input circuit of TTL 1.9.6 Tri-state TTL in high state or low state. Ifthe o high state. The tri-state TTL hi impedance,aati sin high-impedance state, i ° When the output i a tee 33) (0 High wpedance [ves ish fig. 1.24. Tristate logic state inverter Frecnnt ofa st TL inverter isshowa in Fi. 125 The citi. Fig. 1.25. Tristate TH inverter ‘The estate TTL inverter aswo inpus—normal input A and enable input * When te cableiapu is High, the comesponding emitter junction of {teres biased and the circuit operate asa nomal inverter as explained below input, the diode Dai flows through the outputs ini Logie The logic symbols forthe active high and active low enable input inverters are shown in Figs 1.26(a) and (b), respectively (ae Yet Ss = > ly joes zeo——] Eo. Fi. 1.26" Enable inp inven () Active low enable input Application of tristate logic ‘Tri-state buffers play an important role in computer systems. In ease of 8085 microprocessor all the buses are in tri-state whenever the 8085 isin reset mode. Figure 1.27 shows the common bus connected t four output devices, where A, 5, Cand D are the enabled inputs of tri-state buffer. Data present over the bus is Evento the device a per the enabled input signal ofthe tri-state buffer The enabled signal of the input device is active low : 1. isenabled and others are disaby borate veikeieis piven todevice wen ao ceoet vento denna and thes ae disabled, andthe ee pee OS C= LD: sive todevice2.Whend =1,B= 1, Ccorn ay Gable andthe data presentovertheliens, =1.C=1,D=0, butter Disena over the lini givento device 4 eSDigital Beetonicg EDs neti En jof operation i pape anit tems of Dopagation dla sped f oe ra the prepaon ely tne 18.5 15429 stn = Smt n= 7218, tent, = 9222 2 18 5g Power dissipation sf the wastage of powering isi Hsould 3 minimum fost Fora Sandard TTL power dispation 19 mW. ma Current and voltage parameters Via: Its the minimum input voltage to be recognized 28 logic I state, Viz # Its the maximam input voltage to be recognized as logic 0 state, Vou: Itis the minimum output voltage corresponding to logic 1 state Vou. : Its the maximum output voltage corresponding to logic 0 state For a standard TTL family: Vin=2V, Vou=24V, Vi 8V, and Vo =04V sy eS av, 24 | Mu losv You—$—oav k ot ov Input vote eae Fig, 1.28 Voltage range for TTL Fig. 1.29(@) TTL sinking the current from n gates ‘When the outputof the driver gateishigh, 7, acts as a current souree tothe load as shown in Fig, 1.29(b). Ifn similar gates are connected at the output, then the ‘ota source current must be equal to times the input current Iya, where ni the fan-out of TTL. Jou = hy i n= fo. M0UA _ 19 bee tu 40UA 1jit cits imu is iy ofa its ability t0 tolerate @ noise signg mown as the noise margin, SLA ae margin (AO) = Vi. Vou sass SS. (a=08V-04V-=0.4V ature range voltage a rer he examples of standard TTL logic fail The series andthe 54 seis Tresesries pero POne™ St Zoos vk ell ove trae erie range 445 10455¥. “The 4srescan od the Series can workover emperatr Summary of standard TTL sappy voltage of+5V. But its found that they W.75V to +5.25V and the 54 series operas elaly over empeature range of °C t0 70°C, while nperature range of - 55°C to +125°C. “able 1 summarize the typical values of standard TTL parameters, Table 15 Typical values for standard TTL parameters (harctertis 7 series ‘Supply voluge | 475V 0525 V ew IC | Tepe ne | vse Coma] | | Pome sition | Pronaation dey Frat Noise margin 45V0S5V = S5°C to 125°C Vin = 2 V. Von Yu" 08, Vou y= 40 WA, fon = 400 wa 54 series 6mA, fo, = 16 mA 10mw 10ns 10 04 | Logic Families 27 Table 16 Cormeniy use I of sandr TL Te naib] —_‘Desrinnon [IC umber] Deseripion | Tait Tipe Sinpts AND pts | 7400, Ges 2ops NANG en J too [nat inp NOR ses | 7420 | Dus apts NAND st oe eee ee 7404 7408 | Quad 2-inputs AND gates | 7432 | Quad 2-inputs OR gates 7410 _| Triple inputs NAND gates} 7486 1.12 IMPROVED TTL SERIES TTL S4seres74 eres arth most popular and commonly used series of digital ICs These series have the limitation of speed and power dissipation. These limitations are overcome upto a certain limit inthe improved TT. series. The improved TT. series areas follows: 1. 74L series ow power TTL) 2, 74H series high speed TTL) 3. 148 series (Scot TTL) 4. HLS series (low-power Schottey TTL) 5. T4AS series (advanced Schotky TTL) 6. 74ALS series (advanced low power Schottky TTL) 7. TAF setes (fast TTL) 1.12.1 Low Power and High Speed TTL ‘The 74L series were develDigital Electrons is obtained by using « Schottky barrier diag, > Logie Families 9261) The Schothy transis nals of the transistor as shown in F Me sae he collector trina shown in Fig. agg," ae ee ove asa forward based voltage ef 025 Becauseofiy FAMILIES thease andthe collector terminal ofthe transistor, the cope ‘A comparison of TT anlieswithrespectto their common characteristicsisziven Reese not get forward biased and the transistor never Ja amor opeaesincu-ooractverezion. The symbol gr 88 Table tannors shown nF. 130 a Table. 1.7 Comparison of TTL families [Character- | 74 74LS 745 | 74ALS| 74AS| 74F 2 te istics fete, Meciane| “208 | 208 | 208 | 208 | 208 | 208 a Mia Jon | -0ris | -oan6 | 1720 | -oane | -200 | -120 i Nowy | soe) soi) | 20 02) | 0212) | 201-06 | Tyas) 10 3 4 1s 25 e PD. per gate| 10 20 1 20 4 » & F130 Scho transitor and Schoty symbol The 748 sts isan example of Schothy TTL. The propagation delsyqy | 4,44 EMITTER COUPLED LOGIC Schothy TTL is 3 ns only, which is twice as fast asthe 74H series. Figure 1 showsa basic NAND gate in Schottky TTL series. Emitter coupled logic (&CL) is faster than TTL family. The transistors of an emitter ‘coupled logic are operated in cut-off or active region, it never goes in saturation and therefore the storage time is eliminated. Emitter coupled logic family is an example of unsaturated logic family. Figure 1.32 shows the circuit of an emitter= ‘coupled logic OR/NOR gate, Veo=45V Fie. 131 Schottky TTLNAND gate | 1.123 Low Power Schottky TTL | ‘The TALS series is low power: iio, btcsa eet Scot assis stor values ale of chasing resistor than reuit power: Voo=-SV Fig. 1.32 Emiter coupled logic OR/NOR gate delay. The 74.8 The circuit consists of diffe ference amplifiers and emitter | i terminals of the two transistors ge d i cle oe Spe ea eee tiene i eli DC level, The circuit has tw Fee ce MLE TE reduce theDigital ectronics__ = Operation ? The input voltage of Tis Vo= Vee ; he input volta in logic 0, 7, and 7% operate in cup tosic0. ie Va, slow, Ts operates in cut-off and Y> is logic 0, voltage Yon and 7, operates in cut-off, voltage Vo, is low, 7; operates in cut-off ang io ishigh, 7, operates in ativeregion and ¥, sj is logic, voltage V, The operation ofthe circuit is summarized in Table 1.8(a), Table 1.8{a) Operation of ECL circuit [Inputs Transistors | Transistors | Oupay>—~ [a eer tats eee Active [Active [Cutoff] Logic Of Loney [toxic o| Logic| cucot] Acuve [Cutt |Cu-otf[Active [Logi Loge Loic Losi 0 Active [Cutt | cutoff [Cu-ott Active [Lope 1) taped [oie 1| active | active [Cutoff [Cucort| active [Loci 4 Lad |teec 0] Logic 0 | Cu-otf|cuo h [tote 1 Interms of and 1, Table L.8@) can be writen asin Table 1.8(6) Table 10) Opeaton of cet Eman | | o O° cease a 4 (OR) i ‘i i a Nor) 1 OC ate iaen I 1 | 0] Fig. 1.33 symbol of OR/INOR gate [ee Jo ut shown in Fig 1.32 acts asa twosinput OR/NOR gate and is uh saa givenin Table 1.8(0). The symbol ofemitter coupled logic OR/NOR gat: is shown in Fig. 1.33, Wired-OR logic Te EL sais wo cup a tt an ase conned ten an atonal loi eli oa alonal hardware. Consider the circuit shown in Fig. is the output of OR logic and Yas A+ B). When the outputs of two ee is realized without Fig. 1.34 Wired-OR logic A¥B+C+D Wa¥+ %=%,+¥ =A+B+O4D Consider another circuit shown in Fig. 1.35 ¥ com nets % Fig. 1.35 Wired-OR logic Y=} +%; =A+B+C4D ¥s=%+¥y=A+B+C+D (sy Unconnected inputs {Tany one ofthe inputs of the ECL gate is open, then the corresponding transistor Gperates in cutoff and there is no current flow through the transistor. The same condition occurs when the inpu ogic O level and hence the unconnected input of ECL is treated as logic 0. ECL characteristicsy fa ——————_—- 5, Fan-outis 25 Logie Families (33) 1.15 INTEGRATED INJECTION LOGIC (Pr 1.15.1 PLinverter Figuee 1.36 shows a simple inverter circuit If the input V, ig transistor T is ff and Jy, =O The input source at 5 sink forthe current supplied bythe em uiput terminals 10% foi Fig. 1.38 /'L inverter circuit with two output ITTENE Soup Pi IND Gate andthe ouputsat high logic evel Ihe inputs high the base cure 1.15.2 PLNAt Ma ss Figure 1.39 shows the FLNAND gate. When inputs A and B are low or any one ASTER 7 aaa egal ottcinputsis ow, tc caren provided by Fssinked the our Ty OF tndinoupatisigh When othe inpusare high te bse caren athe smofcorens provided te sours tnd Fy wast ON an the bape is low v Table 1.9 Truth Table of NOR gate [—Taputs Dusit [-a B ¥ rag 0 1 Fig. 1.36 PL inverter with current source o I 1 7 1 A 1 can Ett 137 shows a simple inverter circuit with transistor 7; as the const 1 1 Mu ‘Simsot source, henee isin series asa constant current source, comma fetes. When both or anyone ofthe inputs is high, the output of the ‘oresponding inverters low and the resulting outputis low, When both inputs are | low, the output of both, the inverters is | high and the result is also high ” Table 1.10 Truth te zi F137 PL overe vas Sl RS _ i with transistor as, ‘Current source z ue the ipso, tp Ass] soa ease 4 7 ‘si stints high teas Cent and Ts and he out re re Ni mu : “ra aly eso ph ; ON oT isthe sum of currents 1; and Osler fe ; 38m ad the ouput is low. 1} xh eal ude ae i Fou other roan pl terminals, Transsi 5 salon i gy 7 : rectly tothe inputs! on Fig. 1.40 PL NOR gateDigital Hlectronics_ Le % 14g MOseeTLOGIC_ 4 ue to their low power dis, 7 ar very popular due 1 nna Fa 105. di) NMOS, and (i) CMOS. ‘three designs Mtl 1.17 NMOS etter Te. aa crelyrdame enccnen MOSER nem SMS 1.17.1 NMOS Inverter Figur 4 shows the circuit of an NMOS inverter consisting ana MOSFETS. When te drain and gate terminals of MOSFETs then tats asa resistor InFig. 141, MOSFET Q, acts as a load resistor switching element. Q; is always ON; the load resist channel MOSFET. Instead ofload resistance, Q, isu the chip. Q; may be of depletion type or enhancer. ‘enhancement type Operation * When the input si Te shore ind MOSREr gyal ance is equal to Roy ofa ed, which reduces en pe. But Qs sat =a ; ignal is high (positive (J, posse), Osis ON, the current flows through Lo re, | * When the input signals low (OV or negat ornegative Yollage), Q3 is OFF, there is no current flow (qoweh the circuit and the output is high ie op). The operation ofthe bg jcuitissummarized in Table Fig. 1.41 NMOS invete nate of 0 and 2, we ean wees Table 1.11(b). The circuit in Fj 3. 1.41 ik Bivenin Tale Liga nA acts as a NOT gare and its rth a Table 1.11 @) Operation of NMOS inverter leh Table 1.11 (b) Operation of NMOS inverter Raa Logic Families 95 sre molled by thet and BO ny be of depletion ype orenkancement Pe, put Qz and Qs are always en! oe 3 ih po! «When sry ons of tho inputs Jaw (OV ‘or negative), then the corresponding «When inpus ae high ve voltage), Qs and Qs a6 ON. The eu rood otra al ad ae cena Fig. 1.42 A two-input NAND fate using NMOS The operation ofthe circuit is summarized in Table 1.12(a). Table 1.12(@) Operation of NMOS NAND gate a ae ee se A Low | tow | OFF | OFF | HIGH tow | HIGH | orF | on | HIGH uch | Low | on | oFF | HIGH nich | mcH | on | on | Low In terms of O and 1, Table 1.12(a) can be written as in Table 1.12(b), Table 1.12(b) Operation of NMOS NAND gate A B Vo 0 0 1 0 1 1 1 0 1 1 i 0 ‘The circutshown in Fig 1.42 acts as two-input NAND gate and ts truth table is given in Table 1.12) 1.17.3. NMOS NOR Gate Figure 1.43 shows a two-input NMOS gate, Qj acts as a toad resistor. Itis always, ON. MOSFETs @> and Qs ae the switching elements, These swit are connected in parallel, which ar controlled by inputs A and B. Insta nd prone sel which rece the sizeof the chip. Qy my be of depletion Rea aera mene Aa " AUT © 2 a NY aoa pea aROperation < ~ When bath he inputs te low, Qs and 2, are OFF. The though the drain terminal andthe ouput is high Vee cag fh * When any one of the inputs is high (0 v . or —Ve), then th MOSFET is ON, The current flows through the cireuhe One, Circuit and the og Py ut * When inputs are high (#ve voltage), Qs and Qsane nt through the drain terminal and the output is iow." ON’ THE curen, Tre operation ofthe circuits summarized in Table 1.13¢, Table 1.13(a) NMOS NOR gate ASE See Low | Low | org | OFF Low | iicH | or | on HIGH} Low | on | op: mic] mc | on | on In terms of 0 and 1, Table 1.13(a) can be wr ritten as in Table 1.13(, Table 1.13(6) NMOS NOR gate ees Sorcha, a B ioe 0 0 1 0 1 0 1 0 0 t 1 1 0 } The circuit shown in Fig, 1 -43 acts as a two-inputs NAND gate and its truth table is given in Table 1.13(b), Yon 2 % oe ah el Fig. 1.43 NMOS NOR ‘gate 1.17.4 Fan-out Logic Families 137) 1.17.5 Propagation Delay Time : oe Itisa function ofthe capacitor of fed ata te carsing esi I of MOS devices, C capacitor is presenta input and output an the resistor togh whic he capctr gets charged or icharge ils igh Hence rropagaton dely is fargeand the sped of operation is 1. 1.17.6 Power Dissipation ae jncton of caren supply bythe sours and resistance fhe loud, The power aipoly bythe source in MOS osc familys smal nd hence the power disp 1.17.7 Characteristics of NMOS Table 1.14 summarizes the characteristics of NMOS. Table 1.14 Characteristics of NMOS Parameter | Value | Parameter | Value | Parameter | Value Ya | 20. ey 400 WA, Tal 60 ns. yy | osv ce. 2mA ne 45 ns Vox =| 24V | Fan-out 20 PD. 1 mw Vo. _[.0.45-V | Noise margin | 1.5 V 1.18 CMOS (CMOS family uses n-channel andp-channel MOSFETs. In CMOS, p-channel and ‘channel MOS devices are fabricated on the same chip, which makes its fabrication ‘complicated butt reduces the packaging density, and has small power consumption, Hence, CMOS is ideally suited for battery-operated systems. 1.18.1 CMOS Inverter Figure 1.44 shows a CMOS logic inverter, For the circuit, the logic levels are 0 V and Voc. Itis RS important to note that the p-channel MOSFET. a Dy is ON, when the input is 0 V and the n-channel 1 in MOSFET is ON, when the input is Voc. Q, is p- Eas channeland Qzisn-channel, When Q,isON,the 4 —_| o ‘output voltage is equal to Veg and when Q5 is ON, the output voltage is equal to 0V. Frere, ee fea 1 Operation rs * When the inputis tow, is ON and Q, is ; + OFF, output is high, Lhe * When the inputishigh,Q;isOFFandQ, "#8 144 CMOS invert is ON, output is tow. ,38 Dioital ectronics Table 1.15 shows the operation of CMOS inverter. 4 Table 1.15 Operation of CMOS inverter 1.18.2 CMOS NAND Gate Figure 1.45 shows a two-inputs CMOS logic NAND channel and two n-channel M Parallel and n-channel MOS} ‘channel Mos Fig. 145 CMOS NAND gate Operation * When the inputs are low, Q; and Q, are ON, Q3 and Q, are OFF, and the output is high (Vpp), * When any one ofthe inputs is low (OV or ve), then the corresponding MOSFET Q, or Q2is ON, Q;0F Qs ON, and the output is high, * When the inputs are high (+ve voltage), Q, and Q, are OFF, Qyand Q,are ON, and the output is low. ‘The operation ofthe circuit is summarized in Table 1.16, Table 1.16 Operations of CMOS NAND gate aEEaSSSsSsc_xcxc“™“ i} OS NOR Gate sists of wo p-channel is au 1o-inputs CMOS log NOR Bat rae and Ee SSR ma ose ommestedinllng ind two n-channel en Here, Q; and Q2 * connected in series. is low, p> sine ee pies die e a a Noster aes Ya Le Oe METS OPE high, p-channel is OFF and n-channel is ON. Wee 9%, o Fig. 146 CMOS NOR gate Operation * When inputs are low, Q, and Q, are ON, Q3 and Q, are OFF, and the output ishigh (Vpp). * When any one of the inputs is low (0 V or ~ve), then the corresponding MOSFET Q, or Q3is ON, Qs or Quis ON, and the outputs low. * When inputs are high C+ve voltage), Q, and Qs are OFF, Q, and Q, are ON, and the output is low. Table 1.17 Operations of CMOS NOR gate 22 oS Tan ae 1.18.4 Characteristics of CMOS ‘The S4CI74C seties isthe c characteristies of S4C/74C CMOS i il ven it L ee ogic family are given in Table 1.18 fora supplyWO Digital Electronics Table 1.18. Electrical characteristics of SAC/7AC CMOS logic fy Parameter | Value | Parameter | Value a Von 35V) Tn ThA joa 13 he “1A 100 pA | Ye 45V fe ¥ 7 osv | & 360 yA (ana Operation speed of a logic family is defined i terms ofits propagation delay 1, The spes propagation delay, fu. * fou 2 60ns +45 ns 2.5 ns Noise margin Itis the capability ofa gate to tolerate noise. Logic | level noise margin = Von — Vins 5V-35V=1V al Logic 0 level noise margin = Vj, = Voy. 40=15V-05V=1V Farrout MOS devices have a very high input impedance; therefore, the fan-out is large Fan-out of a CMOS is 50 for low frequency and less than 50 for high frequency | inputs | erate | Itisa function of current supply by the source. The current drawn from the supply _ in CMOS logicisless, Hence the power consumption in MOS circuitis ess. over dissipation for CMOS logic family is 1 mW at 1 MHz. Itis less than 1 mW for frequencies less than 1 MHz. Unused inputs ‘The IC of a logic family may have more than one gate. CMOS inputs have tobe Connected with a fixed voltage level orto another input. If inputs of unused CMOS ules are open, they are susceptible to noise and static charge that could bias both and n-channel MOSFETs in the conductive state and power dissipation is increased: 1.18.5 Buffered and Unbuffered Gates (CMOS circuits are available intwo vers thbufferedou! 204(6) CMOS wit nbd oe ey OMOS wi We have discussed unbuffered, : ora eanive discussed unbuffered outputs of CMOS inverter, CMOS NAND gat: togic Families ati) cea te is increased and it reduces the speed the output, the propagation delay oft of operation |.18.6 Transmission Gates : NMOS, Gues of ©} and Qs are controlled by the controled inputs C and C, Repastely = Whenc=1 (igh), Q\and Que ONor OFF depeing uponthe input When iyta hgh the 0 BOPP incoming he ohmireien: bees and output ¥ asa small resistance connecting the output tothe inputand output a input Ais low, then Q; is OFF and Qs is conducting in the ohmic region; Q2 beha as.asmall sistance connecting the output ote input and output ¥=A =1ow ‘When C=0 (low), both the MOSFETs are OFF and transmission isnot possible. In hort a transmission gate isa digital controlled CMOS switch. The symbol of transmission gate is shown in Fig. 1.48. 4| Control 2 = apt | Out " on |r } m Fics 2, seu ptas 2 Fig. 1.48 The symbol of Fig. 1.47 Circuit of transmission gate transmission gate 1.18.7 Open Drain Outputs Different outputs are available in CMOS logic family asin the TTL family wehad Aiscussed earlier. InCMOS, opendrain outpatis possible by replacing the transistor with a diode. See Fig. 1.49, Yoo op et Rex [| ro, a joa : 4 Fa L | 2 Ir pac ¥ ¥ Fig. 1.49 Open drain outputs ata ede protection rom electrostatic discharge, A in TTL, an ‘external pull-up resistor is required to take the output. Then nen tees aDigital Electronics rosie Families 49 1.18.8 High Impedance Outputs ee ‘output CMOS logic family issimilarto the restate Ves he high impedance i Saad Thehigh ime eh ahows the hgh impedance oIput CMOS nga | 1.19 COMPARISON OF ¢ Sane To ee ascnclw np Whos Eslow.0;wilteONSSEH | TpgcMOS and TT amis compasdam togrictts and (epa low. Now athesane tine, Qs so Thos iS snus high When he enable ip sow and he input ihigh, yj oS 4.20 Comparizon of CMOS and TTL fails inpsto and Qs respectively, re high. So O; willbe OFF and Qs wi ye! sa —_ " me ‘Sili m4 7a. | 74AS | 74ALS Ena eB ietaee gees Sila OS Saad ~ v Zov | 20v | 20v | 20V aa Laren ae aay fosy | osy | osv Id cate 49V 2av |27v[27V | 27V eee olVv o4v [osv | osv | 04V o Header 5 dav forv|oav [ory os vee 09V oav jo3v | 03v | 04Vv in Sins ios | 1 | 15m | 4m raw | tan BT Ib. cer gu)] 017 mW ome | 2mW [as fete | cise | tose) | sors | 2003 [12g | 4s Fig. 1.50. High impedance output CMOS logic family ae en c-fos ny eabseond and With Wa When the enable input is high, E+ is always high, and E/ is always loy “The fan-out of CMOS is more than TTL. Itis typically 50 for CMOS and 10 for independent of input high. Due to this, Q, and Q; are OFF, and the output is ing ‘TTL. CMOS is more susceptible to noise than TTL. high impedance state. 1.20 INTERFACING CMOS AND TTL DEVICES 1.18.9 Specifications and Standards I Interfacing means connecting two different systems or devices, having different ‘The ELA [Electronic Industries Association] has established certain standard gait electrical characteristics. Insuch case, direct connection isnot possible. The circuit stecicaons for MOS circus. In standards to differentiate buffered CMOS. B Gediocomocceveranl lacie tetsu alist a tein tacos rete ee ified as B-types and unbuffered are identified as VB types, circuit takes the input from the driver and converts it, so that itis compatible with the requirements of the load Following are the important factors to be considered: * The driver output must satisfy the voltage and current requirements of the Table 1.19. Electrical characteristics (Supply voltage Voo = 5 V) Value Toad circuit. a5 * Thedriver and load circuit may require different power supplies. In such cases, aN ‘he outputof both circuits must swing between their specified voltage ranges, 45v 1.20.1 TTL Driving CMOS, OSV in E As TTL is driving CMOS, it must meet the current and irements re the load device. Supply voltage is 5 V. taps i -1pa. 100 uA Table 1.21, Current and voltage requirements of CMOS and TTL 360 pA cmos 2 60ns ; 45ns 1omwIogie Families CAB ‘The above discussion of CMOS and'TTL interfacing is only for standard CMOS and standard TTL logic families. For other families, like high speed, low power, itisncoessary to compare the output capabilities of driver and the input requirements of load on the same lines as above. 1.21 INTERFACING ECL AND TTL DEVICES pigital Blectonics_ le ierei a Jorn te TLtasno oben diveth Chg, From Tube 12h pent of CMOSIS Very OW a COPS an he inpacurenreqiem capatliies of TL fa —+—“J [gies san AP SE Mos Fig. 151 TIL driving CMOS TL 1.20.2 CMOS Driving iisneesary wcheck he CMOS ouputcapacityandthe TTL inputrequiremeny, Table 1.22compars thet. Table 1.22 GMOS output capacity and TTL input requirements ‘EMO (4000 B) TTL Vi (nin) = 495.0 Via (in=20V | (max) = 005 Y (max) | Joy (ie) =04 mA, di (ni gx) = 0.4 0A 4 (max) = | HA microampere and mA ~ miliampere From ibe stove tabi is rved ta the CMOS driving a TTL inthe high state donot nee any special consideration such as, Vow (CMOS) > Vi (TTL) ou (CMOS) > Fy (TTL) Forthe CMOS diving a TTL in Jow state, see the parameter Voy (max) CMOS < Vy, (max) TTL Thissatisies th requrementin the ow state. Now se the curent parameter, iSO ee ; [> fo, (CMOS) < hy (max) Se Buffer meres) es ot satisfy. the TT tapas FUSE CMOS driving TTL Interfacing means connecting two different systems or devices, having different clectrical characteristics. Insuch acase, direct connectionisnot possible, The ci used to connect driverand load circuits called asthe interface circuit. The interface Yo, (TTL) YulECL) > Voy. Translator),[shows that the input logic le logic levels ofa TTL a Vels of, at and the output logic, com, = the input logic levels of we Hevels oF arama ti wiclevelsof an ECL. Fipare "anlar ape Bate. ig 154 Shows they egy, Fig. 1.5 1.21.2 ECL Driving TTL An ECL cannot interface directly with a TTL; it requires a translator. ‘The MCIOH125 is an ECL to TTL translator. The logic diagram of MCIOH124is shown in Fig. 1.55; it isa 16-pin IC and ituses two power supplies. The logic levels of the translator are: =-113V, Vy =-148v, 2.5 V, and Vo, =0.5V Ishows thatthe input logic levels of a translator are compatible with the output logic levels of ECL and the Output logic levels of a translator are compatible with the input logic levels of a TTL, Figure 1.56 shows the ECL gate driving a TTL gate. Til eke ro. pe a anion Sig 54 TTL driving ec (e031) ety xp : Fig. 1.55 Logic diagram of MC Logic Famities (th \ARY TT ges —— sum a ofthe following advan erated iit because ofthe olowing adenine: ten digi systems vse inex ss toa of Scan of dig sytem gets eed, Ds of digital ees 2.The cost of 5: mer comune They have high noise margin They have igh relay. 6. The operating speed is high oe «The foie families ate classified ino two 1 6) Unipolar logic families. cet «pur op faites re fr li oS ta) Und ptr aie asia oi, * Br SRNP Satan amir lope) negated injection fog, Diode: (Diet coupe rani oi, nea injection owe, Di transistor logic, (e) High threshold logic, a ete Pe fd bipolar logic families are: (a) Schottky transistor logic, and (b) Emiter- coupled log «ieee se 8, SNOB, CMOS + The various pramates of itl ICs used to compare their perfomance ae (sero orton, Power dat, 0 geo ent Fe (©) Fain, © Current and voltage parameters, (g) Noise immunity, supply requirements, and (i) Operating temperature. ee BY recom pr (lat Drees ae of operation is low (12 ns), and (8) High power dissipation (typically 12 mW). ‘+ The DCTL is simple than RTL, itis not popular because of the current hogging problem. standar Lup, (b) TEL with + A standard TTL. canbe classified as; () TTL with passive pul-op, (6) ‘otem-pole output (©) TTL with open collector output, and (d) Tri-state TTL. very Tow (@) Bipolar logic families, and rated bipolar logic families, jum KEY TERMS AND DEFINITIONS == Integrated circuit Most ofthe digital circuits are constructed on @ single chip, ‘hich ar refered to as integrated circuits (IC). ‘Logie family The set of compatible ICs with the same logic levels and same supply ‘oltages, fabricated to perform various logic functions, are known as logic family, Unipolar logle family “The logic family having unipolar devices like MOSFETs 45 its key clement is referred to as unipolar logic family. ‘Bipolar logic family “The logic family with transistors and diodes a its key element is refered to as bipolar logic family. Resistortransistor logic (RTL) ‘The logic family that consists of resistors and ‘ransistrs is called as resistor-iransstor loge, ‘Direct basil Gea a) La DansPiode-tranistorlgle (OTL) The logic tamiy With dio s diode as its basic element, which Operates eithes re family ee Integrated injection logic (PL) Tt uses nly transistors for MOSFET logle MOSFETs are vecy popular for logic crn on Power dissipation and high density of fabrication, cathe cng, ante case e uN EXERCISES Review Questions og singles th stag tf 3. Explain the tote, fora TH fora TTL gate * NaND gta das, capa ewan fy, NAND gate. What is the advantage of active load? a eel Dg parameters of digital IC files an gn values for TTL and CMOS families, % a @) Propagation delay (©) Fan-out their ypc () Noise margin @ Figure of merit 7- Explain the following parameters: © Propagation delay (©) Noise margin eit short note on CMOS loge family Tie fetes dele inorored neem poe TL ogc? sis of be following pramctrs for TTL snd CMOS le wes a ae ___ @) Power dissipation ie eel Nie omer sate (@) Power dissipation val nai ti re ‘L NAND gate with a neat diagram. Explain the pepe erinret (©) Totm-poe up (© Tite ona erect Exp tc bcc ECL OR/NOR gue wih not ie cng a ECL family have the lowest propagation delay of all logic pues Give typical values of the following parameters for CMOS logic 2) Heneaegaa () Fan-on : ‘hss en ty asia a yg ee ate ek ate driving CMOS gates and vice vers 16, Explain interfacing of a TTL gate driving aioe 17, Define the following parameters of logic families and give their typical val fora standard TTL pate (©) Propagation detay (6) Fanout (©) Nolte arya {0 ome Exphin witha net cic gram the t-te TTL gate How can the t-te Sita up conned ogee to orm eae a a ek an an be teed om he bun wie? 19, Draw neat circuit diagrams of: @) Two-inputs TTL NAND gate with totem-pole output (©) Two-inputs CMOS NAND gate Multiple Choice Questions Select the correct option. |. Positive logic in a logic circuit is one in which. respectively. () logic 0 voltage level is (9 Totie 0 and I are represented by negative and. poaldve voltagesetn * ¥ re of merit of a logic family is given by Se ‘bandwidth product , e ae ation delay time and power dissipation Ort of one : oise margin and power dissipation (ay produc of nose mare Which of he following uses the least power rm () ECL (9 eMos (€) all use same power Which of the following logics is the fastest @ ™. @) ECL (@ cmos hore {In Schotty-clamped TTL, the purpose of Schottky diode is, (a) to increase propagation delay (b) to achieve efficient non-saturated switching (©) toimprove noise margin @) 10 decrease dissipation Pe ee es { .@ 20) 2 © < Te aa Numser SysTEM AND CODES Chapter Outline + Number systems and thelr interconversion + Sign binary numbers + Binary arithmetic +2 complement arithmetic + BCD code and its arthmotie + Ex0265-3 code and its arithmetic * Gray code «+ Party code, ln lock code, and hamming code 2.1 INTRODUCTION Incase of digital systems, datais represented by the binary digits Oand 1 which are known as bits. A group of eight bts is known as byte and a group of four bits is ‘known as nibble. In digital systems, the information is represented, stored and {ransmitted asa group of bits, Thi group of bits is known as binary code. In othet ‘yaaa the binary code isa binary representation of numbers, alphabets, special ‘This chapter includes the study of different codesber he na aseoft stem adixorbase tm he integer p ner of gis 1h oo jn fractional part 45.7 most significant digit (sb) jest significant digit (sb) i + ofsymbols and radix, number systems are 7 laf of umber nthe bass of ary mune sytem (i) octal umf oy OS aterm 221 Decimal Number System ‘ints ptonn umber Thetis. igthas the mexmaa 8 a ea agi SD) Te a For example (55538).g= 5x10? +5% 10!+5% 10°45 x 10-4592 2.2.2 Binary Number System Inthe inary number system, the total numberof symbols are two (0, 1) bai andthe ax point is known she binary point. These symbols are knowns (binary igits)tisa positional aumbersystem; the weight of abit defined Postion with base 2 For example, (LIM), = 1x24 1x 2 41x 2! 4124 1a $1274 1x2? I 2.2.3 Hexadecimal Number System system and Codes 153 Inthe hexadecimal number system, the radix point is known asthe hexadecimal point. lisa positional number system: the weigh of adigitis defined by itsposition With base 16. 2x 16+ 1x 16 + 5x 16! + 10 x 16° $216" 46% 167 48% 16" For example, (215A.268),6 This number system is used to pass the data to the computer system by using 16 keys. Itis the most commonly used number system in a microprocessor kit. The keyboard ofthe microprocessor kit is known as the HEX keyboard 2.2.4 Octal Number System. ‘The number system with base 8 is known asthe octal number system. Eight symbols are used to represent numbers in this system, and these are: 0, 1;2,3, 4,5, 6, and 7. In the octal number system, the radix point is known as the octal point. Itisalsoa positional number system; the weight ofa digits defined by its position with base 8, For example, (576.217)_=5%8?+7%8! 46x84 2x8" 41x8247 x89 2.3 INTERCONVERSION OF NUMBERS {Computer systems process binary data. The information given by the user may be in the form of decimal number, hexadecimal number, or octal number, So an Understanding ofthe system operation requires the ability to convert the numbers from one number system to another, c fe binary nun ‘onsider the binary number: @cBsBrB\By-B)B2Ba), (2.2) “The frst left bit from the binary points denoted by B, i Decimal eguivalent of (2,858, By «BB 4 2! Bcd ep, x aie +Bax2 eB x23 PB aT a Ry 294 ny see F1X2 40x22 412! =16+8+2+1= 027), rita4 1x2240x27 + 124 ji) (0.1101): = 1x2" + 1X? 1 yt yo+4 2*4° 716 =05 40.25 + 0.0625 (08125)0 x241x240x2 41x20 +0> =8444041405 +0125 +0+0.0605 = (138125) (1101.1101)2 = +1 xaty Gi einai wy 2.3.2 Decimal to Binary Conversion ‘Thereare two methods toconvert decimal number to its equivalent method. i Sum of power method Inthe sum of power method, the decimal number is ex} of 2and then Is and 0s are written in the appropriat opposite of binary to decimal conversion. Pressed as a sum of poy, te bit positions. Ibis jut, 1010), Gi) yo =16+ 8404241 SIXD4 1x2 40x24 1x2! 41x20 = (11010), (il) (075), S1x2441 x22 =D; (®) 21.625) = 6+0+4+041405+40+0,125 XM 40x 341 x 92 1 01 yo Boies +0x241x241 = (10101.101), This method ig sum of maga }Y used, as itneeds the number to be represented but itis dittean est © 8 Power of 2 form, I, bbe easy for a few numbers, ficult for may be easy ies ee aa eA | | | umber System and Codes 551 Repeated division and multiplication method nteper and fractional parts ofa decimal number: are treated separately for the oa integer part of decimal version. The repel vison methods sed forthe integer art of evi ‘hombers andthe repetitive multiplication method is used for the fractional part of decimal numbers 2) Repeated division or integer decimal number) ; * nhe repeated division method, the decimal umber divided by 2and the reminders found afer each vision antl he quotient 05 obtained. Note thatthe inary ess obtained by waiting the rt emainder a the least significant bit and the last remainder as the most significant bit. For example, (25)\0 = (2). Quotient Remainder aseore 12) 1 +LsB 1222 6 0 622 3 0 oa 1 1 ee 0 1 oMSB Ans: (25)0= (110012 Repeated multiplication (for fractional decimal number) Inthe repeated multiplication method, the fractional part of the decimal number is mokipied by 2; the integer part of the multiplication is found afer each multiplication operation, until the fractional part of a decimal number becomes ero, The fractional part of the binary result is obtained by writing the frst bit asthe MSB and the last bit asthe LSB. For example, (0.625) = (2), b) Multiplication Integer part 0.625 x2= 1.25 1 «MsB 025 x2=0.5 0 05x2=1.0 1 + LSB Ans: (0,625)10 = (0.101), Now, letus consider decimal number that includes both an integer part as well ‘sa fractional part. Such a decimal number is converted to its binary enuvaleanby ‘epresentation ofthe integer decimal number and the fractional decimal number For example, consider (57.825)jo. The integer part of this dec is $57 and the fractional partis 0.825, eee Conversion of integer part: Quotient Remainder e 1 + LSB 4 0 a 0 3 1 oe { Gansaniee ae se 1 oMsBy ee : NEED somal pa Conversion offre Imegerpart ttiplication poet ee i ‘The integer part ofthe given decimal number is 79 0 Quotient Remainder B+ 20ha aD: 1 + Lsp ae ete 34219 1 (0.825)10' fhe Zs 7 rs (57825)p= (111001), + (041012 = (11001. 1101, 942 4 1 PEAS o ranplo 21 Coavetefoing inary numbers their decimal equi Ceara oa 0 (@ 10010111 (b) 10111.0110 © wut ee i Mi 1); Solution : eo ati rere eee re ‘The fractional part ofthe given decimal number is 0.515. ne Ixp Mutiplicasion Inceger part 28 + 16444241 0.515 2 = 1.030 1 oMsB rane 0.03 x2 = 0.060 0 vate gente i 0.06 «2 = 0.12 ° ) avast gl le +1xP41x2! pletion al 0.12x2=0.24 ° mae 0.242 =048 ° s16+442414 245 | 0.48 x2=0.96 0 = (233750 0.962 = 1.96 1 oLsp : E (0.515)i9= (0.100001). se © MOUNTS Le O21 1ee8 1oc?? ater a Ans: 79.515) iy ©) (109.125), ates - sersesone ded ‘The integer part ofthe given decimal number is 109, = (47.75)i0 Example 22 Convertthe following decimal Pe ©) 9 vn MERU Ce ae ) rab (©) (109,125),9 SolutionJ ga 3.33 Octal to sion imal Conver a fi soa psitoral number), Wen each og 4 iersystemis ali its position relative to the octal point That rain welt bed Oe guvalentby summing the weight f= canbe forthe conversion ofan octal number to it oe deci rhe octal nu razed method fort ained below ihe octal umber: 0,040:0109 + 0.10.20. Consider the octal points denoted by Oo. Subscript 0 de tnt eccrine Op Steet a tons. ee ent sex uk gui Fines thy Value pa en noone 00 a The dial aber fhe cal number psc ST aeuRORE a0, SOA a snl 40..x87+05x8 cae : i) (7539 7x 82+5x8!43x8' sae aie (ii) (0.235), =2x8143x8245x8> 25+ 0.0468 + 0.00976 (0,30668)0 (ii) 265.731)y =2x8°+6x8! 458947 x84 43x82 41x89 = 128 +48 +5 +0.875 +0.0458 +.0.00195 = (181.92375)i0, 2.3.4 Decimal to Octal Conversion Theintger and fractional parts ofa decimal number are treated separately forth conversion (a) Integer number The integer part of a decimal ‘fumber can be converted to octal by using the repeated division method. The integer part of the decimal number s divided by 8, and the femainder is found after each division until the {Quotient becomes zero, The octal number is obtained by writing the firt remainder as the LSD and the last remainder as the MSD. For example, (266),9= (7), Number System and Codes 59 (0) rsetonal number ; ato pa of cia antec obra oi ca valent using the repeated miplcaton method. The rational part of the uecimal number i muliptied by 8, and the integer prt afer each Imuliplieation operation i found unt the fractional prt Of the decimal number becomes vero. The atonal part ofthe otal rest isabtained by ‘rng the fist nteger asthe MSD and the last integer a the LSD. Fer example: (0250) Multiplication Integerpart 0.256 x8 =2.048 2. #MsD 0.048 x8 = 0.384 ° 0.384 x8 = 3.072 3 0.0728 =0.576 0 0.5768 = 4,608, 4 *LsD Ans: (0.256)y0 = (0.20304), The decimal number that includes an integer part as well a a fractional partis converted to the octal number by using separate treatments over the integer part and the fractional part of the decimal number. The octal representation of such a scel HMieaGees 7 oa (125)o=(D)ig | Conversion offracionalpat I he | Seen Sig ata ts An Sa oat6aig pase a if 4 i B @LsD D)is + (0.33748), = (7.33748), 23 i " a4 Hexadecimal to Binary Conversion A hexaiecina muni ofa 'salsoknownas.a4-iti 3 Table 23, "ambercan be; inary number, because eae! by a4-bit binary number, as ve" [ Weradecimat Binary Hexadecimal Binary (aa of ; ie cag cl A io 3 oon B roi | 7 oul uit | Theconversionofeachhexadecimal dgitoits 4-bit binary equivalent performs the conversion from hexadecimal o binary. () G7A)= Qe 4=0100, 720111, A=1010 Ans: (47A)\g= (0100011 11010), Gi) 0269)6= Or 0010, 6=0110, 5=0101 Ans: (0.265),s = (0,001001100101). (iil) F23.6A1)¢= F=1111, 2=0010, 320011, 6=0110, A=1010, ‘Ans: (F23.6A1)6 = (111100100011.011010100001). 0001 2.3.10 Binary to Hexadecimal Conversion ‘hate at different methods to conver the integer and decimal pats of binary hhumnber into its hexadecimal equivalent (a) Integer part cauivalent by making groups of four bits starting from LSB and moving ‘owards MSB and then replacing e, hexadecimal representation. If ach group of four bits by its equivalent thenumberof bits is less than fourin the last For example, (100011110101), = 1000 1111 o101 SF5);6 (b) Fractional part ‘Sr0up, add zeros to the right side, For example, (0010111101), = 0.0101 1110 1000, i a aetectroi a a rumberbaing both inte and fixcy. it : 3 sort mp 010101 = er part = 101001011 pes F100 = 0010 1001 0111 = 097 01 «ional part = 0.01101 - 0.0110 101 0110 1010 =(06A)g 1010010111,0110101 = (297)¢+ (0.6A)is = 297.6A)ig fhample 27. Conver ie following decimal numbers to thei Hexad egoivalets: (by adding 100s tothe egy (by adding one 010 the righ @ 2)» (©) (03560 © 214356, Solution ( @14) | @ 29 4 Decimal Hex | me 4 6 6 +Lsp 13416 a) Msp Ans: 218)9= D8ig (0) (0356) umber System and Codes 67. Solatton (a) B56) x16? +5 x 16! +6 x 16° 3x256+5%16+6%1 768 +80+6 = (65t)0 (b) 0.21) =2% 16+ 1 x 16 es 16 * 356 =0.125-+0.0039 = (012899 © @AF3Dy X16?+ 10% 16! + 15x 1643 x 1644 1x16? 256+ 10x 16+ 15 +316 1256 =512+ 160+ 15 +0,1875 40.0339 = (687.19},0 Example 2.9 Convert the following binary numbers to their hexadecimal ‘equivalents: (@) 1010110110111 (©) 101011011001.1010100 Solution (@) 010110110111) = 1 0101 1011 O11) =0001 0101 10110111 (by adding three Qs to the left) =(1SB7)i6 el (b) (0.010011011).=0.0100 11011 (b) O.01001101124 SI wor negative signs ar know ened ng re uber who PO ays considered a8 Positive numbers, typ ‘omigmt abe a2 Pen or meas Ihe de BS essen a nebo th umber o define Pog a) se peat ee e berta lefine anegative nyt co ine BY a pers negative and when ij! ee oe epee NE the number is neg tisq ste ub sin ti Men menisci enone eeentatn 2 sods sed to represent sign binary numbers, + 2'scomplement p tation 1-Magnitude Representa by oe resentation of abinary number, the MSB represents aor ruinng bs eresent its magnitude. When the MSB is 1, the and the reninng bits represen negative; and when its, the signi positive Consider te binary number: (BB BB BBB By where By represent the ign and Bt By represent the magnitude of the bing umber. Forexample: 00001000 48 0091000 8 oun #127 mn 127 bedi sig ‘The unsigned hi binay representation can represent the maximum deta Wet the pstve number using Pits Step 4: Find the decimal equivalent. —_ 7 (460 = (010000002 MOOLI1= 1x 284 1x 28-+0x2440 x24 12? + 1x2! + 1X2 rhe sconpinetepresntatin ofa postivenamber Same ase 264432444261 ‘ie representation ofa positive m ie Fenn scomplement representation of (+ 649 = 01000000 Hence, the decimal equivalent of (1001 1001);=(-103),0 e number. ‘ 2 «)_ Sep | Fine binary equivalent of the m (b) Given number is (01100111). anil Quotient Remainder ‘Step 1: Check the sign of the given number. 22M 1 +1sB “The mos significant bit ofthe given number is O, the sign of the number is : positive ee aeate v Step 2: Since the number is positive, goto step 3. ee ee e Step 3: Since the number is positive, go to step 4. Me? 5 1 Step 4: Find the decimal equivalent. Sates i MOOI =1x26+ 128 +0%24 +0241 x24 1x2! +12 at ont p =68432444241 eer 1 +MSB 2103 Hence, (89)p= (1011001) Hence, the decimal equivalent of (01100111) = (+103)jo Caan earns) 10 te tel) (©) Step 1: Check the sign of the given number. ‘Step 2: Write the positive number using 8-bits. ‘The most significant bitof the given number is 1; the sign of the number is (+89}o= (01011001), negative. ‘Step 3: Find the 1's complement by replacing 0 by 1 and 1 by 0. Step 2: Find the 1's complement of the number. 1’s complement of (10101011); = 01010100, 1's complement of (+89) o = (-89)io = (10100110)2 Step 4: Find the 2's complement by adding 1 to 1’s complement. 7's complement of (+-89),9=(-89)jg= 10100110 Step 3: Find the 2’s complement of the number. 01010100 a 1 * 1 oa 010 01010101 10100111 cit : ‘Step 4: Find the decimal equivalent. Hees hes complement representation of (= 89)q = 10100111 1010101 = 1x 2°+0x25+1x 2440x241 x240x2! + 1x2? Example 2.16 @ (10101011): oi Serenata ile =85, é, * Hence, the decimal equivalent of (10101011).=(85)jg Piet: | see | Find decimal equivalent ofthe following binary numbes 2644164441 itp ertints H oea pot REPRESENTATION. OF NuMBER sn a imran 709.739is represented in scientif 1729.739is rept titi notin, be afied pint faction Mis tepresengig | compen a afrction 10 times By an exponen iseauvale sap exressed bythe sciente NtaiON no | the! hating Pn spats: the first part represents & signed, fixed point nuts set a tat oon catia a The eatng pint numbers represented (ayx Sinica) xP = 26 ste sin bit defined as s=Oforpostive numbers and s= 1 fornegat ae ert a a conto the ange ofthe number. These mantissa and bias exponent ax ‘Rpesetedy th number ofbitsinbinary. Thenumber ofits is used to deter ‘roscsuracy ofthe stem. IEEE has defined two floating point standards alk assingle precision and double precision. ; In single precision, the word size of the floating point number is 32-bit ani 127 isthe bis, The format of single precision floating point number is showni Fig, 21. Outof these 32-bits, MSB (Ds,)is used for sign, LSB 23-bits (Dz1oD) are used fo significant and 8-bits (D3pt0 Dax) are used for bias exponent. sidered ere the mantisssconsidee tt the nu ary by the expression Du Dp Dn Dm Do 3 [Basen | Scar] Fig. 2.1. Format of single precision floating point number Let us consider the example of a decimal number 44.25. Its bin! representationis Number System and Codes (7 ‘Significant = 10110001000000000000000 the sum of exponent value (5) and bias (127). Itis given as feaeres Blas exponent 5 +127 (1320 sng be converion techniques. itsbinny representation lias exponent = 10000100 ‘he mnheris poste, ene the sigaits 0, and he sngle precision oating pola appeceaa fe pressntet ie [0 [10000100 [_1011000;000000000000000 tn double precision, the word wz ofthe lating pont numbers 4-bits and asestbe bin, Te fmt of double precision floating pont numbers shown in Fig 22 Ouot hese Ohi, MSB (Dy sued fr sign, LSB 52-is Ds 10 Do) Sind for significant and IIs (Deto Dy) ate used for bias exponent. Das Da Ds Psy Do nas [Bias exp Fig. 2.2 Format of double precision floating point number Let us consider the example of a decimal number 144.125. Its binary representations (144.125),9 = 10010000.001 0010000001 x 2” ‘The mantissa is converted to 52-bits significant value by putting zeros to the right side of the number as ‘Significant = 1001000000 100000000000000000000000000000000000000000 ‘The bias exponent is the sum of exponent value 7 and bias 256. Itis given as Bias exponent =5 +256 = (261)yo Using the conversion techniques, its I1-bits binary representation is Bias exponent = 00100000111 ‘The number is negaitive, hence the sign bitis 1, and the double precisic floating. Point representation of the given numberis: Sera {901000001 11] 1001000000100000000000000000000000000000000000000000) 2.6 BINARY ARITHMETIC ‘The computer is a digital system that supports various arithmetic operations. Performs addition, subtraction, multiplication, ietayschyoe denna! learn the basic circuits of a digital system, it is necessary to study binary‘multiplication, and binary division. 2.6.1 Binary Addition “The addition of two binary numbers is performed exactly inthe same aoe toate On oressccrin tendon St bis 000, d=}, 140=1, and 141210458 hsm = anda, ‘The rules of binary addition are given in Table 2.4 Table 2.4 Sum of Binary bits A |B | Sum | Carry o fo] o 0 ° 1 1 o 1 ° 1 0 1 1 o 1 ‘When the binary number re more than one bit the addition takes pace ity bit, which starts from left side. The cary of the previous sum is added to the ny bit addition. : 10110111 #A +O01110101 B 1110111 _ ¢Canry 100101100 For example, 2.6.2 Binary Subtraction ‘The subtraction of two binary numbersis performed exactly in the same manneris the subtraction of decimal numbers. Only four cases occur in the subtraction two binary bits. 0-0=0,0- =-1,1-0=1,and1-1=0 ‘InO~-1=-1, the resultis negative. Itindicates that the second numberis gr than the first one. Similar to decimal number: a peuraeeer I \When the binary numbers are more than one bit, the subtraction takes place bit by bit, which starts from the left side. The borrow of the previous subtraction is subtracted from the next bit subtraction, For example, 10100111 #A -01110101 B i oo110010 + Borrow 2.6.3 Binary Multiplication ‘The binary multiplication is similarto the decimal multiplication. Ifthe multiplier bitis 1, then the partial product is same as the multiplicand. Ifthe multiplier bit is (0, then the partial product is 0. Consider the example:1010 x 1001 1.0.10 @ multiplicand x 1001 ¢ multiplier SsTrosoe 0000- 0000-- 1010 Torio1o 2.6.4 Binary Division ‘The binary division is same asthe decimal division. Binary division has tworesults, lene and remainder. Let us consider the example: 10011011 is divided 100110 1o0o0/10011011% 100tal lectronics ;) Addition of postive and negative number: 4 84-9 step 1; Find the number of Bits required to represent the 1 >max (8,9, 1) and n=5 pa ome, gt-1>9 1's complement representation of (+8) = 01099 jon of (-9) = I’s complement of (01001) Step 2: 1's complement represent = 1's comp) Pemena Binary addition: 01000 +A +10110 +B 1110 Step 3: The most significant bt is 1, so the answer is negative, a 1's complement form. a Result = ~(00001) iti (iii) Addition of two negative numbers: (8)+(-9) 17 ‘Step 1: Find the number of bits required to represent the number, 2" 1 >max (8,9, 17) 2'_1>17 and n=6 ‘Step 2: 1's complement representation of (-8) = 1's complement of (001000) | 10111 t "s complement of 1's complement representation of (-9) = 1's complement of! s complement of (001001) t 10110 ‘Step 3: Binary addition: 110111 @A + 110110 +B 1a ¢ Carry 1101101 L__,1 ¢Camyis added 101110 ‘The most significant bits 1, so the answer is negative, aml es 1's complement form. Result = -(010001) = 17 umber System and Codes (89 ‘Subtraction The subtraction of a binary number B from another binary numbe to the addition of 1's complement of B to A ic. (AB) =A + 1's comple 3B. The algorithm for binary subtraction using 1's complements is: 1. Find the numberof bits required to represent the sign number. The number ofbits required to represent the sign number is, such that 2" '—1 is greater than or equal to the maximum of the magnitude of A; B; A ~ B. 2. Find the 1's complement ofthe subtrahend. 3, Add A and the 1's complement of B 4. Check the cary, ifthe carry is generated, add the carry in LSB position and take the 1°s complement of the result. If the MSB of result is 1, then the answer is negative; itis in 1's complement form. Ifthe MSB is 0, then the answer is positive and in true form. fer A is equivalent ment of Consider the following examples. @ 8+ ‘Step I> Find the number of bits required to represent the number, 21> max@8,9, 1) 21159 and n = 8+ I's complement of Step 2: 1's complement of (+9)= 1's complement of (01001) 0110 Step 3: Binary addition: 01000 +A + 10110 # 1’scomplement of B Tio ‘The most significant bitis 1, the answer is negative, and itis in 1's ‘complement form. Result =-(00001) = 9+ 1's complement of 8 Find the numberof bits required to represent the number. 2-1 >max@,9, 1) 2-1>9 and n=5 Step 2:_ 1's complement representation of (+9) = 01001 1s complement of (+8) = I's complement of (01000) =10111Step 3: Binary addition: 01001 6a . 101115 6.1’scorpa, 1111 * Carry ae 100000 ¢ Carry is added ‘The mos significant itis 0, the answerig form, Postini Result = (00001) = 1 } 2.7.2 2's Complement Arithmetic Addition The addition of sign-binary numbers takes place Using 2's co, algorithm for sign binary number addition using 2s complement Consider A and 8 are two sign numbers mplemeny iSpiventay 1. Find the number of bits Tequired to represent the sign number, Thenumber ofbitsrequired to represent the sign ‘number isn, such that 2 Fie let than or equal to the maximum ofthe magai i 4. Find the binary addition, 5. Discard the carry ifit is generated. ‘Consider the following examples. (i) Addition of two positive numbers: 84+9=17 Step 1: Find the numberof bits required to represent the number, 2-1 > maxi8, 9, 17) 2"-1>17 and Step 2: V's complement ‘Tepresentation of (+8) = 001000 __ | Scomplement representation of (49) = 001001 3: 2's complement Tepresentation of (+8) = 001000 Fepresentation of (+9) = 001001 ition: Number System and Codes 85) Gi) Addition of positive and negative numbers: 8+(-9)=-1 Step 1: Find the number of bits required to represent the num! 21 >max(&, 9, 1) -1>9 and’ 01000 's complement of (+9) Step 2: 1's complement representation of (+8) 1's complement representation of (-9) = I’s complement of (01001) =10110 ‘Step 3: 2's complement representation of (+8) =01000 2's complement representation of (-9) = 10110 + 1 =10111 Step 4: Binary addition: 01000 «a +10111 0B arias ‘The most significant itis 1, the answer is negative, and itis in 2's complement form. Result =-2's complement of (11111) —I's complement of (11111) + 1 (00000) +1 =I Addition of two negative numbers: ‘Step 1: Find the number of bits required to represent the number. 21> max (8,9, 17) WW 1>17 and n=6 1's complement representation of (-8) = I's complement of (001000) =o 1's complement representation of CS)=1's complement of (+9) 1's complement of (001001) = 110110 Step 3: 2's: ‘complement representation of (8) 1's complement of (001000) + 1 MOLL+1 = 111000 . v Step 2: "s complement of (48)‘complement representation of (- a =110110+1 ty Su ae ae means ad Step 4: Binary adition Step 4: Binary addition: 01000 +A 111000... «A #10111 ¢ 2's complement of B +110111 4B ‘i Seren TTia a ‘The mos significant btis I, the answer s negative, and itisin2’s EET oe teeny mate ta xe most significant bitis 1, the answer sng ”s complement of (LL ‘complement form. Batives andi, th seat aa met Result = 2's complement of (101111) =1's complement (101111) +1 (010000) +1 (010001) hay I 9 8=9+1's complement of 8 ‘Step 1: Find the number of bits required to represent the number. ‘Subtraction | 21 >max (8,9, 1) ‘The subtraction of abinary number B from another binary number iseqgn. 1-159 and n=5 tothe addition ofthe2's complement of B with A i.e.(A~B)=A+2'scony Step 2: 1's complement of (+8) = 1's complement of (01000) of B. The algorithm for binary subtraction using 2's complements as fala ont 1. Find the number of bits required to represent the sign number. Step 3: 2's complement of (48) = I's complement of (+8) + 1 The numberof bits required to represent the sign-binary numberisy "complement of (01000) +1 that 2°"! — 1 is greater than or equal to the maximum ofthe magus = 1011 +1 A:BA-B. 1000 2. Find the 1’s complement ofthe subtrahend by replacing 0 by 1 and Step 4: Binary addition: 3. Find the2"scomplement of the subtrahend by adding I tothe I'sco 01001 +A 4, Add these numbers using binary addition. 11000. ¢2°s complement of B 5, Discard the cary, ifit is generated, 1 Cary IfMSB of the esult i 1, then the answer is negative; itis in 2's co 00001 ¢ Discard the carry form. Ifthe MSB is 0, then the answer is positive; itis in tue form, Sera ae ‘The MSB is 0, the answer is positive, and itis in true form. (ab cos + Result = (00001) =1 8-9=8+2'scomplement of 9 Example 2.21 Perform the following operations by using 1°s complement Step 1: Pe the number of bits required to represent the number. method. Dei scuia9, » (@) 42-22 (b) 20-42 (©)-42-20 Solution @ 42-22=20 ae 42-22= 4241's Step 1 pea eee eer 211 > max(42, 20, 22) _ = 1’s complement of (01001) +! ae cae Q-1>42 and n=7 nOf (+9) = 1's complement of (49) +1gg) _Digital Electronics 1's complement of (422) = 1's complement of 1101001 sp 3: Bir aio 0101010 +A dab iteiti texctooncn ora, 70010011 L —! “poi0700~ The MSB is 0 the answer is positive, and iis inte fom Result = +(0010100) = +20 20-42=20+ I’s complement of 42 ‘Step 1: Find the number of bits required to represent the number: 211 > max(20, 42, 22) t-1>42 and n=7 Siep 2: 1's complement of (+42) = I’s complement of (0101010) = 1010101 Step 3: Binary addition: 0010100 +A #1010101 ¢1’scomplement of B 1101001 ‘The MSB is I, the answer is negative, anditisin complement ia Result =-1"s complement of (1101001) = (0010110) 22 (©) ~42-20=-62 ‘Step 1: Find the number of bits required to represent the number. 2011 > max(42, 20, 62) 2"1-1>62 and n=7 ’scomplement representation of (-42)= 1's complement oft =1’s complement of (0101010) = 1010101 ‘'scomplement representation of (-20) = 1's complement of 's complement of (0010100) = 1101011 | 10149. > umber System and Codes (88) Step 3: Binary addition: 1010101 6A + 1101011 +B LLL 9 Cany Troo0000 41 ¢ Camry is added —reo0001 “The MSBis the answers negative, anditis in I's complement form Result =-1's complement of (1000001) (ou1110) 2 Examples 2.22 Perform the following operations by using 2's complement method. (a) 46-23 (b) 23-46 (@)-46-25 Solution (a) 46-23=23 46-23 = 46 + 1's complement of 23, Step 1: Find the number of bits required to represent the number. 1 > max(46, 23,23) =1>46 and Step 2: 1's complement of (+23) = 1's complement of (0010111) 1101000, ‘Step 3: 2's complement of (+23) = 1's complement of (+23) +1 =1’s complement of (0010111) + 1 1101000 + 1 = 1101001 Step 4: Binary addition: 0101110 4A +1101001 ¢2'scomplement of B Tt ¢ Carry EOOLOTIT ¢ Discard the carry ‘The MSB is 0, the answer is positive, and itis in true form. + Result = (0010111) 2423 (b) 23-46 =-23 23-46 =23 +2’s complement of 46 Step 1: Find the number of bits required to represent the number. geil. a ta eesuep sep 4: Binary ation: 010 41010010 ¢ 2's complement of B 1010001 = 1010001 +1 = 1010010 111 6A root 's complement of M1149) mplement of (.gg) 's complement of (4 111g), ‘he MSBis I sotheanswerisnezaiveanditsin2 ony, form, Result 2’s complement of (1101001) 'scomplement of (1101001) + 1 =-(0010110) +1 (0010111) Step I; Find the numberof bts required to represent the number, 2011 > max(46, 25,71) 1>71 and ‘Step 2: 1'scomplement representation of (46) = 1's complementof Sep: 1's complement = 11010001 of (00101110) {'scomplement representation of (-25) = 1's complementofl = I's complement of (00011001) 1100110 2's complement representation of (~46) = (46)+1 = 11010001 +1 = 11010010 's complement of (00101110) + 1 *s complemet 2.3 complement representation of (-25) = 1's complem®! (25)41 =1'scomplement +1 of 00011001) +1 umber System and Codes Step 4: Binary addition: 11010010 6A +11100111 6B 1 1t oCany FIOLI1001 ¢ Discard the carry ‘The MSB is |, the answers negative, and its in 2's complement form. Result =-2's complement of (10111001) 1's complement of (10111001) + 1 (01000110) + 1 (01000111) =-71 ARITHMETIC OVERFLOW. When we add two positive or negative binary numbers and the result exceeds the original length of the number, itis known as overflow result. Overflow causes a sign change. Letus consider the examples ofthe sum of two positive binary numbers as Case | and the sum of two negative binary numbers as Case 2. Case 1: Sum of two positive numbers Consider the sum of +125 and +75 +125 Olliiio1 +75 01001011 titi $200 11001000 As the decimal sum of +125 and +75 is-+200; the length of the numberis 8-bit, the result is 9-bit and an overflow occurs. This overflow changes the sign of the result and the answer is wrong, Result shows that the sum of two positive numbers is negative, which is wrong. Case 2: Sum of two negative numbers Consider the sum of -61 and 43, 61 10111101 -43 10101011 wit =104 101101000 As the decimal sum of 61 and ~43 is 104, the length of the number i i the result is 9-bit and an overflow occurs. By A iy eg ox yk‘Codes arethe representa d symbols, which man ¢, iat may incl pers, alphabets, aM oN 2.9.1 Classification Computers eco ‘of Codes india data, Tedgital data3s an input tthe mag puetciecciaceer toe come mn pnts, 2269 ume punctutio of tand0. When t sane contol characters should be represented by unique ge Missoni of and Oarereleredas the code fog data is transmited over long distance, itis transmitted ne cove words, Daring the transmission process, errors may be introduced 1 tntcoret the erors, special codes are used in digital communication, ‘The commonly used binary codes are classified as: 1, Weightedcodes if-complementary codes 3, Unitdistance codes 4, Alphanumerical codes 5. Cycliccodes 6, Error detecting and correcting codes Weighted codes Inweighted codes, the weight ofadigitora bit depends on its position, For indecimal code 589, the weight of is 500, weight of 8 is 80, and weight oft Similarly in binary ode, the value oft depends on its position. Binary, BCD, 8 and 2-2-1 are the examples of weighted codes which will be discussed ‘next section the example of sel. ; complement of he exec Sle complementary code. In this code, te i excess-3 code isthe excess-3 code for the 9's comple Number System and Codes 1980 Alphanumerical codes ‘The binary codes of alphabets, numbers, and special symbols are known as aiphanumerical codes. ASCII (American Standard Code for Information interchange) and EBCDIC (Extended Binary Coded Decimal Interchange Code) ‘are commonly used alphanumerical codes, ASCII and EBCDIC codes will be “discussed in detail inthe next section Error detecting and correcting codes \When information in digital form is transmitted toa long distance, errors may get introduced and I becomes 0 and 0 becomes 1, Special codes are used to detect and correct such errors. Parity and Hamming codes are commonly used for error detection and correction. 2.9.2 Binary Coded Decimal Code (BCD CODE) Itis a 4-bit binary coded decimal number. Each digit of the decimal number is represented by four-bits, the digit 0 in BCD is represented as 0000 and the digit 9 is represented as 1001. The BCD codes of Oto 9 are given in Table 2.6. Table 2.6 BCD cades Decimal BOD Code Digit B B By Bo 0 0 0 ° ° 1 ° 0 ° 1 2 0 o 1 ° 3 & o 1 1 4 ° 1 ° } 5 ° 1 ° i 6 ° 1 { mi 7 ° i 1 1 % i 0 0 0 9 i a a p ‘Thecodes, 1010, 1011, 1100, 1101, 1110,and 1111 are invalid. The weights of Bs, Bo, By, and By are 8, 4,2, and 1. Hence, BCD code is also known as 8-4-2-1 code ‘An N digit decimal numbers represented by 4 x Nits in BCD code. The BCD ‘code of (15)19 is 00010101, and the binary code of (15),g is (1111). The BCD ‘code of (15)jo is eight bits and the binary code of (15),9 is four bits; it shows that ‘the BCD code is not efficient as compared to binary. The BCD code requires more space and time to transmit the information. The arithmetic of BCD code is also complex, A few examples are given below. (Decimal 2 6 BCDegivalent 00100110 (ii) Decimal 8 -84 _ Digital Flectronics BCD arithmetic 2 BCD Addition In BCD addition, each digit ofa decimat np int ts 4bit binary equivalent and the addition of two BC hey, using the rules of binary addition. esis ay “After the addition of two BCD codes, the result may be an BCD. Ifthe resutis invalid, itis converted into a valid BCD by ly, (Gyo forthe 4-bit addition cary is generated ater the addition 806 added to the next bit. Ong’ Algorithm for BCD addition: 1. Convert the decimal numbers into their equivalent BCD cog, 2 Add the BCD numbers using the rules of binary addition, 3. Check therestit itis valid less than orequal 09), no corectig and ifthe rest is invalid (greater than 9), 0 to the next stp a stop ~ 4, Add 0110 to the 4-bit sum to get the correct result (i) Addition of Sand 3 in BCD 3 0101 * BCD cole, +3 0011 ¢ BCD code, 3 111 ¢Cany 1000 + BCDeoky, The addition of wo BCD numbers, 0101 and 0011 is caried outusngh addition and the sum, 1000, is obtained which is the BCD code for, (ii) Addition of 8 and 5 in BCD 8 1000 BCD coded +5 0101 ¢ BCD coded 3B 1101 ¢ Invalid BCD (1101), isthe binary equivalent of 13 in decimal. Itis an invalid ie It-canbe corrected by the addition of (0110) to the invalid BCD rest 1101 ¢ Invalid BCD +0110 1 ¢Cany 00010011 ¢ BCD code of 13 Addition of 7 and 9 in BCD # BCD code of7 # BCD code of ¢ Cary ¢ Invalid BCD! +9 umber System and Codes 95 To correct the result, add OL10 10000 + 0110 “00070110 ¢ BCD code of 16 Example 2.23 Perform the addition of the following numbers in BCD (6-421): 847 (i344 i849 Solution @ 8 1000 a3 oil te OL +4 +0100 5 TIT ¢ Invalid BCD code eae +0110 Add6 00010101 ¢ BCD code of 15, Gin 8 1000 +9 + 1001 ae TOOOT ¢ Invalid BCD code + 0110 Add6 00010111 # BCD code of 17 Example 2.24 Perform the addition of the following numbers in BCD. (84-21): (15 +24 Gi) 19 +22 Gi) 91+ 81 Solution wo 1S 0001 0101 BCD code of 15 +14 oo1 0100 ¢ BCD code of 14 228, 1 1 Carry 0010 1001 ¢ BCD code of 29 (ii) 19 0001 1001 ¢@ BCD code of 19 + 22 +0010 0010 BCD code of 22 TH 0011 TOTT ¢ Invalid BCD code + 0110 ¢Add6 1 1 Caer es196 Digital Flectronics Gi) 91 1001 0001 @BCDecg +81 +1000 0001 s BeDeoge tl a Tela teiceo nn eeclas Cesena T0001 0010 « Soon, coo i +0110 0000 # Add oro sing ooo1o1tt 010 02 secong fl oor # BCD covcor me Example 2.25. Perfo the alton of the foto wing re (8-4.2-1) ( 1914171 (i) 9174215 Solution @ 19 0001 1001 00014 +17 +0001 oui 00014 - U1 it itso =a 0011 0000 Since carry is propagated from the second digi, the a invalid BCD, Add 6 to the second digit to correct the onli a 0011 0000 0010 + 110 + Adas OOIT 01100010 5 Eg at Denied pers @) 917 1001 0001 O111 ¢ BCDeod +215. +0010 0001 0101 + BCDeaie 132, 1 111_¢Cany ion 010 1100 # BCDeoie ‘The first and third digits are invalid BCD. Add 6 to both the digs 1011 0010 1100 +0110 0110 # adds Lu 1 ¢Cany 7 0001 0010 10010 ¢ Propagaet 0001 0001 ool 0010 ¢ BCD coded BCD Subtraction The subtraction of numbers is nothing but an additi second negative number with the first number, ie., A-B=A4(-B) In other words, the subtraction of numbers is the addition of a signe Theaddition of signed BCD numberscan be performed using 9’ sor 10° ‘pie negative BCD number can be expressed by the 9's or 10's comple BCD number,’ umber {CDsubtracon using 'scomplement bacon othe second nunbet ace utnunberistheatstomscomplementof te secondnumber wih sar per Thc3'seomplenentotadscial ure ixcisined by SUDAN sa thc dectnal number om. The 9's complements af he dein Sos re enn Table Table 2.7. 9's complement of decimal digits Decimal Digit Decimal Digit | 9'5 complement x complement 9 1 8 1 4 3 2 a 0 5 _Ngorih for BED subtraction using 9s complement: {) Find the 9s complement ofthe subrctr. (i) Perform BCD addition of the ist number wth the 9s complement ofthe second mober Gi) HTear is generated thenthe results postive, Add the carry tothe resltto eth correct result. Ircarry is not generated, then the resus negative fd itis in scomplement frm. Tookat few examples (a) 8-3 8-3 =84+(0's complement of 3) 846 1000 ¢ BCD code ot 8 +0110 ¢ BCD code of 6 THO’ ¢ tavalid BCD. 110 + Adds u T0100 Loot + adie cary to LSB 0101 ¢ BCD code of 5 2 ©) 3-8 aaa 3-8=3+(0'scomplementof8) 1 =341 +e 4-1 4— 1 =4+(9"s complement of 1) +8 ; 0100 # BCDeade of 4 +1000 ¢ BCDeode of 8 T100 ¢ Invalid BCD code. +110 # Adds 1 Toorsoe) Digital Mectromics _ s complement Su 4 (a BCD subraction using 10's complement Subraction gp, (Br st st namie isthe dition of 10's complemen oh ay umber tne The 10 scomplemen' fa decimal mga rane wath "s complement of the decimal number, The ge Praplements ofthe decimal digits are given in Table 2.8 aa Table 2.8 9's and 10's complements of decimal digits pay 9 |e [Decimal | 9% erin! | plement complement | aig | complement | cgi) 0 9 10 5 i sen 1 8 9 6 3 : 2 : 8 7 2 © 3 6 7 8 1 a 4 5 ‘ 3 ° 2 “Algorithm for BCD subtraction using 10's complement: 1. Find the 9's complement ofthe subtractor 2, Find the 10's complement [ie., 9's complement + 1} 3: Perform BCD addition of thefirst number and 10’scomplement of hese number, 4, If carry isnot generated, then the result is negative, and its in jp, complement form, fcarry is generated, then the results postive, dca, the carry to get the comect result. Let us look at afew examples. (a) (8-3)=8+.(10's complement of 3) =8+ (0's complement of 3+ 1) =8 +7 1000 # BCDcode of § 40111 # BCDeodie of 7 TI11 ¢ Invalid BCD code + 110 ¢Aad6 11 ¢Cany XO101 ¢ Discard the cary 0101 #BCDcodeofs (6) G=1)=4+ (10's complement of 1) =4+ (9's complement of 1 +1) =4+9 0100 ¢ BCD code of 4 +1001 ¢ BCD code of: 4 (10°s complement of 8) {3 +0°s complement of 8+ 1)=3-+2 0011 # BCD code of 3 40010 # BCD ode of? ‘0101 ¢ 10's complement of 5 Carry isnot generated, hence the result is negative. Result=—5 (a) (—4)=(1 + 10's complement of 4) =14(0's complement of 4+ 1) =1+6 0001 # BCDcodeof I 40110 #BCDeodeof 6 OLLT ¢ 10'scomplement of 3 Carty is not generated, the result is negative, Result =—3 Example 2.26 Perform the following subtractions of BCD numbers using 9°s complement. Noes 4-8 © Be Solution (a) (8-4) =8+ (0's complement of 4) +5 1000 ¢ BCD eode of 8 +0101 # BCDeode of 5 TION ¢ Invalid BCD code +0110 #Add6 1 Carry ae TOO11 LL—41 ¢ Add the carry LL Cary % Men 0100 #BCDeode of +449s complement of 24) 475 Q110 1000 # BCDcode or 6g soll 0101 ¢ BCD code of 75 Carry ror TTOT + Roehiedisis einai +0110 0110 ¢ Add6tocach digit *Dy, L 1__¢Cany Toor 10011 Lig Lest @ Ada the carry u 11+ Canry 10d 0100 _¢ BCD code of 44 (a) (24-68) =24 + (0's complement of 68) =24431 0010 0100 BCD code of 24 +0011 0001 ¢ BCDeode of 31 0101 0101 ¢9'scomplement of 44 ‘Camy is not generated, the result is negative. Result=—44 Example 2.27 Perform the following subractions of BCD number yy 10°s complement. @s-4 () 4-8 Solution (@) (8—4)=8+ (0'scomplement of 4) 8-+ (9's complement of 4+ 1) =846 (©) 68-24 @ 4-6 1000 BCD code of 8 +0110 + BCD ode of 6 1110 ¢ Invalid BCD. + 110 Adie 1000 0001 0010 Add3tocachdigit, > 0011 0011 9011 ua 1 Excess-3codeof 812 > 1011 0100 0101 ‘9's complement of 812 = I's complement of (1011 0100 0101) =0100 1011 1010 (0100 isthe excess-3 code of 1, 1011 is the excess-3 code of 8, and 1010s the excess-3 code of 7. ©—— nal 2.98 Gray Code age, Decimal number. 01015, te repreg eae Fe cee RIES ikon aw distence code TS cry 220 malts ey cater forte lowing dial umba codes. Tis Ce ne bit position: ey @ ©) Bore rare aatecnmea. | oui se NN pe, Becalse ofthis he Gray codes ogo a) AS 1D: ) 14.9= 110), . _ By=1-By=1,B,=1,By=1 |, By = 1, Bo=0 ( Ms application in anag-10-digital oy ie decimal numbers, 0015, is given nin Gy=By=1 G G,=B:@B)=10 161 hi tions, but BOB, =18 B,@B,=1® ‘Decimal Go= By @ By Go = By BB Ge | aise Gray code of Gray code of rea als ee (©) B)yo= (1000). rielomesbas|oized| Fels | 0 By 1, Ba =0,B) =0,By=0 Sel merc | | tie iy peer a (et to pretnaee| to 1 fei |e at faloteel tal co | 0 alesis | 20.1.5, Gray code of = 1100 Example 2.31 Find the Gray codes for the following binary numbers. oven devimal number, one can notice a ewocanscutve digi fecccme Bing a) 11001100 (01011110 ayeove changes from 0101100100; thgey | Solution (@) 11001100 () o1o1nit0 By =0, B= 1, Bs=0, Bu= ly ‘we examine the Gry cecbitftie Gay code canes changes from 6107. i erg netmost tly. Ths isthe primi characteristic of the Gray eo, Binary-to-Gray code conversion ‘eisificuttoremember ihe Gray code of each decimal number as compared eet Bo So ‘inary code Hence, wit the binary code ofthe decimal number and then cones iy it into Gray code by using binary-to-Gray code conversion technique, Ti Ge=B,® Be=0@1=1 generalized method of conversion for N-bits binary to Gray is as follows: Gs = By @ B: Gyr By (28) G,=Bs® B,=0@1=1 G,=B,8B,= 1814 Gr= B® B,=18 G,=B,®B,=1@0=1 Go =B, ® By=0@0=0 ‘The gray code is 10101010. eats ‘oa expan, N= the Gray codes bined by using the GB aeumber System and Codes 108) Gray code GL Glo me] ne generalized method of conversion for Nits Gray-to-Binary codeisas follows a (2.18) o| o By_2=By=1 @Gy—2 19) ! o}o By=3=By-2OGy—3 (2.20) 2 0 0 Pe aslaelete cir ce tet Pe Sasa ne ene of ' 2.22) Gael cali dialaeledor| Bich so% (4 223) Tc etal esa eS eat tH ciclo the Binary codeis obtained by using the following : pepepo lx) 1 | 0 og ti re iisieandetey ta Opel, 224 L 2.25) «ty Te ei binary coe represent te decimal umbers, 010 15-Theg 0 i cen ofthe decal TOMDer re git eo (226) tn ca inten 27) 5 | example 2.33 Find the Binary codes forthe following Gray codes: Tuble216_ it binary code and ts Gray code a at see aaa Fase . oS [Sane FRET ET TG Te |S Gren raycotts1000. (0) Given Gray cadet 1010, ofofofofofo}ofo | Gs=1,G,=0,G,=0,G)=0 G5=1,G)=0,G)=1, G0) ofofofi}o}o}oly 2 acae oes Pleciaieers iene] 5 | hal ay B= ®G,=100=1 B,=B,@G)=100=1 oleralse | SoHer cho ae 5y=B2@6;=10 2,=2,06,=1@1=0 apereatiy: ara adil c(i 2 Bo=B, @Gy= 1 By=B, ®Gy=0@0=0 earns 1 Roel a Mi ‘The Binary code is 1111 ‘The Binary code is 1100, shies en iaiendl st.) js0, 0, (©) Given Gray codes 1111. Looe latsleds| ov |. oo; ln G=LG=LG=16 Lele ot feat alo. | a By=G,=1 wate rvel 05) telaet | des B,=B,0G,=18 We lle cla Pod abate nO scl neds | ct By=B,®G)=1@1=0 o r Aten | earch ghey) ‘The Binary code is 1010. \ ida. Leptin isi Ltt 2.9.9 Seven-Segment Code Gray-toBin 'y-to-Binary code conversion Inmostof the applications, seven segments are used to display the | —"— result. Binary or decimal digits cannot be dispalyed directly over } Inatelephone communieation, ae ion system the, ‘ {Gray coe. Butane reciente SEY betransmitedinthefom | the seven segments, The seven segment display includes seven / aoe isnecessary tocomer he Gry difficult to decode the message ‘Segments, which are refered as a, b, c,d,e,fand g. The segment |__& 'y-to-Binary code converter, ‘into its equivalent binary by using will be ON or OFF according to the input data and the type of | noe ee abe serenseaments ar ofwotypesa) common anode . common cathode type. The seven segments are shown. inthe nuceceR gure ae oh aaaDigital Blectronies_—_ ea ‘Common anode type Ina common anode type seven segment, the anode of lighten, smnnected togeter 10 Ve. When the input iso, grein dita penne (segment) are connected to i » the coreg ge ,/tS,*,etc. Inother words, alphanumeric codes are the binary representa Om Se geand EBCDICare the examples of alphanumeric codes. an a umber System and Codes 4441 segment is ON; ie seethseement cove for common anode types ven in Table 2 19 Table 2.17, Sovensegment code of decimal digits and hexadecima}g ASCII code ce ieee matt Ta [OTe TATE LT Te Tap gets) Acme cad tices n mow of te microcomputers 8d of efefe fe fe fo Ps Fr TARR) onan anna mations vat steele Wha? 28 1 “sifio attl al ja os ansible ede groups. ll the keys ofa keyboard are represented by 7 bit binary 3 ° Jo Ofodi (4 bola ae ‘eulcomputrs, and stored it the memory. The ASCI code and its octal an 4 tfofof1]fa fofofy % vexadecimal equivalents are given in Table 2.19. : Cabs sear eta Dl 2p 8 | 4 Character |7-Bit ASCH Hex] Character [7-Bit ASCH | Octal |Hex 8 eee eae | 21. aoa 5 | 1000010 42| 2 | tortor | 152 | 5a a D 100 0100. 44 1 101 0001 | 161 | 31 SI ts E 100 0101 45, 2 101 0010 | 162 } 32, Ina common cathode type seven segment, the cathode of light emmiting ding | F | 100 0110 46 3 toi 0011} 163) 35 (eam) areconnectdtngetherto round. When he inputs 1th comespn | a | woo 47| 4 {1010100 | 164 | 34 SamentisON:and viene aptin iecreponding segment wore | | ¥ | 100100 fio | 48] 5 | ror o1or | 165 | 35 ‘seven-segment code for common cathode type is given in Table 2.18, | f 400.108, ey = tor Diigo Table 2.18 Seven-segment code of decimal digits and hexadecimal equiva rays] 00 1B AB e 1110004) ei ea cae TTS Te PoP amwee]) |e | toon | is [40] suann | toro | a | 2 | 1 op ee ea elena 8 a N | 100 1110 4B ror ino | os6 | 28 2 Te arses tea |' 1! |, | 2 eee ar ( 101 1000 | 050 | 28 3 TE ema peekep | pa | P| 100 0000 sof + | ior tom | 053 | 28 4 OH al cetindl DN Sear bey R @ | 100 001 st} s | 101 o100 | oaa | 24 3 1s al met te | 66 R | 100 0010 52 . 101 1010 | 052 | 2a 6 Sho etal a 0 Be S| 100 0011 33 ) 1011001} ost | 29 : fale teliaal eles lin)” BE T | 100 0100 34 2 tor 1101 | 055 | 20 8 tLe lata iah sy, ew EO y 100 0101 55 ' vor iit | 057 | aF 9 1 id ean ey sa ifo FE 100 0110. 56 101 1100 | 054 | 2¢ 1 1} o F6 w 100 0111 57 101 1101 | 075 | 3D. is cn x | 100 1000 | 130 | Se [exerenn| ror uot | 018 | op i || 101 1010 | 012 | 0A eee seem alphabets, andspecial symbols Tacha teat consisting ofmumercas | FBCDIC alphabets and special symbols tog, ismeeessary to have binary codes ft Extended Binary Coded Decimal Interchange ate called alphanumeric codes ‘code. This isan 8-bit code and so, ithas 2 26 uppercest Code (EBCDIO) is anatphanumeric 256 possible code groups. The EBCDIC ‘Acomplete alphanumeric, codes Jevers, 10 numeric digits 7aNumber system and Codes _ 86 ebit | Character] 5 “pows hat heres erorinweducedoverthechanael tal ncoic aa Ceaser smaitshowatio sroducedoverthe channel, etal ae ne erie changed over hePal Fore mf tio0900! |G | mtotso | ee ane 2.21 it mesage wih even party and ol pay 0 = www} 2 Yon | 7 | unan| a icv | Oi prin coded : inio0010 | 8 4 PL Me| Ms] Mi Ma |? | Mol a [ats [Mo p | sre0ot00 | § 11111009 joo | 9 eet io] 12 [° E 11000101 T uw TNT 100) tlololots joo olo\t Ernie | w_| tvont@e | BLANK | tone 1491 oye |e \oll coal ela Fe fy. fatgeian | ot) oteoien +) eel clan |e eon etalaianlae So resin een ee aus Leek etl malcas | at hah ee Rea racer luo enivondi| 2+. *!f o}botiy ofolifofs | syals ye dy 1 [ranoet | yf anon | $ | ototion ofojryrtetstel sys la ig eae eet pancou | foe | ONT fo yee ean a aortic] be euat@onk| ps3) oiorst 1 /te[oedl mile )ets at an Me of trosoran | > 1) | 1saioor 01100000 baa ees PS hata feed ess di MO icretotl le amen aLegO te |, rae) Oh oat | efo: fem | eyes ate ea o =| tantaito’). 3% seen " o1t01011 0.) tea [ot /eee ya etl ete eo 4 | tnttoroo |= | atte { [1 janhoilet |) eam 1 ao: Vio at a ‘ tis setae a 2.9.11 Error-detecting Codes "The I-bitparity code word can detect {-biterrors,butit cannot detect the Tocation of the error or correct the error. "The circuit that generates the parity bit at the or ey enn caled party generator and thecircithatchesks the PaNiS A tir oceiving end is called a parity checker. The designs of panty generator and parity checker will be discussed in Chapter 4. ‘ Inga commonicatonth digital dais sentoverelepone ines using fea nas codes, During the transmission, beats of mois signal, may become a Pin pecome O, and wrong infomation may be received at the destination, Thi oblemsof communication is overeoneby wngeror- detecting codes. Thesimple prove detecting codes ae: () parity codes and (i) block parity codes. vt tre ay ace ec Usually ASCII codes used for ending digital data overtelephone lines. The |-bi rare than two bits, the parity of the message may be unch ‘or more than I-biterors may occu in transmitted dat, To detect these er1or Tooker eannot detect the error. This imitation of parity code is over party bicomalremenes aee “Atthereceiving end, party [| _certainextentin block parity codes. Inthis technique, SAE SE vile eee aoe a Mga Me M9 "Ms; | information as a block, each block consists of Mo where P is a parity bitand My. t0Mo are N message bis. There are two | FB 2.3. Party bits can be assigned to both types of parity: () even parity and (i) odd parity block consisting of four words, each word c ‘For an even parity code, the total number of Is in the parity code word is eve: $ i ee sy aS iy cre te ikea AE eh ic wd soi hl a cage with even parity andoddperiyisgivenin Table 221, -Thosinle part bitcode can detect singlebitemos the “ bi tuitcannot be detected. Forexampl assume the even espe teT Co oe eter ea of received code word is odd, it shows that a bit receiveris 1001 1, the pant oe But ithe receiving coe Wrdis 100 tenth pean io ohne pay ofrecivecole4 ~ sitrcevestheblockof dataand checks the ‘The receiver cite 1e parity of rows and cx Parity anda. rere cage in he PAE of ONE TOW and on ‘hy iseran F ante poston of or termined by yy aang etus consider Fig. 24 “hey ror 00010 ot 011 0|1 < Parity eror 1000 1000/0 orto 10100 Tigo oroilt f arity error fig. 24 Block code with 1-bit error ‘There isa parity error in row number 2 and column number 3. The posi ovis shown inFig.24by dark shadow. This can be corrected by complemen! tho er bit fthere isachange of parity of more than one rows or column Ts ee umber System and Codes _ 445 Linear block code Fhe sie of linea codes bits, where = +r isthe number of message 1 a liber ofcheck bits, The block code is designated as (nk) code, The "whether the error is present or not withthe help of check bits are represented by a mattix recoding oflinearblock codes Linear block codes are represent Encodes thesizofthemessageand inthe ize othe ina oes code (n= K+). The block code C isobtained by the multiplication of message bits sid the generation mati MxG 2.28) white doing the matrix mltipication, MOD 2 operations are used. The generation matrix is constructed as Gath: Alen (2.29) canere is the identity matrix of order k and A isthe arbitrary matrix of order (kx. “The arbitrary matrix is selected such that the resulting code should be capable tno tan|bitemer has occured, as shown in Fig. 2.5 st todetect and correct errors at the receiving end C=MxG 100 TH10 O101 01 Tf eariyeror ie 011 0001 | 0 x 2.30) 1000 0110] 1 [C102 = Gy) = (MaMa «Mad Uh AY 2.30) 1000 1000] 0 For example, consider the matrix 119 1010/0 1 Fig2.5. Block code with more than 1-bit error and message bits are (01 1) "The linear block code C = (M1 x {G} Her the pry enor sineolnn nubers3 nd 4. This error canotbe cone (Ma: AT because there is no information about parity error in rows, and hence the postin of error bits cannot be located. 100 5100 : =[011)x{ 010: 101 2.9.12 Error-correcting Codes oor: tt The ing codes se rmccra esi codes canot define the poston of an error and cannot ome Tce snedoracoe which can detectas well as coret ther detect ion capability ofa code depends on the nuke of entra bits that are added ina message to get the code words, which increasestt distance between adjacent code w Ha isthe shortest distance between any tage nt distance of coding shee dyin the numnber of errors that canbe two distinct codes. For a minimum distan that can be corrected is (dgi~ 1/2, is (djr~1)and the number of ene =(0x11X0@1x0,0x081x1@1x0,0x0@1x081x1, 0x1@1x1@1%1,0%01x0 1%1,0x0 1x1 61x11 =10©080,08160,08081,00101,00001,081 81] =[011010} Decoding of linear block cades The receiver circuit receives the linear block ‘code of nbitsitdoes not know the transmitted message. Thereceiver checks whether ‘or not an error is present in the receiving message with the help of an matrix, The receiver circuit calculates the parity check matrix, H=(A":1) aera ‘ee isthe nity matrix of rer ran Tis the transpose fmt A, ye ak aaAVG. Digital Mectromies ‘The parity check matrix, H, and the transpose of the received mae snug ti dsted wheter theres SHEE SCOT orga trultiplicaton (H > R) is zero, then the receiving MeSSABe is Correct, cg there isan error in the receiving coe. hig Error correction The error correction capability of a code depends, ‘minimum distance. For a (6, 3) block code, minimum distance is 3, it cay Stentor and coat herr. The cometon proce 8 8 flog 1. ind the syndrome matrix. Itisa row matrix and is calculated as S=RH™ 4 xy ‘where Ris the received code of order (1 x1), HTis the transpose of check matrix H of order (07) ™" 2. Match the row matrix $ with the ow of. The number ofa 109 Whe, match occurs gives the eror poston. ‘ For example, if matrix § matches with the third row of matrix 7 then the ey is at the third position ofthe received message. Forexample, letusassume that the messagerectived by the receiver R=01 jy and the matrix ‘The parity check matrix His calculated as follows: 111: 100 H={AT:1)=|001: 010 011; 001 R= [011000] 111: 100 xR =1001: 010] O11: 001 0 1 wel? 0 0 0 =10@101600080, = 010} (xR) is notequal 107210, . —— __ uber sytem and Godes_ : : serxst'011000}! 0 = 100181 ©06080,08001808060,08161 02080) =(010) Syndrome matrix S matches with the S® row of H which shoves thatthe errr ixartne 5" postion in the received message R. The correct result is obtained By woking the complement ofthe 5* bit ofthe received message R. Conrect received message =01 1010 Example 2.34 Find all the code vectors for the given generator matrix of & (63) block code, 100: Ow G=|o10 : 101 oor = 110 Solution ‘The linear block code C= [M] x {G] 100: On sine M=(000},C={000}x|010 + 101 . ool: 110. @0x080x eos italy — M=(001),C=(001);x1 oa a 100 = ot] eprt.c=(01Nx/O10 101) =101101 [oor : 110] fio: o1 wa(100,c=1100}x]010 + 191/=1100011) oor : 110) fioo : Olt) wepo1.cetonx|o1 = 101/=[01104 oor : 110, 100 : OW] me(110,C=(110}x]010 : 101] =[1 10110) oor: 110 | 100: 11] | Taiiee ie paca let iow aa an | ‘Hamming code araming code detects the eroraswellas locates the position of the error, state rococo. scons ding parity bitsinan-itmessage ‘et of Hamming code i 1, hee isthe numberof parity bis aden nessa Thenumbeof pty bit depends upon the umber of messages Fa message, thenumber of party bitsisk, Te value ofk must be chosen suhthi Montel For at mesa he ramber of pry bi i 3. ation parity bitsinthe Haming code cores gos ponds toan ascending tw0(2,2122),.) Te hesnot iy band nage bts genes by Me Be! he, 2B Binar yuival 0 1 H oe Ment 11 110101100 ont oi oot Hanmig 6 wi Al Hg 5 a parity bits Ps, Pa and P, depend upon i 7 Procedure to assign the vale tothe pay big ig 2 message bits: TH * Find the binary location of the mal E28 folly: = Check the position of 1 in the big * Check the bit’s location, which equivalent of parity bit, hy the binat?, rer System and Coes For example, assign the value t P inary Tocation ofthe parity bit Py is 001 + position of 1 in the binary equivalent is Py 1 postion of 1 at dis found in bits Ma, Ma. Mi, Py roceven parity, Hamming code assigns the value to P, such thatthe pasty of Ma Mae Min Pi is even. + rod parity, Hamming code assigns the value of Py My, May Mi Pr 8 0 such thatthe parity of ‘Assign the value to Py + Binary location of the parity bit P; is O10. + Position of 1 inthe binary equivalent is By, 1 Position of 1 at by is found in bts Ma, Mas My, Ps For even parity, Hamming code assigns the value to P, such that the parity of MaMa, M,, P2is even. ‘ror odd parity, Hamming code assigns 1 Ma Myo Mis Pa is 0d. the value of P, such that the parity of Assign the value to Py ‘Binary location of the parity bit P3 is 100. + Position of 1 in the binary equivalent is b. «+ Position of 1 at by is found in bits Ma, May Mas Ps For even party, Hamming code assigns the value to P, such that the parity of Mg, Ms, May Pyis even. ‘ror odd parity, Hamming code assigns the value of P, such thatthe parity of Ma, May Ma, Pyis odd “ct the receiving end, the Hamming code bts are separated as message bits and parity bits. The parity ofeach group is checked and it assigns the valle as O ifthe purity iscorrect, otherwise itassigns the value as 1. Ithe assigned values ofall the froups are zero then there is no error, otherwise there is an error. The position of an errorin the receiving messages defined by the digital equivalent of (Cs, C>, Ci). ‘where C; is assigned the value of group one (Ma, Moy Mi, P;), Cais assigned the value of group two (M2, My, Mf, P:), and Cs is assigned the value of group three (Mey Mss May Ps). Example 2.35 Determine the single error-detecting code for the message code 1011 for even parity. Solution Given message code is 1011. (i) Find the number of parity bits () required ecek Dentkel Deaektl 30 prone Bg Be By aaa umber System and Gobe_ 1 it number i 1 101 100 O11 gig Gi) Position of parity bit Binary equivalent Bit number By By By Be Bs By Bs Br By Paris pisaryequivaleat 1001 1000 O111 0110 101 0100 0011 0010 0001 Party its «| Bh. eee aaa Mi My, a ee PMP, Pi Messagebit Ms ‘Hamm M; Px My Ms Hamming © pissschthatthe parity of acodeiseven, | cach hat the parity of (Ma Ma, Mi.F,) 8 even i ol ar assign the value 1 P2 Such that the parity of iy Assign the valve to the parity bits such that the parity of the code is od party of (101 P3)is even, P2=0. Assign ts a ‘Assign the value to P, such thatthe parity of (Ms, Mg, Ma, Mi, Pais odie. My,MzsP3)iseven, ic. party of Ig) y8 | parity of (1110 P,) is odd, P, =0. Assign the value to P2 suc thatthe parity 4 ‘of (My, M3, M,, P2) is odd, i.e. parity of (100 P,) is odd, Pa: Assign the onus to Ps such thatthe parity of (My, Ma, Ma, sod je. paity of (10 Assign the valu tothe parity the value to Pi (UPpiseven, Pi MyM, Pp isevens ie to Pa such that the party of (Ms iseven, Ps ss i ‘The Hamming code forthe message (1011) i610 if apis odd, P= 1. Assign the value to Py such that the parity of (Ms,Pa) is rror-correcting code ‘5, parity of (1 P9) is 044, Py =O. ample 236. Avansnitersesasinglceor-comecting cod foe meng : fale evenage eens sega 11010,chg | ra Fo forthe message (11010) 8 101011000 and coret the ero. es SOLVED XM as Solution Example 2.37: Perform the following: “The message atthe receiving endis 1110101 (i) The format of Hamming code is Mg Ms Ma Pa ee eas Seve FAD24 sa iy Check the parity ofthe group and assign the value to Cs, Cand Cy, Cee eect Parity of (Ma, Mo, My, P,) = Parity of (11 1 1)= even, hence C; = 0. (e) Encode the binary word 1010 into 7-bit even Hamming code, Party of (Mi MG, My, P2)= Patty of (1 11.0) #even, hence C, =. ain arity of (Mz, Msy Mz, Ps) = Party of (1 1 1 0)#even, hence C; “a (5531)p— 32614 + (100),0 CCC, =(110)40and therefore, an error is present atthe position oft ‘Convert octal to decimal: decimal equivalent of (1 10) =6 (5531)_=(2950),oand (3261),=(1713)j9 (refer octal to decimal conversion) CConectinessage is 1010101 (5531), ~ (8261), + (100)19= 2950)i0~ (17130 + 100)i0 = 03370 Example 2.37 Determine the single eror-correcting code for the message (0) Conver: tae eae i aie6, ane ictiieaeed, “The integer part of (19.75) ois 19 and its fractional partis 0.75. ‘ Conversion ofthe integer part of decimal numbe; Solution Given message codes 11010 (Find the numberof parity bit (A required denskel este kaa ‘The length of the message =, ntk=544=9 (9)i9 = (10011). (a) (5531) ~ G261}s + 100).0 M PoP)ae ea te inane —— oa i part decimal number: “a nf aco umber System and Cd heaion Sa oo wees *MsB 2's complement representation of (17 ; complement representation of (-17)9= 2's complement of (+17) oie 1 +LsB = 1°s complement of (010001) + 1 ie = 101111 ring +12 = (HOO 1), ( frample 2.40 Perform the following subrractios using 2's complement ai (FADD - method titel 4x6 + 1516" = (62674),, {i (0011.1001) = (O001.1110) Gi). Fp She Solution i) 011.1001 —0001.1110 1's complementrepresentation of number I's complement of (000.1110) 110.0001 *s complement + 1 s complement of (0001.1110) + 1 110.0001 +1.0 2's complement = numbers into decimal: wert the following Example 2. ji) (11001101.1 ouecp) — a) | ND; ee ti) Gn, Zina Binary addition : 011.1001 A 1001 0011 1000. 0111 + 1111,0001_¢ 2's complement of B (938.710, +1111,0001_ x24 0x2! + 1X24 1X2 +0X 240x284) SO : 41X24 1X D+ 1X27 +1 x2? LE ee Result i car Solution i) 19010011 1000.0111(BCI iy (1001101.11Da= x dep 444846441 nga ee ae oe aici = 205875)i0 ‘seat es Eas v4 : Gi) (CE S)5= 15x 16+ 12x16! +5 x16" Given message code is 1010. i‘ i = 2073125) (i) Find the number of parity bit (&) required Gv) Q2)g=4x543.x5! 42x57 dentkel =o edektl Example 2.39 Write the sig jtude 1"; Yt pt k=3 cage Eee 's complement and 2°s complemes Tie hee e 495 (i170 Position of parity bit fy Solution () +95 =(+95)io= (1001.1), Spenappne rennin of 19.9) = 01001. 1 Seomplnest representation of (49) = 01001: ‘complement representation of (+9.5) = 01001.1 Gi) (79 = (Lo000), Pinna reeseniaton of 17) = 110001 of (-17),pean 0 sta te Ty OF 1, Assign th “101 s) is ever Pa = 0. ; ve, it HEPAT message (1010) is LOLO010. erage eae PO Seg | Temes 0101010 SUMMARY sate mmber of synbols sed; MIME system, ‘sont iso ax ae HE >~ cima nme syste 5 pay mabe 5 oa mumbe ste Sema ae 8 ema pein ny nr das Te information given by compere 0 va Cae a hina eos mun. hee a de se emis atiy emer mUNbe on on eggs pant. » aa woe methods wet represetsgn-inary numbers 1 sign magnitoe representation 2, re emplement representation 5.2 complement represeiation «Insignia epesnation, te mos significant it represent he sin ae ps epesent its magica. When the most significant bts sreivcguve and we the most significant bits 0, the sign is poste «the ['sconplenent of binary numbers obtained by subtracting each bitty fuer fo 1 The I's complement of Ois 1 O= 1 and the 1's complemen Tis1=1=0 «The 2's complement ofa binary number is obtained by adding 1 to the Is complement of the ins) number. The rules of binary addition are given inthe following table. A B__[ Sum [Carry a y 0 0 0 1 1 0 1 ° i . be 1 0 1 * The rules of binary suk binary subtraction are given in the following table. Borrow 0 1 0 0 amber Sytem and Codes _ Subtraction of a binary number B from another binary numiber Ais equivalent to Subvigtion of 2's complement of Band A, ie. (A ~B) =A + 2's complement of B «eitne commonly used binary codes are classified as 1. Weighted codes 3 Self complementary codes 3. Unit distance codes 4. Alphanumerieal codes 5, Cyclic codes vor detecting and correcting codes ‘s-There are two methods of BCD subtraction: T'BED subtraction using 9°s complement J. BCD subtraction using 10's complement “e-zhe 9° complement of decimal number is obtained by subtracting each digit of the decimal number from 9. «he 10% complement of a decimal number is obtained by adding 1 with the 9's TBmplement of the decimal number. «tne Gray code representation forthe decimals 0 10 15 is given in the following: He eee Gray code Decimal Gray code ‘ict |G |G 1G | & | “ee |G |G |G | Ge an Ce es ee ee ial SOs Dao a 9 | dy lode jaa go Peel a ee aoe on) roe ee ae a wooo er (0 a a PO Var ial fa Oe fis all eh ees dead feamay)s eat! goon gel sana eof eute| sta ian ia tie aaa pn | co fect) ont] as se semmmmmmemms KEY TERMS AND DEFINITIONS Smee Number systems A number is « collection of symbols. Each symbol's value is a function ofthe type of system and its positon. All the number systems are positional because the value of a symbol depends upon its position, jgned binary number ‘The numbers with a positive or negative sign are known as signed binary numbers. 1’s complement representation The 1's complement of binary number is ‘obtained when each bit of a binary number is subtracted from 1. 2's complement representation ‘The 2's complement of a binary number is obizined by adding 1 to the 1's complement of a binary number. ‘Codes It is the epresentation of information in a particular format. The information ‘may include numbers, alphabets, and symbols, which men and machine can recognize. Al the computer systems understand only the machine code, the basic property of ‘machine code is binary in nature,poniss_— iit Be It is the 4-bit bi a oo pcp code) Naty cog, i cod Prapreteand by 4b, oe edo O01 ON eee "ty Beith etal a wee coco il inber i oe Bene oak arnt ee eae TAT ee we FY STP eto “ay, be sonia lof Cit. The me nal number is repres ee Fr Te oie dein mer epee yal am co te iE BCD cose, CAC i of deny ge imi ach odes ae known. 86 Sit BCD oy hy tena eed swe foe string te 807 Magnetic ype fh i anc sina ii ©)- Ever code OUP has wo I, Theatr hc ote wel fore detetion, Py ease wisn vied THU BCD coe. Each digit Of the dina Lepoel we 7 bits are divided into two subj by 7 inary gis. The BrOUPS, G i nent Bb) nd re ws SH Ce i mamer = jas of only one 1. This code is also known as sy Eh sabrupconsss of Hl mas soe coe. reseSowde [BCD cade or by ang 3 t0 each di Gayeoie Gay codes: 4bnuneic cn; decimal numbers 01015 ae Satna cle. This cole is aso known as unit distance code becaute jy ect co iflerin nly 1 bt poston. The Gray code is an unweighted ca, Ah br pos inte cal rp do no have any specific weight assigned io th, rordetng codes In cgtal communication, tbe digital data is sen ov ee telephone lines wing feet inary codes. During the transmission, becases tvs sil, muy Become ToL may Become O and an incorcect information my be vd atthe desinn. This problem of communication is overcome by wi rordetetng codes. The simple eror-detecting codes arc: (i) parity codes and (i ‘lock parity coves. amofifed BCD coe. Tis code is obtained by adding 3s gy, git ofthe decimal number, I EXERCISES Review Questions 1. Whats the adi, unter jase ted inca of dina, inary, otal, and heradeciaa ot ; 3 What do you mean by ‘sal and hexadecimal numbers over binaries? ‘subtraction with sui tion with vitae Number System and Codes 4277 4, Explain the role of codes. \What is BCD code? What are the rules for BCD addition? Explain with suitable example, What is excess-3 code? Explain the rules of addition of two exeest-3 code numbers. Find out the BCD, excess-3, and Gray code forthe decimal numbers 0 t0 9 |What do you mean by self-complementary code? What are the two self complementary codes? ‘Write the Gray code fora bit binary number. xy code? Give the advantages of Gray code over binary code 10. 1 12. 13. What is 14, Explain even and odd parity codes. 15, Write short notes on the following codes: (i Excess-3 code (ii) BED code (ii) Gray code (iv) Unit distance code () S:bit code (si) Biquinary code ‘What is a linear block code? Derive the mattix equation relating to K-message bits, neoded message bits, and the generator matrix for a linear block code. 17, Explain with examples, how Hamming code is useful for detecting and conecting errors in digital data transmission. 18, Design a BCD to Excess-3 code converter using truth table, K-maps, and logic 19. Design the following code converters: () Binary to BCD (Gi) Binary to Excess-3 (9) BCD to Excess-3 (vi) Binary to Gray (ii) BCD 10 Binary iv) Bxcess-3 to Binary (vi) Excess-3 to BCD (ili). Gray to Binary Problems. 1. Perform BCD addition of the following numbers: @) 24436 Gi 08 + 10 Gil) 106 + 305 2, Perform the following additions of BCD numbers: (@ 801 +205 Gi) 99+ 10 3, Perform the following subtractions of BCD numbers using 9s complement: @ 9-2 2-9 Gi) 33-77 1-3 4. Perform the following subtractions of BCD numbers using 10°s complement: @ 1-3 3-7 Gi) 36-69 ) 69-36 5. Perform the following sublractions using (i) 1’s complement method, (ii) 2's ‘complement method: (11010), ~ (10000), Gi) (1000100), ~ (1010100). 6. Perform the following operation: (738), (123) + 100)jp aoe $ 7. Convert the following decimal numbers to binary: Aa spats (© (1206259 i), 120828),9.0 8. Encode the following binary words into 7-bit even parity Hamming code: (i) 1000 i) 1011 #}lowing ss TRUE/YESION represent lope | anf tg My ‘sa events can be recogni these logics associate Wi Inbinary logic, the event represent logic 0 3.2.1 Principle of Logic Circuits ran aga dines dileentogcl oes, eS erties, Bovkan ls ch ae krownas oil ccai Te tang tem gal onc Both net and oui ae Sa tia eli. Switching ect one ofthe ext xan ce ichingSeuitconissof evOTAZesOUTCe, switches eS a seed sachs represent Boolean variables. ON and OFF ety Hefeped tas ogc 1 and logic 0, whereas close and open states eye {signed as ope Land logic O respectively aig ‘Hau kewsaswitching cil TheswitchesAand Bae connec and the lap ners withthe source. The witches A and B repeses ‘arial andthe lp iste out asiable. Te lamp wil be ON Gee theswiches And Bae oowloranyonetheswtchis closed othe, SL Ce ne ERM ean ea ts Qise L_Asswiteh v eee | Fig. 3.1 Switching circuit Table 3.1(a)_ Operation of circuit Table 3.1(b) Truth table [seach a [viene [nae] [Toa 3 a oven | OFN | OFF . 0 0 oven | cuose | ow ; i i cose | on | ow ; és i ciose_} cuose | ox i : Open = ogi 0, Close = logic 1 ON = ai 1, OFF gio 3.2.2 Boolean Constants, Variables and Function Boolean algebra differs in a major way 3 input/output terminals ofa circuit. The Bogjees VL Present on a wire or at or logic 1. These 0 and 1 are known as Value of variable is either Io ‘Boolean algebras relatively easy war on ateONsans, because of only two values. In Boolean, negative numbers, square 1001S, cube roy are only three basic funetions, that is Boolean Algebra and Loic Gates 439. ‘These basic functions are called logic operations. The cicuits, which perform nese logic operations, are known a gates, The gates can be constructed from diodes, transistors, and resistors connected i such away thatthe cireuitoutputsthe result bfbasic logic operations performed on the inputs, Letus describe and analyse these basic logic operations ‘OR Operation ‘me switching circuit shown in Fig. 3.2 has two switches A and B, which are connected in parallel and the lamp in series with the source. The lamp iseither ON Gr OFF depending on the state of switch A and switch B. Assis A q ae | There are four possible states ofthe switches: (i) BothA and B are open Gi) A sclosed and Bis open. Gii) A is open and B is closed. (iv) Both A and B are closed. ‘When we think logically, keeping basic ideas of electrical circuits in mind, one can conclude that out of four possible combinations, the lamp willbe ON forthe case (i), ii), and (iv) and it will be OFF for case (i). In other words, the lamp is ON if either switch A or switch B is closed or both are closed. Significance of this logical Statement lis in the words ‘either... or’ which simply represents ‘OR® operation withthe symbol +”. The Boolean expression for this switching circuits. AORB A+B “The operation of the switching circuit shown in Fig. 3.2 is summarized in Tables 3.2 (a) and (b). BL) Table 3.2(a) Operation of circuit Table 3.206) Truth table ‘Switch A_| Switch B | LAMP me ‘OPEN | OPEN | OFF ° ° 0 open | cose | on 0 1 1 ciost | open | oN 1 ° 1 cuose_| cuose | oN fs 1 1 (pen 0, Closed = 1, ON =1, OFF =0. x AND Operation Inthe switching circuit shown in Fig. 3.2 the switches were arranged in parallel, ‘whereas in the switching circuit of Fig. 3.3, they are arranged in series.492 Digital Hectronics sey . mea i Fig. 3.3 Switching circuit for AND logic ntsc gram, amp wilde ON 001 bh ey closed, otherwise the lamp will be OFF. This logic is known as AND jog: My Nae eee peonexesson fr AND operant mt Yeap 03 ‘The behaviour of AND operations summarized in Tables 3.3) ang, , Table 3.3(a) Operation of circuit Table 3.306) _ Truth table ‘Switch A_| Switch B | LAMP. A cap ‘OPEN | OPEN | OFF 0 ° 7 oven | ciose | oFF 0 1 ¢ ctose | open | om 1 0 é ctose_| close | ON 1 af Open =0, Cloed= 1, ON= 1, OFF =0 NOT Operation ‘The switching circuit shown in Fig. 34 has one switch and a lamp. Whenever switch is open, the lamp is ON; and when the switch is closed, the lamp is OF because the current always passes through low resistance path. This operation Known as NOT operation. As per standard notations, output Ys not equal tings ‘A. This means that Vis equal to the complement of A. This can be expressed fed Gy) ‘The operation of the circuit shown in Fig. 34 is summarized in Tables 3:4 and 3.4(b) Table 3.4(a) Operation of circut (Switch a] Lamp wii OPEN | ON ciose |_oFF Table 3.4(6) Truth table al A_ | ¥ea 0 1 o 1 Fis. 3.4 switching circuit for open = 0, Closed = 1, ON = 1, OFF =0 NOT logic A Boolean Algebra and Logic Gates 439) 43.2.3 Basic Laws of Boolean Algebra “The basic Inws of Boolean algebra are given a: () AtO=A ow Gari 63) (ii) AtA=A oo) en G8) 69) 6.10) (iti) AA =0 Gan) In Boolean algebra, the value of a vasibleis either logic 1 or logic . proofs of Basic Laws of Boolean Algebra Gi) A¥1=7 Oral 14t=1 Hence,A+1=1 Hence, A.0=0 (ili) Av A =? Hence, A.1=A Hence, A. A 3.2.4 Boolean Theorems Boolean algebra can be used to analyse a logic circuit and express its operations ‘mathematically. It plays an important role in digital system design. Boolean theorems help us minimize the Boolean equations. The basic Boolean theoremsare listed below. They are also known as single variable Boolean theorems cor basic Boolean laws. Law LA+0=A Law 5:4-0= Law2:A+ Law6:4 ¥1=A Law3A+A=A — Law7:AvAsA Law4:A+ A Law8:A. A =0 Boolean multivariable theorems involve more than one variable. Boolean algebra supports the basic laws of ordinary algebra such as: (1) Commutative law, (i) Associative law, and (iii) Distributive law.4 ectronics 4 “ommutative Law Fee a spat bcerkisi bo rctien Ga oman m0 Law9:A+ +A Pew ited:A “Associative Law ssc hw seta the aouping of Variables in AND o, op & doesnt affect the esl Law I:A+(B+O=(4+B)+C Law 12:A+(B-Q=(A+B)+C Distributive Law Distributive law tates that muplying term-by-term in just the same We "ya inary algebra can expand an expression. Lay 13:4-(B+C)=A-B+A.C Law Ids(A+8)-(C+D)=AC+AD + BC + BD Law IS:AB+AC=A- (B40) 135 0 (AA =a) q 4 (142-0 Gia amin =(A+B\A+ A) _ AA+AA +AB+ AB A+0+AB+ AB Oy Gn (AR = and AA=A) Example 3.1 Prove the following Boolean theorems: oy ne ane aad (@) AFBC=(A+B)(A+Q) () AB+AB= eo () A+B)(A+ B)=A Aa i AB sa 3 © a @ A+ Ape eh Oa A Data + AB=(A+B) () AB+AC+BC=AB+ AC © AA +e)=4B Soltion @) AtBC=Us A406) (2 B+ B =1) [A+B | 4sC] Atac (A+ BYA+O0 | ane e 0 sPohsrail” 0 @) A+B A+ B)=A 3 F aa 7 7 (A+B\A+ B)=AA+AB +AB+BB ees! 7 A+AB +AB+0 _ igs 1 A(L+ B)+AB CURR SS ie feaaiie 1 A+AB Li | 4 1 jl A(+B) +B=1) a ih =RHS. e re i () AB+AC=A+OG +R _ + (A+O(A+B)=AA + AC+AB+BC 0+ AC+AB+BC AC+AB+BC+1mnie 2 aB+ AC+BC(A+ A) p+ AC+aac+ ABC ascarid AB+ AC us aa hts: {A,B C,D)=ABD+ABD Soltin Y=ABD+ABD WA,B,C,D)=AB\D + D) =AB-1 B Example 3.3. Simply the following Boolean equations () MAB. C)=aBC AB +4Be Gi) A,B,C, D)=ACD+ ABCD Solution @ 14.3.0) =ABIC+ 0) Je HABA TB © %A.8,6D)=AcDsapey = CDi sm) Wehave seen that 4.475 Fax. ABCD) =Coasg \CD+.BcD oolean Algebia and Logie Gates 41972 Example 3.4 Simplify the following Boolean equations C+aae ABCD +4 E+ABe Cus (since 1+B=1) Gi) Given Boolean expressions BD (incec+ C=1) 3.3 OVERVIEW OF LOGIC CIRCUIT Logie Gates Logie gate is digital circuit. Ithas one or more inputs and only one output. The inpu(s) andthe output of agate is logic | orlogicO- Here the word ‘logic’ is used because the values of I and O are not fixed. The gates, which perform logical OR, AND and NOT operations are known as basi gates. Any Boolean expression can be realized using these gates. Truth Table Atruth able is ameans to describe how the output of alogiceireuit dependson the logic level present atthe inputs). The table lists all possible combinations of logic levels present a the inputs) along with the corresponding output. There are four entries for the two-inputs truth table, eight entries fora three-inputs truth table, and o on. The number of input combinations will be equal to 2 for an N-input truth table The list ofall possible input combinations follows the binary counting Types of Gates Listed below are the different types of gates: 1. ANDgate 2. OR gate 3. NOT gate 4, NAND gate 5. NOR gate 6. EX-OR gate 7. EX-NOR gateLe Sg en ary of logic gates as sone tocando ster Boolean - : ; rien Seca es Ces 198 expression sookean Expression for Logic Circuits | expression _| any logic eieult, no mater how complex itis, can be deseribed using Boolean -Avyessions. The gates are the basic building blocks ofthe digital systems Examples 1. Consider the logic circuit shown in Fig. 3.5. ‘Thecircuitconsists oftwo AND gates, ‘one OR gate, and the inputs to the OR fzte are the outputs of AND gate, and ‘AND gate. Since the inputs of AND. gate, are A and B, the output will be ‘A«B,andsince the inputsof AND gate; fare Cand D, the output will be C+D. Fig. 3.5. Logic ciruit ‘The output of OR gate is YA, B, C, D)=AB+ CD 2, Consider the logic circuit shown in Fig. 3.6. “Thecircuitconsists of woOR gates, one AND gate, and the inputs to AND gate 4 eS peaupaiet Ol greg Sieedanl Bare the inputs to OR gate), the output eS a oatbed eBiandsine Contacte °—)3>—S 0) lapis DOR gate, be output willbe C snp theeutpitef AND els (A,B, 36 Lonic cru Eye +B). (C+D), 4. Consider tbe topic ot shi in 2 ‘The cleat consists of an AND tnd u NOT gale, Wheaover a NOT gate is po ee A[B teas ste daca) é a [a reat NOT ae ate NC expressions simply equal tothe input "Fig 3.7 Logie circuit yor of1} 0 expression with a bar over it. 3 f ‘The output of AND gate is A « B, and. the output ofthe given logic diagram is ‘The operation of logic circuits is defined by B diagram can be implemented directly from the:eb SO 8g plemented FIE3:9 Implemenya. canbe imply an Booleanexprean Oy nga AND aston it 3.9 s AB+A anexpression Y=! ins three terms (AB. A meds ¥,=AB, ye isshown in Fig. 3.10, "Ty Boole Implement se Be 1 conti Tus exes ogee TH Joga ig ipsa Soe ees —_ = —_ —y tee eee = ABC} fa oa : plementation ofthe Boolean 3.10 I orate Fe eresion Y= AB + AC + ABC 3.4 DeMORGAN'S THEOREMS DeMorgan contributed te wo mest important theorems of Boolean algebra, Thy Deseret nce th Deora’ ist orem states tha he complement of sum of digital sign qi profits complet ie FBeCHAN =A B.C WN oy nother words whenthe ORing ofthe variablesis inverted, itis same as inventing ach varabeindviduallyandhen ANDing these inverted variables. Fig. 3:11)_ Implementation of DeMorgan's first theorem ‘Thesmallcitcleatthe inpatsof : i 3 fan hen gen AND go nett input signals DeMorgan's second theorem sates that the, ‘signal is equal tothe sum ois complement, ‘complement of a product of digit! ROWE, oy In other words, when he cach variable individually Rosle Algebra and Look Gates Nat = - p> Fig. 3.1116) Implementation of DeMorgan's second theorem Example 3.5 Simplify the expression G+O-+D) MA, B, C.D). Solution ‘Given Boolean expressionis WA. B,C,D)=A+0)-(B4D) Using DeMorgan'stheore YA, B, C, D)=(A+C)+(B4D) G.0)+@.d) (A.0) +B.) =A.T +B. Example 3.6 Simplify the Boolean expression: YA, B)=(A+B) Solution Given Boolean expressions. 3.5 STANDARD REPRESENTATION FOR LOGICAL FUNCTIONS Boolean expressions are also known as logic expressions. Logical functions are expressed in terms of logical variables. The value assumed by logical variables is inbinary form. The logical functions can be represented in two forms, viz. (i) Sum of products form (ii), Product of sums form 3.5.1 Sum of Products (SOP) Insum: ‘of products form, the Boolean expressions are defined by the sum of product terms. This form consists of two or ‘more AND terms that are ORed together, Each AND term consists of one or more variables appearing in either complemented or uncomplemented form.ores eapaBC + input B. The first ANI t 2 ete nan tera sai mc OY N (POS) juct of Sums ( aes 3.5.2 Prod ee Bann xeon a fined BY the prog nett oes er cor ta 0 OR LE, Which ht shen fof one oF more Variables in coy terms TH Oke cami maa fs leat fom For esa . reek Ti ft OF am contin ry 8 amon he varnles (A+B co spon : eh ei goer eB 346 MINTERM AND MAXTERM sron(421)sinte form ofsum of products, and the output is a fune eircom hme viable each termin the sum of products form contains all the variables (lie seatbeespesnshna stondard sin of products form or canonical sn products foranexchindsdualtem nstandard sum of products formiscay sinter. “The SOP fem cane conerdo standard SOP form by ANDing the tess theexpression withthe tems frmed by ORing the variables which are not peer in that erm athe complements. For example, YA,B,C)=AB+ABC +B G3] The first term of (3.23)hastwovaiales andthe third term has one vat abs eft. val Cismising:in the third term, variables Aa missing an hee gt te standard SOP form, multiply the first tem! (C+ C) andthe hind emby (A 2) (CG), ee i YA,B,O) NCSO)+48C+ Bus Zy(047) SOME ABC SABC ABT + Theta ninemsn ee? ARCH =m Aaya ABC(100)=m, TBogg a a BC+aBe BC ABC+T BC+ om ABC(01) ABC (000) =m Boolean Algebra and Logic Gates 44 Equation (3.24) can be written asa sum of minterms, as follows: YA. B, C= Dm, 1, 4,5, 6,7) each term ofthe producto sums contains al the variables, then the expression jsknown as standard product of sumsformor canonical product ofsumsform, a3 ‘och individual term inthe standard product of sun form is called as mater. “The POS form can be converted to standard POS by ORing the terms in the expression with te terms formed by ANDing the variables which are not present in that term and their complements. For example, YA, B, C)=(A+ BYA+B+ C) ‘The firs erm ofthe above equation has two variables, variable C is missing. and hence to get the standard POS, the term (C) inthe first term must be ORed. YA,B,0)=(A+B+C0)-A+8+ 0) (A+B Clas B+ TyA4B+ 0) 25) “The otal maxterms are thee, which ae (A+ B +0010) = (A+B +Tyo11) =m, (4+B+T)(001) =m, Equation (3.25) can be written as a product of maxterms, as follows: YA, B, ©) =TIM(, 2,3) For SOP, the uncomplemented variable corresponds to logic 1 and the ‘complemented variable corresponds o logic 0. ForPOS, the uncomplemented variable corresponds to logic 0 and the complemented variable corresponds to logic 1. The ‘minterm and maxterm for three variables are given in Table 3.6, Table 3.6 Minterm and maxterm for three variables a seo : of ol o 35C A+B+C=My Csaba ABC=m AxBsC =M, cl ses at a A+B+C =m, eae ae ab AtBsE om, | De | cs [ean ABC =m, AABEC=My 1 uaa ABC=ms — A+B+T = Ms sia (ett ABC =m ete de eae ABC =m cepiers for he fancton Beoiesn Agta and Lone Stes _ 7 te 2 sample ape “Tis equation can be converted nto standard POS by ORtng the first erm by (c@>), second term by (A), and thied term by (BB). a Zsad a.074B (A+ B4CKA+B+TYA4B+CXA+B4C) averted into standard SOP form by muy, a mine #0) (A+B+O1A+B +0) A+B + O)A+B+C)(T+B+0)A+B +O, Hach term of the standard POS is called as maxterm, ig +B (A+B401000)=My (A B4ZYOO1)= Mh = ABC(00) =m 2 a agcqon=m 450 GrarTwoy=M, A B+ CHOI) = Me ‘ABcao) =m, ABC(O10) =m “The expression in terms of maxterms can be written as ners of miners, the expresson Will YA, B, ©)=TIMO,1,2,5) 6) TA O=T0 245 3.7 SIMPLIFICATION OF BOOLEAN EXPRESSION 3 flloving Boolean fnetion into standard Sop gy ‘ample 3.8 Convert expres tin terms of miners. 1U,B.O=AB+AC +BC ‘The design of digital system is nothing but to determine the Boolean expression from the given information and to implement the Boolean expressions by using suitable digital components [.e. gates and flip-flops]. To reduce the requirements ‘ofhardware, itis necessary to simplify the Boolean expressions. Boolean expressions can be simplified using (i) Algebraic simplification, (Gi) Karnaugh map method, or (iii) Quine-MeCluskey method. Solution Given equations 14,8, =4B+AC +BC ‘Thisequion an cone ito stndard SOP by multiplying thefstey + (C+ ©), second em by (B+ B), and the third term by (A + A), MA,B,©) =ABIC+C)+AC(B + B)+ BCA + A) =ABC+ABC +ABC +ABC +ABC+ ABC =ABC+ABT +ABC + ABC ach tem of the standard SOP canbe represented by a minterm. 3.7.1 Algebraic Method Algebraic method is one ofthe simplest methods to simplify the Boolean expression. Inthis method, Boolean theorems are used o simplify the expression. The drawback. ofthis methodisthatthere sno way to distinguish whether the simplified expression isin ts simplest form or it canbe simplified further. For example, ‘Y(A, B,C) =AB+AB (A + C) ABCA) =m, ABT(110) = mg ABC(010) =m, (since A« A=0) be written as A,B, 0 =5n0,4,6,2) Frample 3.9 Convert the Example 3.10 Simplify the logic circuit shown in Fig. 3.12. cxpres hit ere of mani movin Boolean function into standard POS a! s WA,B.O)= (A+ ByB 42 5 Solton eo 4 Given equation is a YA, B.O)=(A +.) 4 B Fig. 3.12 Logic circuitpital Best us_Beln Be a Solution given logic ercuitis “The expression forthe yerthets f Solution a ABC, Ys=AB “Ouiput Ysa summation of miaterms mma. ms nd me. yoAB+ABC+AB Be m= 010-4 BC mp=100 = ABE me=l10 = ABE 2AB+ABC ‘Boolean expression in standard SOP form: WA,B, ©) =A BC + ABC +ABC +ane Example 3.11 Simplify te expresion: YA, B,D) = (A + ayy aa J ACE +B) +ACB +B) =A 4AT Solution Given Booleanexpressionis YA, B, D) =(A+B)(A+B+D)D EA +a) =(4+)(AD+8D+DD) in =(4+)(AD+BD) (since DD =o) Example 3.14. Sicaplty te follwing tateevariibls Greene =4A4D +4BD+ ABD + BBD si ee eae : = ABD+ABD+BD (since A = anda Solution | oe eee =BD(A+A)+BD (Output ¥ is a summation of minterms mp, mt, mma, ma, mm ac M- =D +BD (ince A +a=1) =D my= 111 = ABC Erample 312 Sy tefolovng eve expen sng Bi Boolean expression in standard SOP form: : 8 nti i 8,0) =ABC+ABC + ABC +A.BC + ABC. YA, B, C= 3m 0, 1,3,4,7) ae + ABC +ABC + AB Solution =4RC+0+4BC+0)+ABC+0)+A8 Output Visa summation of misters mm, ms, and my. =AB+AB+AB +AB meme my = O11 = Hae 4 2A@+B)+AB +B) me10=ABC melt =agc a Boolean expression in standard SOP form: WA, B,C)eer AaB eC +B+OKR+ B +e) a+ B+oK Rh ie rc. ~ eM cobs BBSCB+AT+ BCT @, 14,8 O- UAT 4 ABeBBHBCHAC HBC, (Aa+a Be m sumac ciphapace ne ores Beto or ABY eh Bi ar, a Far TKATB)+ ACs Tayp vue cyeaedy+ CBK (B+) 4AtCBKA + AC+E astand oo (A+) 1A.B.O= 1A. ae na BO=A+CBKA +E) wangagaakoreeen” Wa,B,20+AC +4 pate 1a,8, =AC +(AFDCB WA,B.O= AC+CB 3.7.2 Karnaugh Map Simplification tied: "pete implication mead sa drawback that teres 0 easy Way ty es ei el enericnin sd fet Ts problem falgebraesimplifation methods overcome in Kamaugh imap Knap) sina, f : enc apical cigs to simply Boolean expressions. It provides a is 0;thetermof group 1 is CD. For group 2, variable Aand variable Bis O or 1s and they are eliminated, Cis 1 ‘and D is 1; the term of group 2 is CD. The simplified ‘equation isthe sum of these two groups, it. Fig. 3.33 Kemapae tele. sn eilone ats ‘Me same logic can be extended to 16, 32, and 64 adjacent Is, The procedure simplify the Boolean expression using K-map is 1 Represent the sum of products expression on a K-map, 2, Form the groups of possible adjacent 1s a8 8,4,2, 1 3, Write the Boolean term of each group, ‘4, Write the simplified expression in sum of products form. { “Fig 3.34 Kimap ‘éxample 3.18 Minimize the following expressions using K-map: (a) YA.B,©)=2n(1,3,5,7) = ABCD +ABCD+ ABCD + ABEp OA Oe oe B DAR c= Em(0, 2, 4,6) A BcD+ABCD+ABCD Bey} MA,B. C= Em00,2, 4,6) ACpe+B)+AC Tenis Solution CODY B)tACHB+B +A CDGB)sreyy | a) WA. B,C)=2m( 3.5.) Aeb+ATD+ Acb+acp si “The representation of SOP by K-map is shown in Fig. 3.36(a). Foic+0)+AD(C+C) eee Y(A,B.O=C =D(A+A)=D es Fig. 3.36(a) YA, B,C) = Em{1, 3, 5,7) ‘hsexpesson canbe directly obtained from K-map by using the fy procedure: = (b) YA, B, C) = Emi(0, 1,4, 5) “The representation of SOP by K-map is shown in Fig. 3.36(b). 1, enfant Is eet valveo the variables associated with thea the varies thos ate Oo wil eliminated. Other variables wl in ANDed frm, In his form, the variable 4p wilbeiauncomplementedformifitis Land cj 00 01 inthe complemented form ifs 0. 00 7 [ Talo 2. Ifthe groups are more than one, then the 4 a epatectorcicn ©! 3.3616) YA, B, C) = Em(0, 1, 4,5) Wiseman Besimpedention 1 © YA, B,C)=Em(0, 2,4, 6) in ct frm sobained by ORi 0 ene ceaheee wyORing | “The representation of SOP by K-map is shown in Fig. 3.36(c). ait loing example, Fig, 3.35 Kan oo _o1_1_0 ager na 1,CisOor 1, Dis0 or 1 and they are elimina 9 YUB.O~ i Ye : meee Intheabove, Fig. 3.360 iA, 8, O - m0, 2, 4, 6) Example 3.19 Minimize the following expressions using K-map: (@) YA, B, C)=Em(0, 1,2, 3,4,5,6.7) int (b) YA, B, C) =Em(0, 2, 4) ci ‘sfoundthaySS™#OUPSOF2 4 and 8 adjacent Is are considered, anety s. pista Bee x sotution (a) YB se K-map epresenaton sh 3,4,5:6-7) 5. cp=3m00. 1s fown in Fig. 3:37(a. YAB.O=1 ig 327 WA @ = Em0, 1,2, 3,4,5,6,7) (ey 1,8, C= 20.2.9) map represen shown i FB: 3. 370), 4 vida, =70+FC ieee Aca Fe 3570) WA 5 “0 = Bmi0,2, 4) srample 320. viinine te folowing expressions wing mar Mey AB, C,D)=Er(0 12,3, 44546, 111510) (0) WA.B,C,D)=2m0, 247,810.12 19) Solution oa heb, C,D)= Bf 1, 23.4 5.6.7, 119 1) se Kamp representation is shown in Fig: 33800, 4+ BCD + BCD + BCD Fig, 3.3810) YA, B,C D) = m0, 1,2,3,4,5, 6,7, 11, 314) ‘The simplified Boolean express is YA,B,C,D)= A +BCD+BCD+BCD (0) YA, B, C,D)=¥m0,2,4,7,8, 10, 12, 13) ‘The K-map representation is shown in Fig. 3.38(b). _ apse ITT er cean Beolean alge and Logie Sates _ | y-CD+BB+ABC+ABCD fig, 33000) YA, B,C, 0) = Emi, 2,4 7,8, 10, 12,73) se simplified Boolean expressions WA, B, €,D) ED +BB +ABbC + ABCD rample 2.21. Minimize te following log fnetion using Kamae "1B, C,D)= S(O, 1.2.3, 5.7.89, 1a 14) and implement it using logic BES Solution The logical function is YA, B,C, D) =2m(0, 192.3, 5:728.9 11,14) rhe K-map representation is shown in Fig. 339, ‘The simplified Boolean expression is YA,B,C.D)= 4B + AD+BC+BD+ABCD -thi expression canbe implemented using AND, OR, and NOT gs Fig3.29 YA,B,C,D) = Zm(0,1,2,3,5,7,8:9: 1,14) eee oe OR Fig 3.40. Implementation of WA, B, CD) ~ Asample 3.22 Minimize te followin 198 fonction wy ra sing Ky A,B,C, D)= 20. 1.2. " and implement it using logic gates. 4.7.8.9, 10,11, 12,14) Solution ‘he logical fonetion is A.B. C.D) = 3m, 23.4.7, 8,9: 10,11 12,14 tue K-map presentation is shown in Fig. 3.41 Ot aE ofall uw 7 a wu Fig341 A,B,C, D) = 200, 1,2,3, 4,7, 8, 9, 10,17, 12,14) D+AcD+4ap ‘Simplified Boolean expression is YA.B,C,D)= ACD+AD + D +B “This expression can be implemented using AND, OR, and NOT gates go Fig 3.42. Implementation of 1A, B,C, 0) = B + TD + ACD + ABD Example 3.23 Simplify the following Boolean expressions: (a) YA.B, C, D)= Dn, 2,5,6,8,9) (b) YA. B,C, D)=Bn(0, 1,2,3,4,5,6, 11) , Solution (a) The Booleanexpressionis YA, B, C, D)=Em1,2, 5,6,8,9) “The K-map representation is shown i Fig. 3.43(a). a " oN wo ot h YAB.CD)= AEDs RCD 4ABT 1 a Fig 3.43) Boolean Alga and Log Gates SN6S. (py The Boolean expressionis WA.B,C,D)=Em(0,1,2.34,5,6 10) - « K-map representation is shown in 3.4300). -The simplified Boolean expression is ABCD) AB+A D+BeD Fig 3.4300) xample 3.24 Minimize the following Boolean expressions SN K-map: B+CB+C () MA,B,C,D)=ABE +BCD+BCD Solution Sem: fhe given SOP isnot ina standard Form should be converted into standard SOP. sep 2: Weite the expression in terms of intr, ‘ep 3 Represent the expression by K-maP. Sica: Form the groups of posible adjacent 1s a8 8,442: Sep 5s Writ the Boolean term for e8ch E100P sr Write the simplified expression n sum of prot forms (a) YA,B,C)=AB + CB +C see ipa hrce-variable Boolean expression Variable Ci missing 8 fist term, Ais missing in the second term, A and B are ‘missing in the third raserad the expression is notin a standard form ANDing the fis \e5T ‘with (C +0), second term with (A +A), and third term with +”) (+B) the standard sum of products form is obtained (A, B, C= AB(C +E) + CBA +B) + CUA + AB +B)) =ABC+ABC+ABC+A C+ ABC+ABC+A BC+A BC =ABC4+ABC +ABC+A BC+A BC Inminterms, the Boolean expression can be written YA, B,C) = Bm(7, 6, 5,153) “The K-map representation is shown in Fig. 3.44(@).Te simplified Boolean xeon 1A, B= C442 ¢.pyeae +8CD+BCD able enenereson sem iy sia en, Assn the cond ee | ‘standard form, a Dest en tn sn 0 ANDi get a geseoatemih t+ 3th nar sum of pods frm Oba ‘ pO(D+ D)+BCDA+A)+ BCD (A 3, ‘Thisisal is missing in WA.B.CD) = } o=nM0.3,5.7) shown in Fig 3.54 (2). ee menace: ?/%7) ii pootean expressions A,B, C)= C (oy The Booka xpesionis A.B, )=11M 0. 1,4,5) is shown in Fig. 3.54 (b). oo i 3546) YA, 8,0) ~ FIMO, 1,4, 5) “Te simpliied Boolean expression is (A,B, C) = B (A, B,C) =TIM(,2, 4,6) en a an ta Ger, Fig. 355) YA, 8, = TIM, 1,2,3,4,5,6,7) “the simplified Boolean expression is YA, B,C) =0 {py The Boolean expressions YA, B,C) =TIMO, 24,5) ‘The K-map representation is shown in Fig. 3.55(b). 4B too ovo Fig. 35506) YA, B, © = IMO, 2, 4,5) “the simplified Boolean expression is ¥(A, B, ©) =(A+ €)-( A+B) Example 3.30 Rede the following fonetion using K-map technique, (A, B, C, D)=TIM(O, 2,8, 9, 12,13, 15) Solution ‘The Boolean expression is ¥ (A, B, C, D)=TIM(O, 2, 8,9, 12, 13,15) “The K-map representation is shown in Fig. 3.56. 4B. @ 00] o oim sions shown in Fig. 3.57. & ‘The K-map representa __Bonean high and Logic Gates 479 ‘The simplified Boolean expressions YA,B.CD) A+B +C4DVA+ BVA Dyas) example 3.33. Simplify he following Boolean expressions: (a) WA. B, C.D) =T1M (1, 2, 5,6,8,9, 10, 11,15) {by YALB.C,D)= TIM, 1,2,3,5.6,7,12, 14) solution wad A = 1IMO, 1, 2, 3,8, 9, 10,11, 12, 13) (a) The Boolean expression is YA, B, C, D)=TLM(1, 2,5, 6,89, 15) ne 2 ‘The K-map representation is showin in Fig, 3.59(0, T+0, as rhe simplied Boolean expressions WA. B,C,D)=(4 + OB a Seen Example 3.32. Simplify he following Boolean expressions aS (a) HA, B, C.D)= TIM, 2,5,6,8, 9515) ; () MAB, C.D) =TIMO, 1,2, 3,5: 6,75 12) “| Solution a (a) The Boolean expression is WA, B,C, D) = TIM(L, 2, 5,6, 8,9, 15) “The K-map representation is shown in Fig. 3.58(). Fig. 35%) Y\A, B,C, D) = TIMA, 2,5, 6,8, 9, 10, 11,15) Fo 1 10 “The simplified Boolean expression is tw a ) YA, B,C,D)=(B+ AYA +C + DYA+ C +D\A+C+ D) (b) The Boolean expression is Y(A, B, C, D) =TIM(, 1,2, 3,5.6,7, 12, 14) ‘The K-map representation is shown in Fig, 3.59(b). 4B co tt Fig. 358 YA, 8,C,D) = TIMI, 2,5, 6,8, 9, 15) ; ‘The simplified Boolean expression is - YA.B.C.D)=(4 4+B40(A +B 40 + BAF +D)(A+C+D) ie 0 (b) The Boolean expression is WA B,C, D)=TIM(O, 1,2, 3, 5, 6.7, 12) i ‘The K-map representation is shovin in Fig, 3.58(b). Fig. 3.596) YIA, B, C, D) = TIMO, 1, 2,3, 5,6, 7,12, 14) oy ol 0 ‘The simplified Boolean expression is WA, B,C,D)=(A +B +DXA+BYA+ DA+C) Example 3.34 Minimize the following Boolean expressions using K-map: (@) WA, B,C, D)=(A+B+ CA +B+D) (b) WA, B,C,D)=(A+B + D(A +B+D)