module fullAdder(n1,n2,sum,c_out);

input [3:0]n1;
input [3:0]n2;
output [3:0]sum;
output c_out;

assign {c_out,sum}=n1+n2;
endmodule

//Operation 1
module main(n1,n2,out);
input [3:0] n1;
input [2:0] n2;
output [6:0] out;
//These are the asigned inputs to be given to the adder

wire [3:0] n11;

wire [3:0] n22;
wire [3:0] n33;
assign n11[3] = n2[1] & n1[3];
assign n11[2] = n2[1] & n1[2];
assign n11[1] = n2[1] & n1[1];
assign n11[0] = n2[1] & n1[0];

assign n22[3] = 0;
assign n22[2] = n2[0] & n1[3];
assign n22[1] = n2[0] & n1[2];
assign n22[0] = n2[0] & n1[1];

wire [3:0] sum_in1;

wire [3:0] sum_out;
wire [3:0] sum_in;
wire c_out;

fullAdder f1(n11,n22,sum_in,c_out);

assign out[1]=sum_in[0];

assign sum_in1[0]=sum_in[1];
assign sum_in1[1]=sum_in[2];
assign sum_in1[2]=sum_in[3];
assign sum_in1[3]=c_out;
assign n33[3] = n2[2] & n1[3];
assign n33[2] = n2[2] & n1[2];
assign n33[1] = n2[2] & n1[1];
assign n33[0] = n2[2] & n1[0];

fullAdder f2(n33,sum_in1,sum_out,out[6]);

assign out[2]=sum_out[0];
assign out[3]=sum_out[1];
assign out[4]=sum_out[2];
assign out[5]=sum_out[3];
assign out[0] = n2[0] & n1[0];
endmodule

module test_project;
reg [3:0] n1;
reg [2:0] n2;
wire [6:0] out;

main m1(n1,n2,out);
initial
begin
n1=4'b0110;
n2=3'b010;
#5

n1=4'b1010;
n2=3'b011;
#10
n1=4'b1100;
n2=3'b111;
end
endmodule