Multiplication
More complicated than addition
• Accomplished via shifting and addition
More time and more area
Let's look at 3 versions based on grade school algorithm
01010010 (multiplicand)
x 01101101 (multiplier)
Negative numbers: convert and multiply
Use other better techniques like Booth’s encoding
ECE 369 :: Fundamentals of Computer Architecture 1
ECE 369 - Fundamentals of Computer Architecture
Multiplication
01010010(multiplicand) 01010010 (multiplicand)
× 01101101 (multiplier) × 01101101 (multiplier)
00000000 00000000
01010010 ×1 01010010 ×1
01010010 00101001 0 (add & shr)
000000000 ×0 00000000 0 ×0
00010100 10 (add & shr)
001010010
01010010 00 ×1
0101001000 ×1
00110011 010 (add & shr)
0110011010
01010010 000 ×1
01010010000 ×1
01000010 1010 (add & shr)
10000101010
00000000 0000 ×0
000000000000 ×0
00100001 01010 (add & shr)
010000101010
01010010 00000 ×1
0101001000000 ×1
00111001 101010 (add & shr)
0111001101010
01010010 000000 ×1
01010010000000 ×1
01000101 1101010 (add & shr)
10001011101010
00000000 0000000 ×0
000000000000000 ×0 00100010 11101010 (add & shr)
0010001011101010
1
Multiplication: Implementation
Start
Multiplier0 = 1 1. Test Multiplier0 = 0
Multiplier0
Multiplicand
Shift left
64 bits
1a. Add multiplicand to product and
place the result in Product register
Multiplier
64-bit ALU Shift right
32 bits
2. Shift the Multiplicand register left 1 bit
Product
Control test
Write
64 bits
3. Shift the Multiplier register right 1 bit
No: < 32 repetitions
32nd repetition?
Yes: 32 repetitions
Done
ECE 369 :: Fundamentals of Computer Architecture 3
Second version
Start
Multiplier0 = 1 1. Test Multiplier0 = 0
Multiplier0
Multiplicand
32 bits
1a. Add multiplicand to the left half of
the product and place the result in
Multiplier the left half of the Product register
32-bit ALU Shift right
32 bits
Shift right 2. Shift the Product register right 1 bit
Product Control test
Write
64 bits
3. Shift the Multiplier register right 1 bit
No: < 32 repetitions
32nd repetition?
Yes: 32 repetitions
Done
ECE 369 :: Fundamentals of Computer Architecture 4
Final version
Start
Product0 = 1 1. Test Product0 = 0
Multiplicand Product0
32 bits
1a. Add multiplicand to the left half of
32-bit ALU the product and place the result in
the left half of the Product register
Shift right Control
Product
Write test
64 bits 2. Shift the Product register right 1 bit
No: < 32 repetitions
32nd repetition?
Yes: 32 repetitions
Done
ECE 369 :: Fundamentals of Computer Architecture 5
Multiplication example: 0010 x 0110
Original Algorithm
Iteration Multiplicand
Step Product
0 0010 Initial values 0000 0110
1: 0 -> No operation 0000 0110
1 0010
2: Shift right 0000 0011
1a: 1 -> Product =
0010 0011
2 0010 Product + Multiplicand
2: Shift right 0001 0001
1a: 1 -> Product =
0011 0001
Product + Multiplicand
3 0010
2: Shift right 0001 1000
1: 0 -> No operation 0001 1000
4 0010
2: Shift right 0000 1100
ECE 369 :: Fundamentals of Computer Architecture 6
ECE 369 - Fundamentals of Computer Architecture
Signed Multiplication
The easiest way to deal with signed numbers is to first convert the
multiplier and multiplicand to positive numbers and then remember the
original sign.
It turns out that the last algorithm will work with signed numbers
provided that when we do the shifting steps we extend the sign of the
product.
2
ECE 369 - Fundamentals of Computer Architecture
Speeding up multiplication (Booth’s Algorithm)
The way we have done multiplication so far consisted of repeatedly
scanning the multiplier, adding the mutiplicand (or zeros) and shifting
the result accumulated.
Observation:
if we could reduce the number of times we have to add the multiplicand
that would make the all process faster.
Let say we want to do:
b x a where a=7ten=0111two
With the algorithm used so far we successively:
add b, add b, add b, and add 0
If we “recode” the number 7ten as (8-1)ten = (1000 – 0001)two = 100-1
all we need to do is:
sub b, add 0, add 0, add 0, and add b
3
ECE 369 - Fundamentals of Computer Architecture
Booth’s Algorithm
Observation: If besides addition we also use subtraction, we
can reduce the number of consecutives additions and therefore
we can make the multiplication faster.
This requires to “recode” the multiplier in such a way that the number
of consecutive 1s in the multiplier (indeed the number of consecutive
additions we should have done) are reduced.
The key to Booth’s algorithm is to scan the multiplier and classify group
of bits into the beginning, the middle and the end of a run of 1s
A string of 0s
0 1 1 1 1 0 already avoids arithmetic,
so we can leave them alone
End of Run Beginning of Run
Middle of Run
4
ECE 369 - Fundamentals of Computer Architecture
Using Booth’s encoding for multiplication
If the initial content of A is an-1…a0 then i-th multiply step, the
low-order bit of register A is ai and step (i) in the multiplication
algorithm becomes:
1. If ai=0 and ai-1=0, then add 0 to P
2. If ai=0 and ai-1=1, then add B to P
3. If ai=1 and ai-1=0, then subtract B from P
4. If ai=1 and ai-1=1, then add 0 to P
(For the first step when i=0, then add 0 to P)
Current bit Bit to the right Type Action
1 0 Beg. Run Subtract the multiplicand
1 1 Middle Run No arithmetic operation
1 1 End Run Add the multiplicand
0 0 Middle Run No arithmetic multiplicand
5
ECE 369 - Fundamentals of Computer Architecture
Booth’s algorithm
Start
Test multiplier[i:i-1]
01 10
00 11
Add multiplicand to Subtract multiplicand
the left half of the from the left half of
product and place the product and place
the result in the left the result in the left
half of the product half of the product
register register
< 32 rep
Shift the product register right by 1
= 32 rep
Done
6
Booth's algorithm example
Booth's Algorithm
Iteration Multiplicand
Step Product
0 0010 Initial values 0000 1101 0
10 -> Product =
1110 1101 0
1 0010 Product - Multiplicand
Shift right 1111 0110 1
01 -> Product =
0001 0110 1
Product + Multiplicand
2 0010
Shift right 0000 1011 0
10 -> Product =
1110 1011 0
3 0010 Product - Multiplicand
Shift right 1111 0101 1
11 -> No operation 1111 0101 1
4 0010
Shift right 1111 1010 1
ECE 369 :: Fundamentals of Computer Architecture 9
Division
Even more complicated
Can be accomplished via shifting and addition/subtraction
More time and more area
We will look at 3 versions based on grade school algorithm
0011 | 0010 0010 (Dividend)
(Divisor) 0011 | 0010 0010 (Dividend)
Negative numbers: Even more difficult
There are better techniques, we won’t look at them
ECE 369 :: Fundamentals of Computer Architecture 10
ECE 369 - Fundamentals of Computer Architecture
Division
1001 (Quotient)
Divisor 1000 1001010 (Dividend)
-1000
10
101
1010
-1000
10 (Remainder)
Dividend = Quotient x Divider + Remainder
7
ECE 369 - Fundamentals of Computer Architecture
Division: First Algorithm
Start
1. Subtract the Divisor register from the
Remainder register and place the
result in the Remainder register
Remainder –> 0 Remainder < 0
Test Remainder
2a. Shift the Quotient register to the left, 2b. Restore the original value by adding
setting the new rightmost bit to 1 the Divisor register to the Remainder
register and place the sum in the
Remainder register. Also shift the
Quotient register to the left, setting the
new least significant bit to 0
3. Shift the Divisor register right 1 bit
No: < 33 repetitions
33rd repetition?
Yes: 33 repetitions
Done
8
Division - Implementation
Divisor
Shift right
64 bits
Quotient
64-bit ALU Shift left
32 bits
Remainder Control
Write test
64 bits
Divisor
32 bits
Quotient
32-bit ALU Shift left
32 bits
Shift left Control
Remainder
Write test
64 bits
ECE 369 :: Fundamentals of Computer Architecture 11
Division
Start
1. Shift the Remainder register left 1 bit
Divisor 2. Subtract the Divisor register from the
left half of the Remainder register and
32 bits place the result in the left half of the
Remainder register
32-bit ALU Remainder >
–0 Remainder < 0
Test Remainder
Shift right
Remainder Control 3a. Shift the Remainder register to the 3b. Restore the original value by adding
Shift left
test left, setting the new rightmost bit to 1 the Divisor register to the left half of the
Write Remainder register and place the sum
in the left half of the Remainder register.
64 bits Also shift the Remainder register to the
left, setting the new rightmost bit to 0
No: < 32 repetitions
32nd repetition?
Yes: 32 repetitions
Done. Shift left half of Remainder right 1 bit
ECE 369 :: Fundamentals of Computer Architecture 12
Restoring division example
Divide Algorithm
Iteration Divisor
Step Product
Initial values 0000 0111
0 0010
Shift reminder left by 1 0000 1110
2. Reminder = Reminder - Divisor 1110 1110
1 0010
3b. (Reminder < 0); +Div; Shift left, R0 = 0 0001 1100
2. Reminder = Reminder - Divisor 1111 1100
2 0010
3b. (Reminder < 0); +Div; Shift left, R0 = 0 0011 1000
2. Reminder = Reminder - Divisor 0001 1000
3 0010
3a. (Reminder > 0); Shift left, R0 = 1 0011 0001
2. Reminder = Reminder - Divisor 0001 0001
4 0010
3a. (Reminder > 0); Shift left, R0 = 1 0010 0011
Done 0010 Shift left half of reminder right by 1 0001 0011
ECE 369 :: Fundamentals of Computer Architecture 13
Non-restoring division
How can we avoid adding the divisor back to the reminder?
• Note that this addition is performed whenever the reminder is negative!
So, what exactly are we doing when the reminder is negative?
• We have a certain reminder: R (R < 0)
• We add the divisor back to it: R + D
• We shift the result left by 1: 2*(R + D) = 2*R + 2*D
• We subtract the divisor again in the next step: 2*R + 2*D - D = 2*R + D
• Equivalent of left shifting the reminder R by 1 bit
• Add the divisor in the next step, instead of subtracting
ECE 369 :: Fundamentals of Computer Architecture 14
Non-restoring division example
Divide Algorithm
Iteration Divisor
Step Product
Initial values 0000 0111
0 0010
Shift reminder left by 1 0000 1110
Reminder = Reminder - Divisor 1110 1110
1 0010
(Reminder < 0); Shift left, R0 = 0 1101 1100
Reminder = Reminder + Divisor 1111 1100
2 0010
(Reminder < 0); Shift left, R0 = 0 1111 1000
Reminder = Reminder + Divisor 0001 1000
3 0010
(Reminder > 0); Shift left, R0 = 1 0011 0001
Reminder = Reminder - Divisor 0001 0001
4 0010
(Reminder > 0); Shift left, R0 = 1 0010 0011
Done 0010 Shift left half of reminder right by 1 0001 0011
ECE 369 :: Fundamentals of Computer Architecture 15
Floating point numbers (a brief look)
We need a way to represent
• Numbers with fractions, e.g., 3.1416
• Very small numbers, e.g., 0.000000001
•
Very large numbers, e.g., 3.15576 x 109
Representation
•
Sign, exponent, significand: (–1)sign x significand x 2exponent
• More bits for significand gives more accuracy
• More bits for exponent increases range
IEEE 754 floating point standard
• Single precision: 8 bit exponent, 23 bit significand
• Double precision: 11 bit exponent, 52 bit significand
ECE 369 :: Fundamentals of Computer Architecture 16
IEEE 754 floating-point standard
Leading “1” bit of significand is implicit
Exponent is “biased” to make sorting easier
• All 0s is smallest exponent, all 1s is largest
• Bias of 127 for single precision and 1023 for double precision
•
Summary: (–1)sign x (1+significand) x 2(exponent – bias)
Example
•
Decimal: -.75 = -3/4 = -3/22
•
Binary: -.11 = -1.1 x 2-1
• Floating point: exponent = 126 = 01111110
• IEEE single precision: 1 01111110 10000000000000000000000
ECE 369 :: Fundamentals of Computer Architecture 17
Floating point complexities
Operations are somewhat more complicated (see text)
In addition to overflow we can have “underflow”
Accuracy can be a big problem
• IEEE 754 keeps two extra bits, guard and round
• Four rounding modes
• Positive divided by zero yields “infinity”
• Zero divide by zero yields “not a number”
• Other complexities
Implementing the standard can be tricky
Not using the standard can be even worse
• See text for description of 80x86 and Pentium bug!
ECE 369 :: Fundamentals of Computer Architecture 18
Floating point add/subtract
To add/sub two numbers
• We first compare the two exponents
• Select the higher of the two as the exponent of result
• Select the significand part of lower exponent number and shift it right by the amount equal to
the difference of two exponent
• Remember to keep two shifted out bit and a guard bit
• Add/sub the signifand as required according to operation and signs of operands
• Normalize significand of result adjusting exponent
• Round the result (add one to the least significant bit to be retained if the first bit being thrown
away is a 1
• Re-normalize the result
ECE 369 :: Fundamentals of Computer Architecture 19
Floating point multiply
To multiply two numbers
• Add the two exponent (remember access 127 notation)
• Produce the result sign as exor of two signs
• Multiply significand portions
• Results will be 1x.xxxxx… or 01.xxxx….
• In the first case shift result right and adjust exponent
• Round off the result
• This may require another normalization step
ECE 369 :: Fundamentals of Computer Architecture 20
Floating point divide
To divide two numbers
• Subtract divisor’s exponent from the dividend’s exponent (remember access 127 notation)
• Produce the result sign as exor of two signs
• Divide dividend’s significand by divisor’s significand portions
• Results will be 1.xxxxx… or 0.1xxxx….
• In the second case shift result left and adjust exponent
• Round off the result
• This may require another normalization step
ECE 369 :: Fundamentals of Computer Architecture 21
Summary on Chapter 3
Computer arithmetic is constrained by limited precision
Bit patterns have no inherent meaning but standards do exist
• Two’s complement and IEEE 754 floating point
Computer instructions determine “meaning” of the bit patterns
Performance and accuracy are important so there are many
complexities in real machines (i.e., algorithms and implementation)
We designed an ALU to carry out four function
Multiplication
• Unsigned, Signed, Signed using Booth’s encoding, and Carry save adders and their use
Division
ECE 369 :: Fundamentals of Computer Architecture 22
