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sub2/Msub_c_cy<14>
sub2/Msub_c_cy<15>
CI
XORCY
sub1/Msub_c_cy<42>
sub2/Msub_c_cy<16>
CI
DI
I0
a_42_IBUF
DI
42
I0
S MUXCY
I0
LUT2
40
sub2/Msub_c_cy<12>
41
S MUXCY
sub2/Msub_c_cy<18>
CI
O
sub2/Msub_c_cy<19>
CI
DI
sub2/Msub_c_cy<20>
CI
DI
sub2/Msub_c_cy<21>
CI
DI
S MUXCY
sub2/Msub_c_cy<22>
CI
DI
S MUXCY
sub2/Msub_c_cy<23>
CI
DI
S MUXCY
sub2/Msub_c_cy<24>
CI
DI
S MUXCY
sub2/Msub_c_cy<25>
CI
DI
S MUXCY
sub2/Msub_c_cy<26>
CI
DI
S MUXCY
I0
sub1/Msub_c_lut<41>
I0
LUT2
sub2/Msub_c_cy<28>
sub2/Msub_c_cy<29>
CI
DI
S MUXCY
sub2/Msub_c_cy<30>
CI
DI
S MUXCY
sub2/Msub_c_cy<31>
CI
DI
S MUXCY
sub2/Msub_c_cy<32>
CI
DI
S MUXCY
sub2/Msub_c_cy<33>
CI
DI
S MUXCY
sub2/Msub_c_cy<34>
CI
DI
S MUXCY
sub2/Msub_c_cy<35>
CI
DI
S MUXCY
I0
sub2/Msub_c_cy<36>
CI
DI
S MUXCY
sub2/Msub_c_cy<37>
CI
DI
S MUXCY
sub2/Msub_c_cy<38>
CI
DI
S MUXCY
sub2/Msub_c_cy<39>
CI
DI
S MUXCY
sub2/Msub_c_lut<16>
LUT2
sub2/Msub_c_cy<40>
CI
DI
S MUXCY
sub2/Msub_c_cy<41>
CI
DI
S MUXCY
I0
sub2/Msub_c_cy<43>
CI
DI
S MUXCY
sub2/Msub_c_cy<44>
CI
DI
S MUXCY
sub2/Msub_c_cy<45>
CI
DI
S MUXCY
sub2/Msub_c_lut<17>
S MUXCY
sub2/Msub_c_cy<42>
CI
DI
S MUXCY
I1
O
DI
LUT2
CI
DI
S MUXCY
I1
XORCY
CI
I1
FDCE
sub2/Msub_c_cy<27>
CI
DI
S MUXCY
sub2/Msub_c_lut<15>
CI sub1/Msub_c_xor<41>
O
LI
sub1/Msub_c_cy<41>
Q
D
reg1/out_40
O
DI
S MUXCY
CE
CLR
reg1/out_39
S MUXCY
CI
DI
FDCE
IBUF
IBUF
FDCE
DI
sub2/Msub_c_cy<13>
CI
LUT2
IBUF
reg1/out_41
a_41_IBUF
S MUXCY
LUT2
I1
LUT2
I1
sub2/Msub_c_lut<12>
I1
CLR
S MUXCY
I1
a_40_IBUF
Q
CLR
IBUF
S MUXCY
sub2/Msub_c_lut<14>
O
DI
sub1/Msub_c_lut<42>
C
CE
CI
I0
C
CE
I
sub2/Msub_c_cy<17>
CI
DI
CI
reg1/out_42
sub1/Msub_c_cy<38>
sub1/Msub_c_lut<38>
reg1/out_38
a_38_IBUF
38
sub1/Msub_c_cy<40>
CE
Q
CLR
sub1/Msub_c_lut<40>
FDCE
I0
DI
I0
CI sub1/Msub_c_xor<37>
O
LI
LUT2
33
a_37_IBUF
37
LUT2
IBUF
a_39_IBUF
39
FDCE
CI
O
I0
I0
LUT2
I0
sub2/Msub_c_cy<48>
CI
O
sub2/Msub_c_cy<49>
CI
O
sub2/Msub_c_cy<50>
CI
DI
sub2/Msub_c_cy<51>
CI
DI
S MUXCY
sub2/Msub_c_cy<52>
CI
DI
S MUXCY
sub2/Msub_c_cy<53>
CI
DI
S MUXCY
sub2/Msub_c_cy<54>
CI
DI
S MUXCY
sub2/Msub_c_cy<55>
CI
DI
S MUXCY
sub2/Msub_c_cy<56>
CI
DI
S MUXCY
sub2/Msub_c_cy<57>
CI
DI
S MUXCY
CI
DI
S MUXCY
O
DI
S MUXCY
S MUXCY
S MUXCY
I1
LUT6
LUT2
sub2/Msub_c_lut<21>
I0
I1
sub2/Msub_c_lut<22>
I0
I1
LUT2
sub2/Msub_c_lut<23>
I0
I1
LUT2
XORCY
sub2/Msub_c_lut<24>
I0
O
DI
I0
S MUXCY
sub2/Msub_c_lut<20>
I5
CI sub1/Msub_c_xor<36>
O
LI
CI
sub1/Msub_c_lut<36>
DI
S MUXCY
I1
I4
LUT2
LUT2
sub1/Msub_c_cy<36>
reg1/out_36
sub2/Msub_c_cy<47>
DI
S MUXCY
sub2/Msub_c_lut<19>
I3
S MUXCY
I1
IBUF
Q
CLR
FDCE
CI
DI
S MUXCY
LUT2
I2
XORCY
DI
sub1/Msub_c_lut<39>
I1
I1
XORCY
CI sub1/Msub_c_xor<40>
O
LI
sub1/Msub_c_cy<39>
S MUXCY
I1
CLR
IBUF
I0
XORCY
CI sub1/Msub_c_xor<39>
O
LI
O
DI
I0
a_33_IBUF
IBUF
sub2/Msub_c_lut<18>
Missing_codes_wg_lut<3>
XORCY
S MUXCY
I1
FDCE
LUT2
CI sub1/Msub_c_xor<42>
O
LI
CI
Q
CLR
CI
sub1/Msub_c_lut<37>
C
CE
I
C
CE
sub2/Msub_c_cy<46>
CI
DI
S MUXCY
I1
C
CE
sub1/Msub_c_cy<37>
reg1/out_37
a_31_IBUF
31
reg1/out_28
I1
LUT2
S MUXCY
sub2/Msub_c_lut<25>
I0
CE
Q
I1
CLR
I1
LUT2
LUT2
sub2/Msub_c_lut<26>
I0
FDCE
I
I1
a_36_IBUF
36
LUT2
sub2/Msub_c_lut<27>
I0
IBUF
I1
reg1/out_33
LUT2
sub1/Msub_c_lut<33>
I0
CE
Q
I0
CI
LUT2
IBUF
I0
reg1/out_34
C
sub1/Msub_c_lut<35>
I0
Q
CE
I0
sub1/Msub_c_lut<34>
I0
CI
O
DI
reg1/out_31
sub1/Msub_c_lut<31>
I0
I0
S MUXCY
a_30_IBUF
30
FDCE
I0
Q
S MUXCY
a_21_IBUF
LUT2
21
CLR
LUT2
sub1/Msub_c_cy<2>
IBUF
I0
FDCE
a_19_IBUF
O
19
FDCE
I0
15
sub1/Msub_c_cy<3>
sub1/Msub_c_cy<14>
DI
reg1/out_14
sub1/Msub_c_cy<4>
I0
18
CLR
a_16_IBUF
16
S MUXCY
a_17_IBUF
O
17
IBUF
I0
IBUF
CLR
sub1/Msub_c_lut<17>
I1
I0
I0
I1
sub1/Msub_c_cy<11>
CI
O
DI
LUT2
LUT2
sub1/Msub_c_cy<12>
O
DI
sub1/Msub_c_cy<16>
Q
sub1/Msub_c_lut<18>
I0
CI
CLR
O
DI
XORCY
S MUXCY
I0
CLR
CE
CLR
CE
CLR
CE
CLR
CE
CLR
CE
CLR
CE
CLR
CE
CLR
CE
CLR
XORCY
CI count1/Mcount_out_xor<20>
O
LI
I2
I2
44
S MUXCY
56
a_44_IBUF
O
DI
reg1/out_44
IBUF
I0
a_54_IBUF
CE
Q
I1
CLR
LUT2
a_50_IBUF
sub1/Msub_c_cy<44>
LUT2
50
a_51_IBUF
51
54
a_52_IBUF
52
IBUF
DI
IBUF
IBUF
a_55_IBUF
48
CI sub1/Msub_c_xor<44>
O
LI
a_57_IBUF
I
IBUF
I1
FDCE
FDCE
I0
I0
sub1/Msub_c_cy<53>
I0
CI
sub1/Msub_c_cy<52>
S MUXCY
CI
O
I0
I0
CI
count1/Mcount_out_cy<42>_rt
I0
count1/Mcount_out_cy<32>_rt
I0
count1/Mcount_out_cy<33>_rt
I0
CI
count1/Mcount_out_cy<41>_rt
LUT1
count1/Mcount_out_cy<30>
I0
I0
CI
count1/Mcount_out_cy<35>_rt
CI
O
I0
DI
S MUXCY
XORCY
I0
I0
DI
I0
DI
sub1/Msub_c_cy<50>
CI
O
I1
DI
sub1/Msub_c_cy<49>
CI
O
DI
CI
O
DI
S MUXCY
S MUXCY
S MUXCY
S MUXCY
sub1/Msub_c_cy<47>
XORCY
LUT2
XORCY
I0
sub1/Msub_c_lut<61>
IBUF
a_59_IBUF
59
IBUF
FDCE
I0
CI sub1/Msub_c_xor<58>
O
LI
XORCY
LUT2
sub1/Msub_c_cy<59>
DI
reg1/out_58
I4
I5
CE
I0
LUT6
Q
CLR
D
S MUXCY
CI
O
I1
LUT2
CI sub1/Msub_c_xor<59>
O
LI
S MUXCY
sub1/Msub_c_lut<63>
I0
INV
count1/out_33_rstpot
CI count1/Mcount_out_xor<33>
O
LI
FDCE
LUT4
count1/out_32_rstpot
I0
CE
Missing_codes_wg_cy<10>
count1/out_0
CI
C
DI
S MUXCY
count1/out_0_rstpot_cy
XORCY
XORCY
Missing_codes_wg_lut<10>
CI count1/Mcount_out_xor<32>
O
LI
Q
CLR
D
FDCE
count1/out_31_rstpot
XORCY
I1
CI count1/Mcount_out_xor<31>
O
LI
FDCE
I0
I0
CI count1/Mcount_out_xor<30>
O
LI
LUT1
I3
I4
sub2/Msub_c_lut<56>
I0
I1
LUT2
sub2/Msub_c_lut<57>
I1
I1
I1
count1/out_29_rstpot
LUT6
I1
I0
S MUXCY
Q
CLR
D
reg2/out_61
C
sub2/Msub_c_cy<61>
CE
CI
CLR
DI
S MUXCY
sub2/Msub_c_lut<61>
FDCE
I0
I1
LUT2
LUT1
count1/out_60_rstpot
I0
CI count1/Mcount_out_xor<60>
O
LI
O
DI
S MUXCY
I1
I2
I3
XORCY
count1/out_59_rstpot
CI count1/Mcount_out_xor<59>
O
LI
count1/Mcount_out_cy<58>
LUT4
LUT4
I0
CI count1/Mcount_out_xor<58>
O
LI
O
DI
S MUXCY
I1
I2
I3
XORCY
count1/out_57_rstpot
LUT4
LUT1
count1/out_58_rstpot
count1/Mcount_out_cy<57>
I3
I2
LUT4
I0
S MUXCY
I2
I1
I3
XORCY
count1/Mcount_out_cy<60>_rt
O
DI
LUT4
I0
CI count1/Mcount_out_xor<57>
O
LI
I2
I1
I2
I3
XORCY
count1/out_56_rstpot
LUT4
LUT4
I0
CI count1/Mcount_out_xor<56>
O
LI
I2
count1/Mcount_out_cy<56>
LUT4
count1/Mcount_out_cy<50>_rt
I1
I2
I3
XORCY
LUT4
CI
O
DI
LUT1
S MUXCY
I2
count1/Mcount_out_cy<51>_rt
I0
LUT4
count1/Mcount_out_cy<55>
LUT1
CI
count1/Mcount_out_cy<57>_rt
DI
I0
count1/Mcount_out_cy<52>_rt
I0
LUT4
I0
count1/Mcount_out_cy<54>_rt
CI
O
S MUXCY
I0
DI
S MUXCY
count1/Mcount_out_cy<51>
O
count1/Mcount_out_cy<54>
CI
I2
LUT4
LUT1
S MUXCY
CI
I1
I3
XORCY
I0
count1/Mcount_out_cy<53>
DI
count1/out_54_rstpot
O
DI
S MUXCY
CI count1/Mcount_out_xor<55>
O
LI
count1/Mcount_out_cy<56>_rt
O
DI
CI
DI
I2
LUT1
count1/Mcount_out_cy<52>
I0
LUT1
count1/Mcount_out_cy<50>
CI
count1/out_55_rstpot
count1/Mcount_out_cy<53>_rt
LUT1
count1/Mcount_out_cy<49>
LUT1
S MUXCY
I2
LUT4
CI
I1
S MUXCY
C
CE
FDCE
FDCE
CI
LUT4
I0
S MUXCY
S MUXCY
LUT4
CI count1/Mcount_out_xor<54>
O
LI
count1/Mcount_out_cy<55>_rt
I2
I0
I1
I2
I3
XORCY
I1
O
DI
FDCE
count1/out_61
Q
S MUXCY
I0
S MUXCY
count1/Mcount_out_cy<59>
LUT4
I3
LUT4
LUT1
LUT4
count1/out_53_rstpot
I0
I1
CI count1/Mcount_out_xor<53>
O
LI
I2
I3
I1
I2
I3
XORCY
LUT4
count1/out_52_rstpot
LUT4
I0
I1
CI count1/Mcount_out_xor<52>
O
LI
I2
I3
count1/out_51_rstpot
CI count1/Mcount_out_xor<51>
O
LI
I2
I3
count1/out_50_rstpot
I0
CI count1/Mcount_out_xor<50>
O
LI
count1/out_49_rstpot
I0
CI
count1/Mcount_out_xor<49>
I1
reg2/out_62
I2
C
count1/Mcount_out_cy<62>
LUT4
count1/out_62
S MUXCY
CI
I0
O
DI
count1/out_62_rstpot
CI count1/Mcount_out_xor<62>
O
LI
I0
Q
I1
LUT2
count1/out_63
I2
FDCE
I3
LUT4
count1/out_63_rstpot
I0
CE
Q
CLR
I1
I2
O
FDCE
I3
LUT4
I2
reg2/out_63
C
I3
XORCY
count1/out_48_rstpot
LUT4
I3
CI sub2/Msub_c_xor<63>
O
LI
XORCY
I1
I1
LUT2
FDCE
I2
I3
I0
CLR
D
I2
sub2/Msub_c_lut<63>
CE
LUT4
I0
I1
S MUXCY
sub2/Msub_c_lut<62>
FDCE
CE
CLR
I1
count1/out_61_rstpot
I2
LI
sub2/Msub_c_cy<62>
Q
CLR
O
DI
LUT4
LUT4
I0
I1
I1
CE
CI
I2
XORCY
I2
I3
XORCY
LUT4
I1
I3
XORCY
LUT4
I2
I1
I3
XORCY
LUT4
I0
I1
CI
FDCE
CLR
FDCE
XORCY
DI
DI
LUT4
I2
I2
I3
XORCY
I1
sub2/Msub_c_cy<60>
Q
CLR
CE
Q
CLR
CI
I2
count1/Mcount_out_cy<62>_rt
I0
I1
I2
I0
XORCY
LUT4
LUT2
CE
Q
CLR
count1/out_60
C
CE
CI count1/Mcount_out_xor<61>
O
LI
count1/Mcount_out_cy<61>
I0
XORCY
I3
I1
reg2/out_60
C
CE
FDCE
count1/out_59
LUT1
I3
I2
I0
C
D
FDCE
I0
XORCY
I1
O
DI
reg2/out_59
Q
CLR
Q
CLR
I0
I0
XORCY
XORCY
I0
CI
C
CE
C
CE
CI
I0
count1/Mcount_out_xor<23>
LI
sub2/Msub_c_cy<59>
reg2/out_58
count1/out_58
count1/Mcount_out_cy<61>_rt
I3
XORCY
count1/out_27_rstpot
CI count1/Mcount_out_xor<27>
O
LI
count1/out_26_rstpot
CI count1/Mcount_out_xor<26>
O
LI
count1/out_25_rstpot
CI count1/Mcount_out_xor<25>
O
LI
count1/out_24_rstpot
CI count1/Mcount_out_xor<24>
O
LI
count1/out_23_rstpot
CI
count1/out_22_rstpot
sub2/Msub_c_lut<60>
CLR
count1/Mcount_out_cy<60>
I0
CI count1/Mcount_out_xor<28>
O
LI
XORCY
I0
LUT2
CE
I0
CI count1/Mcount_out_xor<29>
O
LI
count1/out_28_rstpot
CI sub1/Msub_c_xor<0>
O
LI
sub2/Msub_c_lut<59>
LUT2
I1
CLR
FDCE
I0
I1
I1
FDCE
CE
FDCE
I1
S MUXCY
sub2/Msub_c_lut<58>
count1/out_57
C
Q
CLR
LUT4
LUT4
DI
I2
DI
Q
CLR
FDCE
LUT1
CE
FDCE
I3
I3
CI
I1
CI
CE
I0
count1/out_56
LUT4
I2
I2
I3
XORCY
I1
sub2/Msub_c_cy<58>
C
Q
CLR
FDCE
count1/Mcount_out_cy<59>_rt
count1/out_55
Q
CLR
I2
I0
I1
CI
I1
LUT2
reg2/out_57
C
CE
LUT1
C
CE
I1
I3
XORCY
count1/out_41_rstpot
I0
I1
I1
reg2/out_56
Q
CLR
I0
count1/out_54
Q
I0
I3
XORCY
I5
XORCY
XORCY
LUT2
CLR
FDCE
I3
XORCY
count1/out_30_rstpot
count1/Mcount_out_cy<3>_rt
I2
FDCE
CI sub1/Msub_c_xor<1>
O
LI
I0
CE
I0
D
S MUXCY
I0
XORCY
CI sub1/Msub_c_xor<47>
O
LI
sub2/Msub_c_lut<55>
C
CE
FDCE
count1/Mcount_out_cy<58>_rt
FDCE
C
Q
CLR
LUT4
I3
XORCY
CE
CLR
O
CI sub1/Msub_c_xor<2>
O
LI
CI sub1/Msub_c_xor<4>
O
LI
CI sub1/Msub_c_xor<3>
O
LI
LUT2
reg2/out_55
CE
FDCE
LUT4
I3
I3
XORCY
reg2/out_1
C
I1
XORCY
Q
CLR
sub2/Msub_c_lut<54>
Q
CLR
CLR
FDCE
count1/out_53
I3
I2
LUT4
I3
XORCY
CE
I3
CI
C
CE
LUT2
C
CE
CE
Q
Q
CLR
I2
FDCE
I1
I3
I0
O
I2
LUT3
LUT2
reg1/out_63
I2
CI sub1/Msub_c_xor<61>
O
LI
FDCE
S MUXCY
I1
count1/out_52
CE
FDCE
FDCE
I1
I0
I2
I0
CI count1/Mcount_out_xor<34>
O
LI
count1/out_2
CLR
I1
I1
XORCY
count1/out_34_rstpot
FDCE
I0
I0
DI
sub1/Msub_c_cy<60>
DI
sub1/Msub_c_lut<58>
Q
D
I3
count1/out_0_rstpot_lut
XORCY
XORCY
IBUF
XORCY
O
DI
O
I3
S MUXCY
CI sub1/Msub_c_xor<60>
O
LI
CI
CI
I2
I2
count1/out_2_rstpot
CI count1/Mcount_out_xor<0>
O
LI
63
LUT2
I1
sub1/Msub_c_cy<58>
a_63_IBUF
I1
I0
FDCE
I1
DI
LUT2
I0
sub1/Msub_c_lut<59>
I0
I1
sub1/Msub_c_lut<60>
Q
CLR
IBUF
Missing_codes_wg_lut<1>
I0
reg2/out_54
reg2/out_53
Q
CLR
I0
XORCY
count1/out_44_rstpot
I1
I0
I0
CI count1/Mcount_out_xor<35>
O
LI
C
CE
CLR
I1
LUT4
count1/Mcount_out_lut<0>_INV_0
I
sub2/Msub_c_lut<53>
C
CE
FDCE
count1/out_51
Q
CLR
LUT4
I3
count1/out_35_rstpot
count1/out_1
XORCY
XORCY
S MUXCY
CI
LUT2
reg2/out_52
C
CE
I3
LUT4
I0
CI count1/Mcount_out_xor<36>
O
LI
CI count1/Mcount_out_xor<1>
O
LI
CI sub1/Msub_c_xor<63>
O
LI
O
DI
sub1/Msub_c_cy<61>
I1
Q
CLR
I2
I3
I3
XORCY
XORCY
CI
FDCE
I0
C
CE
Q
CLR
FDCE
I1
I2
I0
XORCY
count1/out_36_rstpot
S MUXCY
sub1/Msub_c_cy<62>
LUT2
FDCE
CI count1/Mcount_out_xor<38>
O
LI
count1/out_37_rstpot
CI sub1/Msub_c_xor<62>
O
LI
I1
CLR
Q
CE
I
sub1/Msub_c_lut<62>
C
CE
Q
FDCE
a_58_IBUF
58
CI sub1/Msub_c_xor<45>
O
LI
S MUXCY
reg1/out_62
CLR
sub2/Msub_c_lut<52>
reg2/out_51
C
CE
count1/out_50
I0
I1
I0
S MUXCY
CI count1/Mcount_out_xor<37>
O
LI
O
DI
I0
IBUF
CE
Q
CLR
I1
reg1/out_61
reg1/out_59
XORCY
XORCY
DI
I0
62
C
CE
60
LUT2
reg2/out_50
XORCY
count1/out_47_rstpot
I0
I0
XORCY
count1/out_42_rstpot
CI count1/Mcount_out_xor<42>
O
LI
S MUXCY
XORCY
count1/out_40_rstpot
XORCY
count1/out_39_rstpot
count1/out_38_rstpot
O
DI
CI
S MUXCY
a_62_IBUF
IBUF
reg1/out_60
S MUXCY
a_60_IBUF
LUT2
CI sub1/Msub_c_xor<50>
O
LI
CI sub1/Msub_c_xor<49>
O
LI
CI sub1/Msub_c_xor<48>
O
LI
CI sub1/Msub_c_xor<46>
O
LI
CI
sub1/Msub_c_lut<47>
O
DI
I1
S MUXCY
CI
count1/Mcount_out_cy<1>
O
DI
count1/out_1_rstpot
a_61_IBUF
61
XORCY
sub1/Msub_c_cy<57>
S MUXCY
I0
DI
count1/Mcount_out_cy<37>
S MUXCY
S MUXCY
XORCY
O
DI
CI sub1/Msub_c_xor<52>
O
LI
CI sub1/Msub_c_xor<51>
O
LI
O
DI
S MUXCY
S MUXCY
CI count1/Mcount_out_xor<39>
O
LI
CI
DI
O
DI
LUT1
CI
sub1/Msub_c_lut<57>
XORCY
LUT2
CI
LUT1
count1/Mcount_out_cy<36>
CI
CI
I0
CI sub1/Msub_c_xor<57>
O
LI
Missing_codes_wg_cy<1>
XORCY
LUT2
O
DI
I1
count1/Mcount_out_cy<35>
Missing_codes_wg_cy<9>
EOT_IBUF
CLR
LUT3
I0
sub1/Msub_c_cy<48>
CI
I0
S MUXCY
CI
CE
O
I2
sub1/Msub_c_lut<49>
S MUXCY
sub1/Msub_c_cy<45>
sub1/Msub_c_lut<45>
S MUXCY
XORCY
CI
DI
S MUXCY
CI count1/Mcount_out_xor<40>
O
LI
O
DI
LUT1
count1/Mcount_out_cy<38>
count1/Mcount_out_cy<38>_rt
CI sub1/Msub_c_xor<5>
O
LI
Missing_codes_wg_cy<8>
I0
LUT1
count1/Mcount_out_cy<34>
CI
count1/Mcount_out_cy<0>
S MUXCY
reg1/out_57
XORCY
I1
CI
count1/Mcount_out_cy<39>_rt
count1/Mcount_out_cy<37>_rt
CI
CI count1/Mcount_out_xor<41>
O
LI
O
DI
count1/Mcount_out_cy<39>
LUT1
count1/Mcount_out_cy<33>
S MUXCY
LUT1
O
DI
CI
CI sub1/Msub_c_xor<54>
O
LI
Missing_codes_wg_lut<0>
I0
DI
Q
FDCE
I0
count1/Mcount_out_cy<36>_rt
CI
count1/Mcount_out_cy<1>_rt
Missing_codes_wg_cy<0>
S MUXCY
S MUXCY
CI sub1/Msub_c_xor<53>
O
LI
S MUXCY
count1/Mcount_out_cy<40>_rt
LUT1
count1/Mcount_out_cy<32>
S MUXCY
DI
count1/Mcount_out_cy<40>
LUT1
count1/Mcount_out_cy<31>
LUT1
count1/Mcount_out_cy<34>_rt
O
DI
S MUXCY
S MUXCY
count1/Mcount_out_cy<41>
XORCY
count1/out_43_rstpot
CI count1/Mcount_out_xor<43>
O
LI
O
DI
LUT1
LUT1
CI
S MUXCY
count1/Mcount_out_cy<42>
LUT1
S MUXCY
S MUXCY
CI count1/Mcount_out_xor<44>
O
LI
O
DI
LUT1
count1/Mcount_out_cy<31>_rt
count1/Mcount_out_cy<29>
S MUXCY
DI
I1
FDCE
S MUXCY
I0
count1/Mcount_out_cy<43>_rt
LUT1
count1/Mcount_out_cy<28>
CI
I0
C
CE
I1
I0
count1/Mcount_out_cy<27>
DI
Missing_codes_wg_cy<7>
S MUXCY
sub2/Msub_c_lut<51>
reg2/out_49
I1
CI
O
DI
LUT6
IBUF
DI
DI
DI
O
DI
LUT2
O
DI
CI count1/Mcount_out_xor<48>
O
LI
S MUXCY
XORCY
count1/out_46_rstpot
XORCY
count1/out_45_rstpot
CI count1/Mcount_out_xor<45>
O
LI
O
DI
count1/Mcount_out_cy<43>
count1/Mcount_out_cy<30>_rt
CI
S MUXCY
LUT1
LUT1
count1/Mcount_out_cy<26>
CI
CI
S MUXCY
I1
I0
I0
I0
S MUXCY
CI
LUT2
O
DI
I1
CI
I1
DI
O
sub1/Msub_c_lut<53>
sub1/Msub_c_cy<51>
sub1/Msub_c_lut<51>
LUT2
CLR
O
DI
I0
CLR
count1/Mcount_out_cy<44>_rt
count1/Mcount_out_cy<29>_rt
O
DI
LUT4
I4
DI
CI
O
CI
LUT2
FDCE
LUT2
I0
CE
Missing_codes_wg_cy<6>
CI
S MUXCY
sub2/Msub_c_lut<50>
FDCE
CE
CLR
CI
LUT1
CI
I3
I1
CI sub1/Msub_c_xor<55>
O
LI
sub1/Msub_c_cy<54>
I1
D
LUT2
FDCE
I1
FDCE
O
DI
LUT2
count1/out_49
CLR
FDCE
I0
count1/Mcount_out_cy<25>
I2
S MUXCY
count1/Mcount_out_cy<44>
count1/Mcount_out_cy<28>_rt
FDCE
I0
I2
I0
XORCY
Q
I1
D
O
LUT2
sub1/Msub_c_lut<52>
CE
O
CLR
Q
CLR
I0
Q
CLR
sub1/Msub_c_cy<46>
Missing_codes_wg_cy<5>
CI
S MUXCY
I1
Q
CLR
FDCE
C
CE
FDCE
I1
sub1/Msub_c_lut<50>
C
CE
sub1/Msub_c_lut<48>
C
CE
O
I1
LUT2
O
DI
LUT6
I0
CE
count1/out_48
Q
CLR
LUT1
Missing_codes_wg_lut<9>
S MUXCY
sub2/Msub_c_lut<49>
C
Q
CLR
FDCE
C
CE
I0
CI
O
DI
CI count1/Mcount_out_xor<47>
O
LI
S MUXCY
CI count1/Mcount_out_xor<46>
O
LI
O
DI
LUT1
LUT6
CI
I0
FDCE
reg1/out_52
FDCE
reg1/out_50
FDCE
reg1/out_48
FDCE
Missing_codes_wg_cy<4>
CI
S MUXCY
I5
LUT2
CE
count1/out_47
Q
CLR
count1/Mcount_out_cy<49>_rt
count1/Mcount_out_cy<48>
LUT1
count1/out_17_rstpot
I1
reg2/out_48
C
Q
CLR
FDCE
C
CE
I0
CI
LUT1
I0
LUT1
I5
sub1/Msub_c_cy<56>
CE
count1/out_46
Q
CLR
count1/Mcount_out_cy<48>_rt
count1/Mcount_out_cy<47>
I0
DI
LUT1
I0
I3
LUT4
I1
reg2/out_47
C
Q
CLR
FDCE
C
CE
CI
I0
CI
count1/Mcount_out_cy<45>_rt
count1/Mcount_out_cy<27>_rt
DI
O
DI
I4
LUT2
I0
CE
count1/out_45
Q
CLR
count1/Mcount_out_cy<46>
count1/Mcount_out_cy<46>_rt
count1/Mcount_out_cy<45>
LUT1
I2
sub2/Msub_c_lut<48>
reg2/out_46
C
Q
CLR
FDCE
C
CE
count1/Mcount_out_cy<47>_rt
LUT4
S MUXCY
S MUXCY
CE
count1/out_44
Q
XORCY
I2
DI
XORCY
Missing_codes_wg_cy<3>
CI
O
I3
I1
CI
sub1/Msub_c_lut<55>
Q
CLR
Q
CLR
I0
Q
D
FDCE
Missing_codes_wg_cy<2>
I1
I2
I0
sub1/Msub_c_cy<55>
Q
CLR
LUT2
reg2/out_45
C
Q
CLR
FDCE
I0
CI sub1/Msub_c_xor<7>
O
LI
Q
CLR
C
CE
Q
CLR
CLR
CE
C
CE
sub1/Msub_c_lut<46>
C
CE
CLR
C
CE
CLR
Q
IBUF
reg1/out_47
reg1/out_46
reg1/out_45
I0
sub1/Msub_c_lut<56>
C
CE
reg1/out_55
FDCE
CE
CE
count1/out_43
Q
I1
reg2/out_44
C
Q
CLR
FDCE
LUT4
LI
Missing_codes_wg_lut<2>
XORCY
IBUF
reg1/out_56
reg1/out_49
CE
Q
a_49_IBUF
49
IBUF
I1
reg1/out_54
I0
LUT2
reg1/out_53
reg1/out_51
a_48_IBUF
a_47_IBUF
47
sub1/Msub_c_lut<54>
IBUF
IBUF
IBUF
IBUF
a_53_IBUF
53
S MUXCY
a_46_IBUF
46
I
55
IBUF
CI
FDCE
a_45_IBUF
45
57
IBUF
sub1/Msub_c_lut<44>
I1
I0
CE
count1/out_42
Q
I3
I3
LUT4
sub2/Msub_c_lut<47>
reg2/out_43
C
Q
CLR
FDCE
CI count1/Mcount_out_xor<22>
O
LI
I1
I1
I2
I3
a_56_IBUF
CI
I0
CE
count1/out_41
Q
count1/out_21_rstpot
count1/out_20_rstpot
I0
I1
Q
CLR
CI sub1/Msub_c_xor<8>
O
LI
sub1/Msub_c_cy<9>
sub1/Msub_c_lut<9>
LUT2
reg2/out_42
C
Q
CLR
FDCE
FDCE
CI count1/Mcount_out_xor<21>
O
LI
XORCY
count1/out_19_rstpot
I0
I1
CE
CI
I5
CE
count1/out_40
Q
I1
reg2/out_41
C
Q
CLR
FDCE
FDCE
I3
I0
CE
count1/out_39
Q
FDCE
I0
I3
sub2/Msub_c_lut<46>
reg2/out_40
C
Q
CLR
FDCE
FDCE
S MUXCY
I2
CE
count1/out_38
Q
FDCE
DI
XORCY
LUT2
reg2/out_39
C
Q
CLR
FDCE
FDCE
CI
XORCY
CE
count1/out_37
Q
I1
reg2/out_38
C
Q
CLR
FDCE
FDCE
I0
XORCY
CI sub1/Msub_c_xor<6>
I0
CE
count1/out_36
Q
count1/Mcount_out_cy<26>_rt
I1
sub2/Msub_c_lut<45>
reg2/out_37
C
Q
CLR
FDCE
FDCE
XORCY
I0
I3
count1/out_15_rstpot
CI sub1/Msub_c_xor<10>
O
LI
CE
FDCE
CI sub1/Msub_c_xor<9>
O
LI
LUT2
LUT2
reg2/out_36
C
Q
CLR
count1/out_35
Q
S MUXCY
I1
S MUXCY
I1
FDCE
CE
FDCE
I1
reg2/out_35
C
Q
O
DI
I0
I2
CLR
CI
S MUXCY
XORCY
I1
LUT2
sub1/Msub_c_lut<16>
CI count1/Mcount_out_xor<19>
O
LI
LUT4
LUT4
FDCE
C
CE
FDCE
S MUXCY
LUT1
I0
S MUXCY
S MUXCY
CE
CE
count1/out_34
Q
FDCE
O
DI
I3
CI sub1/Msub_c_xor<11>
O
LI
CI
S MUXCY
O
DI
sub1/Msub_c_cy<18>
CLR
reg1/out_16
CI
CI
LUT2
FDCE
S MUXCY
I1
sub1/Msub_c_cy<13>
DI
I1
sub1/Msub_c_lut<12>
Q
CLR
O
DI
I0
Q
CLR
CLR
FDCE
count1/Mcount_out_cy<24>
CI
S MUXCY
I4
sub1/Msub_c_lut<13>
FDCE
C
CE
CI
sub1/Msub_c_lut<0>
C
CE
CE
FDCE
O
DI
S MUXCY
Missing_codes_wg_lut<8>
LUT2
CE
D
reg1/out_4
sub1/Msub_c_cy<0>
reg1/out_0
CLR
CLR
count1/out_33
Q
LUT1
count1/Mcount_out_cy<23>
CI
O
DI
S MUXCY
XORCY
XORCY
XORCY
CE
FDCE
FDCE
I0
LUT1
count1/Mcount_out_cy<22>
CI
count1/Mcount_out_cy<24>_rt
LUT1
count1/Mcount_out_cy<21>
O
DI
count1/out_16
CI count1/Mcount_out_xor<15>
O
LI
XORCY
CI sub1/Msub_c_xor<13>
O
LI
CI sub1/Msub_c_xor<12>
O
LI
S MUXCY
CE
sub2/Msub_c_lut<44>
I0
CLR
count1/out_32
Q
FDCE
FDCE
I0
XORCY
count1/out_16_rstpot
CI sub1/Msub_c_xor<14>
O
LI
CI sub1/Msub_c_xor<18>
O
LI
LUT2
O
DI
CLR
FDCE
FDCE
count1/Mcount_out_cy<19>_rt
FDCE
CI count1/Mcount_out_xor<16>
O
LI
CI
XORCY
S MUXCY
I1
XORCY
reg1/out_17
LUT2
CE
count1/out_31
Q
I1
CLR
FDCE
FDCE
I0
LUT1
CI
LUT4
O
DI
I0
sub1/Msub_c_cy<17>
CI
FDCE
C
CE
sub2/Msub_c_lut<43>
I0
CE
FDCE
I0
count1/Mcount_out_cy<22>_rt
count1/Mcount_out_cy<20>
S MUXCY
I3
DI
CI
sub1/Msub_c_lut<20>
FDCE
CI sub1/Msub_c_xor<20>
O
LI
sub1/Msub_c_cy<20>
Q
CLR
a_20_IBUF
IBUF
LUT2
reg1/out_13
LUT2
FDCE
I1
CLR
S MUXCY
I1
20
IBUF
CE
DI
D
Q
a_18_IBUF
S MUXCY
sub1/Msub_c_lut<14>
CI
I0
O
DI
CE
S MUXCY
sub1/Msub_c_lut<4>
CI
CI
O
DI
FDCE
sub1/Msub_c_cy<1>
I2
count1/Mcount_out_cy<15>
XORCY
reg1/out_20
FDCE
reg1/out_18
IBUF
CI
LUT2
CE
a_15_IBUF
I1
LUT2
FDCE
LUT2
CLR
count1/out_30
I1
reg2/out_34
CE
FDCE
I0
LUT1
CI
DI
XORCY
I1
S MUXCY
LUT6
reg2/out_33
C
Q
CLR
count1/out_29
FDCE
count1/Mcount_out_cy<21>_rt
LUT1
count1/Mcount_out_cy<19>
CI count1/Mcount_out_xor<18>
O
LI
DI
I5
CE
CE
FDCE
I0
O
DI
S MUXCY
CI
I4
reg2/out_32
C
Q
CLR
CLR
count1/out_28
FDCE
I0
LUT1
I0
XORCY
count1/Mcount_out_cy<14>
O
I3
CE
CE
FDCE
count1/Mcount_out_cy<25>_rt
count1/Mcount_out_cy<23>_rt
count1/Mcount_out_cy<20>_rt
CI
count1/out_18_rstpot
I0
Q
CLR
I1
I0
count1/out_14_rstpot
CI count1/Mcount_out_xor<14>
O
LI
XORCY
I0
I1
reg2/out_31
C
Q
CLR
FDCE
CLR
count1/out_27
sub2/Msub_c_lut<42>
I0
CE
CE
FDCE
count1/Mcount_out_cy<18>
XORCY
CLR
count1/Mcount_out_cy<16>_rt
CI sub1/Msub_c_xor<15>
O
LI
Missing_codes_wg_lut<7>
reg2/out_30
C
Q
CLR
FDCE
CLR
FDCE
S MUXCY
LUT6
I2
Q
D
S MUXCY
CI count1/Mcount_out_xor<17>
O
LI
O
DI
XORCY
CE
CE
FDCE
CLR
O
DI
CI
I5
CI sub1/Msub_c_xor<16>
O
LI
reg2/out_29
C
Q
CLR
FDCE
CLR
FDCE
CE
LUT1
CI
count1/Mcount_out_cy<16>
CE
CI sub1/Msub_c_xor<17>
O
LI
CE
CE
Q
CLR
count1/out_19
FDCE
I0
count1/Mcount_out_cy<17>
LUT1
count1/out_15
CI sub1/Msub_c_xor<19>
O
LI
reg2/out_28
C
Q
CLR
FDCE
CLR
FDCE
C
CE
Q
D
count1/Mcount_out_cy<18>_rt
LUT4
I0
I4
CI sub1/Msub_c_xor<56>
O
LI
S MUXCY
CE
count1/out_26
CE
reg2/out_18
FDCE
CLR
I3
LUT1
LUT1
I3
XORCY
S MUXCY
LUT2
O
DI
LUT2
reg2/out_27
C
Q
CLR
FDCE
CLR
FDCE
CE
I2
count1/Mcount_out_cy<15>_rt
I0
I0
I1
CI
CE
count1/out_25
C
Q
FDCE
Q
CLR
count1/out_18
I1
S MUXCY
S MUXCY
count1/Mcount_out_cy<13>_rt
I1
reg2/out_26
C
Q
CLR
FDCE
count1/out_24
C
CE
Q
CLR
FDCE
CE
FDCE
I0
O
DI
O
DI
count1/Mcount_out_cy<14>_rt
LUT4
sub2/Msub_c_lut<41>
I0
CE
count1/out_23
C
CE
Q
CLR
C
D
count1/out_13_rstpot
XORCY
CI
CI
I3
O
LI
sub1/Msub_c_lut<24>
sub1/Msub_c_cy<19>
LUT2
reg2/out_25
C
Q
CLR
FDCE
count1/out_22
C
CE
Q
CLR
reg2/out_17
Q
CLR
LUT4
CI count1/Mcount_out_xor<13>
O
LI
count1/Mcount_out_cy<13>
count1/Mcount_out_cy<12>
I0
I1
CE
FDCE
count1/out_21
C
CE
C
CE
I3
I2
I3
count1/out_10_rstpot
LUT4
FDCE
I0
reg2/out_24
C
Q
CLR
FDCE
count1/out_20
count1/out_14
FDCE
I1
LUT4
I0
LUT1
I3
sub2/Msub_c_lut<40>
reg2/out_23
C
CE
Q
CLR
FDCE
LUT1
Q
CLR
FDCE
I2
I0
XORCY
I2
I2
DI
Q
CLR
LUT2
reg2/out_22
C
CE
Q
CLR
D
Q
CLR
FDCE
FDCE
I0
CE
reg2/out_21
C
CE
Q
CLR
CE
FDCE
count1/Mcount_out_cy<17>_rt
C
Q
I1
XORCY
count1/out_11_rstpot
CI count1/Mcount_out_xor<11>
O
LI
count1/Mcount_out_cy<12>_rt
I1
I1
reg2/out_20
C
CE
C
Q
CLR
LUT2
count1/out_13
C
CE
CLR
S MUXCY
LUT1
I0
I1
LUT2
CLR
IBUF
sub1/Msub_c_lut<3>
C
CE
I0
Q
I1
Q
reg1/out_3
IBUF
sub1/Msub_c_lut<1>
C
CE
CLR
I0
CE
IBUF
a_3_IBUF
3
reg1/out_1
sub1/Msub_c_lut<19>
LUT2
I0
reg2/out_19
FDCE
count1/out_17
CE
Q
CLR
I1
count1/out_12
FDCE
I0
CI count1/Mcount_out_xor<12>
O
LI
O
DI
I0
count1/out_9_rstpot
LUT4
sub2/Msub_c_lut<39>
Q
CLR
D
I0
CE
S MUXCY
sub2/Msub_c_lut<11>
FDCE
reg2/out_15
C
O
DI
Q
D
count1/out_12_rstpot
count1/Mcount_out_cy<11>
CI
XORCY
count1/Mcount_out_cy<11>_rt
I2
XORCY
I1
CLR
LUT2
C
CE
reg2/out_14
CI
Q
CLR
FDCE
CLR
FDCE
reg2/out_16
LUT2
FDCE
sub2/Msub_c_cy<11>
CE
CE
I1
C
Q
CLR
count1/out_11
Q
CLR
S MUXCY
CI count1/Mcount_out_xor<10>
O
LI
LUT1
I1
I1
I0
Q
CLR
LUT2
CE
FDCE
C
CE
O
DI
XORCY
I0
sub2/Msub_c_lut<38>
I0
sub2/Msub_c_lut<13>
CE
I1
reg2/out_11
CI
CI count1/Mcount_out_xor<9>
O
LI
count1/out_8_rstpot
I3
XORCY
reg1/out_19
CE
LUT2
I0
S MUXCY
sub2/Msub_c_lut<10>
LUT2
reg2/out_10
Q
CLR
count1/out_10
count1/Mcount_out_cy<10>
O
DI
count1/Mcount_out_cy<10>_rt
I0
S MUXCY
sub1/Msub_c_lut<15>
I1
a_4_IBUF
LUT2
reg2/out_13
O
DI
I1
C
CE
FDCE
CI
S MUXCY
I1
I0
reg2/out_9
Q
CLR
FDCE
LUT1
S MUXCY
LUT2
FDCE
I1
DI
reg1/out_15
S MUXCY
I0
Q
I0
CI
sub2/Msub_c_lut<9>
LUT2
C
CE
count1/Mcount_out_cy<9>
I0
DI
I1
sub2/Msub_c_lut<37>
sub2/Msub_c_cy<10>
S MUXCY
I1
Q
CLR
FDCE
XORCY
sub2/Msub_c_cy<3>
CI
S MUXCY
I0
Q
CLR
I0
CI
O
DI
sub1/Msub_c_lut<2>
C
CE
CLR
I0
count1/out_9
CE
CI count1/Mcount_out_xor<8>
O
LI
count1/Mcount_out_cy<9>_rt
O
DI
sub2/Msub_c_lut<3>
LUT2
C
CE
Q
D
FDCE
sub1/Msub_c_cy<15>
CI
reg1/out_2
LUT2
FDCE
O
DI
sub2/Msub_c_lut<7>
LUT1
CI
I1
FDCE
CLR
I1
CI
FDCE
C
Q
CLR
O
DI
S MUXCY
I0
sub2/Msub_c_cy<2>
S MUXCY
I0
reg2/out_3
CI
IBUF
IBUF
I0
CLR
sub2/Msub_c_cy<7>
reg2/out_7
C
CE
LUT4
CI
S MUXCY
count1/Mcount_out_cy<8>_rt
O
DI
sub2/Msub_c_lut<2>
Q
CLR
CE
Missing_codes_wg_lut<6>
I2
sub2/Msub_c_lut<36>
Q
CLR
count1/out_7
I3
O
DI
LUT1
CI
LUT2
C
CE
count1/out_3
sub1/Msub_c_cy<24>
C
CE
a_24_IBUF
24
IBUF
LUT2
CE
C
CE
FDCE
I2
count1/Mcount_out_cy<8>
CI
I0
sub2/Msub_c_cy<1>
I1
LUT6
XORCY
CI sub1/Msub_c_xor<24>
I1
LUT2
Q
D
I1
XORCY
count1/Mcount_out_cy<7>
count1/Mcount_out_cy<7>_rt
I0
reg2/out_2
I5
XORCY
XORCY
CI sub1/Msub_c_xor<21>
O
LI
sub2/Msub_c_lut<35>
CLR
CI count1/Mcount_out_xor<7>
O
LI
FDCE
LUT4
sub2/Msub_c_lut<1>
XORCY
I4
LUT2
reg1/out_24
FDCE
IBUF
a_0_IBUF
count1/out_8
I1
CE
count1/out_7_rstpot
I0
I3
CI count1/Mcount_out_xor<2>
O
LI
I3
CI sub1/Msub_c_xor<23>
O
LI
CI sub1/Msub_c_xor<25>
O
LI
S MUXCY
I1
LUT2
I0
I3
LUT4
LUT1
I2
XORCY
I0
FDCE
LUT4
I2
LUT2
I2
CLR
S MUXCY
I0
I1
CI sub1/Msub_c_xor<26>
O
LI
LUT2
DI
sub1/Msub_c_lut<25>
IBUF
IBUF
FDCE
S MUXCY
I1
O
DI
count1/Mcount_out_cy<2>_rt
XORCY
I0
S MUXCY
I1
sub1/Msub_c_cy<25>
CI
Q
CLR
a_25_IBUF
25
O
DI
D
I
I0
FDCE
C
CE
CI
I1
a_2_IBUF
a_1_IBUF
O
BUFGP
sub1/Msub_c_lut<26>
reg1/out_25
FDCE
sub1/Msub_c_cy<21>
I0
Q
Q
CLR
I1
I1
I1
C
CE
CI
CI sub1/Msub_c_xor<22>
O
LI
Missing_codes_wg_lut<5>
DI
Q
CLR
S MUXCY
LUT2
IBUF
sub1/Msub_c_lut<21>
I0
reg2/out_12
S MUXCY
I3
I0
I0
I0
reg2/out_0
count1/Mcount_out_cy<2>
XORCY
LUT2
FDCE
C
CE
O
DI
I1
Q
CLR
IBUF
reg1/out_21
CE
CLR
a_5_IBUF
5
clk_BUFGP
IBUF
CI
IBUF
CI
C
CE
FDCE
EOT
FDCE
sub1/Msub_c_cy<23>
sub1/Msub_c_lut<23>
I0
sub1/Msub_c_cy<26>
reg1/out_26
a_26_IBUF
26
S MUXCY
reg1/out_23
CLR
a_23_IBUF
23
a_22_IBUF
22
CE
count1/out_4_rstpot
XORCY
sub2/Msub_c_lut<0>
XORCY
CI sub1/Msub_c_xor<29>
O
LI
S MUXCY
I1
O
DI
LUT2
C
CE
FDCE
sub2/Msub_c_lut<34>
O
DI
count1/out_3_rstpot
I0
Q
CLR
CI count1/Mcount_out_xor<3>
O
LI
XORCY
DI
sub1/Msub_c_lut<29>
C
CE
29
IBUF
CI
I0
reg1/out_22
Q
D
a[63:0]
S MUXCY
CI
reg1/out_29
a_29_IBUF
count1/out_4
S MUXCY
CI count1/Mcount_out_xor<4>
O
LI
O
DI
CI sub1/Msub_c_xor<30>
O
LI
sub1/Msub_c_cy<29>
O
IBUF
I2
O
DI
LUT1
CI
XORCY
XORCY
I1
LUT2
I
a_27_IBUF
27
sub1/Msub_c_cy<22>
sub1/Msub_c_lut<22>
I1
clk
I0
count1/Mcount_out_cy<3>
CI sub1/Msub_c_xor<27>
O
LI
CI sub1/Msub_c_xor<28>
O
LI
S MUXCY
sub1/Msub_c_lut<28>
I0
FDCE
28
S MUXCY
S MUXCY
LUT2
sub2/Msub_c_cy<9>
CI
O
DI
LUT2
a_28_IBUF
O
DI
S MUXCY
C
CE
CLR
O
DI
I1
S MUXCY
count1/Mcount_out_cy<4>_rt
XORCY
LUT2
FDCE
sub1/Msub_c_cy<28>
CI
I1
CLR
CI
LUT2
O
DI
LUT2
reg1/out_9
IBUF
CI
I0
O
DI
count1/Mcount_out_cy<4>
CI sub1/Msub_c_xor<43>
O
LI
S MUXCY
I1
IBUF
O
DI
sub1/Msub_c_lut<27>
C
CE
sub1/Msub_c_cy<10>
I1
CI
I1
sub1/Msub_c_cy<6>
I1
S MUXCY
FDCE
CI
Q
CLR
CI
reg1/out_27
LUT2
FDCE
I0
sub1/Msub_c_cy<8>
I0
a_9_IBUF
9
LUT2
S MUXCY
I0
O
DI
count1/out_6_rstpot
CI
I5
LUT6
I0
CE
a_43_IBUF
43
sub1/Msub_c_cy<27>
I1
sub1/Msub_c_lut<10>
S MUXCY
sub1/Msub_c_lut<43>
S MUXCY
LUT2
FDCE
IBUF
I0
Q
CLR
FDCE
O
DI
sub1/Msub_c_lut<8>
I1
DI
sub2/Msub_c_lut<33>
CI
Q
CLR
DI
reg1/out_43
O
DI
I1
D
D
sub1/Msub_c_lut<11>
C
CE
IBUF
CI
LUT2
FDCE
I0
CI
LUT2
sub2/Msub_c_cy<8>
LUT2
CE
S MUXCY
FDCE
LUT4
sub2/Msub_c_cy<0>
I4
CI
CI
I0
CLR
CLR
IBUF
reg1/out_11
Q
CLR
sub1/Msub_c_cy<7>
I1
sub1/Msub_c_cy<5>
I1
O
I1
O
DI
sub2/Msub_c_lut<5>
I0
I3
XORCY
I3
XORCY
sub1/Msub_c_cy<43>
sub1/Msub_c_cy<30>
Q
Q
a_12_IBUF
12
C
CE
a_10_IBUF
10
I0
Q
CLR
IBUF
FDCE
I2
LI
I2
XORCY
CI sub1/Msub_c_xor<35>
O
LI
FDCE
sub1/Msub_c_lut<30>
C
CE
IBUF
reg1/out_10
FDCE
sub1/Msub_c_lut<7>
C
CE
a_8_IBUF
I
sub1/Msub_c_lut<6>
Q
CLR
I1
sub2/Msub_c_lut<32>
I0
I0
CI
S MUXCY
reg2/out_5
D
C
I1
LI
LUT2
reg1/out_30
reg1/out_7
C
CE
I0
Q
sub2/Msub_c_lut<8>
reg2/out_8
O
DI
Q
CLR
LUT2
S MUXCY
LUT2
sub2/Msub_c_cy<5>
CI
C
CE
I0
I1
I1
sub2/Msub_c_cy<4>
LUT2
count1/out_5
XORCY
count1/out_5_rstpot
CI count1/Mcount_out_xor<5>
I1
O
DI
sub2/Msub_c_lut<6>
I1
CI count1/Mcount_out_xor<6>
O
LI
O
DI
S MUXCY
I1
CLR
IBUF
O
IBUF
CE
11
Q
CLR
IBUF
reg1/out_6
sub1/Msub_c_lut<5>
I0
CI
FDCE
I0
count1/Mcount_out_cy<5>
CI
I0
sub2/Msub_c_lut<31>
sub2/Msub_c_cy<6>
Q
CLR
FDCE
sub2/Msub_c_lut<4>
O
LUT1
Missing_codes_wg_lut<4>
CI sub1/Msub_c_xor<31>
CE
a_14_IBUF
14
reg1/out_12
a_11_IBUF
C
CE
IBUF
CE
LUT2
FDCE
O
DI
S MUXCY
I0
XORCY
LUT2
a_13_IBUF
13
reg1/out_8
a_7_IBUF
7
a_6_IBUF
reg1/out_5
reg2/out_6
CLR
CE
CI
count1/Mcount_out_cy<5>_rt
CI sub1/Msub_c_xor<34>
O
LI
S MUXCY
I1
S MUXCY
O
DI
count1/Mcount_out_cy<6>
sub1/Msub_c_cy<32>
LUT2
CI
LUT1
XORCY
CI
DI
I1
sub1/Msub_c_cy<31>
CE
Q
count1/Mcount_out_cy<6>_rt
CI sub1/Msub_c_xor<32>
O
LI
sub1/Msub_c_cy<34>
FDCE
C
Q
CLR
S MUXCY
LUT2
FDCE
I0
FDCE
I1
CLR
sub1/Msub_c_lut<32>
Q
CLR
I0
I1
CE
Q
CLR
I
IBUF
C
CE
O
IBUF
sub2/Msub_c_lut<30>
count1/out_6
DI
reg1/out_35
C
CE
a_34_IBUF
34
reg1/out_32
a_32_IBUF
LUT2
reg2/out_4
I1
XORCY
sub1/Msub_c_cy<35>
CI
32
sub2/Msub_c_lut<29>
CI sub1/Msub_c_xor<33>
O
LI
S MUXCY
a_35_IBUF
35
FDCE
I1
DI
LUT2
sub2/Msub_c_lut<28>
sub1/Msub_c_cy<33>
O
I1
CLR
error1
I3
LUT4
error_OBUF
I0
LUT4
I1
count1/Mcount_out_xor<63>_rt
I0
LUT1
CI count1/Mcount_out_xor<63>
O
LI
XORCY
OBUF
I2
LUT3
error