DIGITAL SYSTEM DESIGN USING VHDL (10EE755)

COURSE OBJECTIVES:
I
Understand different methods for logic representation, manipulation, and optimization, for
both combinational and sequential logic.
II Describe the major modeling features of VHDL language.
III Appreciate the implementation and testing of digital systems using FPGAs.
COURSE OUTCOMES:
SN
DESCRIPTION
O
1
Identify several fundamental concepts that can be applied to a wide variety of
digital design problems.
2
Write, compile, and simulate VHDL models of digital systems.
3
Work in relevant topics for their academic projects.
QUESTIONS BASED ON OUTCOME 2:
Each question carries 1 mark
1. VHDL stands for ______________________________
2. List the different VHDL design styles.
3. Write the general syntax of entity declaration.
4. The symbol <= implies ________________________
5. What is sensitivity list in a VHDL process?
Each question carries 2 marks
1. Under what conditions do the two assignments below result in the same behavior?
out<= reject 5 ns inertial (not a) after 20 ns;
out<= transport (not a) after 20 ns;
2. Write the architecture of a half adder using concurrent signal assignment
statements.
3. Explain VHDL package with the general syntax.
Each question carries 5 marks
1. Model a 4 to 1 MUX using mixed style.
2. Write a VHDL description of the following combinational network using
concurrent statements.