Behavior model

1. 2 bit comparator

module comp(agb,alb, aeb ,b,a);

input [1:0] a;
input [1:0] b;
output alb,agb,aeb;
reg alb,agb,aeb;
always @(a)
begin
agb=0;
alb=0;
aeb=0;
if(a>b)
agb=1;
if(a<b)
alb=1;
if(a==b)
aeb=1;
end
endmodule

2. D flip flop positive clock cycle

module dff1(d, rst, clk, q, qbar);

input d;
input rst;
input clk;
output q;
output qbar;
reg q,qbar;
always @ (posedge clk or posedge rst)
begin
if(rst==1)
begin
q=0;
qbar=1;
end
if(clk==1)
begin
q=d;
qbar=~d;
end
end
endmodule
3. D flip flop negative clock cycle

module dff1(d, rst, clk, q, qbar);

input d;
input rst;
input clk;
output q,qbar;
reg q,qbar;
always @ (negedge clk or negedge rst)
begin
if(rst==1)
begin
q=0;
qbar=1;
end
if(clk==1)
begin
q=d;
qbar=~d;
end
end
endmodule

4. D latch positive enable

module dlatch1(d, cntrl, rst, q, qbar);

input d;
input cntrl;
input rst;
output q;
output qbar;
reg q,qbar;
always @ (d,rst)
begin
if(rst==1)
begin
q=0;
qbar=1;
end
if(cntrl==1)
begin
q=d;
qbar=~d;
end
end
endmodule
5. T flip flop Synchronous reset

module tff(t, rst, clk, q, qbar);

input t;
input rst;
input clk;
output q;
output qbar;
reg q,qbar;
always@(posedge clk or posedge rst)
begin
if(rst==1)
begin
q=0;
qbar=1;
end
if(clk==1)
if(t==1)
begin
q=~q;
qbar=~qbar;
end
end
endmodule

6. SR flip flop

module srff1(s, r, clk, rst, q, qbar);

input s;
input r;
input clk;
input rst;
output q;
output qbar;
reg q,qbar;
always @(posedge clk or posedge rst)
begin
if(rst==1)
begin
q=0;
qbar=1;
end
if(clk==1)
begin
 case({s,r})
2'b00:begin
q=0;
qbar=1;
end
2'b01:begin
q=s;
qbar=r;
end
2'b10:begin
q=s;
qbar=r;
end
endcase
end
end
endmodule

7. JK flip flop positive clock cycle

module jkff(j,k,clk,reset, q,qbar);

input j,k,clk,reset;
output q,qbar;
reg q,qbar;
always @ (posedge clk or posedge reset)
begin
if(reset==1)
begin
q=0;
qbar=~q;
end
if(clk==1)
begin
if(j==0 & k==0)
begin
q=q;
qbar=~q;
end
if(j==0 & k==1)
begin
q=0;
qbar=~q;
end
if(j==1 & k==0)
begin
q=1;
 qbar=~q;
end
if(j==1 & k==1)
begin
q=~q;
qbar=~q;
end
end
end
endmodule

8. Conversion of D to T flip flop

module ffdtot1(t, clk, rst, q, qbar,d);

input t;
input clk;
input rst;
output q;
output qbar,d;
reg q,qbar,d;
always @ (posedge clk or posedge rst)
begin
if(rst==1)
begin
q=0;
qbar=1;
end
if(clk==1)
begin
d=t^q;
q=d;
qbar=~d;
end
end
endmodule

9. Conversion of T to D flip flop

module ffttod1(d, clk, rst,t, q, qbar);

input d;
input clk;
input rst;
output q;
output qbar,t;
reg q,qbar,t;
always @ (posedge clk or posedge rst)
 begin
if(rst==1)
begin
q=0;
qbar=1;
end
if(clk==1)
begin
t=d^q;
if(t==0)
begin
q=q;
qbar=qbar;
end
else
begin
q=~q;
qbar=~qbar;
end
end
end
endmodule

10. Conversion of JK to T flip flop

module ffconv(t,clk,reset, q,qbar,j,k);

input t,clk,reset;
output q,qbar,j,k;
reg q,qbar,j,k;
always @ (posedge clk or posedge reset)
begin
if(reset==1)
begin
j=t;
k=t;
q=0;
qbar=~q;
end
if(clk==1)
begin
j=t;
k=t;
if(j==0 & k==0)
begin
q=q;
qbar=~q;
 end
if(j==1 & k==1)
begin
q=~q;
qbar=~q;
end
end
end
endmodule

11. 2:4 Decoder

module deco24(o,i,en);
input en;
input [1:0] i;
output [3:0] o;
reg [1:0] o;
always @ (en,i)
begin
if(en==1)
begin
o[0]= (~i[0])&(~i[1]);
o[1]= (~i[0])&i[1];
o[2]= i[0]&(~i[0]);
o[3]=i[0]&i[1];
end
end
endmodule

12. 3:8 Decoder

module deco38(o,i,en);
input en;
input [2:0] i;
output [7:0] o;
reg [1:0] o;
always @ (en,i)
begin
if(en==1)
begin
o[0]= (~i[0])&(~i[1])&(~i[2]);
o[1]= (~i[0])&(~i[1])&(i[2]);
o[2]= (~i[0])&(i[1])&(~i[2]);
o[3]= (~i[0])&(i[1])&(i[2]);
o[4]= (i[0])&(~i[1])&(~i[2]);
 o[5]= (i[0])&(~i[1])&(i[2]);
o[6]= (i[0])&(i[1])&(~i[2]);
o[7]= (i[0])&(i[1])&(i[2]);

end
end
endmodule

13. 4:2 Encoder

module enco42(o,i,en);
input en;
input [3:0] i;
output [1:0] o;
reg [1:0] o;
always @ (en,i)
begin
if(en==1)
begin
o[1] = i[2]^i[3];
o[0]= i[1]^i[3];
end
end
endmodule

14. 8:3 Encoder

module enco83(o,i,en);
input en;
input [7:0] i;
output [2:0] o;
reg [1:0] o;
always @ (en,i)
begin
if(en==1)
begin
o[2]=i[4]^i[5]^i[6]^i[7];
o[1]= i[2]^i[3]^i[6]^i[7];
o[0]= i[1]^i[3]^i[5]^i[7];
end
end
endmodule
15. 4 bit serial adder

module sa(a,b,c,clk,s,c1);
input [3:0]a,b;
input clk,c;
output reg [3:0] s;
output reg c1;
always@(posedge clk)
begin
{c1,s}=a+b+c;
end
endmodule

16. 4 bit parallel adder

module pa(a,b,c,s,c1);
input [3:0]a,b;
input c;
output reg [3:0]s;
output reg c1;
always @(*)
begin
{c1,s}=a+b+c;
end
endmodule

17. 8 bit multiplier

module mul(a, b, c);

input [7:0]a;
input [7:0]b;
output [15:0]c;
reg [15:0]c;
always @(a or b)
begin
c=a*b;
end
endmodule
 18. Synchronous counter

module cntr(q,clk,rst,load,inp);
input clk,rst,load;
input [3:0] inp;
output [3:0] q;
reg [3:0] q;
always @ (posedge clk or posedge rst)
begin
if(rst==1)
q=0;
else if(clk==1)
begin
if(load==1)
q=inp;
else
q=q+1;
end
end
endmodule

Data Flow model

1. Full adder using 2 half adder

module fav1(a, b, c, s, ca);

input a;
input b;
input c;
output s;
output ca;
wire s1,s2,s3;
assign s1=a^b;
assign s=s1^c;
assign s2=a&b;
assign s3=s1&c;
assign ca=s2|s3;
endmodule
2. Full Subractor using 2 half Subractor

module fav1(a, b, c, s, ca);

input a;
input b;
input c;
output s;
output ca;
wire s1,s2,s3;
assign s1=a^b;
assign s=s1^c;
assign s2=(~a)&b;
assign s3=s1&c;
assign ca=s2|s3;
endmodule

3. BCD to Excess 3 conversion

module bcdex3(b1,b2,b3,b0,e0,e1,e2,e3);
input b0,b1,b2,b3;
output e0,e1,e2,e3;
assign e0=~b0;
assign e1= ( (~b1) & (~b0)) | ( b1 & b0) ;
assign e2= ( b2 & (~b1) & (~b0)) | ((~b2) &( b0 | b1));
assign e3 = b3 | ( b2 & (b0 | b1));
endmodule

4. Binary to Gray conversion

module b2g(b1,b2,b3,b0,g0,g1,g2,g3);
input b0,b1,b2,b3;
output g0,g1,g2,g3;
assign g0 = ( b1^ b0) ;
assign g1 = ( b2 ^ b1);
assign g2 = ( b3 ^ b2 );
assign g3 = b3;
endmodule

5. Equation solving F(A,B,C,D)=∑(1,4,7,9,15)

module eq1(a,b,c,d,f);
input a,b,c,d;
output f;
assign f=((~b)&(~c)&d)|(b&c&d)|((~a)&b&(~c)&(~d));
6. Equation solving F(A,B,C,D)=∑(0,2,,5,6,7)

module eq2(a,b,c,d,f);
input a,b,c,d;
output f;
assign f=((~a)&(~b)&(~d))|((~a)&b&d)|((~a)&b&c);
endmodule

7. Equation solving F(A,B,C,D)=∏(0,1,4,5,6,8,9,12,13,14)

module eq3(a,b,c,d,f);
input a,b,c,d;
output f;
assign f=c&((~b)|d);
endmodule

8. Mux 8:1

module mux81(i,s1,s2,s3,y);
input [7:0]i;
input s1,s2,s3;
output y;
wire ns1,ns2,ns3;
assign ns1=~s1;
assign ns2=~s2;
assign ns3=~s3;

assign y=(i[0]&ns1&ns2&ns3)|
(i[1]&ns1&ns2&s3)|
(i[2]&ns1&s2&ns3)|
(i[3]&ns1&s2&s3)|
(i[4]&s1&ns2&ns3)|
(i[5]&s1&ns2&s3)|
(i[6]&s1&s2&ns3)|
(i[7]&s1&s2&s3);
endmodule

9. DeMux 1:8

module demux18(d,s1,s2,s3,y);
input s1,s2,s3,d;
output [7:0]y;
wire ns1,ns2,ns3;
assign ns1=~s1;
 assign ns2=~s2;
assign ns3=~s3;
assign y[0]=d&ns1&ns2&ns3;
assign y[1]=d&ns1&ns2&s3;
assign y[2]=d&ns1&s2&ns3;
assign y[3]=d&ns1&s2&s3;
assign y[4]=d&s1&ns2&ns3;
assign y[5]=d&s1&ns2&s3;
assign y[6]=d&s1&s2&ns3;
assign y[7]=d&s1&s2&s3;
endmodule

Gate Level Model 

1. SR latch using nand Gate level

module srnand (q, qBar, set, reset);

output q, qBar;
input set, reset;

nand #2
(q, qBar, set),
(qBar, q, reset);
endmodule

2. SR  latch using nor Gate level

module srnor (q, qBar, set, reset);

output q, qBar;
input set, reset;

nor #2
(q, qBar, set),
(qBar, q, reset);
endmodule
Schematic method

1. Full adder using Nor gate only  Schematic

S=((~a)&(~b)&c) |((~a)&b&(~c))|(a&(~b)&(~c))|(a&b&c)

Cout=(a&b)|(a&c)|(b&c)
2. Full Subractor using Nand gate only Schematic

d=((~a)&(~b)&c) |((~a)&b&(~c))|(a&(~b)&(~c))|(a&b&c)

bout=((~a)&b)|((~a)&c)|(b&c)
Traffic light controller
 
1. Four way traffic light controller

module tr_4way(clk, reset, p1, p2, p3, p4, pl,pm);

input clk;
input reset;
output [4:0] p1;
output [4:0] p2;
output [4:0] p3;
output [4:0] p4;
output [3:0] pl,pm;
reg[4:0] p1;
reg[4:0] p2;
reg[4:0] p3;
reg[4:0] p4;
reg[3:0] pl,pm;
reg[5:0] sig;
reg[21:0] pulse;
reg proclk=0;
always@(posedge clk or posedge reset)
begin
if(reset==1)
pulse<=22 'b0;
else
begin
if(pulse==22'b1111010000100100000000)
begin
proclk=proclk+1;
pulse<=22 'b0;
end
else
pulse<=pulse+1;
end
end
always@(posedge proclk or posedge reset)
begin
if(reset==1)
begin
p1=5 'b00100;
p2=5 'b00100;
p3=5 'b00100;
p4=5 'b00100;
pl=4 'b1111;
pm=~pl;
sig=6 'b111111;
end

else
begin
sig=sig+1;
case(sig[5:0])
6 'b000000:begin //path1 & 3 green(SG & LG)
p1=5 'b00100;
p2=5 'b00100;
p3=5 'b00100;
p4=5 'b00100;
pl=4 'b1111;
pm=~pl;
end
6 'b000010: begin //path1 & 3 yellow
p1=5 'b01000;
end

6 'b000100: begin //path1 & 3 green(only RG)

p1=5 'b10011;
end

6 'b001100: begin //path2 & 4 green(SG & LG)

p1=5 'b01000;
p2=5 'b01000;
end

6 'b001110: begin //path2 & 4 yellow

p1=5 'b00100;
p2=5 'b10011;
end

6 'b010110: begin //path2 & 4 green(only RG)

p2=5 'b01000;
p3=5 'b01000;
end

6 'b011000: begin //pedestrian are green

p2=5'b00100;
p3=5'b10011;
end

6 'b100000: begin
p3=5'b01000;
p4=5'b01000;
end
 6 'b100010: begin
p3=5'b00100;
p4=5'b10011;
end

6 'b101010: begin
p4=5'b01000;
end

6 'b101100: begin
p4=5'b00100;
end

6 'b101110: begin
pl=4'b0000;
pm=~pl;
end

6 'b111000: begin
pl=4'b1111;
pm=~pl;
end

6 'b111010:sig=6 'b111111;
default:begin
end
endcase
end
end
endmodule

///
#PACE: Start of Constraints generated by PACE

#PACE: Start of PACE I/O Pin Assignments

NET "clk" LOC = "p181" ;
NET "p1<0>" LOC = "p122" ;
NET "p1<1>" LOC = "p125" ;
NET "p1<2>" LOC = "p120" ;
NET "p1<3>" LOC = "p119" ;
NET "p1<4>" LOC = "p123" ;
NET "p2<0>" LOC = "p147" ;
NET "p2<1>" LOC = "p130" ;
NET "p2<2>" LOC = "p126" ;
NET "p2<3>" LOC = "p131" ;
NET "p2<4>" LOC = "p146" ;

NET "p3<0>" LOC = "p111" ;

NET "p3<1>" LOC = "p150" ;
NET "p3<2>" LOC = "p108" ;
NET "p3<3>" LOC = "p113" ;
NET "p3<4>" LOC = "p152" ;

NET "p4<0>" LOC = "p114" ;

NET "p4<1>" LOC = "p107" ;
NET "p4<2>" LOC = "p109" ;
NET "p4<3>" LOC = "p106" ;
NET "p4<4>" LOC = "p115" ;

NET "pl<0>" LOC = "p124" ;

NET "pl<1>" LOC = "p149" ;
NET "pl<2>" LOC = "p13" ;
NET "pl<3>" LOC = "p117" ;

NET "pm<0>" LOC = "p128" ;

NET "pm<1>" LOC = "p148" ;
NET "pm<2>" LOC = "p12" ;
NET "pm<3>" LOC = "p116" ;

NET "reset" LOC = "p182" ;

#PACE: Start of PACE Area Constraints

#PACE: Start of PACE Prohibit Constraints

#PACE: End of Constraints generated by PACE

P1NORTH
P2WEST.
P3SOUTH.
P4EAST.
BIT 4 3 2 1 0
LOCATION
LIGHT Straight yellow Red Left Right
green green green

2. Two way traffic light controller