Design and implement the circuit as in the blocks diagram of figure.

It must do the following:

A 4-bit binary number can be loaded by the latch circuit, the number pass to the shift registers by means of a clock signal F of 5 Hz,
then the data can be rotated in the displays, or the data can be erased with a frequency of 1 Hz.

SWo to SW3 Data input

SW5(Push button) = with one pulse, the data (from D type FF´s) are loaded to U1 by means of the shift registers.

SW4 = 1L data is shifted to the next display or re-circulated; with 0L the shifting is stopped and a new data can be loaded with a pulse
in SW5, again to U1.

SW6 = 1L, data can re-circulate, 0L, The displays are erased (blanked) at a frequency of 1 Hz. (not all at the same time, but one by one
at the indicated frequency)

Hint: You can use the following IC’s among others 74116N, 74194N, or any one other at your convenience.
 Do
SWo LATCH
D1
SW1
D2
SW2
D3 D TYPE
SW3 F-F’s

F-F

SHIFT SHIFT SHIFT SHIFT

REGISTER REGISTER REGISTER REGISTER

M
U
1 2 3 4 5 6 7 8 9 10 11 12 X
COMB.
CIRCUIT

1 4 7 10 2 5 8 11 3 6 9 12
SW5 SW4 F

F1
SW6
0,5Hz

U1 U2 U3 U4