ENGINEERING MATHEMATICS – III

PART – B
Sub Code : 06MAT31 IA Marks : 25
Hrs/ Week : 04 Exam Hours : 03 UNIT 5:
Total Hrs. : 52 Exam Marks : 100 Numerical Methods
Introduction, Numerical solutions of algebraic and transcendental equations:-
PART – A Newton-Raphson and Regula-Falsi methods. Solution of linear simultaneous
equations : - Gauss elimination and Gauss Jordon methods. Gauss - Seidel
UNIT 1: iterative method. Definition of eigen values and eigen vectors of a square
Fourier Series matrix. Computation of largest eigen value and the corresponding eigen
Periodic functions, Fourier expansions, Half range expansions, Complex vector by Rayleigh’s power method.
form of Fourier series, Practical harmonic analysis. 6 Hours

7 Hours UNIT 6:
UNIT 2: Finite differences (Forward and Backward differences) Interpolation,
Fourier Transforms Newton’s forward and backward interpolation formulae. Divided differences
Finite and Infinite Fourier transforms, Fourier sine and consine transforms, – Newton’s divided difference formula. Lagrange’s interpolation and inverse
properties. Inverse transforms. interpolation formulae. Numerical differentiation using Newton’s forward
6 Hours and backward interpolation formulae. Numerical Integration – Simpson’s
one third and three eighth’s value, Weddle’s rule.
UNIT 3: (All formulae / rules without proof)
Partial Differential Equations (P.D.E) 7 Hours
Formation of P.D.E Solution of non homogeneous P.D.E by direct
integration, Solution of homogeneous P.D.E involving derivative with UNIT 7:
respect to one independent variable only (Both types with given set of Calculus of Variations
conditions) Method of separation of variables. (First and second order Variation of a function and a functional Extremal of a functional, Variational
equations) Solution of Lagrange’s linear P.D.E. of the type P p + Q q = R. problems, Euler’s equation, Standard variational problems including
6 Hours geodesics, minimal surface of revolution, hanging chain and Brachistochrone
problems.
UNIT 4: 6 Hours
Applications of P.D.E
Derivation of one dimensional wave and heat equations. Various possible UNIT 8:
solutions of these by the method of separation of variables. D’Alembert’s Difference Equations and Z-transforms
solution of wave equation. Two dimensional Laplace’s equation – various Difference equations – Basic definitions. Z-transforms – Definition,
possible solutions. Solution of all these equations with specified boundary Standard Z-transforms, Linearity property, Damping rule, Shifting rule,
conditions. (Boundary value problems). Initial value theorem, Final value theorem, Inverse Z-transforms.
7 Hours Application of Z-transforms to solve difference equations.
7 Hours

3 4
 Note:
Text Book: Higher Engineering Mathematics by Dr. B.S. Grewal (36th
Edition – Khanna Publishers) 1. One question is to be set from each unit.
2. To answer Five questions choosing atleast Two questions from each part.
Unit Chapter Article Numbers Page Nos.
No. No.
I 10 10.1 to 10.7, 10.10 and 10.11 375 – 400 ANALOG ELECTRONIC CIRCUITS
(Common to EC/TC/EE/IT/BM/ML)
II 22 22.4, 22.5 716 – 722
Sub Code : 06ES32 IA Marks : 25
III 17, 18 17.1 to 17.5, 18.2 541 – 547 Hrs/ Week : 04 Exam Hours : 03
562 – 564 Total Hrs. : 52 Exam Marks : 100

IV 18 18.4, 18.5, 18.7 564 – 578

580 – 582 PART – A
UNIT 1:
V 24 24.1, 24.2, 24.4 to 24.6, 24.8 820 – 826 Diode Circuits: Diode Resistance, Diode equivalent circuits, Transition and
829 – 840 diffusion capacitance, Reverse recovery time, Load line analysis, Rectifiers,
843 – 845 Clippers and clampers. (Chapter 1.6 to 1.14, 2.1 to 2.9)
6 Hours
VI 25 25.1, 25.5, 25.12 to 25.14, 25.16 846, 847
857 – 862 UNIT 2:
871 – 878 Transistor Biasing: Operating point, Fixed bias circuits, Emitter stabilized
881 – 887 biased circuits, Voltage divider biased, DC bias with voltage feedback,
Miscellaneous bias configurations, Design operations, Transistor switching
VII 30 30.1 to 30.5 1018 – 1025 networks, PNP transistors, Bias stabilization. (Chapter 4.1 to 4.12)
7 Hours
VIII 26 26.1, 26.2, 26.9 to 26.15, 26.20, 888, 889
26.21 899 – 913 UNIT 3:
Transistor at Low Frequencies: BJT transistor modeling, Hybrid equivalent
model, CE Fixed bias configuration, Voltage divider bias, Emitter follower,
CB configuration, Collector feedback configuration, Hybrid equivalent
Reference Books:
model. (Chapter 5.1 to 5.3, 5.5 to 5.17)
1. Higher Engineering Mathematics by B.V. Ramana (Tata-Macgraw
Hill). 7 Hours
2. Advanced Modern Engineering Mathematics by Glyn James –
Pearson Education. UNIT 4:
Transistor Frequency Response: General frequency considerations, low
frequency response, Miller effect capacitance, High frequency response,
multistage frequency effects. (Chapter 9.1 to 9.5, 9.6, 9.8, 9.9)
6 Hours
5 6
 PART – B Question Paper Pattern: Student should answer FIVE full questions out of
UNIT 5: 8 questions to be set each carrying 20 marks, selecting at least TWO
(a) General Amplifiers: Cascade connections, Cascode connections, questions from each part.
Darlington connections. (Chapter 5.19 to 5.27)
3 Hours
(b) Feedback Amplifier: Feedback concept, Feedback connections type, LOGIC DESIGN
Practical feedback circuits. (Chapter 14.1 to 14.4) (Common to EC/TC/EE/IT/BM/ML)
3 Hours
Sub Code : 06ES33 IA Marks : 25
UNIT 6: Hrs/ Week : 04 Exam Hours : 03
Power Amplifiers: Definitions and amplifier types, series fed class A Total Hrs. : 52 Exam Marks : 100
amplifier, Transformer coupled Class A amplifiers, Class B amplifier
operations, Class B amplifier circuits, Amplifier distortions. (Chapter 12.1 to
12.9) PART –A
7 Hours
UNIT 1:
UNIT 7: Principles of combinational logic-1: Definition of combinational logic,
Oscillators: Oscillator operation, Phase shift Oscillator, Wienbridge Canonical forms, Generation of switching equations from truth tables,
Oscillator, Tuned Oscillator circuits, Crystal Oscillator. (Chapter 14.5 to Karnaugh maps-3, 4 and 5 variables, Incompletely specified functions (Don’t
14.11) (BJT version only) Care terms), Simplifying Max term equations. [(Text book 1) 3.1, 3.2, 3.3,
6 Hours 3.4].
7 Hours
UNIT 8:
FET Amplifiers: FET small signal model, Biasing of FET, Common drain UNIT 2:
common gate configurations, MOSFETs, FET amplifier networks. (Chapter Principles of combinational Logic-2: Quine-McCluskey minimization
8.1 to 8.13) technique- Quine-McCluskey using don’t care terms, Reduced Prime
7 Hours Implicant Tables, Map entered variables [(Text book 1) 3.5, 3.6]
7 Hours
TEXT BOOK:
1. “Electronic Devices and Circuit Theory”, Robert L. Boylestad and UNIT 3:
Louis Nashelsky, PHI/Pearson Eduication. 9TH Edition. Analysis and design of combinational logic - I: General approach,
Decoders-BCD decoders, Encoders. [(Text book 1) 4.1, 4.3, 4.4]
6 Hours
UNIT 4:
REFERENCE BOOKS: Analysis and design of combinational logic - II: Digital multiplexers-
1. ‘Integrated Electronics’, Jacob Millman & Christos C. Halkias, Tata - Using multiplexers as Boolean function generators. Adders and subtractors-
McGraw Hill, 1991 Edition Cascading full adders, Look ahead carry, Binary comparators. [(Text book 1)
2. “Electronic Devices and Circuits”, David A. Bell, PHI, 4th Edition, 4.5, 4.6 - 4.6.1, 4.6.2, 4.7]
2004 6 Hours
7 8
 PART –B REFERENCE BOOKS:
1. “Fundamentals of logic design”, Charles H Roth, Jr; Thomson
UNIT 5: Learning, 2004.
Sequential Circuits – 1: Basic Bistable Element, Latches, SR Latch, 2. “Logic and computer design Fundamentals”, Mono and Kim,
Application of SR Latch, A Switch Debouncer, The S R Latch, The gated Pearson, Second edition, 2001.
SR Latch, The gated D Latch, The Master-Slave Flip-Flops (Pulse-Triggered
Flip-Flops): The Master-Slave SR Flip-Flops, The Master-Slave JK Flip-
NETWORK ANALYSIS
Flop, Edge Triggered Flip-Flop: The Positive Edge-Triggered D Flip-Flop,
(Common to EC/TC/EE/IT/BM/ML)
Negative-Edge Triggered D Flip-Flop. [(Text book 2) 6.1, 6.2, 6.4, 6.5]
Sub Code : 06ES34 IA Marks : 25
7 Hours
Hrs/ Week : 04 Exam Hours : 03
UNIT 6:
Total Hrs. : 52 Exam Marks : 100
Sequential Circuits – 2: Characteristic Equations, Registers, Counters -
Binary Ripple Counters, Synchronous Binary counters, Counters based on
Shift Registers, Design of a Synchronous counters, Design of a Synchronous
PART – A
Mod-6 Counter using clocked JK Flip-Flops Design of a Synchronous Mod-6
Counter using clocked D, T, or SR Flip-Flops [(Text book 2) 6.6, 6.7, 6.8,
UNIT 1:
6.9 – 6.9.1 and 6.9.2]
Basic Concepts: Practical sources, Source transformations, Network
7 Hours reduction using Star – Delta transformation, Loop and node analysis With
linearly dependent and independent sources for DC and AC networks,
UNIT 7: Concepts of super node and super mesh
Sequential Design - I: Introduction, Mealy and Moore Models, State
7 Hours
Machine Notation, Synchronous Sequential Circuit Analysis, [(Text book 1)
UNIT 2:
6.1, 6.2, 6.3]
Network Topology: Graph of a network, Concept of tree and co-tree,
6 Hours incidence matrix, tie-set, tie-set and cut-set schedules, Formulation of
equilibrium equations in matrix form, Solution of resistive networks,
UNIT 8: Principle of duality.
Sequential Design - II: Construction of state Diagrams, Counter Design
7 Hours
[(Text book 1) 6.4, 6.5]
UNIT 3:
6 Hours Network Theorems – 1: Superposition, Reciprocity and Millman’s
theorems
TEXT BOOKS: 6 Hours
1. “Digital Logic Applications and Design”, John M Yarbrough,
Thomson Learning, 2001.
UNIT 4:
2. “Digital Principles and Design “, Donald D Givone, Tata McGraw Hill
Network Theorems - II:
Edition, 2002.
Thevinin’s and Norton’s theorems; Maximum Power transfer theorem
6 Hours

9 10
 Question Paper Pattern: Student should answer FIVE full questions out of
PART – B 8 questions to be set each carrying 20 marks, selecting at least TWO
questions from each part.
UNIT 5: Resonant Circuits: Series and parallel resonance, frequency-
response of series and Parallel circuits, Q –factor, Bandwidth. Coverage in the Texts:
6Hours UNIT 1: Text 2: 1.6, 2.3, 2.4 (Also refer R1:2.4, 4.1 to 4.6; 5.3, 5.6; 10.9
This book gives concepts of super node and super mesh)
UNIT 6: UNIT 2: Text 2: 3.1 to 3.11
Transient behavior and initial conditions: Behavior of circuit elements UNIT 3 and UNIT 4: Text 2 – 7.1 to 7.7
under switching condition and their Representation, evaluation of initial and UNIT 5: Text 2 – 8.1 to 8.3
final conditions in RL, RC and RLC circuits for AC and DC excitations. UNIT 6: Text 1 – Chapter 5;
UNIT 7: Text 1 – 7.4 to 7.7; 8.1 to 8.5
7 Hours UNIT 8: Text 1 – 11.1 to 11.6
UNIT 7:
Laplace Transformation & Applications : Solution of networks, step, ELECTRONIC INSTRUMENTATION
ramp and impulse responses, waveform Synthesis (Common to EC/TC/IT/BM/ML)
7 Hours
Sub Code : 06IT35 IA Marks : 25
UNIT 8: Hrs/ Week : 04 Exam Hours : 03
Two port network parameters: Definition of z, y, h and transmission Total Hrs. : 52 Exam Marks : 100
parameters, modeling with these parameters, relationship between parameters
sets PART – A
6 Hours UNIT – 1:
TEXT BOOKS: Introduction
1. “Network Analysis”, M. E. Van Valkenburg, PHI / Pearson Education, (a) Measurement Errors: Gross errors and systematic errors, Absolute and
3rd Edition. Reprint 2002. relative errors, Accuracy, Precision, Resolution and Significant figures. (Text
2. “Networks and systems”, Roy Choudhury, 2nd edition, 2006 re-print, 2: 2.1 to 2.3)
New Age International Publications. (b) Voltmeters and Multimeters Introduction, Multirange voltmeter,
Extending voltmeter ranges, Loading, AC voltmeter using Rectifiers – Half
REFERENCE BOOKS: wave and full wave, Peak responding and True RMS voltmeters. (Text 1:
1. , “Engineering Circuit Analysis”, Hayt, Kemmerly and DurbinTMH 6th 4.1, 4.4 to 4.6, 4.12 to 4.14, 4.17, 4.18)
Edition, 2002 07 Hours
2. “Network analysis and Synthesis”, Franklin F. Kuo, Wiley UNIT – 2:
International Edition, Digital Instruments
3. “Analysis of Linear Systems”, David K. Cheng, Narosa Publishing Digital Voltmeters – Introduction, DVM’s based on V – T, V – F and
House, 11th reprint, 2002 Successive approximation principles, Resolution and sensitivity, General
4. “Circuits”, Bruce Carlson, Thomson Learning, 2000. Reprint 2002 specifications, Digital Multi-meters, Digital frequency meters, Digital
measurement of time(Text 1: 5.1 to 5.6; 5.9 and 5.10; 6.1 to 6.4)
07 Hours

11 12
UNIT – 3:
Oscilloscopes
Introduction, Basic principles, CRT features, Block diagram and working of
each block, Typical CRT connections, Dual beam and dual trace CROs,
Electronic switch(Text 1: 7.1 to 7.9, 7.12, 7.14 to 7.16)
06 Hours
UNIT – 4:
Special Oscilloscopes
Delayed time-base oscilloscopes, Analog storage, Sampling and Digital
storage oscilloscopes(Text 2: 10.1 to 10.4 )
06 Hours
PART – B
UNIT – 5:
Signal Generators
Introduction, Fixed and variable AF oscillator, Standard signal generator,
Laboratory type signal generator, AF sine and Square wave generator,
Function generator, Square and Pulse generator, Sweep frequency generator,
Frequency synthesizer(Text 1: 8.1 to 8.9 and Text 2: 11.5, 11.6 )
06 Hours
UNIT – 6:
Measurement of resistance, inductance and capacitance
Whetstone’s bridge, Kelvin Bridge; AC bridges, Capacitance Comparison
Bridge, Maxwell’s bridge, Wein’s bridge, Wagner’s earth connection (Text
1: 11.1 to 11.3, 11.8, 11.9, 11.11, 11.14 and 11.15 )
07 Hours
UNIT – 7:
Transducers - I
Introduction, Electrical transducers, Selecting a transducer, Resistive
transducer, Resistive position transducer, Strain gauges, Resistance
thermometer, Thermistor, Inductive transducer, Differential output
transducers and LVDT, (Text 1: 13.1 to 13.11 )
07 Hours
13
UNIT – 8:
Miscellaneous Topics
(a) Transducers - II –Piezoelectric transducer, Photoelectric transducer,
Photovoltaic transducer, Semiconductor photo devices, Temperature
transducers-RTD, Thermocouple (Text 1: 13.15 to 13.20)
(b) Display devices: Digital display system, classification of display, Display
devices, LEDs, LCD displays(Text 1: 2.7 to 2.11)
(c) Bolometer and RF power measurement using Bolometer (Text 1: 20.1 to
20.9)
(d) Introduction to Signal conditioning(Text 1: 14.1 )
06 Hours
TEXT BOOKS:
1. “Electronic Instrumentation”, H. S. Kalsi, TMH, 2004
2. “Electronic Instrumentation and Measurements”, David A Bell, PHI
/ Pearson Education, 2006.
REFERENCE BOOKS:
1. “Principles of measurement systems”, John P. Beately, 3rd Edition,
Pearson Education, 2000
2. “Modern electronic instrumentation and measuring techniques”,
Cooper D & A D Helfrick, PHI, 1998.
3. “Electronic and Electrical measurements and Instrumentation”,
J. B. Gupta, S. K. Kataria & Sons, Delhi
4. Electronics & electrical measurements, A K Sawhney, , Dhanpat Rai
& sons, 9th edition.
Question Paper Pattern: Student should answer FIVE full questions out of
8 questions to be set each carrying 20 marks, selecting at least TWO
questions from each part
Coverage in the Texts:
UNIT – 1: (a) Text 2: 2.1 to 2.3; (b) Text 1: 4.1, 4.4 to 4.6, 4.12 to 4.14,
4.17, 4.18
UNIT – 2: Text 1:5.1 to 5.6; 5.9 and 5.10; 6.1 to 6.4
UNIT – 3: Text 1: 7.1 to 7.9, 7.12, 7.14 to 7.16
UNIT – 4: Text 2: 10.1 to 10.5
UNIT – 5: Text 1: 8.1 to 8.9 and Text 2: 11.5, 11.6
UNIT – 6: Text 1: 11.1 to 11.3, 11.8, 11.9, 11.11, 11.14 and 11.15
UNIT – 7: Text 1: 13.1 to 13.11
UNIT – 8: (a) Text 1: 13.15 to 13.20.2 (b) Text 1: 2.7 to 2.12 (c) Text 1:
20.1 to 20.9, (d) Text 1: 14.1
14
 Stokes’ theorem, magnetic flux and flux density, scalar and Vector magnetic
potentials
(Chapter 8 – 8.1, 8.2, 8.3, 8.4, 8.5, 8.6)
FIELD THEORY 06 Hours
(Common to EC/TC/ML/EE)
PART – B
Sub Code : 06ES36 IA Marks : 25 UNIT 5:
Hrs/ Week : 04 Exam Hours : 03 a. Magnetic forces: Force on a moving charge and differential current
Total Hrs. : 52 Exam Marks : 100 element, Force between differential current elements, Force and torque on a
closed circuit. (Chapter 9 – 9.1, 9.2, 9.3, 9.4)
03 Hours
PART – A b. Magnetic materials and inductance: Magnetization and permeability,
UNIT 1: Magnetic boundary conditions, Magnetic circuit, Potential energy and forces
a. Coulomb’s Law and electric field intensity: Experimental law of on magnetic materials, Inductance and Mutual Inductance.( Chapter 9 – 9.6,
Coulomb, Electric field intensity, Field due to continuous volume charge 9.7, 9.8, 9.9, 9.10)
distribution, Field of a line charge (Chapter 2 – 2.1, 2.2, 2.3 2.4) 04 Hours
03 Hours UNIT 6:
b. Electric flux density, Gauss’ law and divergence: Electric flux density, Time varying fields and Maxwell’s equations: Faraday’s law,
Gauss’ law, Divergence, Maxwell’s First equation(Electrostatics), vector displacement current, Maxwell’s equation in point and Integral form,
operator ∇ and divergence theorem(Chapter 3 – 3.1, 3.2, 3.5, 3.6, 3.7) retarded potentials(Chapter 10)
04 Hours 06 Hours
UNIT 2: UNIT 7:
a. Energy and potential : Energy expended in moving a point charge in an Uniform plane wave: Wave propagation in free space and dielectrics,
electric field, The line integral, Definition of potential difference and Poynting’s theorem and wave power, propagation in good conductors – (skin
Potential, The potential field of a point charge and system of charges, effect).( Chapter 12 – 12.1 to 12.4)
Potential gradient , Energy density in an electrostatic field (Chapter 4 – 4.1, 07 Hours
4.2, 4.3, 4.4, 4.5 4.6, 4.8 ) UNIT 8:
04 Hours Plane waves at boundaries and in dispersive media: Reflection of uniform
b. Conductors, dielectrics and capacitance: Current and current density, plane waves at normal incidence, SWR, Plane wave propagation in general
Continuity of current, metallic conductors, Conductor properties and directions.
boundary conditions, boundary conditions for perfect Dielectrics, capacitance ( Chapter 13 – 13.1, 13.2, 13.4)
and examples. (Chapter 5 - 5.1, 5.2, 5.3, 5.4; Chapter 6 – 6.2, 6.3, 6.4) 06 Hours
03 Hours TEXT BOOK:
UNIT 3: “Engineering Electromagnetics”, William H Hayt Jr. and John A Buck,
Poisson’s and Laplace’s equations: Derivations of Poisson’s and Laplace’s Tata McGraw-Hill, 7th edition, 2006
Equations, Uniqueness theorem, Examples of the solutions of Laplace’s and REFERENCE BOOKS:
Poisson’s equations (Chapter 7 – 7.1, 7.2, 7.3, 7.4) 1. “Electromagnetics with Applications”, John Krauss and Daniel A
06 Hours Fleisch, McGraw-Hill, 5th edition, 1999
UNIT 4:
The steady magnetic field: Biot-Savart law, Ampere’s circuital law, Curl,
15 16
2. “Electromagnetic Waves And Radiating Systems,” Edward C. Jordan
and Keith G Balmain, Prentice – Hall of India / Pearson Education, 2nd
edition, 1968.Reprint 2002
3. “Field and Wave Electromagnetics”, David K Cheng, Pearson
Education Asia, 2nd edition, - 1989, Indian Reprint – 2001.
Question Paper Pattern: Student should answer FIVE full questions out of
8 questions to be set each carrying 20 marks, selecting at least TWO
questions from each part
Coverage in the Text book:
UNIT 1: (a) Chapter 2 (b) Chapter 3
UNIT 2: (a) Chapter 4 except section 4.7
(b) Chapter 5 (except sections 5.5 and 5.6); 6.2, 6.3, 6.4
UNIT 3: Chapter 7 except sections 7.5 and 7.6
UNIT 4: Chapter 8 except section 8.7
UNIT 5: Chapter 9 except Section 9.5
UNIT 6: Chapter 10
UNIT 7: Chapter 12
UNIT 8: Chapter 13 – 13.1, 13.2, 13.4, 13.7
5. Testing for the performance of BJT – Hartley & Colpitts Oscillators for
RF range f0 ≥100KHz.
6. Testing for the performance of BJT -Crystal Oscillator for f0 > 100 KHz
7 Testing of Diode clipping (Single/Double ended) circuits for peak clipping,
peak detection
8. Testing of Clamping circuits: positive clamping /negative clamping.
9. Testing of a transformer less Class – B push pull power amplifier and
determination of its conversion efficiency.
10. Testing of Half wave, Full wave and Bridge Rectifier circuits with and
without Capacitor filter. Determination of ripple factor, regulation and
efficiency
11. Verification of Thevinin’s Theorem and Maximum Power Transfer
theorem for DC Circuits.

12. Characteristics of Series and Parallel resonant circuits.

ANALOG ELECTRONICS LAB
(Common to EC/TC/EE/IT/BM/ML) LOGIC DESIGN LAB
(Common to EC/TC/EE/IT/BM/ML)
Sub Code : 06ESL37 IA Marks : 25
Hrs/ Week : 03 Exam Hours : 03 Sub Code : 06ESL38 IA Marks : 25
Total Hrs. : Exam Marks : 50 Hrs/ Week : 03 Exam Hours : 03
Total Hrs. : Exam Marks : 50
1. Wiring of RC coupled Single stage FET & BJT amplifier and
determination of the gain-frequency response, input and output impedances. 1. Simplification, realization of Boolean expressions using logic
gates/Universal gates.
2. Wiring of BJT Darlington Emitter follower with and without bootstrapping 2. Realization of Half/Full adder and Half/Full Subtractors using logic
and determination of the gain, input and output impedances (Single circuit) gates.
(One Experiment) 3. (i) Realization of parallel adder/Subtractors using 7483 chip
(ii) BCD to Excess-3 code conversion and vice versa.
3. Wiring of a two stage BJT Voltage series feed back amplifier and 4. Realization of Binary to Gray code conversion and vice versa
determination of the gain, Frequency response, input and output impedances 5. MUX/DEMUX – use of 74153, 74139 for arithmetic circuits and code
with and without feedback (One Experiment) converter.
6. Realization of One/Two bit comparator and study of 7485 magnitude
4. Wiring and Testing for the performance of BJT-RC Phase shift Oscillator comparator.
for f0 ≤ 10 KHz 7. Use of a) Decoder chip to drive LED display and b) Priority encoder.
17 18
8. Truth table verification of Flip-Flops: (i) JK Master slave (ii) T type and 6 Hours
(iii) D type. UNIT 4:
9. Realization of 3 bit counters as a sequential circuit and MOD – N Series solution of Ordinary Differential Equations and Special Functions
counter design (7476, 7490, 74192, 74193). Series solution – Frobenius method, Series solution of Bessel’s D.E. leading
10. Shift left; Shift right, SIPO, SISO, PISO, PIPO operations using 74S95. to Bessel function of fist kind. Equations reducible to Bessel’s D.E., Series
11. Wiring and testing Ring counter/Johnson counter. solution of Legendre’s D.E. leading to Legendre Polynomials. Rodirgue’s
12. Wiring and testing of Sequence generator. formula.
7 Hours

ENGINEERING MATHEMATICS - IV
PART – B
Sub Code : 06MAT41 IA Marks : 25
Hrs/ Week : 04 Exam Hours : 03 UNIT 5:
Total Hrs. : 52 Exam Marks : 100 Statistical Methods
Curve fitting by the method of least squares: y = a + bx, y = a + bx + cx2,
PART – A y = axb y = abx, y = aebx, Correlation and Regression.

UNIT 1: Probability: Addition rule, Conditional probability, Multiplication rule,

Numerical Methods Baye’s theorem.
Numerical solutions of first order and first degree ordinary differential 6 Hours
equations – Taylor’s series method, Modified Euler’s method, Runge – Kutta
method of fourth order, Milne’s and Adams-Bashforth predictor and UNIT 6:
corrector methods (All formulae without Proof). Random Variables (Discrete and Continuous) p.d.f., c.d.f. Binomial, Poisson,
Normal and Exponential distributions.
6 Hours 7 Hours
UNIT 2:
Complex Variables UNIT 7:
Function of a complex variable, Limit, Continuity Differentiability – Sampling, Sampling distribution, Standard error. Testing of hypothesis for
Definitions. Analytic functions, Cauchy – Riemann equations in cartesian means. Confidence limits for means, Student’s t distribution, Chi-square
and polar forms, Properties of analytic functions. Conformal Transformation distribution as a test of goodness of fit.
– Definition. Discussion of transformations: W = z2, W = ez, W = z + (I/z), 7 Hours
z ≠ 0 Bilinear transformations.
7 Hours UNIT 8:
Concept of joint probability – Joint probability distribution, Discrete and
UNIT 3: Independent random variables. Expectation, Covariance, Correlation
Complex Integration coefficient.
Complex line integrals, Cauchy’s theorem, Cauchy’s integral formula.
Taylor’s and Laurent’s series (Statements only) Singularities, Poles, Probability vectors, Stochastic matrices, Fixed points, Regular stochastic
Residues, Cauchy’s residue theorem (statement only). matrices. Markov chains, Higher transition probabilities. Stationary
distribution of regular Markov chains and absorbing states.
19 20
 6 Hours
Note:

Text Book: Higher Engineering Mathematics by Dr. B.S. Grewal (36th 1. One question is to be set from each unit.
Edition – Khanna Publishers) 2. To answer Five questions choosing atleast Two questions from each part.

Unit Chapter Article Numbers Page Nos.

No. No. MICROCONTROLLERS
27 27.1, 27.3, 27.5, 27.7, 27.8 914, 916 – 922 (Common to EC/TC/EE/IT/BM/ML)
924, 933
Sub Code : 06ES42 IA Marks : 25
20 20.1 to 20.10 630 – 650 Hrs/ Week : 04 Exam Hours : 03
Total Hrs. : 52 Exam Marks : 100
20 20.12 to 20.14, 20.16 to 20.19 652 – 658
661 – 671
PART – A
16 16.1 to 16.6, 16.10, 16.13, 16.14 507 – 514,
521 – 523 UNIT 1:
526 – 529 Microprocessors and microcontroller. Introduction, Microprocessors and
Microcontrollers, A Microprocessors survey. RISC & CISC CPU
1 1.12 to 1.14 20 – 25 Architectures, Harvard & Von-Neumann CPU architecture.
The 8051 Architecture: Introduction, 8051 Microcontroller Hardware, Input /
23 23.9, 23.10, 23.11, 23.14, 23.16 755 – 762, 765 Output Pins, Ports and Circuits External Memory, Counter and Timers,
to 23.18 768 – 776 Serial Data Input / Output, Interrupts.
7 Hours
23 23.19 to 23.22, 23.26 to 23.30 776 – 780
783 – 798 UNIT 2:
Addressing Modes and Operations: Introduction, Addressing modes, External
23 23.31 to 23.37 791 – 816 data Moves, Code Memory, Read Only Data Moves / Indexed Addressing
mode, PUSH and POP Opcodes, Data exchanges, Example Programs; Byte
level logical Operations, Bit level Logical Operations, Rotate and Swap
Unit – VIII: Text book: Probability by Seymour Lipschutz (Schaum’s Operations, Example Programs. Arithmetic Operations: Flags, Incrementing
series) Chapters 5 & 7 and Decrementing, Addition, Subtraction, Multiplication and Division,
Decimal Arithmetic, Example Programs.
Reference Books: 7 Hours
1. Higher Engineering Mathematics by B.V. Ramana (Tata-Macgraw
Hill). UNIT 3:
2. Advanced Modern Engineering Mathematics by Glyn James – Jump and Call Instructions: The JUMP and CALL Program range, Jumps,
Pearson Education. calls and Subroutines, Interrupts and Returns, More Detail on Interrupts,
Example Problems
21 22
 6 Hours

UNIT 4: REFERENCE BOOKS:

8051 programming in C: Data types and time delays in 8051C, I/O 1. “Programming and Customizing the 8051 Microcontroller” Predko ;–,
programming, logic operations, data conversion programs, accessing code TMH
ROM space, data serialization. 2. Microcontrollers: Architecture, Programming, Interfacing and
6 Hours System Design”,Raj Kamal, “Pearson Education, 2005
3. “Microcontrollers- Theory and Applications”, Ajay V.Deshmukh;
PART – B TMH,2005
UNIT 5: 4. “Microcontroller and its applications”, Dr.Ramani Kalpathi and Ganesh
Timer / Counter Programming in 8051: Programming 8051 Timers, Counter Raja; Sanguine Technical publishers,Bangalore-2005
Programming, programming timers 0 and 1 in 8051 C
6 Hours Question Paper Pattern: Student should answer FIVE full questions out of
8 questions to be set each carrying 20 marks, selecting at least TWO
UNIT 6: questions from each part.
8051 Serial Communication: Basics of Serial Communication, 8051
connections to RS-232, 8051 Serial communication Programming, Coverage in the Text books:
Programming the second serial port, Serial port programming in C. UNIT 1:Text 1 – Chapter 1( excluding 1.2 and 1.4) and chapter 3, R1 -
7 Hours chapter 1
UNIT 2:Text 1-chapters 5, 6 & 7
UNIT 7: UNIT 3: Text 1 - chapter 8
Interrupts Programming: 8051 Interrupts, Programming Timer Interrupts, UNIT 4:Text 2 – chapter 7
Programming External Hardware Interrupts, Programming the Serial UNIT 5: Text 2 – chapter 9
Communication Interrupts, Interrupt Priority in the 8051/52, Interrupt UNIT 6: Text 2 – chapter 10
programming in C UNIT 7: Text 2 – chapter 11
6 Hours UNIT 8: Text 2 – chapter 12, chapter 13(13.1&13.2), chapter 17 ( except
17.1 )
UNIT 8:
8051 Interfacing and Applications: Interfacing 8051 to LCD, Keyboard, CONTROL SYSTEMS
parallel and serial ADC, DAC, Stepper motor interfacing, DC motor (Common to EC/TC/EE/IT/BM/ML)
interfacing and PWM
7 Hours Sub Code : 06ES43 IA Marks : 25
Hrs/ Week : 04 Exam Hours : 03
TEXT BOOKS: Total Hrs. : 52 Exam Marks : 100
1. “The 8051 Microcontroller Architecture, Programming &
Applications”, 2e Kenneth J. Ayala ;, Penram International, 1996 /
Thomson Learning 2005 PART – A
2. “The 8051 Microcontroller and Embedded Systems – using assembly
and C ”-, Muhammad Ali Mazidi and Janice Gillespie Mazidi and UNIT 1:
Rollin D. McKinlay; PHI, 2006 / Pearson, 2006 Modeling of Systems: The control system, Mathematical models of physical
23 24
systems – Introduction, Differential equations of physical systems – 7 Hours
Mechanical systems, Friction, Translational systems (Mechanical
accelerometer, Levered systems excluded), Rotational systems, Gear trains, UNIT 8:
Electrical systems, Analogous systems Introduction to State variable analysis: Concepts of state, state variable
6 Hours and state models for electrical systems, Solution of state equations.
UNIT 2: 6 Hours
Block diagrams and signal flow graphs: Transfer functions, Block diagram
algebra, Signal Flow graphs (State variable formulation excluded), TEXT BOOK :
7 Hours 1. J. Nagarath and M.Gopal, “Control Systems Engineering”, New Age
UNIT 3: International (P) Limited, Publishers, Fourth edition – 2005
Time Response of feed back control systems: Standard test signals, Unit
step response of First and second order systems, Time response
specifications, Time response specifications of second order systems, steady REFERENCE BOOKS:
– state errors and error constants.
7 Hours 1. “Modern Control Engineering “, K. Ogata, Pearson Education Asia/
PHI, 4th Edition, 2002.
UNIT 4: 2. “Concepts of Control Systems”, P. S. Satyanarayana; Dynaram
Stability analysis: Concepts of stability, Necessary conditions for Stability, publishers, Bangalore, 2001
Routh- stability criterion, Relative stability analysis; More on the Routh 3. “Control Systems – Principles and Design”, M. Gopal, TMH, 1999
stability criterion 4. “Feedback control system analysis and synthesis”, J. J. D’Azzo and
6 Hours C. H. Houpis; McGraw Hill, International student Edition.

PART – B Question Paper Pattern: Student should answer FIVE full questions out of
UNIT 5: 8 questions to be set each carrying 20 marks, selecting at least TWO
Root–Locus Techniques: Introduction, The root locus concepts, questions from each part
Construction of root loci.
6 Hours COVERAGE IN THE TEXT BOOK:
UNIT 1: 1.1, 2.1, 2.2, 2.7
UNIT 6: UNIT 2: 2.4, 2.5, 2.6, 2.7
Stability in the frequency domain: Mathematical preliminaries, Nyquist UNIT 3: 5.1, 5.2, 5.3, 5.4, 5.5
Stability criterion, (Inverse polar plots excluded), Assessment of relative UNIT 4: 6.1, 6.2, 6.4, 6.5, 6.6
stability using Nyquist criterion, (Systems with transportation lag excluded). UNIT 5: 7.1, 7.2, 7.3
UNIT 6: 9.1, 9.2, 9.3, 9.4,
7 Hours UNIT 7: 8.1, 8.2, 8.4, 8.5, 8.6
UNIT 8: 12.1, 12.2, 12.3, 12.6
UNIT 7:
Frequency domain analysis: Introduction, Correlation between time and
frequency response, Bode plots, All pass and minimum phase systems,
Experimental determination of transfer functions, Assessment of relative
stability using Bode Plots.
25 26
 SIGNALS & SYSTEMS UNIT 6:
(Common to EC/TC/IT/BM/ML) Applications of Fourier representations: Introduction, Frequency response
of LTI systems, Fourier transform representation of periodic signals, Fourier
Sub Code : 06EC44 IA Marks : 25 transform representation of discrete time signals
Hrs/ Week : 04 Exam Hours : 03 7 Hours
Total Hrs. : 52 Exam Marks : 100 UNIT 7:
Z-Transforms – 1: Introduction, Z – transform, properties of ROC,
PART – A properties of Z – transforms, inversion of Z – transforms.
UNIT 1: 07 Hours
Introduction: Definitions of a signal and a system, classification of signals, UNIT 8:
basic Operations on signals, elementary signals, Systems viewed as Z-transforms – 2: Transform analysis of LTI Systems, unilateral Z-
Interconnections of operations, properties of systems. Transform and its application to solve difference equations.
7 Hours 06 Hours
TEXT BOOK
UNIT 2: Simon Haykin and Barry Van Veen “Signals and Systems”, John Wiley &
Time-domain representations for LTI systems – 1: Convolution, impulse Sons, 2001.Reprint 2002
response representation, Convolution Sum and Convolution Integral.
6 Hours REFERENCE BOOKS:
1. Alan V Oppenheim, Alan S, Willsky and A Hamid Nawab, “Signals
UNIT 3: and Systems” Pearson Education Asia / PHI, 2nd edition, 1997. Indian
Time-domain representations for LTI systems – 2: properties of impulse Reprint 2002
response representation, Differential and difference equation Representations, 2. H. P Hsu, R. Ranjan, “Signals and Systems”, Scham’s outlines, TMH,
Block diagram representations. 2006
7 Hours 3. B. P. Lathi, “Linear Systems and Signals”, Oxford University Press,
2005
UNIT 4: 4. Ganesh Rao and Satish Tunga, “Signals and Systems”, Sanguine
Fourier representation for signals – 1: Introduction, Discrete time and Technical Publishers, 2004
continuous time Fourier series (derivation of series excluded) and their Question Paper Pattern: Student should answer FIVE full questions out of
properties . 8 questions to be set each carrying 20 marks, selecting at least TWO
6 Hours questions from each part
Coverage in the Text:
PART – B UNIT 1: 1.1, 1.2, 1.4 to 1.8
UNIT 2: 2.1, 2.2
UNIT 5: UNIT 3: 2.3, 2.4, 2.5
Fourier representation for signals – 2: Discrete and continuous Fourier UNIT 4: 3.1, 3.2, 3.3, 3.6
transforms(derivations of transforms are excluded) and their properties. UNIT 5: 3.4, 3.5, 3.6
UNIT 6: 4.1, 4.2, 4.3, 4.5, 4.6.
6 Hours UNIT 7: 7.1, 7.2, 7.3, 7.4, 7.5

27 28
UNIT 8: 7.6 (Excluding ‘relating the transfer function and the State-Variable
description, determining the frequency response from poles and zeros) and PART-B
7.8
UNIT 5: Procedures, Tasks, and Functions: Highlights of Procedures,
FUNDAMENTALS OF HDL tasks, and Functions, Procedures and tasks, Functions.
(Common to EC/TC/IT/BM/ML) Advanced HDL Descriptions: File Processing, Examples of File Processing

Sub Code : 06EC45 IA Marks : 25 7 Hours

Hrs/ Week : 04 Exam Hours : 03
Total Hrs. : 52 Exam Marks : 100 UNIT 6:
Mixed –Type Descriptions: Why Mixed-Type Description? VHDL User-
Defined Types, VHDL Packages, Mixed-Type Description examples
6 Hours
PART-A
UNIT 1: UNIT 7:
Introduction: Why HDL? , A Brief History of HDL, Structure of HDL Mixed –Language Descriptions: Highlights of Mixed-Language
Module, Operators, Data types, Types of Descriptions, simulation and Description, How to invoke One language from the Other, Mixed-language
synthesis, Brief comparison of VHDL and Verilog Description Examples, Limitations of Mixed-Language Description
6 Hours
7 Hours
UNIT 2: UNIT 8:
Data –Flow Descriptions: Highlights of Data-Flow Descriptions, Structure Synthesis Basics: Highlights of Synthesis, Synthesis information from Entity
of Data-Flow Description, Data Type – Vectors and Module, Mapping Process and Always in the Hardware Domain.
6 Hours
6 Hours
UNIT 3:
Behavioral Descriptions: Behavioral Description highlights, structure of TEXT BOOKS:
HDL behavioral Description, The VHDL variable –Assignment Statement, 1. HDL Programming (VHDL and Verilog)- Nazeih M.Botros-
sequential statements. Dreamtech Press
7 Hours 2. (Available through John Wiley – India and Thomson Learning) 2006
Edition
UNIT 4:
Structural Descriptions: Highlights of structural Description, Organization REFERENCE BOOKS:
of the structural Descriptions, Binding, state Machines, Generate, Generic, 1. Verilog HDL –Samir Palnitkar-Pearson Education
and Parameter statements. 2. VHDL -Douglas perry-Tata McGraw-Hill
7 Hours 3. A Verilog HDL Primer- J.Bhaskar – BS Publications
4. Circuit Design with VHDL-Volnei A.Pedroni-PHI

29 30
 LINEAR IC’s & APPLICATIONS
(Common to EC/TC/IT/BM/ML) PART – B
UNIT 5:
Sub Code : 06EC46 IA Marks : 25 More applications: Clamping circuits, Peak detectors, sample and hold
Hrs/ Week : 04 Exam Hours : 03 circuits, V to I and I to V converters, Log and antilog amplifiers, Multiplier
Total Hrs. : 52 Exam Marks : 100 and divider, Triangular / rectangular wave generators, Wave form generator
design, phase shift oscillator, Wein bridge oscillator. (Text 1: Chapter 7 –
PART - A 7.4, 7.5, 7.6; Chapters 10 -10.1, 10.2, 10.3, 10.5; Text 2: Sections 4.5, 4.8 and
UNIT 1: 4.9)
Operational Amplifier Fundamentals: Basic Op-Amp circuit, Op-Amp 6 Hours
parameters – Input and output voltage, CMRR and PSRR, offset voltages and
currents, Input and output impedances, Slew rate and Frequency limitations; UNIT 6:
Op-Amps as DC Amplifiers- Biasing Op-Amps, Direct coupled -Voltage Non-linear circuit applications: crossing detectors, inverting Schmitt
Followers, Non-inverting Amplifiers, Inverting amplifiers, Summing trigger circuits, Monostable & Astable multivibrator, Active Filters –First
amplifiers, Difference amplifier. (Text 1: Chapter 1 – 1.2, Chapter 2 – 2.1, and second order Low pass & High pass filters. (Text 1: Chapter 9 – 9.2, 9.3,
2.2, 2.3, 2.4, 2.5, and Chapter 3 – 3.1, 3.2, 3.3, 3.4, 3.5, 3.6) 9.5, 9.6; Chapter 11 – 11.2, 11.3, 11.4, 11.5)
7 Hours 7 Hours
UNIT 7:
UNIT 2: Voltage Regulators: Introduction, Series Op-Amp regulator, IC Voltage
Op-Amps as AC Amplifiers: Capacitor coupled Voltage Follower, High regulators, 723 general purpose regulator, Switching regulator. (Text 2:
input impedance - Capacitor coupled Voltage Follower, Capacitor coupled Chapter 6)
Non-inverting Amplifiers, High input impedance - Capacitor coupled Non- 6 Hours
inverting Amplifiers, Capacitor coupled Inverting amplifiers, setting the UNIT 8:
upper cut-off frequency, Capacitor coupled Difference amplifier, Use of a Other Linear IC applications: 555 timer - Basic timer circuit, 555 timer
single polarity power supply. (Text 1: Chapter 4) used as astable and monostable multivibrator, Schmitt trigger; PLL-
6 Hours operating principles, Phase detector / comparator, VCO; D/A and A/ D
UNIT 3: converters – Basic DAC Techniques, AD converters(Text 2: Chapter 8 –
Op-Amps frequency response and compensation: Circuit stability, 8.1, 8.2, 8.3, 8.4, 8.5; Chapter 9 – 9.1, 9.2, 9.3, 9.4; Chapter 10 – 10. 1,
Frequency and phase response, Frequency compensating methods, Band 10.2, 10.3 ; Except 8.3.1, 8.4.1, 10.2.5, 10.4)
width, Slew rate effects, Zin Mod compensation, and circuit stability 7 Hours
precautions. (Text 1: Chapter 5 – 5.1, 5.2, 5.3, 5.5, 5.6, 5.9, 5.10)
6 Hours TEXT BOOKS:
UNIT 4: 1. “Operational Amplifiers and Linear IC’s”, David A. Bell, 2nd edition,
OP-AMP Applications: Voltage sources, current sources and current sinks, PHI/Pearson, 2004
Current amplifiers, instrumentation amplifier, precision rectifiers, Limiting 2. “Linear Integrated Circuits”, D. Roy Choudhury and Shail B. Jain, 2nd
circuits, (Text 1: Chapter 6 – 6.1, 6.2, 6.4, 6.8, and Chapter 7 – 7.1, 7.2, 7.3) edition, Reprint 2006, New Age International
7 Hours

31 32
REFERENCE BOOKS: MICROCONTROLLERS LAB
1. “Op - Amps and Linear Integrated Circuits”, Ramakant A. (Common to EC/TC/EE/IT/BM/ML)
Gayakwad, 4th edition, PHI,
2. “Operational Amplifiers and Linear Integrated Circuits”, Robert. F. Sub Code : 06ESL47 IA Marks : 25
Coughlin & Fred.F. Driscoll, PHI/Pearson, 2006 Hrs/ Week : 03 Exam Hours : 03
3. “Op - Amps and Linear Integrated Circuits”, James M. Fiore, Total Hrs. : 42 Exam Marks : 50
Thomson Learning, 2001
4. “Design with Operational Amplifiers and Analog Integrated
Circuits”, Sergio Franco, TMH, 3e, 2005 I. PROGRAMMING
Question Paper Pattern: Student should answer FIVE full questions out of
8 questions to be set each carrying 20 marks, selecting at least TWO 1. Data Transfer - Block move, Exchange, Sorting, Finding largest element in
questions from each part an array.
2. Arithmetic Instructions - Addition/subtraction, multiplication and division,
Coverage in the Text books: square, Cube – (16 bits Arithmetic operations – bit addressable).
UNIT 1: (Text 1: Chapter 1 – 1.2, Chapter 2 – 2.1, 2.2, 2.3, 2.4, 2.5, and 3. Counters.
Chapter 3 – 3.1, 3.2, 3.3, 3.4, 3.5, 3.6) 4. Boolean & Logical Instructions (Bit manipulations).
UNIT 2: Text 1: Chapter 4 5. Conditional CALL & RETURN.
UNIT 3: Text 1: (Text 1: Chapter 5 – 5.1, 5.2, 5.3, 5.5, 5.6, 5.9, 5.10) 6. Code conversion: BCD – ASCII; ASCII – Decimal; Decimal - ASCII;
UNIT 4: (Text 1: Chapter 6 – 6.1, 6.2, 6.4, 6.8, and Chapter 7 – 7.1, 7.2, 7.3) HEX - Decimal and Decimal - HEX .
UNIT 5: (Text 1: Chapter 7 – 7.4, 7.5, 7.6; Chapters 10 -10.1, 10.2, 10.3, 7. Programs to generate delay, Programs using serial port and on-Chip timer /
10.5; Text 2: Sections 4.5, 4.8 and 4.9) counter.
UNIT 6: Text 1: Chapter 9 – 9.2, 9.3, 9.5, 9.6; Chapter 11 – 11.2, 11.3, 11.4,
II. INTERFACING:
11.5
UNIT 7: Text 2: Chapter 6
UNIT 8: Text 2: Chapter 8 – 8.1, 8.2, 8.3, 8.4, 8.5; Chapter 9 – 9.1, 9.2, 9.3, Write C programs to interface 8051 chip to Interfacing modules to develop
9.4; Chapter 10 – 10. 1, 10.2, 10.3; Except 8.3.1, 8.4.1, 10.2.5, single chip solutions.
10.4 8. Simple Calculator using 6 digit seven segment display and Hex Keyboard
interface to 8051.
9. Alphanumeric LCD panel and Hex keypad input interface to 8051.
10. External ADC and Temperature control interface to 8051.
11. Generate different waveforms Sine, Square, Triangular, Ramp etc. using
DAC interface to 8051; change the frequency and amplitude.
12. Stepper and DC motor control interface to 8051.
13.. Elevator interface to 8051.

33 34
 HDL LAB
(Common to EC/TC/IT/BM/ML) • ALU should use combinational logic to calculate an output based on the
four bit op-code input.
Sub Code : 06ECL48 IA Marks : 25 • ALU should pass the result to the out bus when enable line in high, and
Hrs/ Week : 03 Exam Hours : 03 tri-state the out bus when the enable line is low.
Total Hrs. : 42 Exam Marks : 50 • ALU should decode the 4 bit op-code according to the given in example
below.

Note: Programming can be done using any compiler. Download the OPCODE ALU OPERATION
programs on a FPGA/CPLD boards such as 1. A+B
Apex/Acex/Max/Spartan/Sinfi/TK Base or equivalent and performance 2. A–B
testing may be done using 32 channel pattern generator and logic analyzer 3. A Complement
apart from verification by simulation with tools such as Altera/Modelsim or 4. A*B
equivalent.
5. A AND B
6. A OR B
PROGRAMMING (using VHDL and Verilog)
7. A NAND B
8. A XOR B
1. Write HDL code to realize all the logic gates
2. Write a HDL program for the following combinational designs
a. 2 to 4 decoder 5. Develop the HDL code for the following flip-flops, SR, D, JK, T.
b. 8 to 3 (encoder without priority & with priority) 6. Design 4 bit binary, BCD counters (Synchronous reset and
c. 8 to 1 multiplexer Asynchronous reset) and “any sequence” counters
d. 4 bit binary to gray converter
e. Multiplexer, de-multiplexer, comparator.
3. Write a HDL code to describe the functions of a Full Adder Using three
modeling styles.

4. Write a model for 32 bit ALU using the schematic diagram shown below INTERFACING (at least four of the following must be covered using
A (31:0) B (31:0) VHDL/Verilog)

1. Write HDL code to display messages on the given seven segment display
and LCD and accepting Hex key pad input data.
Opcode (3:0)
2. Write HDL code to control speed, direction of DC and Stepper motor.

3. Write HDL code to accept 8 channel Analog signal, Temperature sensors

Enable and display the data on LCD panel or Seven segment display.
Out

35 36
4. Write HDL code to generate different waveforms (Sine, Square,
Triangle, Ramp etc.,) using DAC change the frequency and amplitude.

5. Write HDL code to simulate Elevator operations

6. Write HDL code to control external lights using relays.

***********

37