1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

6V:1 6V_CLK:1 6V:1 6V_TX:1 6V:1 6V_RX:1

Q
Vunreg:1 6V:1 Q
3_3V:1 L107 L119 L120
D101

4.7uF CER X5R 25V

L122
3_3V:1 3_3V:1
AVDD_TX:1 AVDD_RX:1

1
C1173 0.1uF
L103 L102

1
PMEG4005ET
0.47uF C1203
47uF
Vunreg:1 C540 C1183 C1186

2
C1169
C1003 C1119 C541 C1181 C1182 C1184 C1185

1
47uF 47uF 47uF

2
0.1uF 1uF 0.1uF 1uF 0.1uF 1uF

D102
1 4 P
P U14 20 B360
C1011 C1012 C1009 C1010 C1013 C1006 C1007 C1004 C1005 C1008

2
6.5uH

L101A
BST1 0.1uF 220pF 0.1uF 220pF 47uF 0.1uF 220pF 0.1uF 220pF 47uF
4.7uF CER X5R 25V C1001 1 2 L101 8uH
Vin1 SW1

pg1 5 PG1 IND1 3 2 3

18 4 AGND_TX:1 AGND_RX:1
Vc1 Vout1
LT3510−A

C1147 10pF
16 RT/SYNC FB1 17 24.9K

Front Panel Power ALT Power

sync1
O
O R101
15 SHDN SS/Track1 19

C1148

470pF
3_3V:1 3_3V:1
GND_EP DVDD_RX:1 DVDD_TX:1 Vunreg:1 J102

C1149 0.1uF
F101 F102
21 C1150 L109 L108 J101
SMD−XXX L118 L121 SMD−XXX
R103 1 1
40.2K NONE
8.06K

C1002
R102 R104 0.47uF

100uF 30V
2

1
2
22uF CER X5R 6.3V C1170 0.47uF

1
3 C1176
N
N
C1129 C1130 C1127 C1128 C1131 C1124 C1125 C1122 C1123 C1126

2
0.1uF 220pF 0.1uF 220pF 47uF 0.1uF 220pF 0.1uF 220pF 47uF

2
D103

PMEG4005ET
0.47uF
3_3V:1
1_2V:1 DVDD_FPGA:1
M
Vunreg:1 C1152 M
L106
FAN Power

D104
11 B360 1 4
U14
Vunreg:1

1
F103 J108

6.5uH

L113A
BST2
4.7uF CER X5R 25V C1151 10 9 L113 8uH 500mA
Vin2 SW2 12
1
6 8 2 3 C1114 C1115 C1112 C1113 C1116

2
pg2 PG2 IND2

C1179 0.1uF
0.1uF 220pF 0.1uF 220pF 47uF R130
2

4.7uF CER X5R 25V

13 Vc2 Vout2 7
LT3510−B L
L
C1153 10pF

C1175
FB2 14 4K
R105
SS/Track2 12
C1154

470pF

M1 M2 M3 M4 M5 M6 M7 M8 M9 M10
GND_EP
C1155 0.1uF

21 C1156 2_5V:1 2_5V:1

2_5V_FPGA:1 2_5V_ETH:1
R107 L112 L110
40.2K
8.06K
K
R106
22uF CER X5R 6.3V
Power Supplies K

1
6V Daughterboard Power (<1A)
C1144 C1145 C1142 C1143 C1146 C1134 C1135 C1132 C1133 C1136 3.3VAN LTC2284 (200mA), AD9777 (<500mA)

2
0.1uF 220pF 0.1uF 220pF 47uF 0.1uF 220pF 0.1uF 220pF 47uF

3.3VCLK AD9510 (<500mA), CLOCK (88mA)

2_5V:1
J D105 3.3VDIG All IO (<2A) J

PMEG4005ET
2.5V FPGA AUX (<100mA), Ethernet Core (<300mA), SERDES (<150mA)
0.47uF 2_5V:1 2_5V:1
2_5V_SER:1 2_5V_RAM:1
Vunreg:1 C1158
L111 L801 1.8V Ethernet Core (~500mA)
1.2V FPGA Core (<2A)
D106

B360 1 4
U15 20

1
I
6.5uH

L114A

I BST1
4.7uF CER X5R 25V C1157 1 2 L114 8uH
Vin1 SW1 DVDD_RX:1
C1139 C1140 C1137 C1138 C1141 C801 C802 C803 C804 C805 AVDD_RX:1

2
5 3 2 3 0.1uF 220pF 0.1uF 220pF 47uF 0.1uF 220pF 0.1uF 220pF 47uF
pg3 PG1 IND1

18 Vc1 Vout1 4 DVDD_TX:1 AVDD_TX:1

LT3510−A
C1159 10pF

16 RT/SYNC FB1 17 16.9K

49

32

63

18

10
R108 U2

7
sync2

10

18

26

36

43

51

61

63

65

76

78

80
15 SHDN SS/Track1 19 U3
C1160

470pF

LTC2284−PWR
1

3
H

DVdd

DVdd

AVdd

AVdd

AVdd

AVdd
AD9777−PWR

CLKGND CLKVDD

CLKGND CLKVDD

DVDD

DVDD

DVDD

DVDD

DVDD

DVDD

AVDD

AVDD

AVDD

AVDD

AVDD

AVDD
GND_EP
C1161 0.1uF

21 C1162
C1059C1058C1061C1060

GND_EP
DGND_EP
R110 C1064C1065 0.1uF 0.1uF 0.1uF 0.1uF

DGND

DGND
40.2K NONE

GND

GND
8.06K C1072C1073C1070C1071 C1068C1069C1066C1067 C1092C1093 C1090C1091C1088C1089 0.1uF 0.1uF

DGND

DGND

DGND

DGND

DGND

DGND

AGND

AGND

AGND

AGND

AGND

AGND

AGND

AGND

AGND

AGND
R109 R111
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
22uF CER X5R 6.3V

50

31

65

64

17
R138 R139

17

25

35

44

52

81

62

64

66

67

70

71

74

75

77

79
61.9K 61.9K
ps_osc_1 pg1 G
G

sync1
D107 AGND_TX:1
R136 R137 AGND_RX:1
61.9K 61.9K
ps_osc_2 pg3
PMEG4005ET 1_8V:1
0.47uF
sync2
Vunreg:1 C1164
F
D108

F
11 B360 1 4
U15
6.5uH

L115A

BST2
4.7uF CER X5R 25V C1163 10 9 L115 8uH
Vin2 SW2 3_3V:1 1_2V:1 2_5V_FPGA:1
U23
pg4 6 PG2 IND2 8 2 3
1 6 ps_osc_1
V+ OUT1
13 Vc2 Vout2 7 2 5 ps_osc_2
LT3510−B GND OUT2
R131 3 4 R132
C1165 10pF

FB2 14 10K SET MOD E

E
190K 0 3_3V:1
R112 Removed C1014−C1021 b/c they don’t fit
12 C1208 LTC6908S6−X R133
SS/Track2
C1166

470pF

0.1uF TSOT−23 C1054C1055 C1053C1050C1051C1024 C1022C1023

NONE 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
GND_EP R134
C1167 0.1uF

SSFM Modulation
21 C1168
OFF NONE
R114 1/64 R135
40.2K
8.06K
R113 1/32 NONE
22uF CER X5R 6.3V
1/16 C1209 D
D Removed C1025, C1052, C1056, C1057 b/c they don’t fit
1000pF

1_2V:1 2_5V_FPGA:1

3_3V:1 2_5V:1 1_8V:1 1_2V:1

U1

AB17
G16

G15

AB6
C

R16

H16

U22

A17
T16

T15

F22
G8

G7
R7

H7

U1

A6
T8

T7

F1
C
1

XC3SXX00FG456−PWR
VCCINT

VCCINT

VCCINT

VCCINT

VCCINT

VCCINT

VCCINT

VCCINT

VCCINT

VCCINT

VCCINT

VCCINT

VCCAUX

VCCAUX

VCCAUX

VCCAUX

VCCAUX

VCCAUX

VCCAUX

VCCAUX
C1204 C1205 C1206 C1207
2

47uF 47uF 47uF 47uF

B
B

3_3V:1 J104 2_5V:1 J105 1_8V:1 J106 1_2V:1 J107 6V:1 J103

1 1 1 1 1
GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND
2 2 2 2 2
AB22

AB1

AA21

AA2

Y14

Y9

P20

P14

P13

P12

P11

P10

P9

P3

N14

N13

N12

N11

N10

N9

M14

M13

M12

M11

M10

M9

L14

L13

L12

L11

L10

L9

K14

K13

K12

K11

K10

K9

J20

J14

J13

J12

J11

J10

J9

J3

C14

C9

B21

B2

A22

A1
USRP2 Power
A
A TITLE $Date$
FILE: power.sch REVISION: $Revision$
PAGE 1 OF 8 DRAWN BY: $Author$
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Q Q

U1
XC3SXX00FG456−IO7 U1
XC3SXX00FG456−IO1
P C1 C2 P
SEN_TX_DB IO_L16P_7/VREF_7 IO clk_sel1
ADC00_B A12 IO IO/VREF_1 E13
SCLK_TX_DB D3 IO_L19N_7/VREF_7 IO_L01N_7/VRP_7/DCI C3 clk_sel0
ADC01_B E16 IO IO/VREF_1/400NC F14
SDO_TX_DB G3 IO_L26N_7/400NC IO_L01P_7/VRN_7/DCI C4 clk_en0
ADC02_B F12 IO IO_L06N_1/VREF_1 A19
SDI_TX_DB G4 IO_L26P_7/400NC IO_L16N_7 D1 clk_en1
ADC03_B F13 IO IO_L10N_1/VREF_1 A18
SEN_TX_ADC G2 IO_L27P_7/VREF_7 IO_L17N_7 E4 io_tx_15
O ADC04_B F16 IO IO_L19N_1/400NC C16 O
SCLK_TX_ADC H1 IO_L28N_7/400NC IO_L17P_7 D4 io_tx_14
ADC05_B F17 IO IO_L19P_1/400NC D16
SDO_TX_ADC H2 IO_L28P_7/400NC IO_L19P_7 D2 io_tx_13
ADC06_B C19 IO_L01N_1/VRP_1/DCI IO_L22N_1/400NC A16
SDI_TX_ADC J4 IO_L29N_7/400NC IO_L20N_7 F4 io_tx_12
ADC07_B B20 IO_L01P_1/VRN_1/DCI IO_L22P_1/400NC B16
SEN_TX_DAC H4 IO_L29P_7/400NC IO_L20P_7 E3 io_tx_11
ADC08_B B19 IO_L06P_1 IO_L31N_1/VREF_1 D12
SCLK_TX_DAC J5 IO_L31N_7/400NC IO_L21N_7 E1 io_tx_10
N ADC09_B C18 IO_L09N_1 N
SDI_TX_DAC J6 IO_L31P_7/400NC IO_L21P_7 E2 io_tx_09
LTC2284−A U2
ADC10_B D18 IO_L09P_1
SDI J1 IO_L32N_7/400NC IO_L22N_7 G6 io_tx_08
VINP_A 16 VIN+_B D0_B 24 ADC00_B
ADC11_B B18 IO_L10P_1
SDO J2 IO_L32P_7/400NC IO_L22P_7 F5 io_tx_07
VINN_A 15 VIN−_B D1_B 25 ADC01_B
ADC12_B D17 IO_L15N_1
SCLK K5 IO_L33N_7/400NC IO_L23N_7 F2 io_tx_06
CLK_ADC 9 CLK_B D2_B 26 ADC02_B
ADC13_B E17 IO_L15P_1
SEN_CLK K6 IO_L33P_7/400NC IO_L23P_7 F3 io_tx_05
ADC_OE_B_N 23 OEB_B D3_B 27 ADC03_B
M ADC_OVF_B B17 IO_L16N_1 M
SEN_DAC L1 IO_L40N_7/VREF_7 IO_L24N_7 H5 io_tx_04
ADC_PDN_B 22 PDWN_B D4_B 28 ADC04_B
ADC_OE_B_N C17 IO_L16P_1
IO_L24P_7 G5 io_tx_03
D5_B 29 ADC05_B
ADC_PDN_B D15 IO_L24N_1
IO_L27N_7 G1 io_tx_02
D6_B 30 ADC06_B E15 IO_L24P_1
IO_L34N_7 K3 io_tx_01
D7_B 33 ADC07_B B15 IO_L25N_1
IO_L34P_7 K4 io_tx_00
L D8_B 34 ADC08_B L
A15 IO_L25P_1
IO_L35N_7 K1 PPS_IN
D9_B 35 ADC09_B D14 IO_L27N_1
IO_L35P_7 K2 TX15_A
D10_B 36 ADC10_B E14 IO_L27P_1
IO_L38N_7 L5 TX14_A
D11_B 37 ADC11_B
AD9777−CH1 U3 ADC00_A A14 IO_L28N_1
IO_L38P_7 L6 TX13_A
D12_B 38 ADC12_B
ADC01_A B14 IO_L28P_1
IO_L39N_7 L3 TX12_A TX15_A 11 DB15_P1 IOUT1_P 73 IOUTN_B
K D13_B 39 ADC13_B K
ADC02_A C13 IO_L29N_1
IO_L39P_7 L4 TX11_A TX14_A 12 DB14_P1 IOUT1_N 72 IOUTP_B
OVF_B 40 ADC_OVF_B
ADC03_A D13
VCCO_7

VCCO_7

VCCO_7

VCCO_7

VCCO_7

L2 13 IO_L29P_1
IO_L40P_7 TX10_A TX13_A DB13_P1

ADC04_A A13 IO_L30N_1

TX12_A 14 DB12_P1
L7

K7

J7

H6

H3

ADC05_A B13 IO_L30P_1

DVDD_FPGA:1 TX11_A 15 DB11_P1

VCCO_1

VCCO_1

VCCO_1

VCCO_1

VCCO_1
ADC06_A E12 IO_L31P_1
TX10_A 16 DB10_P1
J J
TX09_A 19 DB9_P1

C15

F15

G12

G13

G14
LTC2284−A U2 DVDD_FPGA:1
J305 20
Removed C318, C320 b/c they don’t fit TX08_A DB8_P1

VINP_B 1 VIN+_A D0_A 41 ADC00_A

21
4

TX07_A DB7_P1
C317C316 C319
0.1uF0.1uF 0.1uF VINN_B 2 VIN−_A D1_A 42 ADC01_A
DVDD_FPGA:1 TX06_A 22 DB6_P1
DVDD_FPGA:1
CLK_ADC 8 CLK_A D2_A 43 ADC02_A
330

R315

TX05_A 23 DB5_P1 Removed C323−325 b/c they don’t fit

I I
ADC_OE_A_N 58 OEB_A D3_A 44 ADC03_A
TX04_A 24 DB4_P1 C322C321
0.1uF0.1uF
330

R316

ADC_PDN_A 59 PDWN_A D4_A 45 ADC04_A

U1 TX03_A 27 DB3_P1
1K
1K D5_A 46 ADC05_A
R311 XC3SXX00FG456−IO0 TX02_A 28 DB2_P1
R312
A3

D6_A 47 ADC06_A
LED1 TX01_A 29 DB1_P1
RXD A3 IO/VREF_0 IO A10 TX09_A
A1

slot=3 48
LED2 30 D7_A ADC07_A U1
H C7 D9 TX00_A DB0_P1
slot=1 TXD IO/VREF_0 IO TX08_A H
51 XC3SXX00FG456−IO2
ADC08_A
K3

D8_A
LED1 F7 IO/VREF_0 IO D10 TX07_A
K1

D9_A 52 ADC09_A ADC07_A C22 IO IO_L17P_2/VREF_2 D22 SEN_RX_DB

LED2 E5 IO/VREF_0/400NC IO F6 TX06_A
D10_A 53 ADC10_A ADC08_A C20 IO_L01N_2/VRP_2/DCI IO_L23N_2/VREF_2 F19 SCLK_RX_DB
DVDD_FPGA:1

LED3 B7 IO_L19N_0/400NC IO_L01N_0/VRP_0/DCI B4 TX05_A

R301 D11_A 54 ADC11_A ADC09_A C21 IO_L01P_2/VRN_2/DCI IO_L26N_2/400NC G20 SDO_RX_DB
SCL A7 IO_L19P_0/400NC IO_L01P_0/VRN_0/DCI A4 TX04_A
D12_A 55 ADC12_A ADC10_A D20 IO_L16N_2 IO_L26P_2/400NC H19 SDI_RX_DB
2.2K
DVDD_FPGA:1

G LED0 E8 IO_L22N_0/400NC IO_L06N_0 D5 TX03_A AD9777−CH2 U3 G

D13_A 56 ADC13_A ADC11_A D19 IO_L16P_2 IO_L28N_2/400NC H18 SEN_RX_ADC
R302 D8 C5
SDA IO_L22P_0/400NC IO_L06P_0 TX02_A 31 69
TX15_B DB15_P2/IQSEL IOUT2_P IOUTP_A 57 D21 J17
2.2K OVF_A ADC_OVF_A ADC12_A IO_L17N_2 IO_L28P_2/400NC SCLK_RX_ADC
K2

LED4 C11 IO_L31P_0/VREF_0 IO_L09N_0 B5 TX01_A

TX14_B 32 DB14_P2/ONEPORTCLK IOUT2_N 68 IOUTN_A
K2

ADC13_A E18 IO_L19N_2 IO_L29N_2/400NC H21 SDO_RX_ADC

IO_L09P_0 A5 TX00_A
TX13_B 33 DB13_P2
slot=2
K3

ADC_OVF_A F18 IO_L19P_2 IO_L29P_2/400NC H22 SDI_RX_ADC

LED1 E6
A2

slot=2 IO_L10N_0 34 AVDD_RX:1

TX12_B DB12_P2 E19 J18
ADC_OE_A_N SEN_RX_DAC
A2

LED2 IO_L20N_2 IO_L31N_2/400NC

F slot=3 IO_L10P_0 D6 DAC_LOCK F
R319 TX11_B 37 DB11_P2
LED2 ADC_PDN_A E20 J19 SCLK_RX_DAC
A3

IO_L20P_2 IO_L31P_2/400NC
1K C6
IO_L15N_0 38
TX10_B DB10_P2 E21 J21
R314 IO_L21N_2 IO_L32N_2/400NC SDI_RX_DAC
R313 IO_L15P_0 B6 TX15_B 0 2V Range
1K TX09_B 39 DB9_P2 0
1K R305 io_rx_15 E22 IO_L21P_2 IO_L32P_2/400NC J22
E7 LTC2284−CTRL U2 R304
IO_L16N_0 TX14_B 40 R317
DVDD_FPGA:1 TX08_B DB8_P2 G17 K17
1K io_rx_14 IO_L22N_2 IO_L33N_2/400NC
D7 C302 3 62
IO_L16P_0 TX13_B 41 REFH_A SENSE_A
TX07_B DB7_P2 G18 K18
io_rx_13
AGND_RX:1

IO_L22P_2 IO_L33P_2/400NC
E B8 1uF C304 4 19 E
IO_L24N_0 TX12_B REFH_A SENSE_B

AVDD_RX:1
TX06_B 42 DB6_P2 0.1uF
DVDD_FPGA:1 io_rx_12 G19 IO_L23P_2 IO_L34N_2/VREF_2 K19
DVDD_FPGA:1 IO_L24P_0 A8 TX11_B 5 REFL_A MUX 21
TX05_B 45 DB5_P2 C301
io_rx_11 F20 IO_L24N_2 IO_L40P_2/VREF_2 L22
F9 C303 1uF 2.2uF 6 60 R306 1V Range
IO_L25N_0 TX10_B 46 REFL_A MODE
TX04_B DB4_P2 NONE R307 F21
io_rx_10 IO_L24P_2
E9 C306 13 61 NONE
IO_L25P_0 TX09_B 47 REFH_B VCM_A
TX03_B DB3_P2 G21
io_rx_09
AGND_RX:1

IO_L27N_2
B9 1uF C308 14 20
IO_L27N_0 TX08_B 48 REFH_B VCM_B
TX02_B DB2_P2 0.1uF G22
D io_rx_08 IO_L27P_2 D
IO_L27P_0 A9 TX07_B 11 REFL_B
TX01_B 49 DB1_P2 C305
R318 io_rx_07 K20 IO_L34P_2
F10 C307 1uF 2.2uF 12 C351 C350
IO_L28N_0 TX06_B 50 REFL_B 2K
TX00_B DB0_P2 C309 C310 1uF 1uF K21
io_rx_06 IO_L35N_2
E10 2.2uF 2.2uF
IO_L28P_0 TX05_B
io_rx_05 K22 IO_L35P_2
IO_L29N_0 C10 TX04_B MODE ==> 2/3Vdd = 2’s Comp, w/DCS
io_rx_04 L17 IO_L38N_2
MUX ==> A−> A, B −> B AGND_RX:1
IO_L29P_0 B10 TX03_B
SENSE ==> 1 Vpp or 2 Vpp Range L18
C io_rx_03 IO_L38P_2 C
IO_L30N_0 F11 TX02_B
io_rx_02 L19 IO_L39N_2
IO_L30P_0 E11 TX01_B
io_rx_01 L20 IO_L39P_2
VCCO_0

VCCO_0

VCCO_0

VCCO_0

VCCO_0

IO_L31N_0 D11 TX00_B

VCCO_2

VCCO_2

VCCO_2

VCCO_2

VCCO_2
io_rx_00 L21 IO_L40N_2
G11

G10

G9

F8

C8

DVDD_FPGA:1

H17

H20

J16

K16

L16
B DVDD_FPGA:1 B

Removed C312, C314, C315 b/c they don’t fit

C311C313
0.1uF0.1uF C327C326C328C329C330 USRP2 FPGA and CODECs
A 0.1uF0.1uF0.1uF0.1uF0.1uF A
TITLE $Date$
FILE: fpga.sch REVISION: $Revision$
PAGE 3 OF 8 DRAWN BY: $Author$
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

K K

DVDD_FPGA:1
R231 130K

2_5V_FPGA:1
Both JTAG ports are 2.5V R232 NONE
U24 2_5V_FPGA:1

R234
NONE
J J203 R233 100K J
TMS 1 7 POR
XIL−PLAT−CABLE 2_5V_FPGA:1 TMS RSTin/MRn RESETn
R22110 A20
8200pF C206 2 6 WDI
TDI_PORT TDI_CPLD TDO_FPGA SWT WDI
TDO 2_5V_FPGA:1
1 GND Vref/Vref 2 B22 3 5
SRT WDS
R22210 TDI_FPGA C207 0.1uF
3 4 B1 TDI
GND PROG/TMS TMS TDO_CPLD TDI_FPGA MAX6749KA+T
TCK 2_5V_FPGA:8
5 6 A21 TCK R203

R229
GND CCLK/TCK TCK R22310 GND:4

NONE
TDO_FPGA TDO_PORT 10K

10K
7 GND Done/TDO 8 TDO_PORT
I XC3SXX00FG456−JTAG U1 pg1 POR I

9 10 R224NONE

R206
GND Din/TDI TDI_PORT
TDI_PORT TDI_FPGA 2_5V_FPGA:1 U11
11 GND NC/NC 12 24Cxx
R225NONE 1 A0 C201
13 14 TDO_FPGA TDI_CPLD 2 7
GND INIT/NC A1 n/c NONE
3 A2 SCL 6 SCL
R226NONE 5
SDA SDA
TDO_CPLD TDO_PORT
1K 24LC024/SN H
H U10 DVDD_FPGA:8
R202 1K GND:4
XC9572−VQ44−IO
1K R214 2_5V_FPGA:1

2
0
39 5 R201 DVDD_FPGA:1
2_5V_FPGA:1 IO_B1MC2 IO_B3MC2 CLK_25MHZ
330

2
R211 40 6 D201
CLK_25MHZ_EN

1
IO_B1MC5 IO_B3MC5

A1
0
R213 41 7 LED1
IO_B1MC6 IO_B3MC8
D202 slot=1

26

35

15
U10

1
G
G R210 POR 42 IO_B1MC8 IO_B3MC9 8

XC9572−VQ44−PWR
VccIO

VccINT

VccINT
K1
cpld_detached 43 IO_B1MC9/GCK1 IO_B3MC11 12

AB21

AA22
C202 C204 C205
AB3

AA1

AB2

U1 cpld_misc 44 IO_B1MC11/GCK2 IO_B3MC14 13 cpld_clk

A2

B3
C203 0.1uF 0.1uF 0.1uF

GND

GND

GND
0.1uF

XC3SXX00FG456−CFG
1 14
PROG_B

M2

M1

M0

HSWAP_EN

DONE

CCLK
1 IO_B1MC14/GCK3 IO_B3MC15 cpld_start

25

17

4
2 2 IO_B1MC15 IO_B3MC16 18 cpld_mode
F
F 3 3 IO_B1MC17 IO_B3MC17 16 cpld_done

J204 29 19 J201
4 IO_B2MC2 IO_B4MC2 sd_prot
IO_L31P_4/DOUT/BUSY

5 30 IO_B2MC5 IO_B4MC5 20 sd_cs_25 sd_cs_33 1 CD_DAT[3]/NC/nCS 2_5V_FPGA:1

IO_L01N_5/RDWR_B
IO_L27N_4/DIN/D0
IO_L31N_4/INIT_B

IO_L01P_5/CS_B

6 31 IO_B2MC6 IO_B4MC8 21 sd_din_25 sd_din_33 2 CMD/CMD/Din 11

IO_L31N_5/D4

IO_L30N_4/D2

IO_L28N_5/D6
IO_L31P_5/D5

IO_L30P_4/D3

IO_L28P_5/D7

IO_L27P_4/D1

prot_det_com

7 32 IO_B2MC8 IO_B4MC11 22 sd_clk_25 DVDD_FPGA:1 3 Vss1 protect 12 sd_prot

detect 10 sd_det E
E 8 33 IO_B2MC9/GSR IO_B4MC14 23 4 Vdd

R228

R227
9 34 IO_B2MC11/GTS2 IO_B4MC15 27 sd_clk_33 5 CLK
V11

Y12

W11

W12

V12

U12

AA9

AB9

AB14

AA14

AA3

Y4

Pin Defs:
sd_det
ser_loopen 36 28 6 SD/MMC/SPI
10 IO_B2MC14/GTS1 IO_B4MC17 Vss2
cpld_detached

cpld_misc

ser_enable

cpld_done

cpld_mode

cpld_start

cpld_clk
ser_rx_en

10K

10K
ser_prbsen
cpld_din 37 IO_B2MC15 7 DAT[0]/DAT[0]/Dout
2_5V_FPGA:1
38 IO_B2MC17 8 DAT[1]/NC/NC
4.7K
TCK
TDO_CPLD 24 TDO

TMS
TDI

D
D 9 DAT[2]/NC/NC

GND

GND
9

11

10
cpld_init_b R212

13

14
TMS
TDI_CPLD

TCK

Slave Serial 2.5V

C
C Bank 4 must be 2.5V
U31 U32 U33
SN74AUP1T57 SN74AUP1T57 SN74AUP1T57

3 A Y 4 sd_cs_33 3 A Y 4 sd_din_33 3 A Y 4 sd_clk_33

sd_cs_25 1 B sd_din_25 1 B sd_clk_25 1 B

B
B
6 C 6 C 6 C
GND

GND

GND
Vcc

Vcc

Vcc
DVDD_FPGA:1

DVDD_FPGA:1

DVDD_FPGA:1
5

2
USRP2 Configuration
A
A TITLE $Date$
FILE: config.sch REVISION: $Revision$
PAGE 2 OF 8 DRAWN BY: $Author$
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
AGND_TX:1
AVDD_TX:1

SCLK_TX_DAC

SDI_TX_DAC
SEN_TX_DAC
K K
AVDD_TX:1

L402

C402
10
7

5
AVDD_TX:1 0.1uF

0.1uF
SYNC

Din

LDAC

CLR

Ref
SCLK
C408

AD56x3

GND
Vdd
J J

3
C407

C401

OUTA

OUTB
AGND_TX:1
AGND_TX:1 U6 7
GND

2
U4

0.1uF
10uF
SDI_TX_ADC SCLK_TX_ADC
4 Din SCLK 3
AD79X2−MSOP SDO_TX_ADC

I2C Address
5 Vin1 Dout 1
AGND_TX:1
SEN_TX_ADC
I 6 Vin0 CS 2 I
Vdd

SCLK_TX_DB

SDO_TX_DB

SDI_TX_DB

SEN_TX_DB
AVDD_TX:1
AVDD_TX:1
6V_TX:1

clock_tx_p

clock_tx_n
8
DVDD_TX:1 AVDD_TX:1
AGND_TX:1 AGND_TX:1 AGND_TX:1

SDA
SCL
Vref

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

56

58

60

62

64
2

8
H
H

J401
35

37

39

41

43

45

47

49

51

53

55

57

59

61

63
1

11

13

15

17

19

21

23

25

27

29

31

33
AGND_TX:1 AGND_TX:1 AGND_TX:1
AGND_TX:1 AGND_TX:1

IOUTN_B

IOUTP_B

IOUTP_A

IOUTN_A
AVDD_TX:1

io_tx_15

io_tx_14

io_tx_13

io_tx_12

io_tx_11

io_tx_10

io_tx_09

io_tx_08

io_tx_07

io_tx_06

io_tx_05

io_tx_04

io_tx_03

io_tx_02

io_tx_01

io_tx_00
G
G AVDD_TX:1

F
F

VINP_B

VINN_B

VINN_A

VINP_A
io_rx_15

io_rx_14

io_rx_13

io_rx_12

io_rx_11

io_rx_10

io_rx_09

io_rx_08

io_rx_07

io_rx_06

io_rx_05

io_rx_04

io_rx_03

io_rx_02

io_rx_01

io_rx_00
AVDD_RX:1
AVDD_RX:1
10 AGND_RX:1 AGND_RX:1 AGND_RX:1
AGND_RX:1 AGND_RX:1

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

56

58

60

62

64
2

E
E

J402
35

37

39

41

43

45

47

49

51

53

55

57

59

61

63
1

11

13

15

17

19

21

23

25

27

29

31

33
Vref

SCLK_RX_DB

SDO_RX_DB

SDI_RX_DB

SEN_RX_DB
AVDD_RX:1
SDA
clock_rx_p

clock_rx_n

SCL

AGND_RX:1 AGND_RX:1 AGND_RX:1

DVDD_RX:1 DVDD_RX:1 AVDD_RX:1 C404 0.1uF D
D 6V_RX:1
AVDD_RX:1 U7 8
AGND_RX:1
I2C Address

Vdd
6 Vin0 CS 2 SEN_RX_ADC
5 Vin1 Dout 1 SDO_RX_ADC
AD79X2−MSOP
SDI_RX_ADC 4 Din SCLK 3 SCLK_RX_ADC
GND
C
C 7

U5

1
AVDD_RX:1
AGND_RX:1

OUTB

OUTA
AD56x3
GND
3

9
Vdd

C403

C405
SCLK
SYNC
LDAC
CLR
Ref

Din
AGND_RX:1 B
B

10

0.1uF

10uF
AVDD_RX:1

SCLK_RX_DAC
SEN_RX_DAC
SDI_RX_DAC
L401 AVDD_RX:1

AGND_RX:1
C406
USRP2 Daughterboad Interface
0.1uF A
A TITLE $Date$

AGND_RX:1 FILE: dboard.sch REVISION: $Revision$

AGND_RX:1 PAGE 4 OF 8 DRAWN BY: $Author$

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

U17 DVDD_CLK:1
L 6V_CLK:1 L
DVDD_CLK:1 ADG3301

6 VccY VccA 1

R528
J502

17.4K
R522 1K
1 5 Y A 2 PPS_IN
U18

GND
EN
DS90CP22 2345
J501 R521

3
R535 Bias VCXO to 1.65V when no reference DVDD_FPGA:1
K 1 0.1uF C533 T501 1 16 49.9 K
clk_sel1 SEL1 EN0 clk_en0 DVDD_CLK:1
3 6 R541
25 2 15 1M 1M
2345 clk_sel0 SEL0 EN1 clk_en1 R517 R518 10K
R503 5, 2 C539
100 49.9 100pF
3 IN0_P OUT0_P 14
R537 R529
R536 AD9510−PLL U9
1 4 4 13
10K IN0_N OUT0_N 3kHz BW, 45 deg Phase margin
R523
R527 1 6
25 6 11 100 REFIN_P CP with 5 MHz compare freq and 3mA CP current J503
clk_exp_in_p IN1_P OUT1_P

17.4K R524 100 2 REFIN_N C523

J clk_exp_in_n 7 IN1_N OUT1_N 10 J
DVDD_CLK:1 R525 0.1uF C531

4
100 14 CLK1_P 1.2uF
8 NC NC 9

GND
0.1uF C532

Vcc
DVDD_CLK:1 15 CLK1_N R504 390 C525 C546 C545

J505
2

1
0.1uF 0.1uF
0.1uF C526

12
10

R505
CLK2_P 33uF
Outputs to: U9
R526
11 DAC −− PECL AD9510−OUTA
10K CLK2_N
0.1uF C537
C527 0.1uF FPGA −− PECL 200
I OUT0_P 58 testclk_p I
200 Expansion −− PECL
R519

12K
R542
OUT0_N 57 testclk_n 200
200 R507 C524 TX−Dboard −− CMOS/LVDS R581 R543
OUT1_P 54 200
200 R508 200 R509 RX−Dboard −− CMOS/LVDS
0.12uF
DVDD_CLK:1 VCTCXO U8 ADC −− CMOS 53 R582 200
OUT1_N
C580
4 3 35 CLK_FPGA_P
Vcc OUT OUT2_P
0.1uF
H 2 1 34 CLK_FPGA_N H
GND ENB/TUNE OUT2_N
DVDD_CLK:1 0.1uF
OUT3_P 29 CLK_DAC_P C581

U22 OUT3_N 28 CLK_DAC_N

6V_CLK:1
LP38692MP

1 EN Vout 3

1
C544 DVDD_CLK:1 DVDD_FPGA:1
G 4 U9 G
Vin 1.3K
J504 825 AD9510−OUTB
1uF XC3SXX00FG456−CLK U1 U20
NC GND C1117 C1118 C1121

2
R515 R514 DS90LT012AH
0.1uF 220pF 47uF 47 3
2 5 1 B11 OUT4_P clkadc_p 5
C542 CLK_FPGA_N IO_L32N_0/GCLK7 4 CLK_ADC
0.1uF 46
2 B12 OUT4_N clkadc_n
C534 R580 CLK_STATUS IO_L32N_1/GCLK5 AVDD_RX:1
0.1uF 43 AGND_RX:2
AA12 OUT5_P clk_exp_out_p
GMII_RX_CLK IO_L32N_4/GCLK1

OUT5_N 42 clk_exp_out_n
F 100 ser_rx_clk AA11 IO_L32N_5/GCLK3 F
25
39 R520
A11 OUT6_P clock_tx_p
CLK_FPGA_P IO_L32P_0/GCLK6
1.3K 38 R506 25
825 C12 OUT6_N clock_tx_n
CLK_FUNC IO_L32P_1/GCLK4
DVDD_CLK:1 R513 R512 OUT7_P 25 R570 25
clock_rx_p
DVDD_TX:1 CLK_TO_MAC AB12 IO_L32P_4/GCLK0

R511 U3 C535 OUT7_N 24 clock_rx_n

DVDD_TX:1 Y11 IO_L32P_5/GCLK2
AD9777−CTRL 25 R571
U9
E
NONE E
AD9510−CTRL 127 R530 83 R531 5 2 C536
CLK_DAC_P CLK_P LPF
1K
NONE
CLK_FUNC 16 FUNCTION CLK_DAC_N 6 CLK_N DATACLK/PLL_LOCK 8 DAC_LOCK
127 R532 83 R533 AVDD_RX:1
CLK_STATUS 17 STATUS 57 RESET FSADJ1 60

SCLK 18 SCLK SDO 53 SDO FSADJ2 59

SDI 19 SDIO SDI 54 SDIO REFIO 58

D R516 D
C543
20 55 NONE
SDO SDO SCLK SCLK 0.1uF
21 56 R510
SEN_CLK CSB SEN_DAC CSB
950 1% AGND_RX:1
C528
0.1uF

AGND_TX:1
C DVDD_CLK:1 C

DVDD_CLK:1

U9
64

60

59

56

52

51

48

45

44

41

40

37

36

33

31

30

26

23

13
5

AD9510−PWR
Vcp

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS
RSET
61

B B
CPRSET

GND_EP
63

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND
C521 C522 C519 C520 C513 C514 C511 C512 C509 C510 C507 C508 C505 C506 C503 C504 C501 C502 C517 C518 C515 C516 R501
R502
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 4.12K 1%
5.1K 1%

65

62

55

50

49

32

27

22

12

3
USRP2 Clocking
A TITLE $Date$ A

FILE: clock.sch REVISION: $Rev$

PAGE 5 OF 8 DRAWN BY: $Author$
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
 1 2 3
U1 4 5 6 7 8 9 10 11 12 13 14 15 16 17

XC3SXX00FG456−IO5

ser_tx_clk U7 IO IO/400NC U9 ser_r02

K K

ser_tklsb U10 IO IO/VREF_5 U6 ser_r03

ser_tkmsb U11 IO IO/VREF_5 AB11 ser_r04 2_5V_SER:1

2_5V_SER_AN:1
ser_t00 V7 IO IO_L19N_5/400NC Y7 ser_r05 200 R709 800 R710
U1
ser_t01 V10 IO IO_L19P_5/VREF_5/400NC W7 ser_r06
XC3SXX00FG456−IO6

49.9

49.9

49.9

49.9
ser_t02 AB4 IO_L06N_5 IO_L22N_5/400NC AB7 ser_r07
J J
ser_r11 Y1 IO IO_L17P_6/VREF_6 W1 ser_r15
AA4 AA7

R711

R712
ser_t03 IO_L06P_5 IO_L22P_5/400NC ser_r08

R707

R708
Y3 U3 U13
ser_r12 IO_L01N_6/VRP_6/DCI IO_L24N_6/VREF_6 debug_12 TLK2XX1−TX U13
Y5 W9 TLK2XX1−RX
ser_t04 IO_L09N_5 IO_L27N_5/VREF_5 ser_r09
ser_r13 Y2 IO_L01P_6/VRN_6/DCI IO_L26N_6/400NC T3 debug_11 0.01uF C710
ser_tx_clk 8 GTX_CLK DOUTTXN 59 ser_out_n 0.01uF C708
ser_t05 W5 IO_L09P_5 IO_L29P_5/VREF_5 W10 ser_r10 ser_rx_en 25 LCKREFN DINRXN 53 ser_in_n
ser_r14 W4 IO_L16N_6 IO_L26P_6/400NC R4 debug_10
ser_tklsb 22 TKLSB/TX_ER DOUTTXP 60 ser_out_p
ser_t06 AB5 IO_L10N_5/VRP_5/DCI ser_rklsb 29 RKLSB/RX_ER/PRBS_PASS DINRXP 54 ser_in_p
debug_31 W3 IO_L16P_6 IO_L28N_6/400NC R5 debug_09 C709 0.01uF
ser_tkmsb 20 TKMSB/TX_EN C707 0.01uF
ser_t07 AA5 IO_L10P_5/VRN_5/DCI ser_rkmsb 30 RKMSB/RX_DV/LOS
I I
debug_30 W2 IO_L17N_6 IO_L28P_6/400NC P6 debug_08
ser_t00 62 TXD0
ser_t08 W6 IO_L15N_5 ser_r00 51 RXD0
debug_29 V5 IO_L19N_6 IO_L29N_6/400NC R2 debug_07
ser_t01 63 TXD1
ser_t09 V6 IO_L15P_5 ser_r01 50 RXD1
debug_28 U5 IO_L19P_6 IO_L29P_6/400NC R1 debug_06
ser_t02 64 TXD2
ser_t10 AA6 IO_L16N_5 ser_r02 49 RXD2
exp_pps_in_n V4 IO_L20N_6 IO_L31N_6/400NC P5 debug_05
ser_t03 2 TXD3
ser_t11 Y6 IO_L16P_5 ser_r03 47 RXD3
exp_pps_in_p V3 IO_L20P_6 IO_L31P_6/400NC P4 debug_04
ser_t04 3 TXD4
ser_t12 W8 IO_L24N_5 ser_r04 46 RXD4 H
H
exp_pps_out_n V2 IO_L21N_6 IO_L32N_6/400NC P2 debug_03
ser_t05 4 TXD5
ser_t13 V8 IO_L24P_5 ser_r05 45 RXD5
exp_pps_out_p V1 IO_L21P_6 IO_L32P_6/400NC P1 debug_02
ser_t06 6 TXD6
ser_t14 AB8 IO_L25N_5 ser_r06 44 RXD6
debug_27 T6 IO_L22N_6 IO_L33N_6/400NC N6 debug_01
ser_t07 7 TXD7
ser_t15 AA8 IO_L25P_5 ser_r07 42 RXD7
debug_26 T5 IO_L22P_6 IO_L33P_6/400NC N5 debug_00
ser_t08 10 TXD8
ser_rklsb V9 IO_L27P_5 ser_r08 40 RXD8
debug_25 U4 IO_L23N_6 IO_L34N_6/VREF_6 N4 debug_clk0
ser_t09 11 TXD9
ser_rkmsb Y10 IO_L29N_5 ser_r09 39 RXD9 G
G
debug_24 T4 IO_L23P_6 IO_L40P_6/VREF_6 M1 debug_clk1
ser_t10 12 TXD10
ser_r00 AB10 IO_L30N_5 ser_r10 37 RXD10
debug_23 U2 IO_L24P_6
ser_t11 14
VCCO_5

VCCO_5

VCCO_5

VCCO_5

VCCO_5

AA10 TXD11 36
ser_r01 IO_L30P_5 ser_r11 RXD11
debug_22 T2 IO_L27N_6
ser_t12 15 TXD12
ser_r12 35 RXD12
debug_21 T1 IO_L27P_6
T9

T10

T11

U8

Y8

ser_t13 16 TXD13
2_5V_FPGA:1 ser_r13 34 RXD13
debug_20 N3 IO_L34P_6
ser_t14 17 TXD14
ser_r14 32 RXD14 F
F
debug_19 N2 IO_L35N_6
ser_t15 19 TXD15
ser_r15 31 RXD15
debug_18 N1 IO_L35P_6
ser_rx_clk 41 RX_CLK
debug_17 M6 IO_L38N_6

IPASS−SAS−X4−SHLD
C724C723C725C726C727 M5
debug_16 IO_L38P_6 J707
0.1uF0.1uF0.1uF0.1uF0.1uF
debug_15 M4 IO_L39N_6
J301 E
E J707
debug_14 M3 IO_L39P_6
MICTOR43−LA IPASS−SAS−X4
VCCO_6

VCCO_6

VCCO_6

VCCO_6

VCCO_6

debug_13 M2 IO_L40N_6

GND

GND

GND

GND

GND

GND

GND

GND

GND
debug_clk0 5 CLK0 CLK1 6 debug_clk1 A1 GND GND B1

R722
100
29

30

31

32

33

34

35

36

37
debug_31 7 A3[7] A1[7] 8 debug_15 ser_in_p A2 RX0_P TX0_P B2 ser_out_p
M7

N7

P7

R3

R6

2_5V_FPGA:1
debug_30 9 A3[6] A1[6] 10 debug_14 ser_in_n A3 RX0_N TX0_N B3 ser_out_n
CML
debug_29 11 A3[5] A1[5] 12 debug_13 A4 GND GND B4 D
D

13 14 C742 0.1uF A5 B5 0.1uF C743

debug_28 A3[4] A1[4] debug_12 2_5V_SER_AN:1 exp_user_in_p RX1_P TX1_P exp_user_out_p
15 16 2_5V_SER:1 A6 B6 R721
debug_27 A3[3] A1[3] debug_11 exp_user_in_n RX1_N TX1_N exp_user_out_n
2_5V_FPGA:1 100
C719C718C720C721C722 L707 C741 0.1uF 0.1uF C744
debug_26 17 A3[2] A1[2] 18 debug_10 0.01uF C711 A7 GND GND B7
0.1uF0.1uF0.1uF0.1uF0.1uF
19 20 C730 0.1uF A8 B8 0.1uF C728
debug_25 A3[1] A1[1] debug_09 clk_exp_in_p RX2_P TX2_P clk_exp_out_p

C debug_24 21 A3[0] A1[0] 22 debug_08 C712 0.01uF 57 R716

10K
clk_exp_in_n A9 RX2_N TX2_N B9 clk_exp_out_n
R730
100
LVDS C

55

48

38

23
C731 0.1uF 0.1uF C729

1
debug_23 23 A2[7] A0[7] 24 debug_07 A10 GND GND B10

TLK2XX1−PWR
VDDA

VDDA

VDD

VDD

VDD

VDD

VDD
25 26 C734 0.1uF A11 B11 0.1uF C732
debug_22 A2[6] A0[6] debug_06 24 exp_pps_in_p RX3_P TX3_P exp_pps_out_p
ser_enable ENABLE

debug_21 27 A2[5] A0[5] 28 debug_05 21

R715
exp_pps_in_n A12 RX3_N TX3_N B12 exp_pps_out_n
R714 LVDS
ser_loopen LOOPEN 100 100
2_5V_SER_AN:1 C713C714C715C716C717 C735 0.1uF 0.1uF C733
debug_20 29 A2[4] A0[4] 30 debug_04 A13 GND GND B13
ser_prbsen 26 PRBSEN
31 32 0.01uF
0.01uF
0.01uF
0.01uF
0.01uF B
B debug_19 A2[3] A0[3] debug_03 200 R713 56 Rref
33 34 R717
debug_18 A2[2] A0[2] debug_02 27 TESTEN 10K
GND_EP

GNDA

GNDA

GNDA

debug_17 35 A2[1] A0[1] 36 debug_01

GND

GND

GND

GND

GND

GND

U13
debug_16 37 A2[0] A0[0] 38 debug_00
65

61

58

52

43

33

28

18

13

5
GND

GND

GND

GND

GND

NC

NC

NC

NC

USRP2 Expansion
39

40

41

42

43

A
A TITLE $Date$
FILE: expansion.sch REVISION: $Revision$
PAGE 7 OF 8 DRAWN BY: $Author$
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

U1
XC3SXX00FG456−IO4
K K

Add caps at 2.5V near PHY R645 NONE

GMII_COL U16 IO IO/VREF_4 V18 MDC
2_5V_ETH:1 GMII_CRS U17 IO IO/VREF_4 Y16 MDIO
R646 NONE

2_5V_ETH:1
GMII_TX_CLK W13 IO IO/VREF_4 AB13 PHY_INTn
R644 909
GMII_TXD0 W14 IO IO_L05N_4/400NC AA19 PHY_RESET

R601 49.9

R602 49.9

R603 49.9

R604 49.9

R605 49.9

R606 49.9

R607 49.9

R608 49.9
C640 C641 CHASSIS_GND:1
0.1uF 0.1uF AA20 AB19 R643 909
J GMII_TXD1 IO_L01N_4/VRP_4/DCI IO_L05P_4/400NC ETH_LED 2_5V_FPGA:1 J

AB20 W18 R642 909

U12 J601 GMII_TXD2 IO_L01P_4/VRN_4/DCI IO_L06N_4/VREF_4 POR DP83865−MAC U12
DP83865−MDI BEL 0826−1X1T−23−F

4.7K
GMII_TXD3 Y18 IO_L06P_4 IO_L19N_4/400NC AA16 GMII_RX_ER

R236
GMII_COL 39 COL/CLK_MACFREQ TXD0 76 GMII_TXD0
MDIA_P 108 11 MDIA_P
GMII_TXD4 AA18 IO_L09N_4 IO_L19P_4/400NC AB16 GMII_RX_DV 33 R640 R648 33
GMII_CRS 40 CRS/RGMII_SEL0 TXD1 75 GMII_TXD1
MDIA_N 109 10 MDIA_N
GMII_TXD5 AB18 IO_L09P_4 IO_L22N_4/VREF_4/400NC V15 reset_fpga 33 R639 R647 33
GMII_TX_CLK 60 TX_CLK/RGMII_SEL1 TXD2 72 GMII_TXD2
MDIB_P 114 4 MDIB_P 33 R641 R650 33

2
GMII_TXD6 V17 IO_L10N_4 IO_L22P_4/400NC W15 WDI
I GMII_RX_CLK 57 RX_CLK TXD3 71 GMII_TXD3 I

C361
0.1uF
115 5

S1
MDIB_N MDIB_N W17 33 R629 R649 33
GMII_TXD7 IO_L10P_4 56 68
GMII_RXD0 RXD0 TXD4 GMII_TXD4
MDIC_P 120 3 MDIC_P Y17 33 R628 R652 33

1
GMII_TX_EN IO_L15N_4 55 67
GMII_RXD1 RXD1 TXD5 GMII_TXD5
MDIC_N 121 2 MDIC_N
GMII_GTX_CLKAA17 IO_L15P_4 33 R631 R651 33
GMII_RXD2 52 RXD2 TXD6 66 GMII_TXD6
MDID_P 126 8 MDID_P
GMII_TX_ER V16 IO_L16N_4
33 R630 R654 33
GMII_RXD3 51 RXD3 TXD7 65 GMII_TXD7
MDID_N 127 9 MDID_N W16 IO_L16P_4 33 R633 R653 33 H
H SHIELD/GND SG1 GMII_RXD4 50 RXD4 TX_EN/TX_EN\ER 62 GMII_TX_EN
2_5V_ETH:1
SHIELD/GND SG2 GMII_RXD0 AA15 IO_L24N_4 33 R632 R655 33
0.1uF C601 GMII_RXD5 47 RXD5 GTX_CLK/TCK 79 GMII_GTX_CLK
12 MCTA
0.1uF C602 GMII_RXD1 AB15 IO_L24P_4 33 R635 R657 33
6 MCTB GMII_RXD6 46 RXD6 TX_ER 61 GMII_TX_ER
0.1uF C603 1 CHASSIS_GND:1 U14 33 R634 R656 33
MCTC GMII_RXD2 IO_L25N_4 45
GMII_RXD7 RXD7
0.1uF C604 7 MCTD V14 33 R636
GMII_RXD3 IO_L25P_4 41
GMII_RX_ER RX_ER/RXDV\ER
R610 330 13 U13 33 R638 G
G LED1(Yellow Cath) GMII_RXD4 IO_L28N_4 44
GMII_RX_DV RX_DV/RCK
R659 0 14
ACT_LED LED1(Yellow Anode) V13 33 R637
GMII_RXD5 IO_L28P_4
R660 0 15 LED2(Grn Cath/Org An)
R609 330 GMII_RXD6 Y13 IO_L29N_4
ETH_LED 16 LED2(Grn An/Org Cath)

VCCO_4

VCCO_4

VCCO_4

VCCO_4

VCCO_4
GMII_RXD7 AA13 IO_L29P_4
2_5V_ETH:1
L603 VCTCXO X2 CLK_25MHZ
LED Polarities!!!

T12

T13

T14

U15

Y15
2_5V_FPGA:1 10 R671 F
F U12 4 Vcc OUT 3 PHY_CLK
DP83865−JTAG
0 R672

Section 5.9 R611 2K 32 TRST

C642
2 GND ENB/TUNE 1
R661 2_5V_ETH:1

31 0.1uF
TDI
1K R662
NONE
28 TDO C609C608C610C611C612 CLK_25MHZ_EN
0.1uF0.1uF0.1uF0.1uF0.1uF
27 TMS E
E DP83865−CFGLED U12
24 TCK
R615 2K 1 7
NON_IEEE_STRAP ACTIVITY_LED/SPEED0_STRAP ACT_LED
2K R623
6 8 LINK10

2_5V_ETH:1
2_5V_ETH:1 2_5V_ETH_A:1 MAN_MDIX_STRAP/TX_TCLK LINK10_LED/RLED/SPEED1_STRAP
1_8V:1 1_8VA:1 2K R624
L601 L602 R616 2K 14 9 LINK100

2_5V_ETH:1
PHYADDR1_STRAP LINK100_LED/DUPLEX_STRAP

R617 2K 17 2K R625
10 LINK1G

2_5V_ETH:1
PHYADDR2_STRAP LINK1000_LED/AN_EN_STRAP
D
D R618 2K 18 2K R626
PHYADDR3_STRAP DUPLEX_LED/PHYADDR0_STRAP 13 DUP_LED
C622C623C624C625C619C620C621C613 C614C615C616C617C618 C636C637C638C639C632C633C634C635C629C630C631C626 C627C628 2K R627
1_8VA:1 R619 2K 95
0.1uF0.1uF0.1uF0.1uF0.1uF0.1uF0.1uF0.1uF 0.1uF0.1uF0.1uF0.1uF0.1uF 0.1uF0.1uF0.1uF0.1uF0.1uF0.1uF0.1uF0.1uF0.1uF0.1uF0.1uF0.1uF 0.1uF0.1uF PHYADDR4_STRAP

R620 2K 94

2_5V_ETH:1
MULTI_EN_STRAP/TX_TRIGGER

10 18 R621 2K 89

2_5V_ETH:1
MDIX_EN_STRAP

R622 2K 88
0.01uF C607 2_5V_ETH_A:1 MAC_CLK_EN_STRAP/TX_SYN_CLK
C
C R613 R612 1_8VA:1 1_8V:1 2_5V_ETH:1 34 VDD_SEL_STRAP
22uF CER X5R 6.3V C605

22uF CER X5R 6.3V C606

Everything on 2.5V
100

123

117

111

105

103

101

U12
84

23

98

96

92

73

63

48

35

25

19

11

90

83

77

69

58

53

42

37

29

21

15
2

2_5V_ETH:1
DP83865−PWR
NC

NC

NC

1V8_AVdd3

1V8_AVdd2

1V8_AVdd1

1V8_AVdd1

1V8_AVdd1

1V8_AVdd1

1V8_AVdd1

2V5_Avdd2

2V5_Avdd1

Core_Vdd

Core_Vdd

Core_Vdd

Core_Vdd

Core_Vdd

Core_Vdd

Core_Vdd

Core_Vdd

IO_Vdd

IO_Vdd

IO_Vdd

IO_Vdd

IO_Vdd

IO_Vdd

IO_Vdd

IO_Vdd

IO_Vdd

IO_Vdd

IO_Vdd

IO_Vdd

U12 B
B DP83865−CLK
102 BG_REF U12
R680

DP83865−MGT
9.76K PHY_CLK 86 CLK_IN
R658
Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

MDC 81 MDC
2K

87 CLK_OUT
128

125

124

122

119

118

116

113

112

110

107

106

104

99

97

93

91

82

78

74

70

64

59

54

49

43

38

36

30

26

22

20

16

12

MDIO 80 MDIO
2K

R614 CLK_TO_MAC 85 CLK_TO_MAC

PHY_INTn 3 INTERRUPT
PHY_RESET 33 RESET USRP2 Ethernet
A
A TITLE $Date$
FILE: ethernet.sch REVISION: $Revision$
PAGE 6 OF 8 DRAWN BY: $Author$
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
 1 2 3 4 5 6 7 8 9 10 11

I I
U19
U1
CY7C1356C−AC−RAM
XC3SXX00FG456−IO3
RAM_D00 58 DQa A 32 RAM_A18
RAM_D10 Y21 IO IO_L17P_3/VREF_3 W19 RAM_D16
RAM_D01 59 DQa A 33 RAM_A17
H H
RAM_D11 Y20 IO_L01N_3/VRP_3/DCI IO_L23P_3/VREF_3 U20 RAM_CE1n
RAM_D02 62 DQa A 34 RAM_A16
RAM_D12 Y19 IO_L01P_3/VRN_3/DCI IO_L26N_3/400NC T20 RAM_A04
RAM_D03 63 DQa A 35 RAM_A15
RAM_D13 W22 IO_L16N_3 IO_L26P_3/400NC T19 RAM_A01
RAM_D04 68 DQa A 44 RAM_A14
RAM_D09 Y22 IO_L16P_3 IO_L28N_3/400NC R22 RAM_WEn
RAM_D05 69 DQa A 45 RAM_A13
RAM_A18 V19 IO_L17N_3 IO_L28P_3/400NC R21 RAM_OEn
RAM_D06 72 DQa A 46 RAM_A12
G G
RAM_D14 W21 IO_L19N_3 IO_L29N_3/400NC P19 RAM_A09
RAM_D07 73 DQa A 47 RAM_A11
RAM_D15 W20 IO_L19P_3 IO_L29P_3/400NC R19 RAM_LDn
RAM_D08 74 DQPa A 48 RAM_A10
RAM_A16 U19 IO_L20N_3 IO_L31N_3/400NC P18 RAM_CENn
RAM_D09 8 DQb A 49 RAM_A09
RAM_A03 V20 IO_L20P_3 IO_L31P_3/400NC P17 RAM_CLK
RAM_D10 9 DQb A 50 RAM_A08
RAM_D17 V22 IO_L21N_3 IO_L32N_3/400NC P22 RAM_A11
RAM_D11 12 DQb A 80 RAM_A07
F F
U19 RAM_A02 V21 IO_L21P_3 IO_L32P_3/400NC P21 RAM_A10
RAM_D12 13 DQb A 81 RAM_A06
CY7C1356C−AC−CTRL T17 N18
RAM_A15 IO_L22N_3 IO_L33N_3/400NC RAM_A14
RAM_D13 18 DQb A 82 RAM_A05
MODE 31 RAM_A17 U18 IO_L22P_3 IO_L33P_3/400NC N17 RAM_A13
RAM_D14 19 DQb A 83 RAM_A04
ZZ 64 RAM_A00 U21 IO_L23N_3 IO_L34P_3/VREF_3 N19 RAM_A12
RAM_D15 22 DQb A 99 RAM_A03
RAM_A08 R18 IO_L24N_3 IO_L40N_3/VREF_3 M22 RAM_D08
RAM_D16 23 DQb A 100 RAM_A02
E E
RAM_A07 T18 IO_L24P_3
RAM_D17 24 DQPb A1 36 RAM_A01
RAM_A06 T22 IO_L27N_3

ADV/LD
A0 37 RAM_A00

CLK

BWa

BWb
CEN
T21

CE1

CE2

CE3
RAM_A05 IO_L27P_3

WE

OE
RAM_D00 N20 IO_L34N_3

98

97

92

87

89

88

86

85

93

94
RAM_CENn
N22

RAM_CE1n
RAM_D02 IO_L35N_3

RAM_WEn

RAM_OEn
RAM_CLK

RAM_LDn
D D
RAM_D01 N21 IO_L35P_3

RAM_D04 M18 IO_L38N_3

U19
2_5V_RAM:1 CY7C1356C−AC−PWR RAM_D03 M17 IO_L38P_3
2_5V_RAM:1
RAM_D06 M20 IO_L39N_3
4 VDDQ GND 5

RAM_D05 M19 IO_L39P_3

11 VDDQ GND 10
C C
VCCO_3

VCCO_3

VCCO_3

VCCO_3

VCCO_3
RAM_D07 M21 IO_L40P_3 2_5V_RAM:1
20 VDDQ GND 17

27 VDDQ GND 21
M16

N16

P16

R17

R20

2_5V_FPGA:1
54 VDDQ GND 26

61 VDDQ GND 40
C806 C807 C808 C809 C810 C811 C812 C813 C814 C815 C816 C817
70 VDDQ GND 55 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
B B
77 VDDQ GND 60

15 VDD GND 67 C332C331C333C334C335

0.1uF0.1uF0.1uF0.1uF0.1uF
41 VDD GND 71

65 VDD GND 76

91 90
USRP2 RAM
VDD GND
A TITLE $Date$ A

FILE: ram.sch REVISION: $Revision$

PAGE 8 OF 8 DRAWN BY: $Author$
1 2 3 4 5 6 7 8 9 10 11