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--
-- Company:
-- Engineer:
--
-- Create Date: 21:33:36 09/18/2010
-- Design Name:
-- Module Name: full_adder_struct - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity full_adder_struct is
port (a,b,cin:in std_logic;
sum,carry:out std_logic);
end ;
architecture full_adder_struct_arch of full_adder_struct is
component ha
port (a,b:in std_logic;
sum,carry:out std_logic);
end component;
component org
port(a,b:in std_logic;
c: out std_logic);
end component;
signal sum1,c1,c2 : std_logic;
begin
h1: ha port map (a=>a,b=>b,sum=>sum1,carry=> c1);
h2: ha port map (a=>sum1,b=>cin,sum=>sum,carry=> c2);
O1: org port map (a=> c1,b=>c2,c=> carry);
end;