9/24/2009

3D Stacking: EDA Challenges &

Opportunities
SEMATECH Symposium
Tokyo, Japan

September 2009

Rajiv Maheshwary
Senior Director
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Why 3D IC Design?

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Packaging Technology Evolution

All these technologies will co-exist
High
2010’s Vertical stack Lateral stack

2000’s
Density
Medium

1990’s
Low

Low Medium High

*Source: Yole Development, 2008
Functionality
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3D IC Market Drivers & Opportunity

Driving Issue Design Challenge Case for 3D (TSV)

Miniaturization More Moore

(Form factor, cost) (2.5X higher costs
per process node)
Memory Bandwidth Requirement
12 9.7
Quad Core 9.3
10
Performance/power 8
6 3.9 4.2
(Memory Bandwidth
4
for Multi-media) 1 1.2 1.5
2
Dual Core
0
+ I/O density 100X 2D

Mixed Technology More IP Reuse

(Heterogeneous (Time to market, cost)
Integration) 45-nm
130-nm

*Source: IBS, Major IDM, 2008

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3D IC TSV Applications

2008: CMOS Image Sensors

2010: High-density Flash, DRAM
2011-2: Logic + memory
2014: Multi-level 3D SiP’s
Source: Micron Technology Source: International Solid-State
Circuits Conference, February 2009

Requirements for
Market Success

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Slide Intentionally
Left Blank For
Handout Purposes

Requirements for 3D (TSV) IC Market Success

3D Definition

TSV process
& Wafer IDM/ Yield
Foundry
Thinning

Cost
OSAT*
3D IC Test
Efficiency Test EDA
Elements Automation

Die EDA Design &

Stacking
Methodology
& Packaging

Eco-System & Standards

*Outsourced Semi Assembly & Test

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Generic EDA Solution To Enable 3D IC Design

Multi die planner

Die 2: Digital
Netlist Die 1: Digital Die RF
manager Passive (Active) Interposer
Package

Abstraction/Dynamic Abstraction/Dynamic
IC-Package Interface
Link Link

Digital RF/AMS Package

Electrical Thermal
Analysis Analysis
Source: STM, DAC 2009

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Enabling 3D (TSV)
IC Design with EDA

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3D (TSV) IC Design Flow Vision

Foundry(Tech Files) EDA Design Methodology
•System level
• TSV stress/ Die (Stack) design exploration

Modeling
reliability analysis
Partitioning • Logic partitioning

TSV
• TSV connectivity
• Special rules TSV Synthesis & checking w/JTAG
DFT • Test methods
DRC/LVS

Timing/Power Analysis
• Multi-die bump &
Physical TSV floorplan
DRC/LVS Design • Auto TSV P&R
• IC-Package I/F
Model Deck
(.lib) • Extract TSV,
Extraction u-bump, backside
RDL metal
Parasitic • TSV aware
Physical
Interconnect

Extraction physical
Modeling

Verification verification

• TSV aware timing,

• Interconnect Stack IR-Drop, EM
technology data
Sign-off analysis
• Thermal analysis

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TSV Induced Stress and Reliability

Transistor is
being squeezed
or stretched
Die 2 by adjacent TSVs
(thin) TSV

Material deformation
m-bump leads to mobility change

Typical Back-to-Front TSV Stack The amount of proximity

effects depend on
Bumps to connect Stress affects transistor geometry shape,
Die 1 location, and orientation
to the package performance
Interconnects
Die 2
TSV Through Silicon Via
(thin)

Interconnects
m-bump
Transistors
Die 2 TSV squeezes
(thin) TSV or stretches
Die 1 adjacent
interconnects
m-bump

De-bonding and
De-lamination
Stress affects BEoL could occur under
Die 1
reliability additional stress

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3D IC Stress/Reliability Analysis Solution

001 Wafer, 110 Orientation
Von Mises Effective Stress (MPa)

t=400um

t=200um Compressive film stress

t=100um Die Thinning

TSV

t=20um
Wafer Warpage Stress Hotspots Performance Variation

Effective Stress

Submodel 1 Submodel 3
Submodel 2

Global Model Multi-scale Modeling Reliability Analysis

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3D IC Test Strategies
• Challenge
– Stack testing (efficiency &
low cost)
– Low pin count test

• Solution
– Test one die at a time with
isolation logic (core or
boundary)
– 1000X test compression at
very low pin cost
– Inter-die testing
methodology
– Use/extend IEEE 1149.1
and 1500 test standards

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3D IC Physical Design Challenges

Substrate
Chip
Bump
3D IC
Package

Today’s Flip Chip Flow

Bumps (solder balls)

are placed overlaying
the complete chip

Chip connections
“re-distributed” Bump
from pads to cell

bumps RDL
route

Re-Distribution • Represent TSV & backside

Layer (RDL) metal in technology file
routing is on • Automatic P&R
upper-most layer IO
pad • Support multiple chips

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TSV, IO and Bump Placement & Routing

Placement
Blockages

TSV’s

Bumps/Lands

TSV’s connected
to I/O

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3D IC Extraction Challenges
Today 3D IC

Substrate
Chip
Bump

Package

• Single-sided substrate
• Includes extraction of routing
& RDL layers
• Parasitic netlist represents a
single die • Parasitic effects of TSV, u-bump,
bonding layer, interposer routing
• Support of multiple chips

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3D IC Extraction Solution: Stacked Die

Interconnect Technology File

Chip 2

Chip 1

• “2D” extraction for Chip 1

• “3D” extraction for Chip 2 with TSV and backside routing
• Generate single spice netlist with parasitics for top, TSV and
back metal layers

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3D IC Thermal Considerations

Peak temperature
is 15% higher

• Challenge
– Multiple heat sources (stack)
– Substrate thinning yields poor heat dissipation per die (2D)
– Elevated thermal gradient in 3D

• Implications
– Reliability
– Timing
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3D IC Thermal Solutions
Thermally Optimized Floor-plan
2
• Accurate thermal
1
modeling & analysis
• Thermal-aware
physical design
– 5% increase in wire-length
3
@ 2D peak temperature
5

4 • Thermal TSV’s

White space
Heat sources
used for
(distributed)
Thermal Vias

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Summary
• 3D IC Market Drivers
– Cost, Performance/Power
– Heterogeneous integration

• Customers expected to have

production devices starting 2011
– Logic + DRAM and Logic + Logic
– $20B* TSV devices by 2013

• Synopsys Focus
– Enable design flow with partners
– Lead definition of emerging
interoperability standards

Source: Gartner Semiconductor Industry Briefing, June 2009

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