Review of Basics of Digital Electronics 1 Lecture 1

Overview

Introduction
Logic Gates
Flip Flops
Registers
Counters
Multiplexer/ Demultiplexer
Decoder/ Encoder

CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT

Review of Basics of Digital Electronics 2 Lecture 1

Introduction

Digital Computer
A computer that stores data in terms of digits (numbers)
and proceeds in discrete steps from one state to the next
Binary digits
The states of a digital computer typically involve binary
digits. A binary digit is called a bit

RAM

CPU

I/P O/P
IOP
Device Device

Block diagram of a digital computer

CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT

Review of Basics of Digital Electronics 3 Lecture 1

Logic Gates
Name Symbol Function Truth Table
A B X
A X=A•B 0 0 0
AND X or 0 1
1 0
0
0
B X = AB 1 1 1
A B X
A
OR X X=A+B
0 0
0 1
0
1
B 1 0 1
1 A1 1
X
I A X X=A
0
1
1
0
A X
0 0
Buffer A X X=A 1 1
A B X
A 0 0 1
NAND X X = (AB)’
0 1
1 0
1
1
B 1 1 0
A B X
A 0 0 1
NOR X X = (A + B)’ 0 1
1 0
0
0
B 1 1 0
A B X
A X=AB
XOR X or
0 0
0 1
0
1
Exclusive OR 1 0 1
B X = A’B + AB’
1 1 0
A B X
A X = (A  B)’
XNOR X or
0 0
0 1
1
0
Exclusive NOR
1 0 0
or Equivalence B X = A’B’+ AB 1 1 1

CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT

Review of Basics of Digital Electronics 4 Lecture 1

Flip Flops

Characteristics
- 2 stable states
- Memory capability
- Operation is specified by a Characteristic Table

The Storage elements employed in clocked sequential

circuits, capable of storing one bit of information, are called
Flip Flops
The most common types of flip flops are
SR (Set Reset)
D (Data)
JK
T (Toggle)

CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT

Review of Basics of Digital Electronics 5 Lecture 1

Clocked Flip Flops

In a large digital system with many flip flops, operations of
individual flip flops are required to be synchronized to a clock
pulse. Otherwise, the operations of the system may be
unpredictable.
Clock pulse allows the flip flop to change state only when there is a
clock pulse appearing at the c terminal (as shown in fig).

S Q S Q
c c
R Q’ R Q’
operates when operates when
clock is high clock is low

Edge Triggered Flip Flops

State transition occurs at the rising edge or falling edge of the clock pulse

CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT

Review of Basics of Digital Electronics 6 Lecture 1

Flip Flops
Flip Flop GraphicalSymbol Characteristic Table

SR (Set
Reset)
S Q S R Q(t+1)
0 0 Q(t)
c 0 1 0
R Q’ 1 0 1
1 1 indeterminate
(forbidden)

D (Data)
D Q(t+1)
J Q
0 0
C 1 1
K Q'

CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT

Review of Basics of Digital Electronics 7 Lecture 1

Flip Flops
Flip Flop GraphicalSymbol Characteristic Table

J-K
J Q SJ RK Q(t+1)
J Q
00 00 Q(t)
Q(t)
cC 00 11 00
RK Q'
Q’ 11 00 11
11 11 indeterminate
Q’(t)
(forbidden)

T (Toggle)
T Q(t+1)
T Q 0 Q(t)
c 1 Q’(t)

CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT